47883 lines
5.4 MiB
47883 lines
5.4 MiB
Restoring blue bitstream lib files
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==================================
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Info: *******************************************************************
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Info: Running Quartus Prime Shell
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Info: Version 19.2.0 Build 57 06/24/2019 Patches 0.01rc SJ Pro Edition
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Info: Copyright (C) 2019 Intel Corporation. All rights reserved.
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Info: Your use of Intel Corporation's design tools, logic functions
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Info: and other software and tools, and any partner logic
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Info: functions, and any output files from any of the foregoing
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Info: (including device programming or simulation files), and any
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Info: associated documentation or information are expressly subject
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Info: to the terms and conditions of the Intel Program License
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Info: Subscription Agreement, the Intel Quartus Prime License Agreement,
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Info: the Intel FPGA IP License Agreement, or other applicable license
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Info: agreement, including, without limitation, that your use is for
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Info: the sole purpose of programming logic devices manufactured by
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Info: Intel and sold by Intel or its authorized distributors. Please
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Info: refer to the applicable agreement for further details, at
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Info: https://fpgasoftware.intel.com/eula.
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Info: Processing started: Sat Mar 6 04:42:33 2021
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Info: Command: quartus_sh -t ./a10_partial_reconfig/flow.tcl -nobasecheck -setup_script ./a10_partial_reconfig/setup.tcl -impl afu_default
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Info: Quartus(args): -nobasecheck -setup_script ./a10_partial_reconfig/setup.tcl -impl afu_default
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Info: flow.tcl version: #1
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Info: Using setup script /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/a10_partial_reconfig/setup.tcl
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Arria 10 Partial Reconfiguration Flow
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-------------------------------------------------------------------------------
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Project name : dcp
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Output directory : output_files
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Base revision name : dcp
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Reconfigurable partition names : green_region
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Implementation Revision : afu_default
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Reconfigurable Partition Name : green_region
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Info: Compiling PR implementation afu_default.
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Info: *******************************************************************
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Info: Running Quartus Prime IP Generation Tool
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Info: Version 19.2.0 Build 57 06/24/2019 Patches 0.01rc SJ Pro Edition
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Info: Processing started: Sat Mar 6 04:42:35 2021
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Info: Command: quartus_ipgenerate dcp -c afu_default --run_default_mode_op
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Info: Found 1 IP file(s) in the project.
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Info: IP file /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/AFU_debug/SCJIO.qsys was found in the project.
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Info: Finished generating IP file(s) in the project.
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Info: Previously generated synthesis files were detected in the Platform Designer IP file generation directory (/nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/AFU_debug/SCJIO).
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Info: Skipped generation of synthesis files for the Platform Designer IP file /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/AFU_debug/SCJIO.qsys based on the current regeneration policy setting (Tools/Options/IP Settings).
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Info: Quartus Prime IP Generation Tool was successful. 0 errors, 0 warnings
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Info: Peak virtual memory: 1136 megabytes
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Info: Processing ended: Sat Mar 6 04:42:35 2021
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Info: Elapsed time: 00:00:00
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Info: *******************************************************************
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Info: Running Quartus Prime Synthesis
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Info: Version 19.2.0 Build 57 06/24/2019 Patches 0.01rc SJ Pro Edition
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Info: Processing started: Sat Mar 6 04:42:37 2021
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Info: Command: quartus_syn --read_settings_files=on --write_settings_files=off dcp -c afu_default
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Info: qis_default_flow_script.tcl version: #1
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Info: Initializing Synthesis...
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Info: Project = "dcp"
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Info: Revision = "afu_default"
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Info: Analyzing source files
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Info (16303): Superior Performance optimization mode selected -- timing performance will be prioritized at the potential cost of increased logic area and compilation time
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Info (16304): Mode behavior is affected by advanced setting Restructure Multiplexers (default for this mode is Off)
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Info (16304): Mode behavior is affected by advanced setting Placement Effort Multiplier (default for this mode is 4.0)
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Info (19806): Entity rebinding has been applied to partition "fpga_top|inst_green_bs". The entity has been remapped from "green_bs" to "green_bs".
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Info (16734): Loading "final" snapshot for partition "root_partition".
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Info (16734): Loading "final" snapshot for partition "root_partition_2cedade0".
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Warning (13228): Verilog HDL or VHDL warning at ccip_if_pkg.sv(36): parameter declared inside package 'ccip_if_pkg' shall be treated as localparam File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/device_if/ccip_if_pkg.sv Line: 36
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Warning (13228): Verilog HDL or VHDL warning at ccip_if_pkg.sv(38): parameter declared inside package 'ccip_if_pkg' shall be treated as localparam File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/device_if/ccip_if_pkg.sv Line: 38
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Warning (13228): Verilog HDL or VHDL warning at ccip_if_pkg.sv(39): parameter declared inside package 'ccip_if_pkg' shall be treated as localparam File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/device_if/ccip_if_pkg.sv Line: 39
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Warning (13228): Verilog HDL or VHDL warning at ccip_if_pkg.sv(41): parameter declared inside package 'ccip_if_pkg' shall be treated as localparam File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/device_if/ccip_if_pkg.sv Line: 41
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Warning (13228): Verilog HDL or VHDL warning at ccip_if_pkg.sv(42): parameter declared inside package 'ccip_if_pkg' shall be treated as localparam File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/device_if/ccip_if_pkg.sv Line: 42
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Warning (13228): Verilog HDL or VHDL warning at ccip_if_pkg.sv(43): parameter declared inside package 'ccip_if_pkg' shall be treated as localparam File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/device_if/ccip_if_pkg.sv Line: 43
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Warning (13228): Verilog HDL or VHDL warning at ccip_if_pkg.sv(45): parameter declared inside package 'ccip_if_pkg' shall be treated as localparam File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/device_if/ccip_if_pkg.sv Line: 45
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Warning (13228): Verilog HDL or VHDL warning at ccip_if_pkg.sv(48): parameter declared inside package 'ccip_if_pkg' shall be treated as localparam File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/device_if/ccip_if_pkg.sv Line: 48
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Warning (13228): Verilog HDL or VHDL warning at ccip_if_pkg.sv(51): parameter declared inside package 'ccip_if_pkg' shall be treated as localparam File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/device_if/ccip_if_pkg.sv Line: 51
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Warning (13228): Verilog HDL or VHDL warning at ccip_if_pkg.sv(53): parameter declared inside package 'ccip_if_pkg' shall be treated as localparam File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/device_if/ccip_if_pkg.sv Line: 53
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Warning (13228): Verilog HDL or VHDL warning at ccip_if_pkg.sv(136): parameter declared inside package 'ccip_if_pkg' shall be treated as localparam File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/device_if/ccip_if_pkg.sv Line: 136
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Warning (13228): Verilog HDL or VHDL warning at ccip_if_pkg.sv(149): parameter declared inside package 'ccip_if_pkg' shall be treated as localparam File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/device_if/ccip_if_pkg.sv Line: 149
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Warning (13228): Verilog HDL or VHDL warning at ccip_if_pkg.sv(178): parameter declared inside package 'ccip_if_pkg' shall be treated as localparam File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/device_if/ccip_if_pkg.sv Line: 178
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Warning (13228): Verilog HDL or VHDL warning at ccip_if_pkg.sv(190): parameter declared inside package 'ccip_if_pkg' shall be treated as localparam File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/device_if/ccip_if_pkg.sv Line: 190
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Warning (13228): Verilog HDL or VHDL warning at ccip_if_pkg.sv(218): parameter declared inside package 'ccip_if_pkg' shall be treated as localparam File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/device_if/ccip_if_pkg.sv Line: 218
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Warning (13228): Verilog HDL or VHDL warning at ccip_if_pkg.sv(223): parameter declared inside package 'ccip_if_pkg' shall be treated as localparam File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/device_if/ccip_if_pkg.sv Line: 223
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Info (16884): Verilog HDL info at ccip_cfg_pkg.sv(31): analyzing included file ./platform/platform_afu_top_config.vh File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/device_cfg/ccip_cfg_pkg.sv Line: 31
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Info (13230): Verilog HDL or VHDL information at ccip_cfg_pkg.sv(31): back to file '/opt/opae/1.1.2/share/opae/platform/platform_if/rtl/device_cfg/ccip_cfg_pkg.sv' File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/device_cfg/ccip_cfg_pkg.sv Line: 31
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Warning (13228): Verilog HDL or VHDL warning at ccip_cfg_pkg.sv(47): parameter declared inside package 'ccip_cfg_pkg' shall be treated as localparam File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/device_cfg/ccip_cfg_pkg.sv Line: 47
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Warning (13228): Verilog HDL or VHDL warning at ccip_cfg_pkg.sv(75): parameter declared inside package 'ccip_cfg_pkg' shall be treated as localparam File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/device_cfg/ccip_cfg_pkg.sv Line: 75
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Warning (13228): Verilog HDL or VHDL warning at ccip_cfg_pkg.sv(76): parameter declared inside package 'ccip_cfg_pkg' shall be treated as localparam File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/device_cfg/ccip_cfg_pkg.sv Line: 76
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Warning (13228): Verilog HDL or VHDL warning at ccip_cfg_pkg.sv(77): parameter declared inside package 'ccip_cfg_pkg' shall be treated as localparam File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/device_cfg/ccip_cfg_pkg.sv Line: 77
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Warning (13228): Verilog HDL or VHDL warning at ccip_cfg_pkg.sv(80): parameter declared inside package 'ccip_cfg_pkg' shall be treated as localparam File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/device_cfg/ccip_cfg_pkg.sv Line: 80
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Warning (13228): Verilog HDL or VHDL warning at ccip_cfg_pkg.sv(87): parameter declared inside package 'ccip_cfg_pkg' shall be treated as localparam File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/device_cfg/ccip_cfg_pkg.sv Line: 87
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Warning (13228): Verilog HDL or VHDL warning at ccip_cfg_pkg.sv(90): parameter declared inside package 'ccip_cfg_pkg' shall be treated as localparam File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/device_cfg/ccip_cfg_pkg.sv Line: 90
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Warning (13228): Verilog HDL or VHDL warning at ccip_cfg_pkg.sv(91): parameter declared inside package 'ccip_cfg_pkg' shall be treated as localparam File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/device_cfg/ccip_cfg_pkg.sv Line: 91
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Warning (13228): Verilog HDL or VHDL warning at ccip_cfg_pkg.sv(94): parameter declared inside package 'ccip_cfg_pkg' shall be treated as localparam File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/device_cfg/ccip_cfg_pkg.sv Line: 94
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Warning (13228): Verilog HDL or VHDL warning at ccip_cfg_pkg.sv(100): parameter declared inside package 'ccip_cfg_pkg' shall be treated as localparam File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/device_cfg/ccip_cfg_pkg.sv Line: 100
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Warning (13228): Verilog HDL or VHDL warning at ccip_cfg_pkg.sv(101): parameter declared inside package 'ccip_cfg_pkg' shall be treated as localparam File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/device_cfg/ccip_cfg_pkg.sv Line: 101
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Warning (13228): Verilog HDL or VHDL warning at ccip_cfg_pkg.sv(104): parameter declared inside package 'ccip_cfg_pkg' shall be treated as localparam File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/device_cfg/ccip_cfg_pkg.sv Line: 104
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Info (16884): Verilog HDL info at hssi_cfg_pkg.sv(31): analyzing included file ./platform/platform_afu_top_config.vh File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/device_cfg/hssi_cfg_pkg.sv Line: 31
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Info (13230): Verilog HDL or VHDL information at hssi_cfg_pkg.sv(31): back to file '/opt/opae/1.1.2/share/opae/platform/platform_if/rtl/device_cfg/hssi_cfg_pkg.sv' File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/device_cfg/hssi_cfg_pkg.sv Line: 31
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Info (16884): Verilog HDL info at local_mem_cfg_pkg.sv(31): analyzing included file ./platform/platform_afu_top_config.vh File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/device_cfg/local_mem_cfg_pkg.sv Line: 31
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Info (13230): Verilog HDL or VHDL information at local_mem_cfg_pkg.sv(31): back to file '/opt/opae/1.1.2/share/opae/platform/platform_if/rtl/device_cfg/local_mem_cfg_pkg.sv' File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/device_cfg/local_mem_cfg_pkg.sv Line: 31
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Warning (13228): Verilog HDL or VHDL warning at local_mem_cfg_pkg.sv(37): parameter declared inside package 'local_mem_cfg_pkg' shall be treated as localparam File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/device_cfg/local_mem_cfg_pkg.sv Line: 37
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Warning (13228): Verilog HDL or VHDL warning at local_mem_cfg_pkg.sv(39): parameter declared inside package 'local_mem_cfg_pkg' shall be treated as localparam File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/device_cfg/local_mem_cfg_pkg.sv Line: 39
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Warning (13228): Verilog HDL or VHDL warning at local_mem_cfg_pkg.sv(40): parameter declared inside package 'local_mem_cfg_pkg' shall be treated as localparam File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/device_cfg/local_mem_cfg_pkg.sv Line: 40
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Warning (13228): Verilog HDL or VHDL warning at local_mem_cfg_pkg.sv(42): parameter declared inside package 'local_mem_cfg_pkg' shall be treated as localparam File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/device_cfg/local_mem_cfg_pkg.sv Line: 42
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Warning (13228): Verilog HDL or VHDL warning at local_mem_cfg_pkg.sv(45): parameter declared inside package 'local_mem_cfg_pkg' shall be treated as localparam File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/device_cfg/local_mem_cfg_pkg.sv Line: 45
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Info (16884): Verilog HDL info at ccip_if_clock.sv(31): analyzing included file /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/platform_if.vh File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/device_if/ccip_if_clock.sv Line: 31
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Info (16884): Verilog HDL info at platform_if.vh(39): analyzing included file ./platform/platform_afu_top_config.vh File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/platform_if.vh Line: 39
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Info (13230): Verilog HDL or VHDL information at platform_if.vh(39): back to file '/opt/opae/1.1.2/share/opae/platform/platform_if/rtl/platform_if.vh' File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/platform_if.vh Line: 39
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Info (16884): Verilog HDL info at platform_if.vh(41): analyzing included file /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/device_if/device_if.vh File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/platform_if.vh Line: 41
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Info (16884): Verilog HDL info at device_if.vh(39): analyzing included file /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/device_if/avalon_mem_if.vh File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/device_if/device_if.vh Line: 39
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Info (13230): Verilog HDL or VHDL information at device_if.vh(39): back to file '/opt/opae/1.1.2/share/opae/platform/platform_if/rtl/device_if/device_if.vh' File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/device_if/device_if.vh Line: 39
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Info (13230): Verilog HDL or VHDL information at platform_if.vh(41): back to file '/opt/opae/1.1.2/share/opae/platform/platform_if/rtl/platform_if.vh' File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/platform_if.vh Line: 41
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Info (13230): Verilog HDL or VHDL information at ccip_if_clock.sv(31): back to file '/opt/opae/1.1.2/share/opae/platform/platform_if/rtl/device_if/ccip_if_clock.sv' File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/device_if/ccip_if_clock.sv Line: 31
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Info (16884): Verilog HDL info at platform_shim_ccip_std_afu.sv(39): analyzing included file /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/platform_if.vh File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/platform_shims/platform_shim_ccip_std_afu.sv Line: 39
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Info (16884): Verilog HDL info at platform_if.vh(39): analyzing included file ./platform/platform_afu_top_config.vh File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/platform_if.vh Line: 39
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Info (13230): Verilog HDL or VHDL information at platform_if.vh(39): back to file '/opt/opae/1.1.2/share/opae/platform/platform_if/rtl/platform_if.vh' File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/platform_if.vh Line: 39
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Info (16884): Verilog HDL info at platform_if.vh(41): analyzing included file /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/device_if/device_if.vh File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/platform_if.vh Line: 41
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Info (16884): Verilog HDL info at device_if.vh(39): analyzing included file /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/device_if/avalon_mem_if.vh File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/device_if/device_if.vh Line: 39
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Warning (16817): Verilog HDL warning at avalon_mem_if.vh(155): overwriting previous definition of avalon_mem_if interface File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/device_if/avalon_mem_if.vh Line: 155
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Info (18437): Verilog HDL info at avalon_mem_if.vh(155): previous definition of module avalon_mem_if is here File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/device_if/avalon_mem_if.vh Line: 155
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Info (13230): Verilog HDL or VHDL information at device_if.vh(39): back to file '/opt/opae/1.1.2/share/opae/platform/platform_if/rtl/device_if/device_if.vh' File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/device_if/device_if.vh Line: 39
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Info (13230): Verilog HDL or VHDL information at platform_if.vh(41): back to file '/opt/opae/1.1.2/share/opae/platform/platform_if/rtl/platform_if.vh' File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/platform_if.vh Line: 41
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Info (13230): Verilog HDL or VHDL information at platform_shim_ccip_std_afu.sv(39): back to file '/opt/opae/1.1.2/share/opae/platform/platform_if/rtl/platform_shims/platform_shim_ccip_std_afu.sv' File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/platform_shims/platform_shim_ccip_std_afu.sv Line: 39
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Info (16884): Verilog HDL info at platform_shim_ccip.sv(36): analyzing included file /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/platform_if.vh File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/platform_shims/platform_shim_ccip.sv Line: 36
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Info (16884): Verilog HDL info at platform_if.vh(39): analyzing included file ./platform/platform_afu_top_config.vh File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/platform_if.vh Line: 39
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Info (13230): Verilog HDL or VHDL information at platform_if.vh(39): back to file '/opt/opae/1.1.2/share/opae/platform/platform_if/rtl/platform_if.vh' File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/platform_if.vh Line: 39
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Info (16884): Verilog HDL info at platform_if.vh(41): analyzing included file /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/device_if/device_if.vh File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/platform_if.vh Line: 41
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Info (16884): Verilog HDL info at device_if.vh(39): analyzing included file /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/device_if/avalon_mem_if.vh File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/device_if/device_if.vh Line: 39
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Warning (16817): Verilog HDL warning at avalon_mem_if.vh(155): overwriting previous definition of avalon_mem_if interface File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/device_if/avalon_mem_if.vh Line: 155
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Info (18437): Verilog HDL info at avalon_mem_if.vh(155): previous definition of module avalon_mem_if is here File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/device_if/avalon_mem_if.vh Line: 155
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Info (13230): Verilog HDL or VHDL information at device_if.vh(39): back to file '/opt/opae/1.1.2/share/opae/platform/platform_if/rtl/device_if/device_if.vh' File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/device_if/device_if.vh Line: 39
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Info (13230): Verilog HDL or VHDL information at platform_if.vh(41): back to file '/opt/opae/1.1.2/share/opae/platform/platform_if/rtl/platform_if.vh' File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/platform_if.vh Line: 41
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Info (13230): Verilog HDL or VHDL information at platform_shim_ccip.sv(36): back to file '/opt/opae/1.1.2/share/opae/platform/platform_if/rtl/platform_shims/platform_shim_ccip.sv' File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/platform_shims/platform_shim_ccip.sv Line: 36
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Info (16884): Verilog HDL info at platform_shim_avalon_mem_if.sv(36): analyzing included file /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/platform_if.vh File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/platform_shims/platform_shim_avalon_mem_if.sv Line: 36
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Info (16884): Verilog HDL info at platform_if.vh(39): analyzing included file ./platform/platform_afu_top_config.vh File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/platform_if.vh Line: 39
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Info (13230): Verilog HDL or VHDL information at platform_if.vh(39): back to file '/opt/opae/1.1.2/share/opae/platform/platform_if/rtl/platform_if.vh' File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/platform_if.vh Line: 39
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Info (16884): Verilog HDL info at platform_if.vh(41): analyzing included file /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/device_if/device_if.vh File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/platform_if.vh Line: 41
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Info (16884): Verilog HDL info at device_if.vh(39): analyzing included file /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/device_if/avalon_mem_if.vh File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/device_if/device_if.vh Line: 39
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Warning (16817): Verilog HDL warning at avalon_mem_if.vh(155): overwriting previous definition of avalon_mem_if interface File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/device_if/avalon_mem_if.vh Line: 155
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Info (18437): Verilog HDL info at avalon_mem_if.vh(155): previous definition of module avalon_mem_if is here File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/device_if/avalon_mem_if.vh Line: 155
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Info (13230): Verilog HDL or VHDL information at device_if.vh(39): back to file '/opt/opae/1.1.2/share/opae/platform/platform_if/rtl/device_if/device_if.vh' File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/device_if/device_if.vh Line: 39
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Info (13230): Verilog HDL or VHDL information at platform_if.vh(41): back to file '/opt/opae/1.1.2/share/opae/platform/platform_if/rtl/platform_if.vh' File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/platform_if.vh Line: 41
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Info (13230): Verilog HDL or VHDL information at platform_shim_avalon_mem_if.sv(36): back to file '/opt/opae/1.1.2/share/opae/platform/platform_if/rtl/platform_shims/platform_shim_avalon_mem_if.sv' File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/platform_shims/platform_shim_avalon_mem_if.sv Line: 36
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Info (16884): Verilog HDL info at avalon_mem_if_async_shim.sv(35): analyzing included file /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/platform_if.vh File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/platform_shims/utils/avalon_mem_if_async_shim.sv Line: 35
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Info (16884): Verilog HDL info at platform_if.vh(39): analyzing included file ./platform/platform_afu_top_config.vh File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/platform_if.vh Line: 39
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Info (13230): Verilog HDL or VHDL information at platform_if.vh(39): back to file '/opt/opae/1.1.2/share/opae/platform/platform_if/rtl/platform_if.vh' File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/platform_if.vh Line: 39
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Info (16884): Verilog HDL info at platform_if.vh(41): analyzing included file /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/device_if/device_if.vh File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/platform_if.vh Line: 41
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Info (16884): Verilog HDL info at device_if.vh(39): analyzing included file /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/device_if/avalon_mem_if.vh File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/device_if/device_if.vh Line: 39
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Warning (16817): Verilog HDL warning at avalon_mem_if.vh(155): overwriting previous definition of avalon_mem_if interface File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/device_if/avalon_mem_if.vh Line: 155
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Info (18437): Verilog HDL info at avalon_mem_if.vh(155): previous definition of module avalon_mem_if is here File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/device_if/avalon_mem_if.vh Line: 155
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Info (13230): Verilog HDL or VHDL information at device_if.vh(39): back to file '/opt/opae/1.1.2/share/opae/platform/platform_if/rtl/device_if/device_if.vh' File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/device_if/device_if.vh Line: 39
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Info (13230): Verilog HDL or VHDL information at platform_if.vh(41): back to file '/opt/opae/1.1.2/share/opae/platform/platform_if/rtl/platform_if.vh' File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/platform_if.vh Line: 41
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Info (13230): Verilog HDL or VHDL information at avalon_mem_if_async_shim.sv(35): back to file '/opt/opae/1.1.2/share/opae/platform/platform_if/rtl/platform_shims/utils/avalon_mem_if_async_shim.sv' File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/platform_shims/utils/avalon_mem_if_async_shim.sv Line: 35
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Info (16884): Verilog HDL info at avalon_mem_if_reg.sv(37): analyzing included file /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/platform_if.vh File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/platform_shims/utils/avalon_mem_if_reg.sv Line: 37
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Info (16884): Verilog HDL info at platform_if.vh(39): analyzing included file ./platform/platform_afu_top_config.vh File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/platform_if.vh Line: 39
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Info (13230): Verilog HDL or VHDL information at platform_if.vh(39): back to file '/opt/opae/1.1.2/share/opae/platform/platform_if/rtl/platform_if.vh' File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/platform_if.vh Line: 39
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Info (16884): Verilog HDL info at platform_if.vh(41): analyzing included file /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/device_if/device_if.vh File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/platform_if.vh Line: 41
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Info (16884): Verilog HDL info at device_if.vh(39): analyzing included file /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/device_if/avalon_mem_if.vh File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/device_if/device_if.vh Line: 39
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Warning (16817): Verilog HDL warning at avalon_mem_if.vh(155): overwriting previous definition of avalon_mem_if interface File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/device_if/avalon_mem_if.vh Line: 155
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Info (18437): Verilog HDL info at avalon_mem_if.vh(155): previous definition of module avalon_mem_if is here File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/device_if/avalon_mem_if.vh Line: 155
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Info (13230): Verilog HDL or VHDL information at device_if.vh(39): back to file '/opt/opae/1.1.2/share/opae/platform/platform_if/rtl/device_if/device_if.vh' File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/device_if/device_if.vh Line: 39
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Info (13230): Verilog HDL or VHDL information at platform_if.vh(41): back to file '/opt/opae/1.1.2/share/opae/platform/platform_if/rtl/platform_if.vh' File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/platform_if.vh Line: 41
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Info (13230): Verilog HDL or VHDL information at avalon_mem_if_reg.sv(37): back to file '/opt/opae/1.1.2/share/opae/platform/platform_if/rtl/platform_shims/utils/avalon_mem_if_reg.sv' File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/platform_shims/utils/avalon_mem_if_reg.sv Line: 37
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Info (16884): Verilog HDL info at avalon_mem_if_reg_simple.sv(39): analyzing included file /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/platform_if.vh File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/platform_shims/utils/avalon_mem_if_reg_simple.sv Line: 39
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Info (16884): Verilog HDL info at platform_if.vh(39): analyzing included file ./platform/platform_afu_top_config.vh File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/platform_if.vh Line: 39
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Info (13230): Verilog HDL or VHDL information at platform_if.vh(39): back to file '/opt/opae/1.1.2/share/opae/platform/platform_if/rtl/platform_if.vh' File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/platform_if.vh Line: 39
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Info (16884): Verilog HDL info at platform_if.vh(41): analyzing included file /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/device_if/device_if.vh File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/platform_if.vh Line: 41
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|
Info (16884): Verilog HDL info at device_if.vh(39): analyzing included file /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/device_if/avalon_mem_if.vh File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/device_if/device_if.vh Line: 39
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|
Warning (16817): Verilog HDL warning at avalon_mem_if.vh(155): overwriting previous definition of avalon_mem_if interface File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/device_if/avalon_mem_if.vh Line: 155
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|
Info (18437): Verilog HDL info at avalon_mem_if.vh(155): previous definition of module avalon_mem_if is here File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/device_if/avalon_mem_if.vh Line: 155
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Info (13230): Verilog HDL or VHDL information at device_if.vh(39): back to file '/opt/opae/1.1.2/share/opae/platform/platform_if/rtl/device_if/device_if.vh' File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/device_if/device_if.vh Line: 39
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Info (13230): Verilog HDL or VHDL information at platform_if.vh(41): back to file '/opt/opae/1.1.2/share/opae/platform/platform_if/rtl/platform_if.vh' File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/platform_if.vh Line: 41
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Info (13230): Verilog HDL or VHDL information at avalon_mem_if_reg_simple.sv(39): back to file '/opt/opae/1.1.2/share/opae/platform/platform_if/rtl/platform_shims/utils/avalon_mem_if_reg_simple.sv' File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/platform_shims/utils/avalon_mem_if_reg_simple.sv Line: 39
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|
Info (16884): Verilog HDL info at platform_utils_ccip_async_shim.sv(41): analyzing included file /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/platform_if.vh File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/platform_shims/utils/platform_utils_ccip_async_shim.sv Line: 41
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Info (16884): Verilog HDL info at platform_if.vh(39): analyzing included file ./platform/platform_afu_top_config.vh File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/platform_if.vh Line: 39
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Info (13230): Verilog HDL or VHDL information at platform_if.vh(39): back to file '/opt/opae/1.1.2/share/opae/platform/platform_if/rtl/platform_if.vh' File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/platform_if.vh Line: 39
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|
Info (16884): Verilog HDL info at platform_if.vh(41): analyzing included file /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/device_if/device_if.vh File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/platform_if.vh Line: 41
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Info (16884): Verilog HDL info at device_if.vh(39): analyzing included file /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/device_if/avalon_mem_if.vh File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/device_if/device_if.vh Line: 39
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Warning (16817): Verilog HDL warning at avalon_mem_if.vh(155): overwriting previous definition of avalon_mem_if interface File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/device_if/avalon_mem_if.vh Line: 155
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|
Info (18437): Verilog HDL info at avalon_mem_if.vh(155): previous definition of module avalon_mem_if is here File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/device_if/avalon_mem_if.vh Line: 155
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Info (13230): Verilog HDL or VHDL information at device_if.vh(39): back to file '/opt/opae/1.1.2/share/opae/platform/platform_if/rtl/device_if/device_if.vh' File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/device_if/device_if.vh Line: 39
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Info (13230): Verilog HDL or VHDL information at platform_if.vh(41): back to file '/opt/opae/1.1.2/share/opae/platform/platform_if/rtl/platform_if.vh' File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/platform_if.vh Line: 41
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|
Info (13230): Verilog HDL or VHDL information at platform_utils_ccip_async_shim.sv(41): back to file '/opt/opae/1.1.2/share/opae/platform/platform_if/rtl/platform_shims/utils/platform_utils_ccip_async_shim.sv' File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/platform_shims/utils/platform_utils_ccip_async_shim.sv Line: 41
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|
Warning (16752): Verilog HDL warning at platform_utils_ccip_async_shim.sv(253): potential always loop found File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/platform_shims/utils/platform_utils_ccip_async_shim.sv Line: 253
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Warning (16752): Verilog HDL warning at platform_utils_ccip_async_shim.sv(390): potential always loop found File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/platform_shims/utils/platform_utils_ccip_async_shim.sv Line: 390
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Info (16884): Verilog HDL info at VX_bypass_buffer.v(1): analyzing included file ../../../../rtl/VX_platform.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/libs/VX_bypass_buffer.v Line: 1
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Info (16884): Verilog HDL info at VX_platform.vh(4): analyzing included file ../../../../rtl/VX_scope.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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|
Info (13230): Verilog HDL or VHDL information at VX_platform.vh(4): back to file '../../../../rtl/VX_platform.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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|
Info (13230): Verilog HDL or VHDL information at VX_bypass_buffer.v(1): back to file '/nethome/lcooper43/vortex-dev/hw/rtl/libs/VX_bypass_buffer.v' File: /nethome/lcooper43/vortex-dev/hw/rtl/libs/VX_bypass_buffer.v Line: 1
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|
Info (16884): Verilog HDL info at VX_multiplier.v(1): analyzing included file ../../../../rtl/VX_platform.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/libs/VX_multiplier.v Line: 1
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Info (16884): Verilog HDL info at VX_platform.vh(4): analyzing included file ../../../../rtl/VX_scope.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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|
Info (13230): Verilog HDL or VHDL information at VX_platform.vh(4): back to file '../../../../rtl/VX_platform.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
|
|
Info (13230): Verilog HDL or VHDL information at VX_multiplier.v(1): back to file '/nethome/lcooper43/vortex-dev/hw/rtl/libs/VX_multiplier.v' File: /nethome/lcooper43/vortex-dev/hw/rtl/libs/VX_multiplier.v Line: 1
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|
Info (16884): Verilog HDL info at VX_rr_arbiter.v(1): analyzing included file ../../../../rtl/VX_platform.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/libs/VX_rr_arbiter.v Line: 1
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|
Info (16884): Verilog HDL info at VX_platform.vh(4): analyzing included file ../../../../rtl/VX_scope.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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|
Info (13230): Verilog HDL or VHDL information at VX_platform.vh(4): back to file '../../../../rtl/VX_platform.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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|
Info (13230): Verilog HDL or VHDL information at VX_rr_arbiter.v(1): back to file '/nethome/lcooper43/vortex-dev/hw/rtl/libs/VX_rr_arbiter.v' File: /nethome/lcooper43/vortex-dev/hw/rtl/libs/VX_rr_arbiter.v Line: 1
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|
Info (16884): Verilog HDL info at VX_stream_demux.v(1): analyzing included file ../../../../rtl/VX_platform.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/libs/VX_stream_demux.v Line: 1
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|
Info (16884): Verilog HDL info at VX_platform.vh(4): analyzing included file ../../../../rtl/VX_scope.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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|
Info (13230): Verilog HDL or VHDL information at VX_platform.vh(4): back to file '../../../../rtl/VX_platform.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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|
Info (13230): Verilog HDL or VHDL information at VX_stream_demux.v(1): back to file '/nethome/lcooper43/vortex-dev/hw/rtl/libs/VX_stream_demux.v' File: /nethome/lcooper43/vortex-dev/hw/rtl/libs/VX_stream_demux.v Line: 1
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|
Info (16884): Verilog HDL info at VX_lzc.v(1): analyzing included file ../../../../rtl/VX_platform.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/libs/VX_lzc.v Line: 1
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|
Info (16884): Verilog HDL info at VX_platform.vh(4): analyzing included file ../../../../rtl/VX_scope.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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|
Info (13230): Verilog HDL or VHDL information at VX_platform.vh(4): back to file '../../../../rtl/VX_platform.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
|
|
Info (13230): Verilog HDL or VHDL information at VX_lzc.v(1): back to file '/nethome/lcooper43/vortex-dev/hw/rtl/libs/VX_lzc.v' File: /nethome/lcooper43/vortex-dev/hw/rtl/libs/VX_lzc.v Line: 1
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|
Info (16884): Verilog HDL info at VX_shift_register.v(1): analyzing included file ../../../../rtl/VX_platform.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/libs/VX_shift_register.v Line: 1
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|
Info (16884): Verilog HDL info at VX_platform.vh(4): analyzing included file ../../../../rtl/VX_scope.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
|
|
Info (13230): Verilog HDL or VHDL information at VX_platform.vh(4): back to file '../../../../rtl/VX_platform.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
|
|
Info (13230): Verilog HDL or VHDL information at VX_shift_register.v(1): back to file '/nethome/lcooper43/vortex-dev/hw/rtl/libs/VX_shift_register.v' File: /nethome/lcooper43/vortex-dev/hw/rtl/libs/VX_shift_register.v Line: 1
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|
Info (16884): Verilog HDL info at VX_sp_ram.v(1): analyzing included file ../../../../rtl/VX_platform.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/libs/VX_sp_ram.v Line: 1
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Info (16884): Verilog HDL info at VX_platform.vh(4): analyzing included file ../../../../rtl/VX_scope.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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|
Info (13230): Verilog HDL or VHDL information at VX_platform.vh(4): back to file '../../../../rtl/VX_platform.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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|
Info (13230): Verilog HDL or VHDL information at VX_sp_ram.v(1): back to file '/nethome/lcooper43/vortex-dev/hw/rtl/libs/VX_sp_ram.v' File: /nethome/lcooper43/vortex-dev/hw/rtl/libs/VX_sp_ram.v Line: 1
|
|
Info (16884): Verilog HDL info at VX_onehot_encoder.v(1): analyzing included file ../../../../rtl/VX_platform.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/libs/VX_onehot_encoder.v Line: 1
|
|
Info (16884): Verilog HDL info at VX_platform.vh(4): analyzing included file ../../../../rtl/VX_scope.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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|
Info (13230): Verilog HDL or VHDL information at VX_platform.vh(4): back to file '../../../../rtl/VX_platform.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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|
Info (13230): Verilog HDL or VHDL information at VX_onehot_encoder.v(1): back to file '/nethome/lcooper43/vortex-dev/hw/rtl/libs/VX_onehot_encoder.v' File: /nethome/lcooper43/vortex-dev/hw/rtl/libs/VX_onehot_encoder.v Line: 1
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|
Info (16884): Verilog HDL info at VX_dp_ram.v(1): analyzing included file ../../../../rtl/VX_platform.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/libs/VX_dp_ram.v Line: 1
|
|
Info (16884): Verilog HDL info at VX_platform.vh(4): analyzing included file ../../../../rtl/VX_scope.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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|
Info (13230): Verilog HDL or VHDL information at VX_platform.vh(4): back to file '../../../../rtl/VX_platform.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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|
Info (13230): Verilog HDL or VHDL information at VX_dp_ram.v(1): back to file '/nethome/lcooper43/vortex-dev/hw/rtl/libs/VX_dp_ram.v' File: /nethome/lcooper43/vortex-dev/hw/rtl/libs/VX_dp_ram.v Line: 1
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Info (16884): Verilog HDL info at VX_matrix_arbiter.v(1): analyzing included file ../../../../rtl/VX_platform.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/libs/VX_matrix_arbiter.v Line: 1
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Info (16884): Verilog HDL info at VX_platform.vh(4): analyzing included file ../../../../rtl/VX_scope.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_platform.vh(4): back to file '../../../../rtl/VX_platform.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_matrix_arbiter.v(1): back to file '/nethome/lcooper43/vortex-dev/hw/rtl/libs/VX_matrix_arbiter.v' File: /nethome/lcooper43/vortex-dev/hw/rtl/libs/VX_matrix_arbiter.v Line: 1
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Info (16884): Verilog HDL info at VX_fifo_queue.v(1): analyzing included file ../../../../rtl/VX_platform.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/libs/VX_fifo_queue.v Line: 1
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Info (16884): Verilog HDL info at VX_platform.vh(4): analyzing included file ../../../../rtl/VX_scope.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_platform.vh(4): back to file '../../../../rtl/VX_platform.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_fifo_queue.v(1): back to file '/nethome/lcooper43/vortex-dev/hw/rtl/libs/VX_fifo_queue.v' File: /nethome/lcooper43/vortex-dev/hw/rtl/libs/VX_fifo_queue.v Line: 1
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Info (16884): Verilog HDL info at VX_fixed_arbiter.v(1): analyzing included file ../../../../rtl/VX_platform.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/libs/VX_fixed_arbiter.v Line: 1
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Info (16884): Verilog HDL info at VX_platform.vh(4): analyzing included file ../../../../rtl/VX_scope.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_platform.vh(4): back to file '../../../../rtl/VX_platform.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_fixed_arbiter.v(1): back to file '/nethome/lcooper43/vortex-dev/hw/rtl/libs/VX_fixed_arbiter.v' File: /nethome/lcooper43/vortex-dev/hw/rtl/libs/VX_fixed_arbiter.v Line: 1
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|
Info (16884): Verilog HDL info at VX_index_queue.v(1): analyzing included file ../../../../rtl/VX_platform.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/libs/VX_index_queue.v Line: 1
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Info (16884): Verilog HDL info at VX_platform.vh(4): analyzing included file ../../../../rtl/VX_scope.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_platform.vh(4): back to file '../../../../rtl/VX_platform.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_index_queue.v(1): back to file '/nethome/lcooper43/vortex-dev/hw/rtl/libs/VX_index_queue.v' File: /nethome/lcooper43/vortex-dev/hw/rtl/libs/VX_index_queue.v Line: 1
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Info (16884): Verilog HDL info at VX_divider.v(1): analyzing included file ../../../../rtl/VX_platform.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/libs/VX_divider.v Line: 1
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Info (16884): Verilog HDL info at VX_platform.vh(4): analyzing included file ../../../../rtl/VX_scope.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_platform.vh(4): back to file '../../../../rtl/VX_platform.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_divider.v(1): back to file '/nethome/lcooper43/vortex-dev/hw/rtl/libs/VX_divider.v' File: /nethome/lcooper43/vortex-dev/hw/rtl/libs/VX_divider.v Line: 1
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Info (16884): Verilog HDL info at VX_fair_arbiter.v(1): analyzing included file ../../../../rtl/VX_platform.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/libs/VX_fair_arbiter.v Line: 1
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Info (16884): Verilog HDL info at VX_platform.vh(4): analyzing included file ../../../../rtl/VX_scope.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_platform.vh(4): back to file '../../../../rtl/VX_platform.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_fair_arbiter.v(1): back to file '/nethome/lcooper43/vortex-dev/hw/rtl/libs/VX_fair_arbiter.v' File: /nethome/lcooper43/vortex-dev/hw/rtl/libs/VX_fair_arbiter.v Line: 1
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Info (16884): Verilog HDL info at VX_stream_arbiter.v(1): analyzing included file ../../../../rtl/VX_platform.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/libs/VX_stream_arbiter.v Line: 1
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Info (16884): Verilog HDL info at VX_platform.vh(4): analyzing included file ../../../../rtl/VX_scope.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_platform.vh(4): back to file '../../../../rtl/VX_platform.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_stream_arbiter.v(1): back to file '/nethome/lcooper43/vortex-dev/hw/rtl/libs/VX_stream_arbiter.v' File: /nethome/lcooper43/vortex-dev/hw/rtl/libs/VX_stream_arbiter.v Line: 1
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Info (16884): Verilog HDL info at VX_serial_div.v(1): analyzing included file ../../../../rtl/VX_platform.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/libs/VX_serial_div.v Line: 1
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Info (16884): Verilog HDL info at VX_platform.vh(4): analyzing included file ../../../../rtl/VX_scope.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_platform.vh(4): back to file '../../../../rtl/VX_platform.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_serial_div.v(1): back to file '/nethome/lcooper43/vortex-dev/hw/rtl/libs/VX_serial_div.v' File: /nethome/lcooper43/vortex-dev/hw/rtl/libs/VX_serial_div.v Line: 1
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Info (16884): Verilog HDL info at VX_index_buffer.v(1): analyzing included file ../../../../rtl/VX_platform.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/libs/VX_index_buffer.v Line: 1
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Info (16884): Verilog HDL info at VX_platform.vh(4): analyzing included file ../../../../rtl/VX_scope.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_platform.vh(4): back to file '../../../../rtl/VX_platform.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_index_buffer.v(1): back to file '/nethome/lcooper43/vortex-dev/hw/rtl/libs/VX_index_buffer.v' File: /nethome/lcooper43/vortex-dev/hw/rtl/libs/VX_index_buffer.v Line: 1
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Info (16884): Verilog HDL info at VX_priority_encoder.v(1): analyzing included file ../../../../rtl/VX_platform.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/libs/VX_priority_encoder.v Line: 1
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Info (16884): Verilog HDL info at VX_platform.vh(4): analyzing included file ../../../../rtl/VX_scope.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_platform.vh(4): back to file '../../../../rtl/VX_platform.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_priority_encoder.v(1): back to file '/nethome/lcooper43/vortex-dev/hw/rtl/libs/VX_priority_encoder.v' File: /nethome/lcooper43/vortex-dev/hw/rtl/libs/VX_priority_encoder.v Line: 1
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Info (16884): Verilog HDL info at VX_elastic_buffer.v(1): analyzing included file ../../../../rtl/VX_platform.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/libs/VX_elastic_buffer.v Line: 1
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Info (16884): Verilog HDL info at VX_platform.vh(4): analyzing included file ../../../../rtl/VX_scope.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_platform.vh(4): back to file '../../../../rtl/VX_platform.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_elastic_buffer.v(1): back to file '/nethome/lcooper43/vortex-dev/hw/rtl/libs/VX_elastic_buffer.v' File: /nethome/lcooper43/vortex-dev/hw/rtl/libs/VX_elastic_buffer.v Line: 1
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Info (16884): Verilog HDL info at VX_scan.v(1): analyzing included file ../../../../rtl/VX_platform.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/libs/VX_scan.v Line: 1
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Info (16884): Verilog HDL info at VX_platform.vh(4): analyzing included file ../../../../rtl/VX_scope.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_platform.vh(4): back to file '../../../../rtl/VX_platform.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_scan.v(1): back to file '/nethome/lcooper43/vortex-dev/hw/rtl/libs/VX_scan.v' File: /nethome/lcooper43/vortex-dev/hw/rtl/libs/VX_scan.v Line: 1
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Info (16884): Verilog HDL info at VX_pending_size.v(1): analyzing included file ../../../../rtl/VX_platform.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/libs/VX_pending_size.v Line: 1
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Info (16884): Verilog HDL info at VX_platform.vh(4): analyzing included file ../../../../rtl/VX_scope.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_platform.vh(4): back to file '../../../../rtl/VX_platform.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_pending_size.v(1): back to file '/nethome/lcooper43/vortex-dev/hw/rtl/libs/VX_pending_size.v' File: /nethome/lcooper43/vortex-dev/hw/rtl/libs/VX_pending_size.v Line: 1
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|
Info (16884): Verilog HDL info at VX_scope.v(1): analyzing included file ../../../../rtl/VX_platform.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/libs/VX_scope.v Line: 1
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Info (16884): Verilog HDL info at VX_platform.vh(4): analyzing included file ../../../../rtl/VX_scope.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_platform.vh(4): back to file '../../../../rtl/VX_platform.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_scope.v(1): back to file '/nethome/lcooper43/vortex-dev/hw/rtl/libs/VX_scope.v' File: /nethome/lcooper43/vortex-dev/hw/rtl/libs/VX_scope.v Line: 1
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Info (16884): Verilog HDL info at VX_skid_buffer.v(1): analyzing included file ../../../../rtl/VX_platform.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/libs/VX_skid_buffer.v Line: 1
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Info (16884): Verilog HDL info at VX_platform.vh(4): analyzing included file ../../../../rtl/VX_scope.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_platform.vh(4): back to file '../../../../rtl/VX_platform.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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|
Info (13230): Verilog HDL or VHDL information at VX_skid_buffer.v(1): back to file '/nethome/lcooper43/vortex-dev/hw/rtl/libs/VX_skid_buffer.v' File: /nethome/lcooper43/vortex-dev/hw/rtl/libs/VX_skid_buffer.v Line: 1
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Info (16884): Verilog HDL info at VX_pipe_register.v(1): analyzing included file ../../../../rtl/VX_platform.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/libs/VX_pipe_register.v Line: 1
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Info (16884): Verilog HDL info at VX_platform.vh(4): analyzing included file ../../../../rtl/VX_scope.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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|
Info (13230): Verilog HDL or VHDL information at VX_platform.vh(4): back to file '../../../../rtl/VX_platform.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_pipe_register.v(1): back to file '/nethome/lcooper43/vortex-dev/hw/rtl/libs/VX_pipe_register.v' File: /nethome/lcooper43/vortex-dev/hw/rtl/libs/VX_pipe_register.v Line: 1
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Info (16884): Verilog HDL info at VX_reset_relay.v(1): analyzing included file ../../../../rtl/VX_platform.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/libs/VX_reset_relay.v Line: 1
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Info (16884): Verilog HDL info at VX_platform.vh(4): analyzing included file ../../../../rtl/VX_scope.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_platform.vh(4): back to file '../../../../rtl/VX_platform.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_reset_relay.v(1): back to file '/nethome/lcooper43/vortex-dev/hw/rtl/libs/VX_reset_relay.v' File: /nethome/lcooper43/vortex-dev/hw/rtl/libs/VX_reset_relay.v Line: 1
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Info (16884): Verilog HDL info at VX_csr_pipe_req_if.v(4): analyzing included file ../../../../rtl/VX_define.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/interfaces/VX_csr_pipe_req_if.v Line: 4
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Info (16884): Verilog HDL info at VX_define.vh(4): analyzing included file ../../../../rtl/VX_platform.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 4
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|
Info (16884): Verilog HDL info at VX_platform.vh(4): analyzing included file ../../../../rtl/VX_scope.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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|
Info (13230): Verilog HDL or VHDL information at VX_platform.vh(4): back to file '../../../../rtl/VX_platform.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(4): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 4
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Info (16884): Verilog HDL info at VX_define.vh(5): analyzing included file ../../../../rtl/VX_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 5
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|
Info (16884): Verilog HDL info at VX_config.vh(4): analyzing included file ../../../../rtl/VX_user_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_config.vh Line: 4
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|
Info (13230): Verilog HDL or VHDL information at VX_config.vh(4): back to file '../../../../rtl/VX_config.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_config.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(5): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 5
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|
Info (16884): Verilog HDL info at VX_define.vh(384): analyzing included file ../../../../rtl/VX_types.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 384
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Info (16884): Verilog HDL info at VX_types.vh(4): analyzing included file ../../../../rtl/VX_define.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_types.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_types.vh(4): back to file '../../../../rtl/VX_types.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_types.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(384): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 384
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Info (13230): Verilog HDL or VHDL information at VX_csr_pipe_req_if.v(4): back to file '/nethome/lcooper43/vortex-dev/hw/rtl/interfaces/VX_csr_pipe_req_if.v' File: /nethome/lcooper43/vortex-dev/hw/rtl/interfaces/VX_csr_pipe_req_if.v Line: 4
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|
Info (16884): Verilog HDL info at VX_perf_memsys_if.v(4): analyzing included file ../../../../rtl/VX_define.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/interfaces/VX_perf_memsys_if.v Line: 4
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|
Info (16884): Verilog HDL info at VX_define.vh(4): analyzing included file ../../../../rtl/VX_platform.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 4
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|
Info (16884): Verilog HDL info at VX_platform.vh(4): analyzing included file ../../../../rtl/VX_scope.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_platform.vh(4): back to file '../../../../rtl/VX_platform.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(4): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 4
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|
Info (16884): Verilog HDL info at VX_define.vh(5): analyzing included file ../../../../rtl/VX_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 5
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Info (16884): Verilog HDL info at VX_config.vh(4): analyzing included file ../../../../rtl/VX_user_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_config.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_config.vh(4): back to file '../../../../rtl/VX_config.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_config.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(5): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 5
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|
Info (16884): Verilog HDL info at VX_define.vh(384): analyzing included file ../../../../rtl/VX_types.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 384
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Info (16884): Verilog HDL info at VX_types.vh(4): analyzing included file ../../../../rtl/VX_define.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_types.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_types.vh(4): back to file '../../../../rtl/VX_types.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_types.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(384): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 384
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|
Info (13230): Verilog HDL or VHDL information at VX_perf_memsys_if.v(4): back to file '/nethome/lcooper43/vortex-dev/hw/rtl/interfaces/VX_perf_memsys_if.v' File: /nethome/lcooper43/vortex-dev/hw/rtl/interfaces/VX_perf_memsys_if.v Line: 4
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|
Info (16884): Verilog HDL info at VX_writeback_if.v(4): analyzing included file ../../../../rtl/VX_define.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/interfaces/VX_writeback_if.v Line: 4
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Info (16884): Verilog HDL info at VX_define.vh(4): analyzing included file ../../../../rtl/VX_platform.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 4
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Info (16884): Verilog HDL info at VX_platform.vh(4): analyzing included file ../../../../rtl/VX_scope.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_platform.vh(4): back to file '../../../../rtl/VX_platform.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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|
Info (13230): Verilog HDL or VHDL information at VX_define.vh(4): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 4
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Info (16884): Verilog HDL info at VX_define.vh(5): analyzing included file ../../../../rtl/VX_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 5
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Info (16884): Verilog HDL info at VX_config.vh(4): analyzing included file ../../../../rtl/VX_user_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_config.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_config.vh(4): back to file '../../../../rtl/VX_config.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_config.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(5): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 5
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Info (16884): Verilog HDL info at VX_define.vh(384): analyzing included file ../../../../rtl/VX_types.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 384
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Info (16884): Verilog HDL info at VX_types.vh(4): analyzing included file ../../../../rtl/VX_define.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_types.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_types.vh(4): back to file '../../../../rtl/VX_types.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_types.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(384): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 384
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Info (13230): Verilog HDL or VHDL information at VX_writeback_if.v(4): back to file '/nethome/lcooper43/vortex-dev/hw/rtl/interfaces/VX_writeback_if.v' File: /nethome/lcooper43/vortex-dev/hw/rtl/interfaces/VX_writeback_if.v Line: 4
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Info (16884): Verilog HDL info at VX_perf_pipeline_if.v(4): analyzing included file ../../../../rtl/VX_define.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/interfaces/VX_perf_pipeline_if.v Line: 4
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Info (16884): Verilog HDL info at VX_define.vh(4): analyzing included file ../../../../rtl/VX_platform.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 4
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Info (16884): Verilog HDL info at VX_platform.vh(4): analyzing included file ../../../../rtl/VX_scope.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_platform.vh(4): back to file '../../../../rtl/VX_platform.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(4): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 4
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Info (16884): Verilog HDL info at VX_define.vh(5): analyzing included file ../../../../rtl/VX_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 5
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Info (16884): Verilog HDL info at VX_config.vh(4): analyzing included file ../../../../rtl/VX_user_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_config.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_config.vh(4): back to file '../../../../rtl/VX_config.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_config.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(5): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 5
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Info (16884): Verilog HDL info at VX_define.vh(384): analyzing included file ../../../../rtl/VX_types.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 384
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Info (16884): Verilog HDL info at VX_types.vh(4): analyzing included file ../../../../rtl/VX_define.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_types.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_types.vh(4): back to file '../../../../rtl/VX_types.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_types.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(384): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 384
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Info (13230): Verilog HDL or VHDL information at VX_perf_pipeline_if.v(4): back to file '/nethome/lcooper43/vortex-dev/hw/rtl/interfaces/VX_perf_pipeline_if.v' File: /nethome/lcooper43/vortex-dev/hw/rtl/interfaces/VX_perf_pipeline_if.v Line: 4
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Info (16884): Verilog HDL info at VX_icache_core_rsp_if.v(4): analyzing included file /nethome/lcooper43/vortex-dev/hw/rtl/interfaces/../cache/VX_cache_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/interfaces/VX_icache_core_rsp_if.v Line: 4
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Info (16884): Verilog HDL info at VX_cache_config.vh(4): analyzing included file ../../../../rtl/VX_platform.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/cache/VX_cache_config.vh Line: 4
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Info (16884): Verilog HDL info at VX_platform.vh(4): analyzing included file ../../../../rtl/VX_scope.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_platform.vh(4): back to file '../../../../rtl/VX_platform.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_cache_config.vh(4): back to file '/nethome/lcooper43/vortex-dev/hw/rtl/interfaces/../cache/VX_cache_config.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/cache/VX_cache_config.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_icache_core_rsp_if.v(4): back to file '/nethome/lcooper43/vortex-dev/hw/rtl/interfaces/VX_icache_core_rsp_if.v' File: /nethome/lcooper43/vortex-dev/hw/rtl/interfaces/VX_icache_core_rsp_if.v Line: 4
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Info (16884): Verilog HDL info at VX_gpr_req_if.v(4): analyzing included file ../../../../rtl/VX_define.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/interfaces/VX_gpr_req_if.v Line: 4
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Info (16884): Verilog HDL info at VX_define.vh(4): analyzing included file ../../../../rtl/VX_platform.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 4
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Info (16884): Verilog HDL info at VX_platform.vh(4): analyzing included file ../../../../rtl/VX_scope.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_platform.vh(4): back to file '../../../../rtl/VX_platform.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(4): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 4
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Info (16884): Verilog HDL info at VX_define.vh(5): analyzing included file ../../../../rtl/VX_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 5
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Info (16884): Verilog HDL info at VX_config.vh(4): analyzing included file ../../../../rtl/VX_user_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_config.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_config.vh(4): back to file '../../../../rtl/VX_config.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_config.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(5): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 5
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Info (16884): Verilog HDL info at VX_define.vh(384): analyzing included file ../../../../rtl/VX_types.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 384
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Info (16884): Verilog HDL info at VX_types.vh(4): analyzing included file ../../../../rtl/VX_define.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_types.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_types.vh(4): back to file '../../../../rtl/VX_types.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_types.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(384): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 384
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Info (13230): Verilog HDL or VHDL information at VX_gpr_req_if.v(4): back to file '/nethome/lcooper43/vortex-dev/hw/rtl/interfaces/VX_gpr_req_if.v' File: /nethome/lcooper43/vortex-dev/hw/rtl/interfaces/VX_gpr_req_if.v Line: 4
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Info (16884): Verilog HDL info at VX_alu_req_if.v(4): analyzing included file ../../../../rtl/VX_define.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/interfaces/VX_alu_req_if.v Line: 4
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Info (16884): Verilog HDL info at VX_define.vh(4): analyzing included file ../../../../rtl/VX_platform.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 4
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Info (16884): Verilog HDL info at VX_platform.vh(4): analyzing included file ../../../../rtl/VX_scope.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_platform.vh(4): back to file '../../../../rtl/VX_platform.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(4): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 4
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Info (16884): Verilog HDL info at VX_define.vh(5): analyzing included file ../../../../rtl/VX_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 5
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Info (16884): Verilog HDL info at VX_config.vh(4): analyzing included file ../../../../rtl/VX_user_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_config.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_config.vh(4): back to file '../../../../rtl/VX_config.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_config.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(5): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 5
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Info (16884): Verilog HDL info at VX_define.vh(384): analyzing included file ../../../../rtl/VX_types.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 384
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Info (16884): Verilog HDL info at VX_types.vh(4): analyzing included file ../../../../rtl/VX_define.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_types.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_types.vh(4): back to file '../../../../rtl/VX_types.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_types.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(384): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 384
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Info (13230): Verilog HDL or VHDL information at VX_alu_req_if.v(4): back to file '/nethome/lcooper43/vortex-dev/hw/rtl/interfaces/VX_alu_req_if.v' File: /nethome/lcooper43/vortex-dev/hw/rtl/interfaces/VX_alu_req_if.v Line: 4
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Info (16884): Verilog HDL info at VX_csr_io_rsp_if.v(4): analyzing included file ../../../../rtl/VX_define.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/interfaces/VX_csr_io_rsp_if.v Line: 4
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Info (16884): Verilog HDL info at VX_define.vh(4): analyzing included file ../../../../rtl/VX_platform.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 4
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Info (16884): Verilog HDL info at VX_platform.vh(4): analyzing included file ../../../../rtl/VX_scope.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_platform.vh(4): back to file '../../../../rtl/VX_platform.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(4): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 4
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Info (16884): Verilog HDL info at VX_define.vh(5): analyzing included file ../../../../rtl/VX_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 5
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Info (16884): Verilog HDL info at VX_config.vh(4): analyzing included file ../../../../rtl/VX_user_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_config.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_config.vh(4): back to file '../../../../rtl/VX_config.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_config.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(5): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 5
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Info (16884): Verilog HDL info at VX_define.vh(384): analyzing included file ../../../../rtl/VX_types.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 384
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Info (16884): Verilog HDL info at VX_types.vh(4): analyzing included file ../../../../rtl/VX_define.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_types.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_types.vh(4): back to file '../../../../rtl/VX_types.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_types.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(384): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 384
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Info (13230): Verilog HDL or VHDL information at VX_csr_io_rsp_if.v(4): back to file '/nethome/lcooper43/vortex-dev/hw/rtl/interfaces/VX_csr_io_rsp_if.v' File: /nethome/lcooper43/vortex-dev/hw/rtl/interfaces/VX_csr_io_rsp_if.v Line: 4
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Info (16884): Verilog HDL info at VX_branch_ctl_if.v(4): analyzing included file ../../../../rtl/VX_define.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/interfaces/VX_branch_ctl_if.v Line: 4
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Info (16884): Verilog HDL info at VX_define.vh(4): analyzing included file ../../../../rtl/VX_platform.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 4
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Info (16884): Verilog HDL info at VX_platform.vh(4): analyzing included file ../../../../rtl/VX_scope.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_platform.vh(4): back to file '../../../../rtl/VX_platform.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(4): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 4
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Info (16884): Verilog HDL info at VX_define.vh(5): analyzing included file ../../../../rtl/VX_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 5
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Info (16884): Verilog HDL info at VX_config.vh(4): analyzing included file ../../../../rtl/VX_user_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_config.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_config.vh(4): back to file '../../../../rtl/VX_config.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_config.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(5): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 5
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Info (16884): Verilog HDL info at VX_define.vh(384): analyzing included file ../../../../rtl/VX_types.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 384
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Info (16884): Verilog HDL info at VX_types.vh(4): analyzing included file ../../../../rtl/VX_define.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_types.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_types.vh(4): back to file '../../../../rtl/VX_types.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_types.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(384): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 384
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Info (13230): Verilog HDL or VHDL information at VX_branch_ctl_if.v(4): back to file '/nethome/lcooper43/vortex-dev/hw/rtl/interfaces/VX_branch_ctl_if.v' File: /nethome/lcooper43/vortex-dev/hw/rtl/interfaces/VX_branch_ctl_if.v Line: 4
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Info (16884): Verilog HDL info at VX_cache_dram_req_if.v(4): analyzing included file /nethome/lcooper43/vortex-dev/hw/rtl/interfaces/../cache/VX_cache_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/interfaces/VX_cache_dram_req_if.v Line: 4
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Info (16884): Verilog HDL info at VX_cache_config.vh(4): analyzing included file ../../../../rtl/VX_platform.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/cache/VX_cache_config.vh Line: 4
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Info (16884): Verilog HDL info at VX_platform.vh(4): analyzing included file ../../../../rtl/VX_scope.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_platform.vh(4): back to file '../../../../rtl/VX_platform.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_cache_config.vh(4): back to file '/nethome/lcooper43/vortex-dev/hw/rtl/interfaces/../cache/VX_cache_config.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/cache/VX_cache_config.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_cache_dram_req_if.v(4): back to file '/nethome/lcooper43/vortex-dev/hw/rtl/interfaces/VX_cache_dram_req_if.v' File: /nethome/lcooper43/vortex-dev/hw/rtl/interfaces/VX_cache_dram_req_if.v Line: 4
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Info (16884): Verilog HDL info at VX_gpu_req_if.v(4): analyzing included file ../../../../rtl/VX_define.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/interfaces/VX_gpu_req_if.v Line: 4
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Info (16884): Verilog HDL info at VX_define.vh(4): analyzing included file ../../../../rtl/VX_platform.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 4
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Info (16884): Verilog HDL info at VX_platform.vh(4): analyzing included file ../../../../rtl/VX_scope.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_platform.vh(4): back to file '../../../../rtl/VX_platform.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(4): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 4
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Info (16884): Verilog HDL info at VX_define.vh(5): analyzing included file ../../../../rtl/VX_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 5
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Info (16884): Verilog HDL info at VX_config.vh(4): analyzing included file ../../../../rtl/VX_user_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_config.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_config.vh(4): back to file '../../../../rtl/VX_config.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_config.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(5): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 5
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Info (16884): Verilog HDL info at VX_define.vh(384): analyzing included file ../../../../rtl/VX_types.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 384
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Info (16884): Verilog HDL info at VX_types.vh(4): analyzing included file ../../../../rtl/VX_define.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_types.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_types.vh(4): back to file '../../../../rtl/VX_types.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_types.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(384): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 384
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Info (13230): Verilog HDL or VHDL information at VX_gpu_req_if.v(4): back to file '/nethome/lcooper43/vortex-dev/hw/rtl/interfaces/VX_gpu_req_if.v' File: /nethome/lcooper43/vortex-dev/hw/rtl/interfaces/VX_gpu_req_if.v Line: 4
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Info (16884): Verilog HDL info at VX_lsu_req_if.v(4): analyzing included file ../../../../rtl/VX_define.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/interfaces/VX_lsu_req_if.v Line: 4
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Info (16884): Verilog HDL info at VX_define.vh(4): analyzing included file ../../../../rtl/VX_platform.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 4
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Info (16884): Verilog HDL info at VX_platform.vh(4): analyzing included file ../../../../rtl/VX_scope.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_platform.vh(4): back to file '../../../../rtl/VX_platform.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(4): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 4
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Info (16884): Verilog HDL info at VX_define.vh(5): analyzing included file ../../../../rtl/VX_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 5
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Info (16884): Verilog HDL info at VX_config.vh(4): analyzing included file ../../../../rtl/VX_user_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_config.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_config.vh(4): back to file '../../../../rtl/VX_config.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_config.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(5): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 5
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Info (16884): Verilog HDL info at VX_define.vh(384): analyzing included file ../../../../rtl/VX_types.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 384
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Info (16884): Verilog HDL info at VX_types.vh(4): analyzing included file ../../../../rtl/VX_define.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_types.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_types.vh(4): back to file '../../../../rtl/VX_types.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_types.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(384): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 384
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Info (13230): Verilog HDL or VHDL information at VX_lsu_req_if.v(4): back to file '/nethome/lcooper43/vortex-dev/hw/rtl/interfaces/VX_lsu_req_if.v' File: /nethome/lcooper43/vortex-dev/hw/rtl/interfaces/VX_lsu_req_if.v Line: 4
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Info (16884): Verilog HDL info at VX_perf_cache_if.v(4): analyzing included file ../../../../rtl/VX_define.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/interfaces/VX_perf_cache_if.v Line: 4
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Info (16884): Verilog HDL info at VX_define.vh(4): analyzing included file ../../../../rtl/VX_platform.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 4
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Info (16884): Verilog HDL info at VX_platform.vh(4): analyzing included file ../../../../rtl/VX_scope.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_platform.vh(4): back to file '../../../../rtl/VX_platform.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(4): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 4
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Info (16884): Verilog HDL info at VX_define.vh(5): analyzing included file ../../../../rtl/VX_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 5
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Info (16884): Verilog HDL info at VX_config.vh(4): analyzing included file ../../../../rtl/VX_user_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_config.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_config.vh(4): back to file '../../../../rtl/VX_config.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_config.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(5): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 5
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Info (16884): Verilog HDL info at VX_define.vh(384): analyzing included file ../../../../rtl/VX_types.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 384
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Info (16884): Verilog HDL info at VX_types.vh(4): analyzing included file ../../../../rtl/VX_define.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_types.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_types.vh(4): back to file '../../../../rtl/VX_types.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_types.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(384): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 384
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Info (13230): Verilog HDL or VHDL information at VX_perf_cache_if.v(4): back to file '/nethome/lcooper43/vortex-dev/hw/rtl/interfaces/VX_perf_cache_if.v' File: /nethome/lcooper43/vortex-dev/hw/rtl/interfaces/VX_perf_cache_if.v Line: 4
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Info (16884): Verilog HDL info at VX_csr_io_req_if.v(4): analyzing included file ../../../../rtl/VX_define.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/interfaces/VX_csr_io_req_if.v Line: 4
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Info (16884): Verilog HDL info at VX_define.vh(4): analyzing included file ../../../../rtl/VX_platform.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 4
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Info (16884): Verilog HDL info at VX_platform.vh(4): analyzing included file ../../../../rtl/VX_scope.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_platform.vh(4): back to file '../../../../rtl/VX_platform.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(4): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 4
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Info (16884): Verilog HDL info at VX_define.vh(5): analyzing included file ../../../../rtl/VX_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 5
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Info (16884): Verilog HDL info at VX_config.vh(4): analyzing included file ../../../../rtl/VX_user_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_config.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_config.vh(4): back to file '../../../../rtl/VX_config.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_config.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(5): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 5
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Info (16884): Verilog HDL info at VX_define.vh(384): analyzing included file ../../../../rtl/VX_types.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 384
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Info (16884): Verilog HDL info at VX_types.vh(4): analyzing included file ../../../../rtl/VX_define.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_types.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_types.vh(4): back to file '../../../../rtl/VX_types.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_types.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(384): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 384
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Info (13230): Verilog HDL or VHDL information at VX_csr_io_req_if.v(4): back to file '/nethome/lcooper43/vortex-dev/hw/rtl/interfaces/VX_csr_io_req_if.v' File: /nethome/lcooper43/vortex-dev/hw/rtl/interfaces/VX_csr_io_req_if.v Line: 4
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Info (16884): Verilog HDL info at VX_icache_core_req_if.v(4): analyzing included file /nethome/lcooper43/vortex-dev/hw/rtl/interfaces/../cache/VX_cache_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/interfaces/VX_icache_core_req_if.v Line: 4
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Info (16884): Verilog HDL info at VX_cache_config.vh(4): analyzing included file ../../../../rtl/VX_platform.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/cache/VX_cache_config.vh Line: 4
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Info (16884): Verilog HDL info at VX_platform.vh(4): analyzing included file ../../../../rtl/VX_scope.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_platform.vh(4): back to file '../../../../rtl/VX_platform.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_cache_config.vh(4): back to file '/nethome/lcooper43/vortex-dev/hw/rtl/interfaces/../cache/VX_cache_config.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/cache/VX_cache_config.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_icache_core_req_if.v(4): back to file '/nethome/lcooper43/vortex-dev/hw/rtl/interfaces/VX_icache_core_req_if.v' File: /nethome/lcooper43/vortex-dev/hw/rtl/interfaces/VX_icache_core_req_if.v Line: 4
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Info (16884): Verilog HDL info at VX_gpr_rsp_if.v(4): analyzing included file ../../../../rtl/VX_define.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/interfaces/VX_gpr_rsp_if.v Line: 4
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Info (16884): Verilog HDL info at VX_define.vh(4): analyzing included file ../../../../rtl/VX_platform.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 4
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Info (16884): Verilog HDL info at VX_platform.vh(4): analyzing included file ../../../../rtl/VX_scope.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_platform.vh(4): back to file '../../../../rtl/VX_platform.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(4): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 4
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Info (16884): Verilog HDL info at VX_define.vh(5): analyzing included file ../../../../rtl/VX_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 5
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Info (16884): Verilog HDL info at VX_config.vh(4): analyzing included file ../../../../rtl/VX_user_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_config.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_config.vh(4): back to file '../../../../rtl/VX_config.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_config.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(5): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 5
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Info (16884): Verilog HDL info at VX_define.vh(384): analyzing included file ../../../../rtl/VX_types.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 384
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Info (16884): Verilog HDL info at VX_types.vh(4): analyzing included file ../../../../rtl/VX_define.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_types.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_types.vh(4): back to file '../../../../rtl/VX_types.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_types.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(384): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 384
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Info (13230): Verilog HDL or VHDL information at VX_gpr_rsp_if.v(4): back to file '/nethome/lcooper43/vortex-dev/hw/rtl/interfaces/VX_gpr_rsp_if.v' File: /nethome/lcooper43/vortex-dev/hw/rtl/interfaces/VX_gpr_rsp_if.v Line: 4
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Info (16884): Verilog HDL info at VX_cache_dram_rsp_if.v(4): analyzing included file /nethome/lcooper43/vortex-dev/hw/rtl/interfaces/../cache/VX_cache_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/interfaces/VX_cache_dram_rsp_if.v Line: 4
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Info (16884): Verilog HDL info at VX_cache_config.vh(4): analyzing included file ../../../../rtl/VX_platform.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/cache/VX_cache_config.vh Line: 4
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Info (16884): Verilog HDL info at VX_platform.vh(4): analyzing included file ../../../../rtl/VX_scope.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_platform.vh(4): back to file '../../../../rtl/VX_platform.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_cache_config.vh(4): back to file '/nethome/lcooper43/vortex-dev/hw/rtl/interfaces/../cache/VX_cache_config.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/cache/VX_cache_config.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_cache_dram_rsp_if.v(4): back to file '/nethome/lcooper43/vortex-dev/hw/rtl/interfaces/VX_cache_dram_rsp_if.v' File: /nethome/lcooper43/vortex-dev/hw/rtl/interfaces/VX_cache_dram_rsp_if.v Line: 4
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Info (16884): Verilog HDL info at VX_commit_if.v(4): analyzing included file ../../../../rtl/VX_define.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/interfaces/VX_commit_if.v Line: 4
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Info (16884): Verilog HDL info at VX_define.vh(4): analyzing included file ../../../../rtl/VX_platform.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 4
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Info (16884): Verilog HDL info at VX_platform.vh(4): analyzing included file ../../../../rtl/VX_scope.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_platform.vh(4): back to file '../../../../rtl/VX_platform.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(4): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 4
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Info (16884): Verilog HDL info at VX_define.vh(5): analyzing included file ../../../../rtl/VX_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 5
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Info (16884): Verilog HDL info at VX_config.vh(4): analyzing included file ../../../../rtl/VX_user_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_config.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_config.vh(4): back to file '../../../../rtl/VX_config.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_config.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(5): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 5
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Info (16884): Verilog HDL info at VX_define.vh(384): analyzing included file ../../../../rtl/VX_types.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 384
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Info (16884): Verilog HDL info at VX_types.vh(4): analyzing included file ../../../../rtl/VX_define.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_types.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_types.vh(4): back to file '../../../../rtl/VX_types.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_types.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(384): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 384
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|
Info (13230): Verilog HDL or VHDL information at VX_commit_if.v(4): back to file '/nethome/lcooper43/vortex-dev/hw/rtl/interfaces/VX_commit_if.v' File: /nethome/lcooper43/vortex-dev/hw/rtl/interfaces/VX_commit_if.v Line: 4
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Info (16884): Verilog HDL info at VX_fpu_req_if.v(4): analyzing included file ../../../../rtl/VX_define.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/interfaces/VX_fpu_req_if.v Line: 4
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Info (16884): Verilog HDL info at VX_define.vh(4): analyzing included file ../../../../rtl/VX_platform.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 4
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Info (16884): Verilog HDL info at VX_platform.vh(4): analyzing included file ../../../../rtl/VX_scope.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_platform.vh(4): back to file '../../../../rtl/VX_platform.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(4): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 4
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Info (16884): Verilog HDL info at VX_define.vh(5): analyzing included file ../../../../rtl/VX_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 5
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Info (16884): Verilog HDL info at VX_config.vh(4): analyzing included file ../../../../rtl/VX_user_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_config.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_config.vh(4): back to file '../../../../rtl/VX_config.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_config.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(5): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 5
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Info (16884): Verilog HDL info at VX_define.vh(384): analyzing included file ../../../../rtl/VX_types.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 384
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Info (16884): Verilog HDL info at VX_types.vh(4): analyzing included file ../../../../rtl/VX_define.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_types.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_types.vh(4): back to file '../../../../rtl/VX_types.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_types.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(384): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 384
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Info (13230): Verilog HDL or VHDL information at VX_fpu_req_if.v(4): back to file '/nethome/lcooper43/vortex-dev/hw/rtl/interfaces/VX_fpu_req_if.v' File: /nethome/lcooper43/vortex-dev/hw/rtl/interfaces/VX_fpu_req_if.v Line: 4
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Info (16884): Verilog HDL info at VX_dcache_core_req_if.v(4): analyzing included file /nethome/lcooper43/vortex-dev/hw/rtl/interfaces/../cache/VX_cache_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/interfaces/VX_dcache_core_req_if.v Line: 4
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Info (16884): Verilog HDL info at VX_cache_config.vh(4): analyzing included file ../../../../rtl/VX_platform.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/cache/VX_cache_config.vh Line: 4
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Info (16884): Verilog HDL info at VX_platform.vh(4): analyzing included file ../../../../rtl/VX_scope.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_platform.vh(4): back to file '../../../../rtl/VX_platform.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_cache_config.vh(4): back to file '/nethome/lcooper43/vortex-dev/hw/rtl/interfaces/../cache/VX_cache_config.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/cache/VX_cache_config.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_dcache_core_req_if.v(4): back to file '/nethome/lcooper43/vortex-dev/hw/rtl/interfaces/VX_dcache_core_req_if.v' File: /nethome/lcooper43/vortex-dev/hw/rtl/interfaces/VX_dcache_core_req_if.v Line: 4
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Info (16884): Verilog HDL info at VX_warp_ctl_if.v(4): analyzing included file ../../../../rtl/VX_define.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/interfaces/VX_warp_ctl_if.v Line: 4
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Info (16884): Verilog HDL info at VX_define.vh(4): analyzing included file ../../../../rtl/VX_platform.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 4
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Info (16884): Verilog HDL info at VX_platform.vh(4): analyzing included file ../../../../rtl/VX_scope.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_platform.vh(4): back to file '../../../../rtl/VX_platform.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(4): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 4
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Info (16884): Verilog HDL info at VX_define.vh(5): analyzing included file ../../../../rtl/VX_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 5
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Info (16884): Verilog HDL info at VX_config.vh(4): analyzing included file ../../../../rtl/VX_user_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_config.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_config.vh(4): back to file '../../../../rtl/VX_config.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_config.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(5): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 5
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Info (16884): Verilog HDL info at VX_define.vh(384): analyzing included file ../../../../rtl/VX_types.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 384
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Info (16884): Verilog HDL info at VX_types.vh(4): analyzing included file ../../../../rtl/VX_define.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_types.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_types.vh(4): back to file '../../../../rtl/VX_types.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_types.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(384): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 384
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Info (13230): Verilog HDL or VHDL information at VX_warp_ctl_if.v(4): back to file '/nethome/lcooper43/vortex-dev/hw/rtl/interfaces/VX_warp_ctl_if.v' File: /nethome/lcooper43/vortex-dev/hw/rtl/interfaces/VX_warp_ctl_if.v Line: 4
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Info (16884): Verilog HDL info at VX_fpu_to_csr_if.v(4): analyzing included file ../../../../rtl/VX_define.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/interfaces/VX_fpu_to_csr_if.v Line: 4
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Info (16884): Verilog HDL info at VX_define.vh(4): analyzing included file ../../../../rtl/VX_platform.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 4
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Info (16884): Verilog HDL info at VX_platform.vh(4): analyzing included file ../../../../rtl/VX_scope.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_platform.vh(4): back to file '../../../../rtl/VX_platform.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(4): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 4
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Info (16884): Verilog HDL info at VX_define.vh(5): analyzing included file ../../../../rtl/VX_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 5
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Info (16884): Verilog HDL info at VX_config.vh(4): analyzing included file ../../../../rtl/VX_user_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_config.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_config.vh(4): back to file '../../../../rtl/VX_config.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_config.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(5): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 5
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Info (16884): Verilog HDL info at VX_define.vh(384): analyzing included file ../../../../rtl/VX_types.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 384
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Info (16884): Verilog HDL info at VX_types.vh(4): analyzing included file ../../../../rtl/VX_define.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_types.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_types.vh(4): back to file '../../../../rtl/VX_types.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_types.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(384): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 384
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Info (13230): Verilog HDL or VHDL information at VX_fpu_to_csr_if.v(4): back to file '/nethome/lcooper43/vortex-dev/hw/rtl/interfaces/VX_fpu_to_csr_if.v' File: /nethome/lcooper43/vortex-dev/hw/rtl/interfaces/VX_fpu_to_csr_if.v Line: 4
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Info (16884): Verilog HDL info at VX_dcache_core_rsp_if.v(4): analyzing included file /nethome/lcooper43/vortex-dev/hw/rtl/interfaces/../cache/VX_cache_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/interfaces/VX_dcache_core_rsp_if.v Line: 4
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Info (16884): Verilog HDL info at VX_cache_config.vh(4): analyzing included file ../../../../rtl/VX_platform.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/cache/VX_cache_config.vh Line: 4
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Info (16884): Verilog HDL info at VX_platform.vh(4): analyzing included file ../../../../rtl/VX_scope.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_platform.vh(4): back to file '../../../../rtl/VX_platform.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_cache_config.vh(4): back to file '/nethome/lcooper43/vortex-dev/hw/rtl/interfaces/../cache/VX_cache_config.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/cache/VX_cache_config.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_dcache_core_rsp_if.v(4): back to file '/nethome/lcooper43/vortex-dev/hw/rtl/interfaces/VX_dcache_core_rsp_if.v' File: /nethome/lcooper43/vortex-dev/hw/rtl/interfaces/VX_dcache_core_rsp_if.v Line: 4
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Info (16884): Verilog HDL info at VX_decode_if.v(4): analyzing included file ../../../../rtl/VX_define.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/interfaces/VX_decode_if.v Line: 4
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Info (16884): Verilog HDL info at VX_define.vh(4): analyzing included file ../../../../rtl/VX_platform.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 4
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Info (16884): Verilog HDL info at VX_platform.vh(4): analyzing included file ../../../../rtl/VX_scope.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_platform.vh(4): back to file '../../../../rtl/VX_platform.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(4): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 4
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Info (16884): Verilog HDL info at VX_define.vh(5): analyzing included file ../../../../rtl/VX_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 5
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Info (16884): Verilog HDL info at VX_config.vh(4): analyzing included file ../../../../rtl/VX_user_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_config.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_config.vh(4): back to file '../../../../rtl/VX_config.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_config.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(5): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 5
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Info (16884): Verilog HDL info at VX_define.vh(384): analyzing included file ../../../../rtl/VX_types.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 384
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Info (16884): Verilog HDL info at VX_types.vh(4): analyzing included file ../../../../rtl/VX_define.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_types.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_types.vh(4): back to file '../../../../rtl/VX_types.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_types.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(384): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 384
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Info (13230): Verilog HDL or VHDL information at VX_decode_if.v(4): back to file '/nethome/lcooper43/vortex-dev/hw/rtl/interfaces/VX_decode_if.v' File: /nethome/lcooper43/vortex-dev/hw/rtl/interfaces/VX_decode_if.v Line: 4
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Info (16884): Verilog HDL info at VX_csr_req_if.v(4): analyzing included file ../../../../rtl/VX_define.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/interfaces/VX_csr_req_if.v Line: 4
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Info (16884): Verilog HDL info at VX_define.vh(4): analyzing included file ../../../../rtl/VX_platform.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 4
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Info (16884): Verilog HDL info at VX_platform.vh(4): analyzing included file ../../../../rtl/VX_scope.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_platform.vh(4): back to file '../../../../rtl/VX_platform.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(4): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 4
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Info (16884): Verilog HDL info at VX_define.vh(5): analyzing included file ../../../../rtl/VX_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 5
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Info (16884): Verilog HDL info at VX_config.vh(4): analyzing included file ../../../../rtl/VX_user_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_config.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_config.vh(4): back to file '../../../../rtl/VX_config.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_config.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(5): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 5
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Info (16884): Verilog HDL info at VX_define.vh(384): analyzing included file ../../../../rtl/VX_types.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 384
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Info (16884): Verilog HDL info at VX_types.vh(4): analyzing included file ../../../../rtl/VX_define.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_types.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_types.vh(4): back to file '../../../../rtl/VX_types.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_types.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(384): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 384
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Info (13230): Verilog HDL or VHDL information at VX_csr_req_if.v(4): back to file '/nethome/lcooper43/vortex-dev/hw/rtl/interfaces/VX_csr_req_if.v' File: /nethome/lcooper43/vortex-dev/hw/rtl/interfaces/VX_csr_req_if.v Line: 4
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Info (16884): Verilog HDL info at VX_ifetch_rsp_if.v(4): analyzing included file ../../../../rtl/VX_define.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/interfaces/VX_ifetch_rsp_if.v Line: 4
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Info (16884): Verilog HDL info at VX_define.vh(4): analyzing included file ../../../../rtl/VX_platform.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 4
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Info (16884): Verilog HDL info at VX_platform.vh(4): analyzing included file ../../../../rtl/VX_scope.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_platform.vh(4): back to file '../../../../rtl/VX_platform.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(4): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 4
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Info (16884): Verilog HDL info at VX_define.vh(5): analyzing included file ../../../../rtl/VX_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 5
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Info (16884): Verilog HDL info at VX_config.vh(4): analyzing included file ../../../../rtl/VX_user_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_config.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_config.vh(4): back to file '../../../../rtl/VX_config.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_config.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(5): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 5
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Info (16884): Verilog HDL info at VX_define.vh(384): analyzing included file ../../../../rtl/VX_types.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 384
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Info (16884): Verilog HDL info at VX_types.vh(4): analyzing included file ../../../../rtl/VX_define.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_types.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_types.vh(4): back to file '../../../../rtl/VX_types.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_types.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(384): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 384
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Info (13230): Verilog HDL or VHDL information at VX_ifetch_rsp_if.v(4): back to file '/nethome/lcooper43/vortex-dev/hw/rtl/interfaces/VX_ifetch_rsp_if.v' File: /nethome/lcooper43/vortex-dev/hw/rtl/interfaces/VX_ifetch_rsp_if.v Line: 4
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Info (16884): Verilog HDL info at VX_join_if.v(4): analyzing included file ../../../../rtl/VX_define.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/interfaces/VX_join_if.v Line: 4
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Info (16884): Verilog HDL info at VX_define.vh(4): analyzing included file ../../../../rtl/VX_platform.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 4
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Info (16884): Verilog HDL info at VX_platform.vh(4): analyzing included file ../../../../rtl/VX_scope.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_platform.vh(4): back to file '../../../../rtl/VX_platform.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(4): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 4
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Info (16884): Verilog HDL info at VX_define.vh(5): analyzing included file ../../../../rtl/VX_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 5
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Info (16884): Verilog HDL info at VX_config.vh(4): analyzing included file ../../../../rtl/VX_user_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_config.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_config.vh(4): back to file '../../../../rtl/VX_config.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_config.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(5): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 5
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Info (16884): Verilog HDL info at VX_define.vh(384): analyzing included file ../../../../rtl/VX_types.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 384
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Info (16884): Verilog HDL info at VX_types.vh(4): analyzing included file ../../../../rtl/VX_define.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_types.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_types.vh(4): back to file '../../../../rtl/VX_types.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_types.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(384): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 384
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Info (13230): Verilog HDL or VHDL information at VX_join_if.v(4): back to file '/nethome/lcooper43/vortex-dev/hw/rtl/interfaces/VX_join_if.v' File: /nethome/lcooper43/vortex-dev/hw/rtl/interfaces/VX_join_if.v Line: 4
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Info (16884): Verilog HDL info at VX_cmt_to_csr_if.v(4): analyzing included file ../../../../rtl/VX_define.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/interfaces/VX_cmt_to_csr_if.v Line: 4
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Info (16884): Verilog HDL info at VX_define.vh(4): analyzing included file ../../../../rtl/VX_platform.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 4
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Info (16884): Verilog HDL info at VX_platform.vh(4): analyzing included file ../../../../rtl/VX_scope.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_platform.vh(4): back to file '../../../../rtl/VX_platform.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(4): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 4
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Info (16884): Verilog HDL info at VX_define.vh(5): analyzing included file ../../../../rtl/VX_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 5
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Info (16884): Verilog HDL info at VX_config.vh(4): analyzing included file ../../../../rtl/VX_user_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_config.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_config.vh(4): back to file '../../../../rtl/VX_config.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_config.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(5): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 5
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Info (16884): Verilog HDL info at VX_define.vh(384): analyzing included file ../../../../rtl/VX_types.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 384
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Info (16884): Verilog HDL info at VX_types.vh(4): analyzing included file ../../../../rtl/VX_define.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_types.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_types.vh(4): back to file '../../../../rtl/VX_types.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_types.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(384): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 384
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Info (13230): Verilog HDL or VHDL information at VX_cmt_to_csr_if.v(4): back to file '/nethome/lcooper43/vortex-dev/hw/rtl/interfaces/VX_cmt_to_csr_if.v' File: /nethome/lcooper43/vortex-dev/hw/rtl/interfaces/VX_cmt_to_csr_if.v Line: 4
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Info (16884): Verilog HDL info at VX_wstall_if.v(4): analyzing included file ../../../../rtl/VX_define.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/interfaces/VX_wstall_if.v Line: 4
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Info (16884): Verilog HDL info at VX_define.vh(4): analyzing included file ../../../../rtl/VX_platform.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 4
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Info (16884): Verilog HDL info at VX_platform.vh(4): analyzing included file ../../../../rtl/VX_scope.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_platform.vh(4): back to file '../../../../rtl/VX_platform.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(4): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 4
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Info (16884): Verilog HDL info at VX_define.vh(5): analyzing included file ../../../../rtl/VX_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 5
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Info (16884): Verilog HDL info at VX_config.vh(4): analyzing included file ../../../../rtl/VX_user_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_config.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_config.vh(4): back to file '../../../../rtl/VX_config.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_config.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(5): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 5
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Info (16884): Verilog HDL info at VX_define.vh(384): analyzing included file ../../../../rtl/VX_types.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 384
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Info (16884): Verilog HDL info at VX_types.vh(4): analyzing included file ../../../../rtl/VX_define.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_types.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_types.vh(4): back to file '../../../../rtl/VX_types.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_types.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(384): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 384
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Info (13230): Verilog HDL or VHDL information at VX_wstall_if.v(4): back to file '/nethome/lcooper43/vortex-dev/hw/rtl/interfaces/VX_wstall_if.v' File: /nethome/lcooper43/vortex-dev/hw/rtl/interfaces/VX_wstall_if.v Line: 4
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Info (16884): Verilog HDL info at VX_ifetch_req_if.v(4): analyzing included file ../../../../rtl/VX_define.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/interfaces/VX_ifetch_req_if.v Line: 4
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Info (16884): Verilog HDL info at VX_define.vh(4): analyzing included file ../../../../rtl/VX_platform.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 4
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Info (16884): Verilog HDL info at VX_platform.vh(4): analyzing included file ../../../../rtl/VX_scope.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_platform.vh(4): back to file '../../../../rtl/VX_platform.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(4): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 4
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Info (16884): Verilog HDL info at VX_define.vh(5): analyzing included file ../../../../rtl/VX_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 5
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Info (16884): Verilog HDL info at VX_config.vh(4): analyzing included file ../../../../rtl/VX_user_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_config.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_config.vh(4): back to file '../../../../rtl/VX_config.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_config.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(5): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 5
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Info (16884): Verilog HDL info at VX_define.vh(384): analyzing included file ../../../../rtl/VX_types.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 384
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Info (16884): Verilog HDL info at VX_types.vh(4): analyzing included file ../../../../rtl/VX_define.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_types.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_types.vh(4): back to file '../../../../rtl/VX_types.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_types.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(384): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 384
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Info (13230): Verilog HDL or VHDL information at VX_ifetch_req_if.v(4): back to file '/nethome/lcooper43/vortex-dev/hw/rtl/interfaces/VX_ifetch_req_if.v' File: /nethome/lcooper43/vortex-dev/hw/rtl/interfaces/VX_ifetch_req_if.v Line: 4
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Info (16884): Verilog HDL info at VX_fpu_fpga.v(1): analyzing included file ../../../../rtl/VX_define.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/fp_cores/VX_fpu_fpga.v Line: 1
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Info (16884): Verilog HDL info at VX_define.vh(4): analyzing included file ../../../../rtl/VX_platform.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 4
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Info (16884): Verilog HDL info at VX_platform.vh(4): analyzing included file ../../../../rtl/VX_scope.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_platform.vh(4): back to file '../../../../rtl/VX_platform.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(4): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 4
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Info (16884): Verilog HDL info at VX_define.vh(5): analyzing included file ../../../../rtl/VX_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 5
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Info (16884): Verilog HDL info at VX_config.vh(4): analyzing included file ../../../../rtl/VX_user_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_config.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_config.vh(4): back to file '../../../../rtl/VX_config.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_config.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(5): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 5
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Info (16884): Verilog HDL info at VX_define.vh(384): analyzing included file ../../../../rtl/VX_types.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 384
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Info (16884): Verilog HDL info at VX_types.vh(4): analyzing included file ../../../../rtl/VX_define.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_types.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_types.vh(4): back to file '../../../../rtl/VX_types.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_types.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(384): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 384
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Info (13230): Verilog HDL or VHDL information at VX_fpu_fpga.v(1): back to file '/nethome/lcooper43/vortex-dev/hw/rtl/fp_cores/VX_fpu_fpga.v' File: /nethome/lcooper43/vortex-dev/hw/rtl/fp_cores/VX_fpu_fpga.v Line: 1
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Info (16884): Verilog HDL info at VX_fp_rounding.v(2): analyzing included file ../../../../rtl/VX_define.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/fp_cores/VX_fp_rounding.v Line: 2
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Info (16884): Verilog HDL info at VX_define.vh(4): analyzing included file ../../../../rtl/VX_platform.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 4
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Info (16884): Verilog HDL info at VX_platform.vh(4): analyzing included file ../../../../rtl/VX_scope.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_platform.vh(4): back to file '../../../../rtl/VX_platform.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(4): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 4
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Info (16884): Verilog HDL info at VX_define.vh(5): analyzing included file ../../../../rtl/VX_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 5
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Info (16884): Verilog HDL info at VX_config.vh(4): analyzing included file ../../../../rtl/VX_user_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_config.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_config.vh(4): back to file '../../../../rtl/VX_config.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_config.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(5): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 5
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Info (16884): Verilog HDL info at VX_define.vh(384): analyzing included file ../../../../rtl/VX_types.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 384
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Info (16884): Verilog HDL info at VX_types.vh(4): analyzing included file ../../../../rtl/VX_define.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_types.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_types.vh(4): back to file '../../../../rtl/VX_types.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_types.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(384): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 384
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Info (13230): Verilog HDL or VHDL information at VX_fp_rounding.v(2): back to file '/nethome/lcooper43/vortex-dev/hw/rtl/fp_cores/VX_fp_rounding.v' File: /nethome/lcooper43/vortex-dev/hw/rtl/fp_cores/VX_fp_rounding.v Line: 2
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Info (16884): Verilog HDL info at VX_fp_div.v(1): analyzing included file ../../../../rtl/VX_define.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/fp_cores/VX_fp_div.v Line: 1
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Info (16884): Verilog HDL info at VX_define.vh(4): analyzing included file ../../../../rtl/VX_platform.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 4
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Info (16884): Verilog HDL info at VX_platform.vh(4): analyzing included file ../../../../rtl/VX_scope.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_platform.vh(4): back to file '../../../../rtl/VX_platform.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(4): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 4
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Info (16884): Verilog HDL info at VX_define.vh(5): analyzing included file ../../../../rtl/VX_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 5
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Info (16884): Verilog HDL info at VX_config.vh(4): analyzing included file ../../../../rtl/VX_user_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_config.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_config.vh(4): back to file '../../../../rtl/VX_config.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_config.vh Line: 4
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|
Info (13230): Verilog HDL or VHDL information at VX_define.vh(5): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 5
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|
Info (16884): Verilog HDL info at VX_define.vh(384): analyzing included file ../../../../rtl/VX_types.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 384
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Info (16884): Verilog HDL info at VX_types.vh(4): analyzing included file ../../../../rtl/VX_define.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_types.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_types.vh(4): back to file '../../../../rtl/VX_types.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_types.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(384): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 384
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|
Info (13230): Verilog HDL or VHDL information at VX_fp_div.v(1): back to file '/nethome/lcooper43/vortex-dev/hw/rtl/fp_cores/VX_fp_div.v' File: /nethome/lcooper43/vortex-dev/hw/rtl/fp_cores/VX_fp_div.v Line: 1
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Info (16884): Verilog HDL info at VX_fp_sqrt.v(1): analyzing included file ../../../../rtl/VX_define.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/fp_cores/VX_fp_sqrt.v Line: 1
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Info (16884): Verilog HDL info at VX_define.vh(4): analyzing included file ../../../../rtl/VX_platform.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 4
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Info (16884): Verilog HDL info at VX_platform.vh(4): analyzing included file ../../../../rtl/VX_scope.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_platform.vh(4): back to file '../../../../rtl/VX_platform.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(4): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 4
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Info (16884): Verilog HDL info at VX_define.vh(5): analyzing included file ../../../../rtl/VX_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 5
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Info (16884): Verilog HDL info at VX_config.vh(4): analyzing included file ../../../../rtl/VX_user_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_config.vh Line: 4
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|
Info (13230): Verilog HDL or VHDL information at VX_config.vh(4): back to file '../../../../rtl/VX_config.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_config.vh Line: 4
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|
Info (13230): Verilog HDL or VHDL information at VX_define.vh(5): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 5
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|
Info (16884): Verilog HDL info at VX_define.vh(384): analyzing included file ../../../../rtl/VX_types.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 384
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Info (16884): Verilog HDL info at VX_types.vh(4): analyzing included file ../../../../rtl/VX_define.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_types.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_types.vh(4): back to file '../../../../rtl/VX_types.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_types.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(384): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 384
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|
Info (13230): Verilog HDL or VHDL information at VX_fp_sqrt.v(1): back to file '/nethome/lcooper43/vortex-dev/hw/rtl/fp_cores/VX_fp_sqrt.v' File: /nethome/lcooper43/vortex-dev/hw/rtl/fp_cores/VX_fp_sqrt.v Line: 1
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Info (16884): Verilog HDL info at VX_fp_type.v(2): analyzing included file ../../../../rtl/VX_define.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/fp_cores/VX_fp_type.v Line: 2
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Info (16884): Verilog HDL info at VX_define.vh(4): analyzing included file ../../../../rtl/VX_platform.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 4
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Info (16884): Verilog HDL info at VX_platform.vh(4): analyzing included file ../../../../rtl/VX_scope.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_platform.vh(4): back to file '../../../../rtl/VX_platform.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(4): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 4
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|
Info (16884): Verilog HDL info at VX_define.vh(5): analyzing included file ../../../../rtl/VX_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 5
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Info (16884): Verilog HDL info at VX_config.vh(4): analyzing included file ../../../../rtl/VX_user_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_config.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_config.vh(4): back to file '../../../../rtl/VX_config.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_config.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(5): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 5
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|
Info (16884): Verilog HDL info at VX_define.vh(384): analyzing included file ../../../../rtl/VX_types.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 384
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Info (16884): Verilog HDL info at VX_types.vh(4): analyzing included file ../../../../rtl/VX_define.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_types.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_types.vh(4): back to file '../../../../rtl/VX_types.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_types.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(384): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 384
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|
Info (13230): Verilog HDL or VHDL information at VX_fp_type.v(2): back to file '/nethome/lcooper43/vortex-dev/hw/rtl/fp_cores/VX_fp_type.v' File: /nethome/lcooper43/vortex-dev/hw/rtl/fp_cores/VX_fp_type.v Line: 2
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Info (16884): Verilog HDL info at VX_fp_fma.v(1): analyzing included file ../../../../rtl/VX_define.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/fp_cores/VX_fp_fma.v Line: 1
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Info (16884): Verilog HDL info at VX_define.vh(4): analyzing included file ../../../../rtl/VX_platform.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 4
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Info (16884): Verilog HDL info at VX_platform.vh(4): analyzing included file ../../../../rtl/VX_scope.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_platform.vh(4): back to file '../../../../rtl/VX_platform.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(4): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 4
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Info (16884): Verilog HDL info at VX_define.vh(5): analyzing included file ../../../../rtl/VX_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 5
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Info (16884): Verilog HDL info at VX_config.vh(4): analyzing included file ../../../../rtl/VX_user_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_config.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_config.vh(4): back to file '../../../../rtl/VX_config.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_config.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(5): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 5
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Info (16884): Verilog HDL info at VX_define.vh(384): analyzing included file ../../../../rtl/VX_types.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 384
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Info (16884): Verilog HDL info at VX_types.vh(4): analyzing included file ../../../../rtl/VX_define.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_types.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_types.vh(4): back to file '../../../../rtl/VX_types.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_types.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(384): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 384
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Info (13230): Verilog HDL or VHDL information at VX_fp_fma.v(1): back to file '/nethome/lcooper43/vortex-dev/hw/rtl/fp_cores/VX_fp_fma.v' File: /nethome/lcooper43/vortex-dev/hw/rtl/fp_cores/VX_fp_fma.v Line: 1
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Info (16884): Verilog HDL info at VX_fp_cvt.v(1): analyzing included file ../../../../rtl/VX_define.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/fp_cores/VX_fp_cvt.v Line: 1
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Info (16884): Verilog HDL info at VX_define.vh(4): analyzing included file ../../../../rtl/VX_platform.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 4
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Info (16884): Verilog HDL info at VX_platform.vh(4): analyzing included file ../../../../rtl/VX_scope.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_platform.vh(4): back to file '../../../../rtl/VX_platform.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(4): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 4
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Info (16884): Verilog HDL info at VX_define.vh(5): analyzing included file ../../../../rtl/VX_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 5
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Info (16884): Verilog HDL info at VX_config.vh(4): analyzing included file ../../../../rtl/VX_user_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_config.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_config.vh(4): back to file '../../../../rtl/VX_config.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_config.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(5): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 5
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Info (16884): Verilog HDL info at VX_define.vh(384): analyzing included file ../../../../rtl/VX_types.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 384
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Info (16884): Verilog HDL info at VX_types.vh(4): analyzing included file ../../../../rtl/VX_define.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_types.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_types.vh(4): back to file '../../../../rtl/VX_types.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_types.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(384): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 384
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Info (13230): Verilog HDL or VHDL information at VX_fp_cvt.v(1): back to file '/nethome/lcooper43/vortex-dev/hw/rtl/fp_cores/VX_fp_cvt.v' File: /nethome/lcooper43/vortex-dev/hw/rtl/fp_cores/VX_fp_cvt.v Line: 1
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Info (16884): Verilog HDL info at VX_fp_ncomp.v(1): analyzing included file ../../../../rtl/VX_define.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/fp_cores/VX_fp_ncomp.v Line: 1
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Info (16884): Verilog HDL info at VX_define.vh(4): analyzing included file ../../../../rtl/VX_platform.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 4
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Info (16884): Verilog HDL info at VX_platform.vh(4): analyzing included file ../../../../rtl/VX_scope.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_platform.vh(4): back to file '../../../../rtl/VX_platform.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(4): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 4
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Info (16884): Verilog HDL info at VX_define.vh(5): analyzing included file ../../../../rtl/VX_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 5
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Info (16884): Verilog HDL info at VX_config.vh(4): analyzing included file ../../../../rtl/VX_user_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_config.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_config.vh(4): back to file '../../../../rtl/VX_config.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_config.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(5): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 5
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Info (16884): Verilog HDL info at VX_define.vh(384): analyzing included file ../../../../rtl/VX_types.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 384
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Info (16884): Verilog HDL info at VX_types.vh(4): analyzing included file ../../../../rtl/VX_define.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_types.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_types.vh(4): back to file '../../../../rtl/VX_types.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_types.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(384): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 384
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Info (13230): Verilog HDL or VHDL information at VX_fp_ncomp.v(1): back to file '/nethome/lcooper43/vortex-dev/hw/rtl/fp_cores/VX_fp_ncomp.v' File: /nethome/lcooper43/vortex-dev/hw/rtl/fp_cores/VX_fp_ncomp.v Line: 1
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Info (16884): Verilog HDL info at VX_bank.v(1): analyzing included file /nethome/lcooper43/vortex-dev/hw/rtl/cache/VX_cache_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/cache/VX_bank.v Line: 1
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Info (16884): Verilog HDL info at VX_cache_config.vh(4): analyzing included file ../../../../rtl/VX_platform.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/cache/VX_cache_config.vh Line: 4
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Info (16884): Verilog HDL info at VX_platform.vh(4): analyzing included file ../../../../rtl/VX_scope.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_platform.vh(4): back to file '../../../../rtl/VX_platform.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_cache_config.vh(4): back to file '/nethome/lcooper43/vortex-dev/hw/rtl/interfaces/../cache/VX_cache_config.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/cache/VX_cache_config.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_bank.v(1): back to file '/nethome/lcooper43/vortex-dev/hw/rtl/cache/VX_bank.v' File: /nethome/lcooper43/vortex-dev/hw/rtl/cache/VX_bank.v Line: 1
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Info (16884): Verilog HDL info at VX_shared_mem.v(1): analyzing included file /nethome/lcooper43/vortex-dev/hw/rtl/cache/VX_cache_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/cache/VX_shared_mem.v Line: 1
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Info (16884): Verilog HDL info at VX_cache_config.vh(4): analyzing included file ../../../../rtl/VX_platform.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/cache/VX_cache_config.vh Line: 4
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Info (16884): Verilog HDL info at VX_platform.vh(4): analyzing included file ../../../../rtl/VX_scope.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_platform.vh(4): back to file '../../../../rtl/VX_platform.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_cache_config.vh(4): back to file '/nethome/lcooper43/vortex-dev/hw/rtl/interfaces/../cache/VX_cache_config.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/cache/VX_cache_config.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_shared_mem.v(1): back to file '/nethome/lcooper43/vortex-dev/hw/rtl/cache/VX_shared_mem.v' File: /nethome/lcooper43/vortex-dev/hw/rtl/cache/VX_shared_mem.v Line: 1
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Info (16884): Verilog HDL info at VX_cache_core_rsp_merge.v(1): analyzing included file /nethome/lcooper43/vortex-dev/hw/rtl/cache/VX_cache_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/cache/VX_cache_core_rsp_merge.v Line: 1
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Info (16884): Verilog HDL info at VX_cache_config.vh(4): analyzing included file ../../../../rtl/VX_platform.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/cache/VX_cache_config.vh Line: 4
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Info (16884): Verilog HDL info at VX_platform.vh(4): analyzing included file ../../../../rtl/VX_scope.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_platform.vh(4): back to file '../../../../rtl/VX_platform.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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|
Info (13230): Verilog HDL or VHDL information at VX_cache_config.vh(4): back to file '/nethome/lcooper43/vortex-dev/hw/rtl/interfaces/../cache/VX_cache_config.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/cache/VX_cache_config.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_cache_core_rsp_merge.v(1): back to file '/nethome/lcooper43/vortex-dev/hw/rtl/cache/VX_cache_core_rsp_merge.v' File: /nethome/lcooper43/vortex-dev/hw/rtl/cache/VX_cache_core_rsp_merge.v Line: 1
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Info (16884): Verilog HDL info at VX_tag_access.v(1): analyzing included file /nethome/lcooper43/vortex-dev/hw/rtl/cache/VX_cache_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/cache/VX_tag_access.v Line: 1
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Info (16884): Verilog HDL info at VX_cache_config.vh(4): analyzing included file ../../../../rtl/VX_platform.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/cache/VX_cache_config.vh Line: 4
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Info (16884): Verilog HDL info at VX_platform.vh(4): analyzing included file ../../../../rtl/VX_scope.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_platform.vh(4): back to file '../../../../rtl/VX_platform.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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|
Info (13230): Verilog HDL or VHDL information at VX_cache_config.vh(4): back to file '/nethome/lcooper43/vortex-dev/hw/rtl/interfaces/../cache/VX_cache_config.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/cache/VX_cache_config.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_tag_access.v(1): back to file '/nethome/lcooper43/vortex-dev/hw/rtl/cache/VX_tag_access.v' File: /nethome/lcooper43/vortex-dev/hw/rtl/cache/VX_tag_access.v Line: 1
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Info (16884): Verilog HDL info at VX_data_access.v(1): analyzing included file /nethome/lcooper43/vortex-dev/hw/rtl/cache/VX_cache_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/cache/VX_data_access.v Line: 1
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Info (16884): Verilog HDL info at VX_cache_config.vh(4): analyzing included file ../../../../rtl/VX_platform.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/cache/VX_cache_config.vh Line: 4
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Info (16884): Verilog HDL info at VX_platform.vh(4): analyzing included file ../../../../rtl/VX_scope.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_platform.vh(4): back to file '../../../../rtl/VX_platform.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_cache_config.vh(4): back to file '/nethome/lcooper43/vortex-dev/hw/rtl/interfaces/../cache/VX_cache_config.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/cache/VX_cache_config.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_data_access.v(1): back to file '/nethome/lcooper43/vortex-dev/hw/rtl/cache/VX_data_access.v' File: /nethome/lcooper43/vortex-dev/hw/rtl/cache/VX_data_access.v Line: 1
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Info (16884): Verilog HDL info at VX_cache_core_req_bank_sel.v(1): analyzing included file /nethome/lcooper43/vortex-dev/hw/rtl/cache/VX_cache_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/cache/VX_cache_core_req_bank_sel.v Line: 1
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Info (16884): Verilog HDL info at VX_cache_config.vh(4): analyzing included file ../../../../rtl/VX_platform.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/cache/VX_cache_config.vh Line: 4
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Info (16884): Verilog HDL info at VX_platform.vh(4): analyzing included file ../../../../rtl/VX_scope.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_platform.vh(4): back to file '../../../../rtl/VX_platform.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_cache_config.vh(4): back to file '/nethome/lcooper43/vortex-dev/hw/rtl/interfaces/../cache/VX_cache_config.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/cache/VX_cache_config.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_cache_core_req_bank_sel.v(1): back to file '/nethome/lcooper43/vortex-dev/hw/rtl/cache/VX_cache_core_req_bank_sel.v' File: /nethome/lcooper43/vortex-dev/hw/rtl/cache/VX_cache_core_req_bank_sel.v Line: 1
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Info (16884): Verilog HDL info at VX_miss_resrv.v(1): analyzing included file /nethome/lcooper43/vortex-dev/hw/rtl/cache/VX_cache_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/cache/VX_miss_resrv.v Line: 1
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Info (16884): Verilog HDL info at VX_cache_config.vh(4): analyzing included file ../../../../rtl/VX_platform.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/cache/VX_cache_config.vh Line: 4
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Info (16884): Verilog HDL info at VX_platform.vh(4): analyzing included file ../../../../rtl/VX_scope.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_platform.vh(4): back to file '../../../../rtl/VX_platform.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_cache_config.vh(4): back to file '/nethome/lcooper43/vortex-dev/hw/rtl/interfaces/../cache/VX_cache_config.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/cache/VX_cache_config.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_miss_resrv.v(1): back to file '/nethome/lcooper43/vortex-dev/hw/rtl/cache/VX_miss_resrv.v' File: /nethome/lcooper43/vortex-dev/hw/rtl/cache/VX_miss_resrv.v Line: 1
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Info (16884): Verilog HDL info at VX_cache.v(1): analyzing included file /nethome/lcooper43/vortex-dev/hw/rtl/cache/VX_cache_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/cache/VX_cache.v Line: 1
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Info (16884): Verilog HDL info at VX_cache_config.vh(4): analyzing included file ../../../../rtl/VX_platform.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/cache/VX_cache_config.vh Line: 4
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Info (16884): Verilog HDL info at VX_platform.vh(4): analyzing included file ../../../../rtl/VX_scope.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_platform.vh(4): back to file '../../../../rtl/VX_platform.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_cache_config.vh(4): back to file '/nethome/lcooper43/vortex-dev/hw/rtl/interfaces/../cache/VX_cache_config.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/cache/VX_cache_config.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_cache.v(1): back to file '/nethome/lcooper43/vortex-dev/hw/rtl/cache/VX_cache.v' File: /nethome/lcooper43/vortex-dev/hw/rtl/cache/VX_cache.v Line: 1
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Info (16884): Verilog HDL info at VX_flush_ctrl.v(1): analyzing included file /nethome/lcooper43/vortex-dev/hw/rtl/cache/VX_cache_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/cache/VX_flush_ctrl.v Line: 1
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Info (16884): Verilog HDL info at VX_cache_config.vh(4): analyzing included file ../../../../rtl/VX_platform.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/cache/VX_cache_config.vh Line: 4
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Info (16884): Verilog HDL info at VX_platform.vh(4): analyzing included file ../../../../rtl/VX_scope.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_platform.vh(4): back to file '../../../../rtl/VX_platform.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_cache_config.vh(4): back to file '/nethome/lcooper43/vortex-dev/hw/rtl/interfaces/../cache/VX_cache_config.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/cache/VX_cache_config.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_flush_ctrl.v(1): back to file '/nethome/lcooper43/vortex-dev/hw/rtl/cache/VX_flush_ctrl.v' File: /nethome/lcooper43/vortex-dev/hw/rtl/cache/VX_flush_ctrl.v Line: 1
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Info (16884): Verilog HDL info at VX_fpu_unit.v(1): analyzing included file /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_fpu_unit.v Line: 1
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Info (16884): Verilog HDL info at VX_define.vh(4): analyzing included file ../../../../rtl/VX_platform.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 4
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Info (16884): Verilog HDL info at VX_platform.vh(4): analyzing included file ../../../../rtl/VX_scope.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_platform.vh(4): back to file '../../../../rtl/VX_platform.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(4): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 4
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Info (16884): Verilog HDL info at VX_define.vh(5): analyzing included file ../../../../rtl/VX_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 5
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Info (16884): Verilog HDL info at VX_config.vh(4): analyzing included file ../../../../rtl/VX_user_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_config.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_config.vh(4): back to file '../../../../rtl/VX_config.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_config.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(5): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 5
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Info (16884): Verilog HDL info at VX_define.vh(384): analyzing included file ../../../../rtl/VX_types.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 384
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Info (16884): Verilog HDL info at VX_types.vh(4): analyzing included file ../../../../rtl/VX_define.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_types.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_types.vh(4): back to file '../../../../rtl/VX_types.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_types.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(384): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 384
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Info (13230): Verilog HDL or VHDL information at VX_fpu_unit.v(1): back to file '/nethome/lcooper43/vortex-dev/hw/rtl/VX_fpu_unit.v' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_fpu_unit.v Line: 1
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Info (16884): Verilog HDL info at VX_gpr_ram_f.v(1): analyzing included file /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_gpr_ram_f.v Line: 1
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Info (16884): Verilog HDL info at VX_define.vh(4): analyzing included file ../../../../rtl/VX_platform.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 4
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Info (16884): Verilog HDL info at VX_platform.vh(4): analyzing included file ../../../../rtl/VX_scope.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_platform.vh(4): back to file '../../../../rtl/VX_platform.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(4): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 4
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Info (16884): Verilog HDL info at VX_define.vh(5): analyzing included file ../../../../rtl/VX_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 5
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Info (16884): Verilog HDL info at VX_config.vh(4): analyzing included file ../../../../rtl/VX_user_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_config.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_config.vh(4): back to file '../../../../rtl/VX_config.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_config.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(5): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 5
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Info (16884): Verilog HDL info at VX_define.vh(384): analyzing included file ../../../../rtl/VX_types.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 384
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Info (16884): Verilog HDL info at VX_types.vh(4): analyzing included file ../../../../rtl/VX_define.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_types.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_types.vh(4): back to file '../../../../rtl/VX_types.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_types.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(384): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 384
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Info (13230): Verilog HDL or VHDL information at VX_gpr_ram_f.v(1): back to file '/nethome/lcooper43/vortex-dev/hw/rtl/VX_gpr_ram_f.v' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_gpr_ram_f.v Line: 1
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Info (16884): Verilog HDL info at VX_csr_data.v(1): analyzing included file /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_csr_data.v Line: 1
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Info (16884): Verilog HDL info at VX_define.vh(4): analyzing included file ../../../../rtl/VX_platform.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 4
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Info (16884): Verilog HDL info at VX_platform.vh(4): analyzing included file ../../../../rtl/VX_scope.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_platform.vh(4): back to file '../../../../rtl/VX_platform.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(4): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 4
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Info (16884): Verilog HDL info at VX_define.vh(5): analyzing included file ../../../../rtl/VX_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 5
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Info (16884): Verilog HDL info at VX_config.vh(4): analyzing included file ../../../../rtl/VX_user_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_config.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_config.vh(4): back to file '../../../../rtl/VX_config.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_config.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(5): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 5
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Info (16884): Verilog HDL info at VX_define.vh(384): analyzing included file ../../../../rtl/VX_types.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 384
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Info (16884): Verilog HDL info at VX_types.vh(4): analyzing included file ../../../../rtl/VX_define.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_types.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_types.vh(4): back to file '../../../../rtl/VX_types.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_types.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(384): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 384
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Info (13230): Verilog HDL or VHDL information at VX_csr_data.v(1): back to file '/nethome/lcooper43/vortex-dev/hw/rtl/VX_csr_data.v' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_csr_data.v Line: 1
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Info (16884): Verilog HDL info at VX_alu_unit.v(1): analyzing included file /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_alu_unit.v Line: 1
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Info (16884): Verilog HDL info at VX_define.vh(4): analyzing included file ../../../../rtl/VX_platform.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 4
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Info (16884): Verilog HDL info at VX_platform.vh(4): analyzing included file ../../../../rtl/VX_scope.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_platform.vh(4): back to file '../../../../rtl/VX_platform.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(4): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 4
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Info (16884): Verilog HDL info at VX_define.vh(5): analyzing included file ../../../../rtl/VX_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 5
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Info (16884): Verilog HDL info at VX_config.vh(4): analyzing included file ../../../../rtl/VX_user_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_config.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_config.vh(4): back to file '../../../../rtl/VX_config.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_config.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(5): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 5
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Info (16884): Verilog HDL info at VX_define.vh(384): analyzing included file ../../../../rtl/VX_types.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 384
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Info (16884): Verilog HDL info at VX_types.vh(4): analyzing included file ../../../../rtl/VX_define.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_types.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_types.vh(4): back to file '../../../../rtl/VX_types.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_types.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(384): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 384
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Info (13230): Verilog HDL or VHDL information at VX_alu_unit.v(1): back to file '/nethome/lcooper43/vortex-dev/hw/rtl/VX_alu_unit.v' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_alu_unit.v Line: 1
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Info (16884): Verilog HDL info at VX_lsu_unit.v(1): analyzing included file /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_lsu_unit.v Line: 1
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Info (16884): Verilog HDL info at VX_define.vh(4): analyzing included file ../../../../rtl/VX_platform.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 4
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Info (16884): Verilog HDL info at VX_platform.vh(4): analyzing included file ../../../../rtl/VX_scope.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_platform.vh(4): back to file '../../../../rtl/VX_platform.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(4): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 4
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Info (16884): Verilog HDL info at VX_define.vh(5): analyzing included file ../../../../rtl/VX_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 5
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Info (16884): Verilog HDL info at VX_config.vh(4): analyzing included file ../../../../rtl/VX_user_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_config.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_config.vh(4): back to file '../../../../rtl/VX_config.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_config.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(5): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 5
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|
Info (16884): Verilog HDL info at VX_define.vh(384): analyzing included file ../../../../rtl/VX_types.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 384
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Info (16884): Verilog HDL info at VX_types.vh(4): analyzing included file ../../../../rtl/VX_define.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_types.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_types.vh(4): back to file '../../../../rtl/VX_types.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_types.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(384): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 384
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|
Info (13230): Verilog HDL or VHDL information at VX_lsu_unit.v(1): back to file '/nethome/lcooper43/vortex-dev/hw/rtl/VX_lsu_unit.v' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_lsu_unit.v Line: 1
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Info (16884): Verilog HDL info at VX_cluster.v(1): analyzing included file /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_cluster.v Line: 1
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Info (16884): Verilog HDL info at VX_define.vh(4): analyzing included file ../../../../rtl/VX_platform.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 4
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Info (16884): Verilog HDL info at VX_platform.vh(4): analyzing included file ../../../../rtl/VX_scope.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_platform.vh(4): back to file '../../../../rtl/VX_platform.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(4): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 4
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|
Info (16884): Verilog HDL info at VX_define.vh(5): analyzing included file ../../../../rtl/VX_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 5
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Info (16884): Verilog HDL info at VX_config.vh(4): analyzing included file ../../../../rtl/VX_user_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_config.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_config.vh(4): back to file '../../../../rtl/VX_config.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_config.vh Line: 4
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|
Info (13230): Verilog HDL or VHDL information at VX_define.vh(5): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 5
|
|
Info (16884): Verilog HDL info at VX_define.vh(384): analyzing included file ../../../../rtl/VX_types.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 384
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Info (16884): Verilog HDL info at VX_types.vh(4): analyzing included file ../../../../rtl/VX_define.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_types.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_types.vh(4): back to file '../../../../rtl/VX_types.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_types.vh Line: 4
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|
Info (13230): Verilog HDL or VHDL information at VX_define.vh(384): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 384
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|
Info (13230): Verilog HDL or VHDL information at VX_cluster.v(1): back to file '/nethome/lcooper43/vortex-dev/hw/rtl/VX_cluster.v' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_cluster.v Line: 1
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Info (16884): Verilog HDL info at VX_ibuffer.v(1): analyzing included file /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_ibuffer.v Line: 1
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Info (16884): Verilog HDL info at VX_define.vh(4): analyzing included file ../../../../rtl/VX_platform.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 4
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Info (16884): Verilog HDL info at VX_platform.vh(4): analyzing included file ../../../../rtl/VX_scope.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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|
Info (13230): Verilog HDL or VHDL information at VX_platform.vh(4): back to file '../../../../rtl/VX_platform.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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|
Info (13230): Verilog HDL or VHDL information at VX_define.vh(4): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 4
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|
Info (16884): Verilog HDL info at VX_define.vh(5): analyzing included file ../../../../rtl/VX_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 5
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Info (16884): Verilog HDL info at VX_config.vh(4): analyzing included file ../../../../rtl/VX_user_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_config.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_config.vh(4): back to file '../../../../rtl/VX_config.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_config.vh Line: 4
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|
Info (13230): Verilog HDL or VHDL information at VX_define.vh(5): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 5
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|
Info (16884): Verilog HDL info at VX_define.vh(384): analyzing included file ../../../../rtl/VX_types.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 384
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Info (16884): Verilog HDL info at VX_types.vh(4): analyzing included file ../../../../rtl/VX_define.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_types.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_types.vh(4): back to file '../../../../rtl/VX_types.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_types.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(384): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 384
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|
Info (13230): Verilog HDL or VHDL information at VX_ibuffer.v(1): back to file '/nethome/lcooper43/vortex-dev/hw/rtl/VX_ibuffer.v' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_ibuffer.v Line: 1
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Info (16884): Verilog HDL info at VX_gpu_unit.v(1): analyzing included file /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_gpu_unit.v Line: 1
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Info (16884): Verilog HDL info at VX_define.vh(4): analyzing included file ../../../../rtl/VX_platform.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 4
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|
Info (16884): Verilog HDL info at VX_platform.vh(4): analyzing included file ../../../../rtl/VX_scope.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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|
Info (13230): Verilog HDL or VHDL information at VX_platform.vh(4): back to file '../../../../rtl/VX_platform.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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|
Info (13230): Verilog HDL or VHDL information at VX_define.vh(4): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 4
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|
Info (16884): Verilog HDL info at VX_define.vh(5): analyzing included file ../../../../rtl/VX_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 5
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|
Info (16884): Verilog HDL info at VX_config.vh(4): analyzing included file ../../../../rtl/VX_user_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_config.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_config.vh(4): back to file '../../../../rtl/VX_config.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_config.vh Line: 4
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|
Info (13230): Verilog HDL or VHDL information at VX_define.vh(5): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 5
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|
Info (16884): Verilog HDL info at VX_define.vh(384): analyzing included file ../../../../rtl/VX_types.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 384
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Info (16884): Verilog HDL info at VX_types.vh(4): analyzing included file ../../../../rtl/VX_define.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_types.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_types.vh(4): back to file '../../../../rtl/VX_types.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_types.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(384): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 384
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|
Info (13230): Verilog HDL or VHDL information at VX_gpu_unit.v(1): back to file '/nethome/lcooper43/vortex-dev/hw/rtl/VX_gpu_unit.v' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_gpu_unit.v Line: 1
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Info (16884): Verilog HDL info at VX_csr_arb.v(1): analyzing included file /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_csr_arb.v Line: 1
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|
Info (16884): Verilog HDL info at VX_define.vh(4): analyzing included file ../../../../rtl/VX_platform.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 4
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Info (16884): Verilog HDL info at VX_platform.vh(4): analyzing included file ../../../../rtl/VX_scope.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_platform.vh(4): back to file '../../../../rtl/VX_platform.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(4): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 4
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Info (16884): Verilog HDL info at VX_define.vh(5): analyzing included file ../../../../rtl/VX_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 5
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Info (16884): Verilog HDL info at VX_config.vh(4): analyzing included file ../../../../rtl/VX_user_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_config.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_config.vh(4): back to file '../../../../rtl/VX_config.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_config.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(5): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 5
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Info (16884): Verilog HDL info at VX_define.vh(384): analyzing included file ../../../../rtl/VX_types.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 384
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Info (16884): Verilog HDL info at VX_types.vh(4): analyzing included file ../../../../rtl/VX_define.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_types.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_types.vh(4): back to file '../../../../rtl/VX_types.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_types.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(384): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 384
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Info (13230): Verilog HDL or VHDL information at VX_csr_arb.v(1): back to file '/nethome/lcooper43/vortex-dev/hw/rtl/VX_csr_arb.v' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_csr_arb.v Line: 1
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Info (16884): Verilog HDL info at VX_muldiv.v(1): analyzing included file /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_muldiv.v Line: 1
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Info (16884): Verilog HDL info at VX_define.vh(4): analyzing included file ../../../../rtl/VX_platform.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 4
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Info (16884): Verilog HDL info at VX_platform.vh(4): analyzing included file ../../../../rtl/VX_scope.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_platform.vh(4): back to file '../../../../rtl/VX_platform.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(4): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 4
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Info (16884): Verilog HDL info at VX_define.vh(5): analyzing included file ../../../../rtl/VX_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 5
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Info (16884): Verilog HDL info at VX_config.vh(4): analyzing included file ../../../../rtl/VX_user_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_config.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_config.vh(4): back to file '../../../../rtl/VX_config.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_config.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(5): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 5
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Info (16884): Verilog HDL info at VX_define.vh(384): analyzing included file ../../../../rtl/VX_types.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 384
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Info (16884): Verilog HDL info at VX_types.vh(4): analyzing included file ../../../../rtl/VX_define.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_types.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_types.vh(4): back to file '../../../../rtl/VX_types.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_types.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(384): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 384
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Info (13230): Verilog HDL or VHDL information at VX_muldiv.v(1): back to file '/nethome/lcooper43/vortex-dev/hw/rtl/VX_muldiv.v' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_muldiv.v Line: 1
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Info (16884): Verilog HDL info at VX_warp_sched.v(1): analyzing included file /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_warp_sched.v Line: 1
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Info (16884): Verilog HDL info at VX_define.vh(4): analyzing included file ../../../../rtl/VX_platform.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 4
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Info (16884): Verilog HDL info at VX_platform.vh(4): analyzing included file ../../../../rtl/VX_scope.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_platform.vh(4): back to file '../../../../rtl/VX_platform.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(4): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 4
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Info (16884): Verilog HDL info at VX_define.vh(5): analyzing included file ../../../../rtl/VX_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 5
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Info (16884): Verilog HDL info at VX_config.vh(4): analyzing included file ../../../../rtl/VX_user_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_config.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_config.vh(4): back to file '../../../../rtl/VX_config.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_config.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(5): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 5
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Info (16884): Verilog HDL info at VX_define.vh(384): analyzing included file ../../../../rtl/VX_types.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 384
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Info (16884): Verilog HDL info at VX_types.vh(4): analyzing included file ../../../../rtl/VX_define.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_types.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_types.vh(4): back to file '../../../../rtl/VX_types.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_types.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(384): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 384
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Info (13230): Verilog HDL or VHDL information at VX_warp_sched.v(1): back to file '/nethome/lcooper43/vortex-dev/hw/rtl/VX_warp_sched.v' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_warp_sched.v Line: 1
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Info (16884): Verilog HDL info at VX_csr_unit.v(1): analyzing included file /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_csr_unit.v Line: 1
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Info (16884): Verilog HDL info at VX_define.vh(4): analyzing included file ../../../../rtl/VX_platform.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 4
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Info (16884): Verilog HDL info at VX_platform.vh(4): analyzing included file ../../../../rtl/VX_scope.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_platform.vh(4): back to file '../../../../rtl/VX_platform.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(4): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 4
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Info (16884): Verilog HDL info at VX_define.vh(5): analyzing included file ../../../../rtl/VX_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 5
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Info (16884): Verilog HDL info at VX_config.vh(4): analyzing included file ../../../../rtl/VX_user_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_config.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_config.vh(4): back to file '../../../../rtl/VX_config.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_config.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(5): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 5
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|
Info (16884): Verilog HDL info at VX_define.vh(384): analyzing included file ../../../../rtl/VX_types.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 384
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Info (16884): Verilog HDL info at VX_types.vh(4): analyzing included file ../../../../rtl/VX_define.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_types.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_types.vh(4): back to file '../../../../rtl/VX_types.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_types.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(384): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 384
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Info (13230): Verilog HDL or VHDL information at VX_csr_unit.v(1): back to file '/nethome/lcooper43/vortex-dev/hw/rtl/VX_csr_unit.v' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_csr_unit.v Line: 1
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Info (16884): Verilog HDL info at VX_fetch.v(1): analyzing included file /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_fetch.v Line: 1
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Info (16884): Verilog HDL info at VX_define.vh(4): analyzing included file ../../../../rtl/VX_platform.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 4
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Info (16884): Verilog HDL info at VX_platform.vh(4): analyzing included file ../../../../rtl/VX_scope.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_platform.vh(4): back to file '../../../../rtl/VX_platform.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(4): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 4
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|
Info (16884): Verilog HDL info at VX_define.vh(5): analyzing included file ../../../../rtl/VX_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 5
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Info (16884): Verilog HDL info at VX_config.vh(4): analyzing included file ../../../../rtl/VX_user_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_config.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_config.vh(4): back to file '../../../../rtl/VX_config.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_config.vh Line: 4
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|
Info (13230): Verilog HDL or VHDL information at VX_define.vh(5): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 5
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|
Info (16884): Verilog HDL info at VX_define.vh(384): analyzing included file ../../../../rtl/VX_types.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 384
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Info (16884): Verilog HDL info at VX_types.vh(4): analyzing included file ../../../../rtl/VX_define.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_types.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_types.vh(4): back to file '../../../../rtl/VX_types.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_types.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(384): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 384
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|
Info (13230): Verilog HDL or VHDL information at VX_fetch.v(1): back to file '/nethome/lcooper43/vortex-dev/hw/rtl/VX_fetch.v' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_fetch.v Line: 1
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Info (16884): Verilog HDL info at VX_scoreboard.v(1): analyzing included file /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_scoreboard.v Line: 1
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Info (16884): Verilog HDL info at VX_define.vh(4): analyzing included file ../../../../rtl/VX_platform.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 4
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Info (16884): Verilog HDL info at VX_platform.vh(4): analyzing included file ../../../../rtl/VX_scope.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_platform.vh(4): back to file '../../../../rtl/VX_platform.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(4): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 4
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|
Info (16884): Verilog HDL info at VX_define.vh(5): analyzing included file ../../../../rtl/VX_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 5
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Info (16884): Verilog HDL info at VX_config.vh(4): analyzing included file ../../../../rtl/VX_user_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_config.vh Line: 4
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|
Info (13230): Verilog HDL or VHDL information at VX_config.vh(4): back to file '../../../../rtl/VX_config.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_config.vh Line: 4
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|
Info (13230): Verilog HDL or VHDL information at VX_define.vh(5): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 5
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|
Info (16884): Verilog HDL info at VX_define.vh(384): analyzing included file ../../../../rtl/VX_types.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 384
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Info (16884): Verilog HDL info at VX_types.vh(4): analyzing included file ../../../../rtl/VX_define.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_types.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_types.vh(4): back to file '../../../../rtl/VX_types.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_types.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(384): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 384
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|
Info (13230): Verilog HDL or VHDL information at VX_scoreboard.v(1): back to file '/nethome/lcooper43/vortex-dev/hw/rtl/VX_scoreboard.v' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_scoreboard.v Line: 1
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Info (16884): Verilog HDL info at VX_instr_demux.v(1): analyzing included file /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_instr_demux.v Line: 1
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Info (16884): Verilog HDL info at VX_define.vh(4): analyzing included file ../../../../rtl/VX_platform.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 4
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|
Info (16884): Verilog HDL info at VX_platform.vh(4): analyzing included file ../../../../rtl/VX_scope.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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|
Info (13230): Verilog HDL or VHDL information at VX_platform.vh(4): back to file '../../../../rtl/VX_platform.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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|
Info (13230): Verilog HDL or VHDL information at VX_define.vh(4): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 4
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|
Info (16884): Verilog HDL info at VX_define.vh(5): analyzing included file ../../../../rtl/VX_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 5
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Info (16884): Verilog HDL info at VX_config.vh(4): analyzing included file ../../../../rtl/VX_user_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_config.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_config.vh(4): back to file '../../../../rtl/VX_config.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_config.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(5): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 5
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|
Info (16884): Verilog HDL info at VX_define.vh(384): analyzing included file ../../../../rtl/VX_types.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 384
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Info (16884): Verilog HDL info at VX_types.vh(4): analyzing included file ../../../../rtl/VX_define.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_types.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_types.vh(4): back to file '../../../../rtl/VX_types.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_types.vh Line: 4
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|
Info (13230): Verilog HDL or VHDL information at VX_define.vh(384): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 384
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|
Info (13230): Verilog HDL or VHDL information at VX_instr_demux.v(1): back to file '/nethome/lcooper43/vortex-dev/hw/rtl/VX_instr_demux.v' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_instr_demux.v Line: 1
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Info (16884): Verilog HDL info at VX_pipeline.v(1): analyzing included file /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_pipeline.v Line: 1
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Info (16884): Verilog HDL info at VX_define.vh(4): analyzing included file ../../../../rtl/VX_platform.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 4
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Info (16884): Verilog HDL info at VX_platform.vh(4): analyzing included file ../../../../rtl/VX_scope.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_platform.vh(4): back to file '../../../../rtl/VX_platform.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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|
Info (13230): Verilog HDL or VHDL information at VX_define.vh(4): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 4
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|
Info (16884): Verilog HDL info at VX_define.vh(5): analyzing included file ../../../../rtl/VX_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 5
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Info (16884): Verilog HDL info at VX_config.vh(4): analyzing included file ../../../../rtl/VX_user_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_config.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_config.vh(4): back to file '../../../../rtl/VX_config.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_config.vh Line: 4
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|
Info (13230): Verilog HDL or VHDL information at VX_define.vh(5): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 5
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|
Info (16884): Verilog HDL info at VX_define.vh(384): analyzing included file ../../../../rtl/VX_types.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 384
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Info (16884): Verilog HDL info at VX_types.vh(4): analyzing included file ../../../../rtl/VX_define.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_types.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_types.vh(4): back to file '../../../../rtl/VX_types.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_types.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(384): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 384
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|
Info (13230): Verilog HDL or VHDL information at VX_pipeline.v(1): back to file '/nethome/lcooper43/vortex-dev/hw/rtl/VX_pipeline.v' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_pipeline.v Line: 1
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Info (16884): Verilog HDL info at VX_mem_arb.v(1): analyzing included file /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_mem_arb.v Line: 1
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Info (16884): Verilog HDL info at VX_define.vh(4): analyzing included file ../../../../rtl/VX_platform.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 4
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Info (16884): Verilog HDL info at VX_platform.vh(4): analyzing included file ../../../../rtl/VX_scope.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_platform.vh(4): back to file '../../../../rtl/VX_platform.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(4): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 4
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Info (16884): Verilog HDL info at VX_define.vh(5): analyzing included file ../../../../rtl/VX_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 5
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Info (16884): Verilog HDL info at VX_config.vh(4): analyzing included file ../../../../rtl/VX_user_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_config.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_config.vh(4): back to file '../../../../rtl/VX_config.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_config.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(5): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 5
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|
Info (16884): Verilog HDL info at VX_define.vh(384): analyzing included file ../../../../rtl/VX_types.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 384
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Info (16884): Verilog HDL info at VX_types.vh(4): analyzing included file ../../../../rtl/VX_define.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_types.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_types.vh(4): back to file '../../../../rtl/VX_types.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_types.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(384): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 384
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Info (13230): Verilog HDL or VHDL information at VX_mem_arb.v(1): back to file '/nethome/lcooper43/vortex-dev/hw/rtl/VX_mem_arb.v' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_mem_arb.v Line: 1
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Info (16884): Verilog HDL info at VX_icache_stage.v(1): analyzing included file /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_icache_stage.v Line: 1
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Info (16884): Verilog HDL info at VX_define.vh(4): analyzing included file ../../../../rtl/VX_platform.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 4
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Info (16884): Verilog HDL info at VX_platform.vh(4): analyzing included file ../../../../rtl/VX_scope.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_platform.vh(4): back to file '../../../../rtl/VX_platform.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(4): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 4
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Info (16884): Verilog HDL info at VX_define.vh(5): analyzing included file ../../../../rtl/VX_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 5
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Info (16884): Verilog HDL info at VX_config.vh(4): analyzing included file ../../../../rtl/VX_user_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_config.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_config.vh(4): back to file '../../../../rtl/VX_config.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_config.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(5): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 5
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Info (16884): Verilog HDL info at VX_define.vh(384): analyzing included file ../../../../rtl/VX_types.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 384
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Info (16884): Verilog HDL info at VX_types.vh(4): analyzing included file ../../../../rtl/VX_define.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_types.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_types.vh(4): back to file '../../../../rtl/VX_types.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_types.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(384): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 384
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|
Info (13230): Verilog HDL or VHDL information at VX_icache_stage.v(1): back to file '/nethome/lcooper43/vortex-dev/hw/rtl/VX_icache_stage.v' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_icache_stage.v Line: 1
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Info (16884): Verilog HDL info at VX_mem_unit.v(1): analyzing included file /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_mem_unit.v Line: 1
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Info (16884): Verilog HDL info at VX_define.vh(4): analyzing included file ../../../../rtl/VX_platform.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 4
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Info (16884): Verilog HDL info at VX_platform.vh(4): analyzing included file ../../../../rtl/VX_scope.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_platform.vh(4): back to file '../../../../rtl/VX_platform.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(4): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 4
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Info (16884): Verilog HDL info at VX_define.vh(5): analyzing included file ../../../../rtl/VX_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 5
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Info (16884): Verilog HDL info at VX_config.vh(4): analyzing included file ../../../../rtl/VX_user_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_config.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_config.vh(4): back to file '../../../../rtl/VX_config.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_config.vh Line: 4
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|
Info (13230): Verilog HDL or VHDL information at VX_define.vh(5): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 5
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|
Info (16884): Verilog HDL info at VX_define.vh(384): analyzing included file ../../../../rtl/VX_types.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 384
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Info (16884): Verilog HDL info at VX_types.vh(4): analyzing included file ../../../../rtl/VX_define.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_types.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_types.vh(4): back to file '../../../../rtl/VX_types.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_types.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(384): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 384
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|
Info (13230): Verilog HDL or VHDL information at VX_mem_unit.v(1): back to file '/nethome/lcooper43/vortex-dev/hw/rtl/VX_mem_unit.v' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_mem_unit.v Line: 1
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Info (16884): Verilog HDL info at VX_decode.v(1): analyzing included file /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_decode.v Line: 1
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Info (16884): Verilog HDL info at VX_define.vh(4): analyzing included file ../../../../rtl/VX_platform.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 4
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Info (16884): Verilog HDL info at VX_platform.vh(4): analyzing included file ../../../../rtl/VX_scope.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_platform.vh(4): back to file '../../../../rtl/VX_platform.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(4): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 4
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Info (16884): Verilog HDL info at VX_define.vh(5): analyzing included file ../../../../rtl/VX_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 5
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Info (16884): Verilog HDL info at VX_config.vh(4): analyzing included file ../../../../rtl/VX_user_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_config.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_config.vh(4): back to file '../../../../rtl/VX_config.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_config.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(5): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 5
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|
Info (16884): Verilog HDL info at VX_define.vh(384): analyzing included file ../../../../rtl/VX_types.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 384
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|
Info (16884): Verilog HDL info at VX_types.vh(4): analyzing included file ../../../../rtl/VX_define.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_types.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_types.vh(4): back to file '../../../../rtl/VX_types.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_types.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(384): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 384
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|
Info (13230): Verilog HDL or VHDL information at VX_decode.v(1): back to file '/nethome/lcooper43/vortex-dev/hw/rtl/VX_decode.v' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_decode.v Line: 1
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Info (16884): Verilog HDL info at VX_decode.v(2): analyzing included file /nethome/lcooper43/vortex-dev/hw/rtl/VX_print_instr.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_decode.v Line: 2
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Info (16884): Verilog HDL info at VX_print_instr.vh(4): analyzing included file /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_print_instr.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_print_instr.vh(4): back to file '/nethome/lcooper43/vortex-dev/hw/rtl/VX_print_instr.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_print_instr.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_decode.v(2): back to file '/nethome/lcooper43/vortex-dev/hw/rtl/VX_decode.v' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_decode.v Line: 2
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Info (16884): Verilog HDL info at VX_writeback.v(1): analyzing included file /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_writeback.v Line: 1
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Info (16884): Verilog HDL info at VX_define.vh(4): analyzing included file ../../../../rtl/VX_platform.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 4
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Info (16884): Verilog HDL info at VX_platform.vh(4): analyzing included file ../../../../rtl/VX_scope.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_platform.vh(4): back to file '../../../../rtl/VX_platform.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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|
Info (13230): Verilog HDL or VHDL information at VX_define.vh(4): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 4
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|
Info (16884): Verilog HDL info at VX_define.vh(5): analyzing included file ../../../../rtl/VX_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 5
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Info (16884): Verilog HDL info at VX_config.vh(4): analyzing included file ../../../../rtl/VX_user_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_config.vh Line: 4
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|
Info (13230): Verilog HDL or VHDL information at VX_config.vh(4): back to file '../../../../rtl/VX_config.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_config.vh Line: 4
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|
Info (13230): Verilog HDL or VHDL information at VX_define.vh(5): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 5
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|
Info (16884): Verilog HDL info at VX_define.vh(384): analyzing included file ../../../../rtl/VX_types.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 384
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Info (16884): Verilog HDL info at VX_types.vh(4): analyzing included file ../../../../rtl/VX_define.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_types.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_types.vh(4): back to file '../../../../rtl/VX_types.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_types.vh Line: 4
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|
Info (13230): Verilog HDL or VHDL information at VX_define.vh(384): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 384
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|
Info (13230): Verilog HDL or VHDL information at VX_writeback.v(1): back to file '/nethome/lcooper43/vortex-dev/hw/rtl/VX_writeback.v' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_writeback.v Line: 1
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|
Info (16884): Verilog HDL info at Vortex.v(1): analyzing included file /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/Vortex.v Line: 1
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Info (16884): Verilog HDL info at VX_define.vh(4): analyzing included file ../../../../rtl/VX_platform.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 4
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Info (16884): Verilog HDL info at VX_platform.vh(4): analyzing included file ../../../../rtl/VX_scope.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_platform.vh(4): back to file '../../../../rtl/VX_platform.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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|
Info (13230): Verilog HDL or VHDL information at VX_define.vh(4): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 4
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|
Info (16884): Verilog HDL info at VX_define.vh(5): analyzing included file ../../../../rtl/VX_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 5
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Info (16884): Verilog HDL info at VX_config.vh(4): analyzing included file ../../../../rtl/VX_user_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_config.vh Line: 4
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|
Info (13230): Verilog HDL or VHDL information at VX_config.vh(4): back to file '../../../../rtl/VX_config.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_config.vh Line: 4
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|
Info (13230): Verilog HDL or VHDL information at VX_define.vh(5): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 5
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|
Info (16884): Verilog HDL info at VX_define.vh(384): analyzing included file ../../../../rtl/VX_types.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 384
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Info (16884): Verilog HDL info at VX_types.vh(4): analyzing included file ../../../../rtl/VX_define.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_types.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_types.vh(4): back to file '../../../../rtl/VX_types.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_types.vh Line: 4
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|
Info (13230): Verilog HDL or VHDL information at VX_define.vh(384): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 384
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|
Info (13230): Verilog HDL or VHDL information at Vortex.v(1): back to file '/nethome/lcooper43/vortex-dev/hw/rtl/Vortex.v' File: /nethome/lcooper43/vortex-dev/hw/rtl/Vortex.v Line: 1
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Info (16884): Verilog HDL info at VX_execute.v(1): analyzing included file /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_execute.v Line: 1
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Info (16884): Verilog HDL info at VX_define.vh(4): analyzing included file ../../../../rtl/VX_platform.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 4
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|
Info (16884): Verilog HDL info at VX_platform.vh(4): analyzing included file ../../../../rtl/VX_scope.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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|
Info (13230): Verilog HDL or VHDL information at VX_platform.vh(4): back to file '../../../../rtl/VX_platform.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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|
Info (13230): Verilog HDL or VHDL information at VX_define.vh(4): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 4
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|
Info (16884): Verilog HDL info at VX_define.vh(5): analyzing included file ../../../../rtl/VX_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 5
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Info (16884): Verilog HDL info at VX_config.vh(4): analyzing included file ../../../../rtl/VX_user_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_config.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_config.vh(4): back to file '../../../../rtl/VX_config.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_config.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(5): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 5
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|
Info (16884): Verilog HDL info at VX_define.vh(384): analyzing included file ../../../../rtl/VX_types.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 384
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Info (16884): Verilog HDL info at VX_types.vh(4): analyzing included file ../../../../rtl/VX_define.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_types.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_types.vh(4): back to file '../../../../rtl/VX_types.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_types.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(384): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 384
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|
Info (13230): Verilog HDL or VHDL information at VX_execute.v(1): back to file '/nethome/lcooper43/vortex-dev/hw/rtl/VX_execute.v' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_execute.v Line: 1
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Info (16884): Verilog HDL info at VX_commit.v(1): analyzing included file /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_commit.v Line: 1
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Info (16884): Verilog HDL info at VX_define.vh(4): analyzing included file ../../../../rtl/VX_platform.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 4
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Info (16884): Verilog HDL info at VX_platform.vh(4): analyzing included file ../../../../rtl/VX_scope.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_platform.vh(4): back to file '../../../../rtl/VX_platform.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(4): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 4
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Info (16884): Verilog HDL info at VX_define.vh(5): analyzing included file ../../../../rtl/VX_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 5
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Info (16884): Verilog HDL info at VX_config.vh(4): analyzing included file ../../../../rtl/VX_user_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_config.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_config.vh(4): back to file '../../../../rtl/VX_config.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_config.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(5): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 5
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Info (16884): Verilog HDL info at VX_define.vh(384): analyzing included file ../../../../rtl/VX_types.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 384
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Info (16884): Verilog HDL info at VX_types.vh(4): analyzing included file ../../../../rtl/VX_define.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_types.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_types.vh(4): back to file '../../../../rtl/VX_types.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_types.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(384): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 384
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Info (13230): Verilog HDL or VHDL information at VX_commit.v(1): back to file '/nethome/lcooper43/vortex-dev/hw/rtl/VX_commit.v' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_commit.v Line: 1
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Info (16884): Verilog HDL info at VX_issue.v(1): analyzing included file /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_issue.v Line: 1
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Info (16884): Verilog HDL info at VX_define.vh(4): analyzing included file ../../../../rtl/VX_platform.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 4
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Info (16884): Verilog HDL info at VX_platform.vh(4): analyzing included file ../../../../rtl/VX_scope.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_platform.vh(4): back to file '../../../../rtl/VX_platform.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(4): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 4
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Info (16884): Verilog HDL info at VX_define.vh(5): analyzing included file ../../../../rtl/VX_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 5
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Info (16884): Verilog HDL info at VX_config.vh(4): analyzing included file ../../../../rtl/VX_user_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_config.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_config.vh(4): back to file '../../../../rtl/VX_config.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_config.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(5): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 5
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|
Info (16884): Verilog HDL info at VX_define.vh(384): analyzing included file ../../../../rtl/VX_types.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 384
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Info (16884): Verilog HDL info at VX_types.vh(4): analyzing included file ../../../../rtl/VX_define.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_types.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_types.vh(4): back to file '../../../../rtl/VX_types.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_types.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(384): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 384
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Info (13230): Verilog HDL or VHDL information at VX_issue.v(1): back to file '/nethome/lcooper43/vortex-dev/hw/rtl/VX_issue.v' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_issue.v Line: 1
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Info (16884): Verilog HDL info at VX_databus_arb.v(1): analyzing included file /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_databus_arb.v Line: 1
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Info (16884): Verilog HDL info at VX_define.vh(4): analyzing included file ../../../../rtl/VX_platform.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 4
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Info (16884): Verilog HDL info at VX_platform.vh(4): analyzing included file ../../../../rtl/VX_scope.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_platform.vh(4): back to file '../../../../rtl/VX_platform.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(4): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 4
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Info (16884): Verilog HDL info at VX_define.vh(5): analyzing included file ../../../../rtl/VX_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 5
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Info (16884): Verilog HDL info at VX_config.vh(4): analyzing included file ../../../../rtl/VX_user_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_config.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_config.vh(4): back to file '../../../../rtl/VX_config.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_config.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(5): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 5
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Info (16884): Verilog HDL info at VX_define.vh(384): analyzing included file ../../../../rtl/VX_types.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 384
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Info (16884): Verilog HDL info at VX_types.vh(4): analyzing included file ../../../../rtl/VX_define.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_types.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_types.vh(4): back to file '../../../../rtl/VX_types.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_types.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(384): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 384
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Info (13230): Verilog HDL or VHDL information at VX_databus_arb.v(1): back to file '/nethome/lcooper43/vortex-dev/hw/rtl/VX_databus_arb.v' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_databus_arb.v Line: 1
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Info (16884): Verilog HDL info at VX_gpr_stage.v(1): analyzing included file /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_gpr_stage.v Line: 1
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Info (16884): Verilog HDL info at VX_define.vh(4): analyzing included file ../../../../rtl/VX_platform.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 4
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Info (16884): Verilog HDL info at VX_platform.vh(4): analyzing included file ../../../../rtl/VX_scope.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_platform.vh(4): back to file '../../../../rtl/VX_platform.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(4): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 4
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Info (16884): Verilog HDL info at VX_define.vh(5): analyzing included file ../../../../rtl/VX_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 5
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Info (16884): Verilog HDL info at VX_config.vh(4): analyzing included file ../../../../rtl/VX_user_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_config.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_config.vh(4): back to file '../../../../rtl/VX_config.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_config.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(5): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 5
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Info (16884): Verilog HDL info at VX_define.vh(384): analyzing included file ../../../../rtl/VX_types.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 384
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Info (16884): Verilog HDL info at VX_types.vh(4): analyzing included file ../../../../rtl/VX_define.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_types.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_types.vh(4): back to file '../../../../rtl/VX_types.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_types.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(384): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 384
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Info (13230): Verilog HDL or VHDL information at VX_gpr_stage.v(1): back to file '/nethome/lcooper43/vortex-dev/hw/rtl/VX_gpr_stage.v' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_gpr_stage.v Line: 1
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Info (16884): Verilog HDL info at VX_csr_io_arb.v(1): analyzing included file /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_csr_io_arb.v Line: 1
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Info (16884): Verilog HDL info at VX_define.vh(4): analyzing included file ../../../../rtl/VX_platform.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 4
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Info (16884): Verilog HDL info at VX_platform.vh(4): analyzing included file ../../../../rtl/VX_scope.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_platform.vh(4): back to file '../../../../rtl/VX_platform.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(4): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 4
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Info (16884): Verilog HDL info at VX_define.vh(5): analyzing included file ../../../../rtl/VX_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 5
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Info (16884): Verilog HDL info at VX_config.vh(4): analyzing included file ../../../../rtl/VX_user_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_config.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_config.vh(4): back to file '../../../../rtl/VX_config.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_config.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(5): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 5
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Info (16884): Verilog HDL info at VX_define.vh(384): analyzing included file ../../../../rtl/VX_types.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 384
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Info (16884): Verilog HDL info at VX_types.vh(4): analyzing included file ../../../../rtl/VX_define.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_types.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_types.vh(4): back to file '../../../../rtl/VX_types.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_types.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(384): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 384
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Info (13230): Verilog HDL or VHDL information at VX_csr_io_arb.v(1): back to file '/nethome/lcooper43/vortex-dev/hw/rtl/VX_csr_io_arb.v' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_csr_io_arb.v Line: 1
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Info (16884): Verilog HDL info at VX_core.v(1): analyzing included file /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_core.v Line: 1
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Info (16884): Verilog HDL info at VX_define.vh(4): analyzing included file ../../../../rtl/VX_platform.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 4
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Info (16884): Verilog HDL info at VX_platform.vh(4): analyzing included file ../../../../rtl/VX_scope.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_platform.vh(4): back to file '../../../../rtl/VX_platform.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(4): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 4
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|
Info (16884): Verilog HDL info at VX_define.vh(5): analyzing included file ../../../../rtl/VX_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 5
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Info (16884): Verilog HDL info at VX_config.vh(4): analyzing included file ../../../../rtl/VX_user_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_config.vh Line: 4
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|
Info (13230): Verilog HDL or VHDL information at VX_config.vh(4): back to file '../../../../rtl/VX_config.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_config.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(5): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 5
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Info (16884): Verilog HDL info at VX_define.vh(384): analyzing included file ../../../../rtl/VX_types.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 384
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Info (16884): Verilog HDL info at VX_types.vh(4): analyzing included file ../../../../rtl/VX_define.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_types.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_types.vh(4): back to file '../../../../rtl/VX_types.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_types.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(384): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 384
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|
Info (13230): Verilog HDL or VHDL information at VX_core.v(1): back to file '/nethome/lcooper43/vortex-dev/hw/rtl/VX_core.v' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_core.v Line: 1
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|
Info (16884): Verilog HDL info at VX_gpr_ram_i.v(1): analyzing included file /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_gpr_ram_i.v Line: 1
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Info (16884): Verilog HDL info at VX_define.vh(4): analyzing included file ../../../../rtl/VX_platform.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 4
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|
Info (16884): Verilog HDL info at VX_platform.vh(4): analyzing included file ../../../../rtl/VX_scope.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_platform.vh(4): back to file '../../../../rtl/VX_platform.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(4): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 4
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Info (16884): Verilog HDL info at VX_define.vh(5): analyzing included file ../../../../rtl/VX_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 5
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Info (16884): Verilog HDL info at VX_config.vh(4): analyzing included file ../../../../rtl/VX_user_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_config.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_config.vh(4): back to file '../../../../rtl/VX_config.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_config.vh Line: 4
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|
Info (13230): Verilog HDL or VHDL information at VX_define.vh(5): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 5
|
|
Info (16884): Verilog HDL info at VX_define.vh(384): analyzing included file ../../../../rtl/VX_types.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 384
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Info (16884): Verilog HDL info at VX_types.vh(4): analyzing included file ../../../../rtl/VX_define.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_types.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_types.vh(4): back to file '../../../../rtl/VX_types.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_types.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(384): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 384
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|
Info (13230): Verilog HDL or VHDL information at VX_gpr_ram_i.v(1): back to file '/nethome/lcooper43/vortex-dev/hw/rtl/VX_gpr_ram_i.v' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_gpr_ram_i.v Line: 1
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Info (16884): Verilog HDL info at VX_ipdom_stack.v(1): analyzing included file /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_ipdom_stack.v Line: 1
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Info (16884): Verilog HDL info at VX_platform.vh(4): analyzing included file ../../../../rtl/VX_scope.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_platform.vh(4): back to file '../../../../rtl/VX_platform.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_ipdom_stack.v(1): back to file '/nethome/lcooper43/vortex-dev/hw/rtl/VX_ipdom_stack.v' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_ipdom_stack.v Line: 1
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Info (16884): Verilog HDL info at ccip_std_afu.sv(9): analyzing included file /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/platform_if.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/afu/ccip_std_afu.sv Line: 9
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Info (16884): Verilog HDL info at platform_if.vh(39): analyzing included file ./platform/platform_afu_top_config.vh File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/platform_if.vh Line: 39
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Info (13230): Verilog HDL or VHDL information at platform_if.vh(39): back to file '/opt/opae/1.1.2/share/opae/platform/platform_if/rtl/platform_if.vh' File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/platform_if.vh Line: 39
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Info (16884): Verilog HDL info at platform_if.vh(41): analyzing included file /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/device_if/device_if.vh File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/platform_if.vh Line: 41
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Info (16884): Verilog HDL info at device_if.vh(39): analyzing included file /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/device_if/avalon_mem_if.vh File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/device_if/device_if.vh Line: 39
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Warning (16817): Verilog HDL warning at avalon_mem_if.vh(155): overwriting previous definition of avalon_mem_if interface File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/device_if/avalon_mem_if.vh Line: 155
|
|
Info (18437): Verilog HDL info at avalon_mem_if.vh(155): previous definition of module avalon_mem_if is here File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/device_if/avalon_mem_if.vh Line: 155
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|
Info (13230): Verilog HDL or VHDL information at device_if.vh(39): back to file '/opt/opae/1.1.2/share/opae/platform/platform_if/rtl/device_if/device_if.vh' File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/device_if/device_if.vh Line: 39
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|
Info (13230): Verilog HDL or VHDL information at platform_if.vh(41): back to file '/opt/opae/1.1.2/share/opae/platform/platform_if/rtl/platform_if.vh' File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/platform_if.vh Line: 41
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|
Info (13230): Verilog HDL or VHDL information at ccip_std_afu.sv(9): back to file '/nethome/lcooper43/vortex-dev/hw/rtl/afu/ccip_std_afu.sv' File: /nethome/lcooper43/vortex-dev/hw/rtl/afu/ccip_std_afu.sv Line: 9
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|
Info (16884): Verilog HDL info at vortex_afu.sv(2): analyzing included file /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/platform_if.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/afu/vortex_afu.sv Line: 2
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|
Info (16884): Verilog HDL info at platform_if.vh(39): analyzing included file ./platform/platform_afu_top_config.vh File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/platform_if.vh Line: 39
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|
Info (13230): Verilog HDL or VHDL information at platform_if.vh(39): back to file '/opt/opae/1.1.2/share/opae/platform/platform_if/rtl/platform_if.vh' File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/platform_if.vh Line: 39
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|
Info (16884): Verilog HDL info at platform_if.vh(41): analyzing included file /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/device_if/device_if.vh File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/platform_if.vh Line: 41
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|
Info (16884): Verilog HDL info at device_if.vh(39): analyzing included file /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/device_if/avalon_mem_if.vh File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/device_if/device_if.vh Line: 39
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|
Warning (16817): Verilog HDL warning at avalon_mem_if.vh(155): overwriting previous definition of avalon_mem_if interface File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/device_if/avalon_mem_if.vh Line: 155
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|
Info (18437): Verilog HDL info at avalon_mem_if.vh(155): previous definition of module avalon_mem_if is here File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/device_if/avalon_mem_if.vh Line: 155
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Info (13230): Verilog HDL or VHDL information at device_if.vh(39): back to file '/opt/opae/1.1.2/share/opae/platform/platform_if/rtl/device_if/device_if.vh' File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/device_if/device_if.vh Line: 39
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|
Info (13230): Verilog HDL or VHDL information at platform_if.vh(41): back to file '/opt/opae/1.1.2/share/opae/platform/platform_if/rtl/platform_if.vh' File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/platform_if.vh Line: 41
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Info (13230): Verilog HDL or VHDL information at vortex_afu.sv(2): back to file '/nethome/lcooper43/vortex-dev/hw/rtl/afu/vortex_afu.sv' File: /nethome/lcooper43/vortex-dev/hw/rtl/afu/vortex_afu.sv Line: 2
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|
Info (16884): Verilog HDL info at vortex_afu.sv(4): analyzing included file ../hw/afu_json_info.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/afu/vortex_afu.sv Line: 4
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|
Info (13230): Verilog HDL or VHDL information at vortex_afu.sv(4): back to file '/nethome/lcooper43/vortex-dev/hw/rtl/afu/vortex_afu.sv' File: /nethome/lcooper43/vortex-dev/hw/rtl/afu/vortex_afu.sv Line: 4
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Info (16884): Verilog HDL info at vortex_afu.sv(13): analyzing included file ../../../../rtl/VX_define.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/afu/vortex_afu.sv Line: 13
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Info (16884): Verilog HDL info at VX_define.vh(4): analyzing included file ../../../../rtl/VX_platform.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 4
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Info (16884): Verilog HDL info at VX_platform.vh(4): analyzing included file ../../../../rtl/VX_scope.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_platform.vh(4): back to file '../../../../rtl/VX_platform.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(4): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 4
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|
Info (16884): Verilog HDL info at VX_define.vh(5): analyzing included file ../../../../rtl/VX_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 5
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Info (16884): Verilog HDL info at VX_config.vh(4): analyzing included file ../../../../rtl/VX_user_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_config.vh Line: 4
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|
Info (13230): Verilog HDL or VHDL information at VX_config.vh(4): back to file '../../../../rtl/VX_config.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_config.vh Line: 4
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Info (13230): Verilog HDL or VHDL information at VX_define.vh(5): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 5
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|
Info (16884): Verilog HDL info at VX_define.vh(384): analyzing included file ../../../../rtl/VX_types.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 384
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|
Info (16884): Verilog HDL info at VX_types.vh(4): analyzing included file ../../../../rtl/VX_define.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_types.vh Line: 4
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|
Info (13230): Verilog HDL or VHDL information at VX_types.vh(4): back to file '../../../../rtl/VX_types.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_types.vh Line: 4
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|
Info (13230): Verilog HDL or VHDL information at VX_define.vh(384): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 384
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|
Info (13230): Verilog HDL or VHDL information at vortex_afu.sv(13): back to file '/nethome/lcooper43/vortex-dev/hw/rtl/afu/vortex_afu.sv' File: /nethome/lcooper43/vortex-dev/hw/rtl/afu/vortex_afu.sv Line: 13
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|
Info (16884): Verilog HDL info at VX_avs_wrapper.v(1): analyzing included file ../../../../rtl/VX_define.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/afu/VX_avs_wrapper.v Line: 1
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|
Info (16884): Verilog HDL info at VX_define.vh(4): analyzing included file ../../../../rtl/VX_platform.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 4
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|
Info (16884): Verilog HDL info at VX_platform.vh(4): analyzing included file ../../../../rtl/VX_scope.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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|
Info (13230): Verilog HDL or VHDL information at VX_platform.vh(4): back to file '../../../../rtl/VX_platform.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_platform.vh Line: 4
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|
Info (13230): Verilog HDL or VHDL information at VX_define.vh(4): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 4
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|
Info (16884): Verilog HDL info at VX_define.vh(5): analyzing included file ../../../../rtl/VX_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 5
|
|
Info (16884): Verilog HDL info at VX_config.vh(4): analyzing included file ../../../../rtl/VX_user_config.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_config.vh Line: 4
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|
Info (13230): Verilog HDL or VHDL information at VX_config.vh(4): back to file '../../../../rtl/VX_config.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_config.vh Line: 4
|
|
Info (13230): Verilog HDL or VHDL information at VX_define.vh(5): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 5
|
|
Info (16884): Verilog HDL info at VX_define.vh(384): analyzing included file ../../../../rtl/VX_types.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 384
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|
Info (16884): Verilog HDL info at VX_types.vh(4): analyzing included file ../../../../rtl/VX_define.vh File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_types.vh Line: 4
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|
Info (13230): Verilog HDL or VHDL information at VX_types.vh(4): back to file '../../../../rtl/VX_types.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_types.vh Line: 4
|
|
Info (13230): Verilog HDL or VHDL information at VX_define.vh(384): back to file '../../../../rtl/VX_define.vh' File: /nethome/lcooper43/vortex-dev/hw/rtl/VX_define.vh Line: 384
|
|
Info (13230): Verilog HDL or VHDL information at VX_avs_wrapper.v(1): back to file '/nethome/lcooper43/vortex-dev/hw/rtl/afu/VX_avs_wrapper.v' File: /nethome/lcooper43/vortex-dev/hw/rtl/afu/VX_avs_wrapper.v Line: 1
|
|
Info (16884): Verilog HDL info at green_bs.sv(30): analyzing included file platform/fpga_defines.vh File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 30
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|
Warning (13228): Verilog HDL or VHDL warning at fpga_defines.vh(70): ignoring re-definition of command line macro 'INCLUDE_DDR4' File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/fpga_defines.vh Line: 70
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|
Info (13230): Verilog HDL or VHDL information at green_bs.sv(30): back to file 'platform/green_bs.sv' File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 30
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|
Info (16884): Verilog HDL info at green_bs.sv(40): analyzing included file /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/platform_if.vh File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 40
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|
Info (16884): Verilog HDL info at platform_if.vh(39): analyzing included file ./platform/platform_afu_top_config.vh File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/platform_if.vh Line: 39
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|
Info (13230): Verilog HDL or VHDL information at platform_if.vh(39): back to file '/opt/opae/1.1.2/share/opae/platform/platform_if/rtl/platform_if.vh' File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/platform_if.vh Line: 39
|
|
Info (16884): Verilog HDL info at platform_if.vh(41): analyzing included file /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/device_if/device_if.vh File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/platform_if.vh Line: 41
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|
Info (16884): Verilog HDL info at device_if.vh(39): analyzing included file /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/device_if/avalon_mem_if.vh File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/device_if/device_if.vh Line: 39
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|
Warning (16817): Verilog HDL warning at avalon_mem_if.vh(155): overwriting previous definition of avalon_mem_if interface File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/device_if/avalon_mem_if.vh Line: 155
|
|
Info (18437): Verilog HDL info at avalon_mem_if.vh(155): previous definition of module avalon_mem_if is here File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/device_if/avalon_mem_if.vh Line: 155
|
|
Info (13230): Verilog HDL or VHDL information at device_if.vh(39): back to file '/opt/opae/1.1.2/share/opae/platform/platform_if/rtl/device_if/device_if.vh' File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/device_if/device_if.vh Line: 39
|
|
Info (13230): Verilog HDL or VHDL information at platform_if.vh(41): back to file '/opt/opae/1.1.2/share/opae/platform/platform_if/rtl/platform_if.vh' File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/platform_if.vh Line: 41
|
|
Info (13230): Verilog HDL or VHDL information at green_bs.sv(40): back to file 'platform/green_bs.sv' File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 40
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|
Info (16884): Verilog HDL info at green_bs.sv(43): analyzing included file platform/pr_hssi_if.vh File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 43
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|
Info (13230): Verilog HDL or VHDL information at green_bs.sv(43): back to file 'platform/green_bs.sv' File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 43
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|
Warning (13228): Verilog HDL or VHDL warning at green_bs.sv(45): parameter declared inside compilation unit '$unit_platform_green_bs_sv' shall be treated as localparam File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 45
|
|
Warning (13228): Verilog HDL or VHDL warning at green_bs.sv(46): parameter declared inside compilation unit '$unit_platform_green_bs_sv' shall be treated as localparam File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 46
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|
Warning (13228): Verilog HDL or VHDL warning at green_bs_resync.v(142): generate block is allowed only inside loop and conditional generate in SystemVerilog mode File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/lib/common/green_bs_resync.v Line: 142
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|
Warning (13228): Verilog HDL or VHDL warning at fpga_defines.vh(70): ignoring re-definition of command line macro 'INCLUDE_DDR4' File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/fpga_defines.vh Line: 70
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|
Info: Elaborating from top-level entity "dcp_top"
|
|
Info (19272): Using dcp.qdb to replace the root partition.
|
|
Info (19534): Using dcp.qdb to replace the partition root_partition_2cedade0.
|
|
Warning (13469): Verilog HDL assignment warning at avalon_mem_if_connect.sv(54): truncated value with size 2 to match size of target (1) File: /opt/opae/1.1.2/share/opae/platform/platform_if/rtl/platform_shims/utils/avalon_mem_if_connect.sv Line: 54
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|
Warning (13416): Verilog HDL warning at vortex_afu.sv(189): ignoring unsupported system task "assertoff" File: /nethome/lcooper43/vortex-dev/hw/rtl/afu/vortex_afu.sv Line: 189
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|
Warning (13469): Verilog HDL assignment warning at vortex_afu.sv(195): truncated value with size 3 to match size of target (2) File: /nethome/lcooper43/vortex-dev/hw/rtl/afu/vortex_afu.sv Line: 195
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|
Warning (13416): Verilog HDL warning at vortex_afu.sv(197): ignoring unsupported system task "asserton" File: /nethome/lcooper43/vortex-dev/hw/rtl/afu/vortex_afu.sv Line: 197
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|
Warning (13469): Verilog HDL assignment warning at vortex_afu.sv(333): truncated value with size 3 to match size of target (2) File: /nethome/lcooper43/vortex-dev/hw/rtl/afu/vortex_afu.sv Line: 333
|
|
Warning (13469): Verilog HDL assignment warning at VX_fp_cvt.v(159): truncated value with size 32 to match size of target (9) File: /nethome/lcooper43/vortex-dev/hw/rtl/fp_cores/VX_fp_cvt.v Line: 159
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|
Warning (13469): Verilog HDL assignment warning at VX_fp_cvt.v(161): truncated value with size 32 to match size of target (9) File: /nethome/lcooper43/vortex-dev/hw/rtl/fp_cores/VX_fp_cvt.v Line: 161
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|
Warning (13469): Verilog HDL assignment warning at VX_fp_cvt.v(166): truncated value with size 10 to match size of target (9) File: /nethome/lcooper43/vortex-dev/hw/rtl/fp_cores/VX_fp_cvt.v Line: 166
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|
Warning (13469): Verilog HDL assignment warning at VX_fp_cvt.v(232): truncated value with size 32 to match size of target (6) File: /nethome/lcooper43/vortex-dev/hw/rtl/fp_cores/VX_fp_cvt.v Line: 232
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|
Warning (13469): Verilog HDL assignment warning at VX_fp_cvt.v(240): truncated value with size 32 to match size of target (6) File: /nethome/lcooper43/vortex-dev/hw/rtl/fp_cores/VX_fp_cvt.v Line: 240
|
|
Warning (13469): Verilog HDL assignment warning at VX_flush_ctrl.v(31): truncated value with size 9 to match size of target (8) File: /nethome/lcooper43/vortex-dev/hw/rtl/cache/VX_flush_ctrl.v Line: 31
|
|
Warning (13469): Verilog HDL assignment warning at VX_flush_ctrl.v(31): truncated value with size 7 to match size of target (6) File: /nethome/lcooper43/vortex-dev/hw/rtl/cache/VX_flush_ctrl.v Line: 31
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[0].core|mem_unit|icache|[0].bank|miss_resrv|altsyncram:addr_table[0][25]__1" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Info (19000): Inferred 1 megafunctions from design logic
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[0].core|mem_unit|icache|[0].bank|miss_resrv|altsyncram:addr_table[0][25]__1"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 26
|
|
Info (286033): Parameter WIDTHAD_A set to 2
|
|
Info (286033): Parameter NUMWORDS_A set to 4
|
|
Info (286033): Parameter WIDTH_B set to 26
|
|
Info (286033): Parameter WIDTHAD_B set to 2
|
|
Info (286033): Parameter NUMWORDS_B set to 4
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[0].core|mem_unit|dcache|[0].bank|miss_resrv|altsyncram:addr_table[0][23]__2" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Info (19000): Inferred 1 megafunctions from design logic
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[0].core|mem_unit|dcache|[0].bank|miss_resrv|altsyncram:addr_table[0][23]__2"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 24
|
|
Info (286033): Parameter WIDTHAD_A set to 3
|
|
Info (286033): Parameter NUMWORDS_A set to 8
|
|
Info (286033): Parameter WIDTH_B set to 24
|
|
Info (286033): Parameter WIDTHAD_B set to 3
|
|
Info (286033): Parameter NUMWORDS_B set to 8
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[0].core|mem_unit|dcache|[1].bank|miss_resrv|altsyncram:addr_table[0][23]__3" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Info (19000): Inferred 1 megafunctions from design logic
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[0].core|mem_unit|dcache|[1].bank|miss_resrv|altsyncram:addr_table[0][23]__3"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 24
|
|
Info (286033): Parameter WIDTHAD_A set to 3
|
|
Info (286033): Parameter NUMWORDS_A set to 8
|
|
Info (286033): Parameter WIDTH_B set to 24
|
|
Info (286033): Parameter WIDTHAD_B set to 3
|
|
Info (286033): Parameter NUMWORDS_B set to 8
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[0].core|mem_unit|dcache|[2].bank|miss_resrv|altsyncram:addr_table[0][23]__4" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Info (19000): Inferred 1 megafunctions from design logic
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[0].core|mem_unit|dcache|[2].bank|miss_resrv|altsyncram:addr_table[0][23]__4"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 24
|
|
Info (286033): Parameter WIDTHAD_A set to 3
|
|
Info (286033): Parameter NUMWORDS_A set to 8
|
|
Info (286033): Parameter WIDTH_B set to 24
|
|
Info (286033): Parameter WIDTHAD_B set to 3
|
|
Info (286033): Parameter NUMWORDS_B set to 8
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[0].core|mem_unit|dcache|[3].bank|miss_resrv|altsyncram:addr_table[0][23]__5" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Info (19000): Inferred 1 megafunctions from design logic
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[0].core|mem_unit|dcache|[3].bank|miss_resrv|altsyncram:addr_table[0][23]__5"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 24
|
|
Info (286033): Parameter WIDTHAD_A set to 3
|
|
Info (286033): Parameter NUMWORDS_A set to 8
|
|
Info (286033): Parameter WIDTH_B set to 24
|
|
Info (286033): Parameter WIDTHAD_B set to 3
|
|
Info (286033): Parameter NUMWORDS_B set to 8
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[1].core|mem_unit|icache|[0].bank|miss_resrv|altsyncram:addr_table[0][25]__6" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Info (19000): Inferred 1 megafunctions from design logic
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[1].core|mem_unit|icache|[0].bank|miss_resrv|altsyncram:addr_table[0][25]__6"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 26
|
|
Info (286033): Parameter WIDTHAD_A set to 2
|
|
Info (286033): Parameter NUMWORDS_A set to 4
|
|
Info (286033): Parameter WIDTH_B set to 26
|
|
Info (286033): Parameter WIDTHAD_B set to 2
|
|
Info (286033): Parameter NUMWORDS_B set to 4
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[1].core|mem_unit|dcache|[0].bank|miss_resrv|altsyncram:addr_table[0][23]__7" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Info (19000): Inferred 1 megafunctions from design logic
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[1].core|mem_unit|dcache|[0].bank|miss_resrv|altsyncram:addr_table[0][23]__7"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 24
|
|
Info (286033): Parameter WIDTHAD_A set to 3
|
|
Info (286033): Parameter NUMWORDS_A set to 8
|
|
Info (286033): Parameter WIDTH_B set to 24
|
|
Info (286033): Parameter WIDTHAD_B set to 3
|
|
Info (286033): Parameter NUMWORDS_B set to 8
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[1].core|mem_unit|dcache|[1].bank|miss_resrv|altsyncram:addr_table[0][23]__8" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Info (19000): Inferred 1 megafunctions from design logic
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[1].core|mem_unit|dcache|[1].bank|miss_resrv|altsyncram:addr_table[0][23]__8"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 24
|
|
Info (286033): Parameter WIDTHAD_A set to 3
|
|
Info (286033): Parameter NUMWORDS_A set to 8
|
|
Info (286033): Parameter WIDTH_B set to 24
|
|
Info (286033): Parameter WIDTHAD_B set to 3
|
|
Info (286033): Parameter NUMWORDS_B set to 8
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[1].core|mem_unit|dcache|[2].bank|miss_resrv|altsyncram:addr_table[0][23]__9" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Info (19000): Inferred 1 megafunctions from design logic
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[1].core|mem_unit|dcache|[2].bank|miss_resrv|altsyncram:addr_table[0][23]__9"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 24
|
|
Info (286033): Parameter WIDTHAD_A set to 3
|
|
Info (286033): Parameter NUMWORDS_A set to 8
|
|
Info (286033): Parameter WIDTH_B set to 24
|
|
Info (286033): Parameter WIDTHAD_B set to 3
|
|
Info (286033): Parameter NUMWORDS_B set to 8
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[1].core|mem_unit|dcache|[3].bank|miss_resrv|altsyncram:addr_table[0][23]__10" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Info (19000): Inferred 1 megafunctions from design logic
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[1].core|mem_unit|dcache|[3].bank|miss_resrv|altsyncram:addr_table[0][23]__10"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 24
|
|
Info (286033): Parameter WIDTHAD_A set to 3
|
|
Info (286033): Parameter NUMWORDS_A set to 8
|
|
Info (286033): Parameter WIDTH_B set to 24
|
|
Info (286033): Parameter WIDTHAD_B set to 3
|
|
Info (286033): Parameter NUMWORDS_B set to 8
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[2].core|mem_unit|icache|[0].bank|miss_resrv|altsyncram:addr_table[0][25]__11" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Info (19000): Inferred 1 megafunctions from design logic
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[2].core|mem_unit|icache|[0].bank|miss_resrv|altsyncram:addr_table[0][25]__11"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 26
|
|
Info (286033): Parameter WIDTHAD_A set to 2
|
|
Info (286033): Parameter NUMWORDS_A set to 4
|
|
Info (286033): Parameter WIDTH_B set to 26
|
|
Info (286033): Parameter WIDTHAD_B set to 2
|
|
Info (286033): Parameter NUMWORDS_B set to 4
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[2].core|mem_unit|dcache|[0].bank|miss_resrv|altsyncram:addr_table[0][23]__12" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Info (19000): Inferred 1 megafunctions from design logic
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[2].core|mem_unit|dcache|[0].bank|miss_resrv|altsyncram:addr_table[0][23]__12"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 24
|
|
Info (286033): Parameter WIDTHAD_A set to 3
|
|
Info (286033): Parameter NUMWORDS_A set to 8
|
|
Info (286033): Parameter WIDTH_B set to 24
|
|
Info (286033): Parameter WIDTHAD_B set to 3
|
|
Info (286033): Parameter NUMWORDS_B set to 8
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[2].core|mem_unit|dcache|[1].bank|miss_resrv|altsyncram:addr_table[0][23]__13" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Info (19000): Inferred 1 megafunctions from design logic
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[2].core|mem_unit|dcache|[1].bank|miss_resrv|altsyncram:addr_table[0][23]__13"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 24
|
|
Info (286033): Parameter WIDTHAD_A set to 3
|
|
Info (286033): Parameter NUMWORDS_A set to 8
|
|
Info (286033): Parameter WIDTH_B set to 24
|
|
Info (286033): Parameter WIDTHAD_B set to 3
|
|
Info (286033): Parameter NUMWORDS_B set to 8
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[2].core|mem_unit|dcache|[2].bank|miss_resrv|altsyncram:addr_table[0][23]__14" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Info (19000): Inferred 1 megafunctions from design logic
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[2].core|mem_unit|dcache|[2].bank|miss_resrv|altsyncram:addr_table[0][23]__14"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 24
|
|
Info (286033): Parameter WIDTHAD_A set to 3
|
|
Info (286033): Parameter NUMWORDS_A set to 8
|
|
Info (286033): Parameter WIDTH_B set to 24
|
|
Info (286033): Parameter WIDTHAD_B set to 3
|
|
Info (286033): Parameter NUMWORDS_B set to 8
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[2].core|mem_unit|dcache|[3].bank|miss_resrv|altsyncram:addr_table[0][23]__15" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Info (19000): Inferred 1 megafunctions from design logic
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[2].core|mem_unit|dcache|[3].bank|miss_resrv|altsyncram:addr_table[0][23]__15"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 24
|
|
Info (286033): Parameter WIDTHAD_A set to 3
|
|
Info (286033): Parameter NUMWORDS_A set to 8
|
|
Info (286033): Parameter WIDTH_B set to 24
|
|
Info (286033): Parameter WIDTHAD_B set to 3
|
|
Info (286033): Parameter NUMWORDS_B set to 8
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[3].core|mem_unit|icache|[0].bank|miss_resrv|altsyncram:addr_table[0][25]__16" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Info (19000): Inferred 1 megafunctions from design logic
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[3].core|mem_unit|icache|[0].bank|miss_resrv|altsyncram:addr_table[0][25]__16"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 26
|
|
Info (286033): Parameter WIDTHAD_A set to 2
|
|
Info (286033): Parameter NUMWORDS_A set to 4
|
|
Info (286033): Parameter WIDTH_B set to 26
|
|
Info (286033): Parameter WIDTHAD_B set to 2
|
|
Info (286033): Parameter NUMWORDS_B set to 4
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[3].core|mem_unit|dcache|[0].bank|miss_resrv|altsyncram:addr_table[0][23]__17" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Info (19000): Inferred 1 megafunctions from design logic
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[3].core|mem_unit|dcache|[0].bank|miss_resrv|altsyncram:addr_table[0][23]__17"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 24
|
|
Info (286033): Parameter WIDTHAD_A set to 3
|
|
Info (286033): Parameter NUMWORDS_A set to 8
|
|
Info (286033): Parameter WIDTH_B set to 24
|
|
Info (286033): Parameter WIDTHAD_B set to 3
|
|
Info (286033): Parameter NUMWORDS_B set to 8
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[3].core|mem_unit|dcache|[1].bank|miss_resrv|altsyncram:addr_table[0][23]__18" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Info (19000): Inferred 1 megafunctions from design logic
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[3].core|mem_unit|dcache|[1].bank|miss_resrv|altsyncram:addr_table[0][23]__18"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 24
|
|
Info (286033): Parameter WIDTHAD_A set to 3
|
|
Info (286033): Parameter NUMWORDS_A set to 8
|
|
Info (286033): Parameter WIDTH_B set to 24
|
|
Info (286033): Parameter WIDTHAD_B set to 3
|
|
Info (286033): Parameter NUMWORDS_B set to 8
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[3].core|mem_unit|dcache|[2].bank|miss_resrv|altsyncram:addr_table[0][23]__19" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Info (19000): Inferred 1 megafunctions from design logic
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[3].core|mem_unit|dcache|[2].bank|miss_resrv|altsyncram:addr_table[0][23]__19"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 24
|
|
Info (286033): Parameter WIDTHAD_A set to 3
|
|
Info (286033): Parameter NUMWORDS_A set to 8
|
|
Info (286033): Parameter WIDTH_B set to 24
|
|
Info (286033): Parameter WIDTHAD_B set to 3
|
|
Info (286033): Parameter NUMWORDS_B set to 8
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[3].core|mem_unit|dcache|[3].bank|miss_resrv|altsyncram:addr_table[0][23]__20" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Info (19000): Inferred 1 megafunctions from design logic
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[3].core|mem_unit|dcache|[3].bank|miss_resrv|altsyncram:addr_table[0][23]__20"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 24
|
|
Info (286033): Parameter WIDTHAD_A set to 3
|
|
Info (286033): Parameter NUMWORDS_A set to 8
|
|
Info (286033): Parameter WIDTH_B set to 24
|
|
Info (286033): Parameter WIDTHAD_B set to 3
|
|
Info (286033): Parameter NUMWORDS_B set to 8
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[0].core|mem_unit|icache|[0].bank|miss_resrv|altsyncram:addr_table[0][25]__21" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Info (19000): Inferred 1 megafunctions from design logic
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[0].core|mem_unit|icache|[0].bank|miss_resrv|altsyncram:addr_table[0][25]__21"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 26
|
|
Info (286033): Parameter WIDTHAD_A set to 2
|
|
Info (286033): Parameter NUMWORDS_A set to 4
|
|
Info (286033): Parameter WIDTH_B set to 26
|
|
Info (286033): Parameter WIDTHAD_B set to 2
|
|
Info (286033): Parameter NUMWORDS_B set to 4
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[0].core|mem_unit|dcache|[0].bank|miss_resrv|altsyncram:addr_table[0][23]__22" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Info (19000): Inferred 1 megafunctions from design logic
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[0].core|mem_unit|dcache|[0].bank|miss_resrv|altsyncram:addr_table[0][23]__22"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 24
|
|
Info (286033): Parameter WIDTHAD_A set to 3
|
|
Info (286033): Parameter NUMWORDS_A set to 8
|
|
Info (286033): Parameter WIDTH_B set to 24
|
|
Info (286033): Parameter WIDTHAD_B set to 3
|
|
Info (286033): Parameter NUMWORDS_B set to 8
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[0].core|mem_unit|dcache|[1].bank|miss_resrv|altsyncram:addr_table[0][23]__23" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Info (19000): Inferred 1 megafunctions from design logic
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[0].core|mem_unit|dcache|[1].bank|miss_resrv|altsyncram:addr_table[0][23]__23"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 24
|
|
Info (286033): Parameter WIDTHAD_A set to 3
|
|
Info (286033): Parameter NUMWORDS_A set to 8
|
|
Info (286033): Parameter WIDTH_B set to 24
|
|
Info (286033): Parameter WIDTHAD_B set to 3
|
|
Info (286033): Parameter NUMWORDS_B set to 8
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[0].core|mem_unit|dcache|[2].bank|miss_resrv|altsyncram:addr_table[0][23]__24" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Info (19000): Inferred 1 megafunctions from design logic
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[0].core|mem_unit|dcache|[2].bank|miss_resrv|altsyncram:addr_table[0][23]__24"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 24
|
|
Info (286033): Parameter WIDTHAD_A set to 3
|
|
Info (286033): Parameter NUMWORDS_A set to 8
|
|
Info (286033): Parameter WIDTH_B set to 24
|
|
Info (286033): Parameter WIDTHAD_B set to 3
|
|
Info (286033): Parameter NUMWORDS_B set to 8
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[0].core|mem_unit|dcache|[3].bank|miss_resrv|altsyncram:addr_table[0][23]__25" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Info (19000): Inferred 1 megafunctions from design logic
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[0].core|mem_unit|dcache|[3].bank|miss_resrv|altsyncram:addr_table[0][23]__25"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 24
|
|
Info (286033): Parameter WIDTHAD_A set to 3
|
|
Info (286033): Parameter NUMWORDS_A set to 8
|
|
Info (286033): Parameter WIDTH_B set to 24
|
|
Info (286033): Parameter WIDTHAD_B set to 3
|
|
Info (286033): Parameter NUMWORDS_B set to 8
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[1].core|mem_unit|icache|[0].bank|miss_resrv|altsyncram:addr_table[0][25]__26" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Info (19000): Inferred 1 megafunctions from design logic
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[1].core|mem_unit|icache|[0].bank|miss_resrv|altsyncram:addr_table[0][25]__26"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 26
|
|
Info (286033): Parameter WIDTHAD_A set to 2
|
|
Info (286033): Parameter NUMWORDS_A set to 4
|
|
Info (286033): Parameter WIDTH_B set to 26
|
|
Info (286033): Parameter WIDTHAD_B set to 2
|
|
Info (286033): Parameter NUMWORDS_B set to 4
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[1].core|mem_unit|dcache|[0].bank|miss_resrv|altsyncram:addr_table[0][23]__27" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Info (19000): Inferred 1 megafunctions from design logic
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[1].core|mem_unit|dcache|[0].bank|miss_resrv|altsyncram:addr_table[0][23]__27"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 24
|
|
Info (286033): Parameter WIDTHAD_A set to 3
|
|
Info (286033): Parameter NUMWORDS_A set to 8
|
|
Info (286033): Parameter WIDTH_B set to 24
|
|
Info (286033): Parameter WIDTHAD_B set to 3
|
|
Info (286033): Parameter NUMWORDS_B set to 8
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[1].core|mem_unit|dcache|[1].bank|miss_resrv|altsyncram:addr_table[0][23]__28" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Info (19000): Inferred 1 megafunctions from design logic
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[1].core|mem_unit|dcache|[1].bank|miss_resrv|altsyncram:addr_table[0][23]__28"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 24
|
|
Info (286033): Parameter WIDTHAD_A set to 3
|
|
Info (286033): Parameter NUMWORDS_A set to 8
|
|
Info (286033): Parameter WIDTH_B set to 24
|
|
Info (286033): Parameter WIDTHAD_B set to 3
|
|
Info (286033): Parameter NUMWORDS_B set to 8
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[1].core|mem_unit|dcache|[2].bank|miss_resrv|altsyncram:addr_table[0][23]__29" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Info (19000): Inferred 1 megafunctions from design logic
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[1].core|mem_unit|dcache|[2].bank|miss_resrv|altsyncram:addr_table[0][23]__29"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 24
|
|
Info (286033): Parameter WIDTHAD_A set to 3
|
|
Info (286033): Parameter NUMWORDS_A set to 8
|
|
Info (286033): Parameter WIDTH_B set to 24
|
|
Info (286033): Parameter WIDTHAD_B set to 3
|
|
Info (286033): Parameter NUMWORDS_B set to 8
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[1].core|mem_unit|dcache|[3].bank|miss_resrv|altsyncram:addr_table[0][23]__30" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Info (19000): Inferred 1 megafunctions from design logic
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[1].core|mem_unit|dcache|[3].bank|miss_resrv|altsyncram:addr_table[0][23]__30"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 24
|
|
Info (286033): Parameter WIDTHAD_A set to 3
|
|
Info (286033): Parameter NUMWORDS_A set to 8
|
|
Info (286033): Parameter WIDTH_B set to 24
|
|
Info (286033): Parameter WIDTHAD_B set to 3
|
|
Info (286033): Parameter NUMWORDS_B set to 8
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[2].core|mem_unit|icache|[0].bank|miss_resrv|altsyncram:addr_table[0][25]__31" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Info (19000): Inferred 1 megafunctions from design logic
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[2].core|mem_unit|icache|[0].bank|miss_resrv|altsyncram:addr_table[0][25]__31"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 26
|
|
Info (286033): Parameter WIDTHAD_A set to 2
|
|
Info (286033): Parameter NUMWORDS_A set to 4
|
|
Info (286033): Parameter WIDTH_B set to 26
|
|
Info (286033): Parameter WIDTHAD_B set to 2
|
|
Info (286033): Parameter NUMWORDS_B set to 4
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[2].core|mem_unit|dcache|[0].bank|miss_resrv|altsyncram:addr_table[0][23]__32" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Info (19000): Inferred 1 megafunctions from design logic
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[2].core|mem_unit|dcache|[0].bank|miss_resrv|altsyncram:addr_table[0][23]__32"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 24
|
|
Info (286033): Parameter WIDTHAD_A set to 3
|
|
Info (286033): Parameter NUMWORDS_A set to 8
|
|
Info (286033): Parameter WIDTH_B set to 24
|
|
Info (286033): Parameter WIDTHAD_B set to 3
|
|
Info (286033): Parameter NUMWORDS_B set to 8
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[2].core|mem_unit|dcache|[1].bank|miss_resrv|altsyncram:addr_table[0][23]__33" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Info (19000): Inferred 1 megafunctions from design logic
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[2].core|mem_unit|dcache|[1].bank|miss_resrv|altsyncram:addr_table[0][23]__33"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 24
|
|
Info (286033): Parameter WIDTHAD_A set to 3
|
|
Info (286033): Parameter NUMWORDS_A set to 8
|
|
Info (286033): Parameter WIDTH_B set to 24
|
|
Info (286033): Parameter WIDTHAD_B set to 3
|
|
Info (286033): Parameter NUMWORDS_B set to 8
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[2].core|mem_unit|dcache|[2].bank|miss_resrv|altsyncram:addr_table[0][23]__34" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Info (19000): Inferred 1 megafunctions from design logic
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[2].core|mem_unit|dcache|[2].bank|miss_resrv|altsyncram:addr_table[0][23]__34"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 24
|
|
Info (286033): Parameter WIDTHAD_A set to 3
|
|
Info (286033): Parameter NUMWORDS_A set to 8
|
|
Info (286033): Parameter WIDTH_B set to 24
|
|
Info (286033): Parameter WIDTHAD_B set to 3
|
|
Info (286033): Parameter NUMWORDS_B set to 8
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[2].core|mem_unit|dcache|[3].bank|miss_resrv|altsyncram:addr_table[0][23]__35" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Info (19000): Inferred 1 megafunctions from design logic
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[2].core|mem_unit|dcache|[3].bank|miss_resrv|altsyncram:addr_table[0][23]__35"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 24
|
|
Info (286033): Parameter WIDTHAD_A set to 3
|
|
Info (286033): Parameter NUMWORDS_A set to 8
|
|
Info (286033): Parameter WIDTH_B set to 24
|
|
Info (286033): Parameter WIDTHAD_B set to 3
|
|
Info (286033): Parameter NUMWORDS_B set to 8
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[3].core|mem_unit|icache|[0].bank|miss_resrv|altsyncram:addr_table[0][25]__36" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Info (19000): Inferred 1 megafunctions from design logic
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[3].core|mem_unit|icache|[0].bank|miss_resrv|altsyncram:addr_table[0][25]__36"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 26
|
|
Info (286033): Parameter WIDTHAD_A set to 2
|
|
Info (286033): Parameter NUMWORDS_A set to 4
|
|
Info (286033): Parameter WIDTH_B set to 26
|
|
Info (286033): Parameter WIDTHAD_B set to 2
|
|
Info (286033): Parameter NUMWORDS_B set to 4
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[3].core|mem_unit|dcache|[0].bank|miss_resrv|altsyncram:addr_table[0][23]__37" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Info (19000): Inferred 1 megafunctions from design logic
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[3].core|mem_unit|dcache|[0].bank|miss_resrv|altsyncram:addr_table[0][23]__37"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 24
|
|
Info (286033): Parameter WIDTHAD_A set to 3
|
|
Info (286033): Parameter NUMWORDS_A set to 8
|
|
Info (286033): Parameter WIDTH_B set to 24
|
|
Info (286033): Parameter WIDTHAD_B set to 3
|
|
Info (286033): Parameter NUMWORDS_B set to 8
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[3].core|mem_unit|dcache|[1].bank|miss_resrv|altsyncram:addr_table[0][23]__38" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Info (19000): Inferred 1 megafunctions from design logic
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[3].core|mem_unit|dcache|[1].bank|miss_resrv|altsyncram:addr_table[0][23]__38"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 24
|
|
Info (286033): Parameter WIDTHAD_A set to 3
|
|
Info (286033): Parameter NUMWORDS_A set to 8
|
|
Info (286033): Parameter WIDTH_B set to 24
|
|
Info (286033): Parameter WIDTHAD_B set to 3
|
|
Info (286033): Parameter NUMWORDS_B set to 8
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[3].core|mem_unit|dcache|[2].bank|miss_resrv|altsyncram:addr_table[0][23]__39" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Info (19000): Inferred 1 megafunctions from design logic
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[3].core|mem_unit|dcache|[2].bank|miss_resrv|altsyncram:addr_table[0][23]__39"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 24
|
|
Info (286033): Parameter WIDTHAD_A set to 3
|
|
Info (286033): Parameter NUMWORDS_A set to 8
|
|
Info (286033): Parameter WIDTH_B set to 24
|
|
Info (286033): Parameter WIDTHAD_B set to 3
|
|
Info (286033): Parameter NUMWORDS_B set to 8
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[3].core|mem_unit|dcache|[3].bank|miss_resrv|altsyncram:addr_table[0][23]__40" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Info (19000): Inferred 1 megafunctions from design logic
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[3].core|mem_unit|dcache|[3].bank|miss_resrv|altsyncram:addr_table[0][23]__40"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 24
|
|
Info (286033): Parameter WIDTHAD_A set to 3
|
|
Info (286033): Parameter NUMWORDS_A set to 8
|
|
Info (286033): Parameter WIDTH_B set to 24
|
|
Info (286033): Parameter WIDTHAD_B set to 3
|
|
Info (286033): Parameter NUMWORDS_B set to 8
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|mem_unit|icache|[0].bank|miss_resrv|altsyncram:addr_table[0][25]__41" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Info (19000): Inferred 1 megafunctions from design logic
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|mem_unit|icache|[0].bank|miss_resrv|altsyncram:addr_table[0][25]__41"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 26
|
|
Info (286033): Parameter WIDTHAD_A set to 2
|
|
Info (286033): Parameter NUMWORDS_A set to 4
|
|
Info (286033): Parameter WIDTH_B set to 26
|
|
Info (286033): Parameter WIDTHAD_B set to 2
|
|
Info (286033): Parameter NUMWORDS_B set to 4
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|mem_unit|dcache|[0].bank|miss_resrv|altsyncram:addr_table[0][23]__42" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Info (19000): Inferred 1 megafunctions from design logic
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|mem_unit|dcache|[0].bank|miss_resrv|altsyncram:addr_table[0][23]__42"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 24
|
|
Info (286033): Parameter WIDTHAD_A set to 3
|
|
Info (286033): Parameter NUMWORDS_A set to 8
|
|
Info (286033): Parameter WIDTH_B set to 24
|
|
Info (286033): Parameter WIDTHAD_B set to 3
|
|
Info (286033): Parameter NUMWORDS_B set to 8
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|mem_unit|dcache|[1].bank|miss_resrv|altsyncram:addr_table[0][23]__43" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Info (19000): Inferred 1 megafunctions from design logic
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|mem_unit|dcache|[1].bank|miss_resrv|altsyncram:addr_table[0][23]__43"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 24
|
|
Info (286033): Parameter WIDTHAD_A set to 3
|
|
Info (286033): Parameter NUMWORDS_A set to 8
|
|
Info (286033): Parameter WIDTH_B set to 24
|
|
Info (286033): Parameter WIDTHAD_B set to 3
|
|
Info (286033): Parameter NUMWORDS_B set to 8
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|mem_unit|dcache|[2].bank|miss_resrv|altsyncram:addr_table[0][23]__44" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Info (19000): Inferred 1 megafunctions from design logic
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|mem_unit|dcache|[2].bank|miss_resrv|altsyncram:addr_table[0][23]__44"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 24
|
|
Info (286033): Parameter WIDTHAD_A set to 3
|
|
Info (286033): Parameter NUMWORDS_A set to 8
|
|
Info (286033): Parameter WIDTH_B set to 24
|
|
Info (286033): Parameter WIDTHAD_B set to 3
|
|
Info (286033): Parameter NUMWORDS_B set to 8
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|mem_unit|dcache|[3].bank|miss_resrv|altsyncram:addr_table[0][23]__45" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Info (19000): Inferred 1 megafunctions from design logic
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|mem_unit|dcache|[3].bank|miss_resrv|altsyncram:addr_table[0][23]__45"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 24
|
|
Info (286033): Parameter WIDTHAD_A set to 3
|
|
Info (286033): Parameter NUMWORDS_A set to 8
|
|
Info (286033): Parameter WIDTH_B set to 24
|
|
Info (286033): Parameter WIDTHAD_B set to 3
|
|
Info (286033): Parameter NUMWORDS_B set to 8
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[1].core|mem_unit|icache|[0].bank|miss_resrv|altsyncram:addr_table[0][25]__46" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Info (19000): Inferred 1 megafunctions from design logic
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[1].core|mem_unit|icache|[0].bank|miss_resrv|altsyncram:addr_table[0][25]__46"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 26
|
|
Info (286033): Parameter WIDTHAD_A set to 2
|
|
Info (286033): Parameter NUMWORDS_A set to 4
|
|
Info (286033): Parameter WIDTH_B set to 26
|
|
Info (286033): Parameter WIDTHAD_B set to 2
|
|
Info (286033): Parameter NUMWORDS_B set to 4
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[1].core|mem_unit|dcache|[0].bank|miss_resrv|altsyncram:addr_table[0][23]__47" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Info (19000): Inferred 1 megafunctions from design logic
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[1].core|mem_unit|dcache|[0].bank|miss_resrv|altsyncram:addr_table[0][23]__47"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 24
|
|
Info (286033): Parameter WIDTHAD_A set to 3
|
|
Info (286033): Parameter NUMWORDS_A set to 8
|
|
Info (286033): Parameter WIDTH_B set to 24
|
|
Info (286033): Parameter WIDTHAD_B set to 3
|
|
Info (286033): Parameter NUMWORDS_B set to 8
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[1].core|mem_unit|dcache|[1].bank|miss_resrv|altsyncram:addr_table[0][23]__48" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Info (19000): Inferred 1 megafunctions from design logic
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[1].core|mem_unit|dcache|[1].bank|miss_resrv|altsyncram:addr_table[0][23]__48"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 24
|
|
Info (286033): Parameter WIDTHAD_A set to 3
|
|
Info (286033): Parameter NUMWORDS_A set to 8
|
|
Info (286033): Parameter WIDTH_B set to 24
|
|
Info (286033): Parameter WIDTHAD_B set to 3
|
|
Info (286033): Parameter NUMWORDS_B set to 8
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[1].core|mem_unit|dcache|[2].bank|miss_resrv|altsyncram:addr_table[0][23]__49" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Info (19000): Inferred 1 megafunctions from design logic
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[1].core|mem_unit|dcache|[2].bank|miss_resrv|altsyncram:addr_table[0][23]__49"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 24
|
|
Info (286033): Parameter WIDTHAD_A set to 3
|
|
Info (286033): Parameter NUMWORDS_A set to 8
|
|
Info (286033): Parameter WIDTH_B set to 24
|
|
Info (286033): Parameter WIDTHAD_B set to 3
|
|
Info (286033): Parameter NUMWORDS_B set to 8
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[1].core|mem_unit|dcache|[3].bank|miss_resrv|altsyncram:addr_table[0][23]__50" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Info (19000): Inferred 1 megafunctions from design logic
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[1].core|mem_unit|dcache|[3].bank|miss_resrv|altsyncram:addr_table[0][23]__50"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 24
|
|
Info (286033): Parameter WIDTHAD_A set to 3
|
|
Info (286033): Parameter NUMWORDS_A set to 8
|
|
Info (286033): Parameter WIDTH_B set to 24
|
|
Info (286033): Parameter WIDTHAD_B set to 3
|
|
Info (286033): Parameter NUMWORDS_B set to 8
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[2].core|mem_unit|icache|[0].bank|miss_resrv|altsyncram:addr_table[0][25]__51" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Info (19000): Inferred 1 megafunctions from design logic
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[2].core|mem_unit|icache|[0].bank|miss_resrv|altsyncram:addr_table[0][25]__51"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 26
|
|
Info (286033): Parameter WIDTHAD_A set to 2
|
|
Info (286033): Parameter NUMWORDS_A set to 4
|
|
Info (286033): Parameter WIDTH_B set to 26
|
|
Info (286033): Parameter WIDTHAD_B set to 2
|
|
Info (286033): Parameter NUMWORDS_B set to 4
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[2].core|mem_unit|dcache|[0].bank|miss_resrv|altsyncram:addr_table[0][23]__52" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Info (19000): Inferred 1 megafunctions from design logic
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[2].core|mem_unit|dcache|[0].bank|miss_resrv|altsyncram:addr_table[0][23]__52"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 24
|
|
Info (286033): Parameter WIDTHAD_A set to 3
|
|
Info (286033): Parameter NUMWORDS_A set to 8
|
|
Info (286033): Parameter WIDTH_B set to 24
|
|
Info (286033): Parameter WIDTHAD_B set to 3
|
|
Info (286033): Parameter NUMWORDS_B set to 8
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[2].core|mem_unit|dcache|[1].bank|miss_resrv|altsyncram:addr_table[0][23]__53" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Info (19000): Inferred 1 megafunctions from design logic
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[2].core|mem_unit|dcache|[1].bank|miss_resrv|altsyncram:addr_table[0][23]__53"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 24
|
|
Info (286033): Parameter WIDTHAD_A set to 3
|
|
Info (286033): Parameter NUMWORDS_A set to 8
|
|
Info (286033): Parameter WIDTH_B set to 24
|
|
Info (286033): Parameter WIDTHAD_B set to 3
|
|
Info (286033): Parameter NUMWORDS_B set to 8
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[2].core|mem_unit|dcache|[2].bank|miss_resrv|altsyncram:addr_table[0][23]__54" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Info (19000): Inferred 1 megafunctions from design logic
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[2].core|mem_unit|dcache|[2].bank|miss_resrv|altsyncram:addr_table[0][23]__54"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 24
|
|
Info (286033): Parameter WIDTHAD_A set to 3
|
|
Info (286033): Parameter NUMWORDS_A set to 8
|
|
Info (286033): Parameter WIDTH_B set to 24
|
|
Info (286033): Parameter WIDTHAD_B set to 3
|
|
Info (286033): Parameter NUMWORDS_B set to 8
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[2].core|mem_unit|dcache|[3].bank|miss_resrv|altsyncram:addr_table[0][23]__55" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Info (19000): Inferred 1 megafunctions from design logic
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[2].core|mem_unit|dcache|[3].bank|miss_resrv|altsyncram:addr_table[0][23]__55"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 24
|
|
Info (286033): Parameter WIDTHAD_A set to 3
|
|
Info (286033): Parameter NUMWORDS_A set to 8
|
|
Info (286033): Parameter WIDTH_B set to 24
|
|
Info (286033): Parameter WIDTHAD_B set to 3
|
|
Info (286033): Parameter NUMWORDS_B set to 8
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[3].core|mem_unit|icache|[0].bank|miss_resrv|altsyncram:addr_table[0][25]__56" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Info (19000): Inferred 1 megafunctions from design logic
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[3].core|mem_unit|icache|[0].bank|miss_resrv|altsyncram:addr_table[0][25]__56"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 26
|
|
Info (286033): Parameter WIDTHAD_A set to 2
|
|
Info (286033): Parameter NUMWORDS_A set to 4
|
|
Info (286033): Parameter WIDTH_B set to 26
|
|
Info (286033): Parameter WIDTHAD_B set to 2
|
|
Info (286033): Parameter NUMWORDS_B set to 4
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[3].core|mem_unit|dcache|[0].bank|miss_resrv|altsyncram:addr_table[0][23]__57" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Info (19000): Inferred 1 megafunctions from design logic
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[3].core|mem_unit|dcache|[0].bank|miss_resrv|altsyncram:addr_table[0][23]__57"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 24
|
|
Info (286033): Parameter WIDTHAD_A set to 3
|
|
Info (286033): Parameter NUMWORDS_A set to 8
|
|
Info (286033): Parameter WIDTH_B set to 24
|
|
Info (286033): Parameter WIDTHAD_B set to 3
|
|
Info (286033): Parameter NUMWORDS_B set to 8
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[3].core|mem_unit|dcache|[1].bank|miss_resrv|altsyncram:addr_table[0][23]__58" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Info (19000): Inferred 1 megafunctions from design logic
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[3].core|mem_unit|dcache|[1].bank|miss_resrv|altsyncram:addr_table[0][23]__58"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 24
|
|
Info (286033): Parameter WIDTHAD_A set to 3
|
|
Info (286033): Parameter NUMWORDS_A set to 8
|
|
Info (286033): Parameter WIDTH_B set to 24
|
|
Info (286033): Parameter WIDTHAD_B set to 3
|
|
Info (286033): Parameter NUMWORDS_B set to 8
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[3].core|mem_unit|dcache|[2].bank|miss_resrv|altsyncram:addr_table[0][23]__59" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Info (19000): Inferred 1 megafunctions from design logic
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[3].core|mem_unit|dcache|[2].bank|miss_resrv|altsyncram:addr_table[0][23]__59"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 24
|
|
Info (286033): Parameter WIDTHAD_A set to 3
|
|
Info (286033): Parameter NUMWORDS_A set to 8
|
|
Info (286033): Parameter WIDTH_B set to 24
|
|
Info (286033): Parameter WIDTHAD_B set to 3
|
|
Info (286033): Parameter NUMWORDS_B set to 8
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[3].core|mem_unit|dcache|[3].bank|miss_resrv|altsyncram:addr_table[0][23]__60" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Info (19000): Inferred 1 megafunctions from design logic
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[3].core|mem_unit|dcache|[3].bank|miss_resrv|altsyncram:addr_table[0][23]__60"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 24
|
|
Info (286033): Parameter WIDTHAD_A set to 3
|
|
Info (286033): Parameter NUMWORDS_A set to 8
|
|
Info (286033): Parameter WIDTH_B set to 24
|
|
Info (286033): Parameter WIDTHAD_B set to 3
|
|
Info (286033): Parameter NUMWORDS_B set to 8
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[0].core|mem_unit|icache|[0].bank|miss_resrv|altsyncram:addr_table[0][25]__61" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Info (19000): Inferred 1 megafunctions from design logic
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[0].core|mem_unit|icache|[0].bank|miss_resrv|altsyncram:addr_table[0][25]__61"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 26
|
|
Info (286033): Parameter WIDTHAD_A set to 2
|
|
Info (286033): Parameter NUMWORDS_A set to 4
|
|
Info (286033): Parameter WIDTH_B set to 26
|
|
Info (286033): Parameter WIDTHAD_B set to 2
|
|
Info (286033): Parameter NUMWORDS_B set to 4
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[0].core|mem_unit|dcache|[0].bank|miss_resrv|altsyncram:addr_table[0][23]__62" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Info (19000): Inferred 1 megafunctions from design logic
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[0].core|mem_unit|dcache|[0].bank|miss_resrv|altsyncram:addr_table[0][23]__62"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 24
|
|
Info (286033): Parameter WIDTHAD_A set to 3
|
|
Info (286033): Parameter NUMWORDS_A set to 8
|
|
Info (286033): Parameter WIDTH_B set to 24
|
|
Info (286033): Parameter WIDTHAD_B set to 3
|
|
Info (286033): Parameter NUMWORDS_B set to 8
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[0].core|mem_unit|dcache|[1].bank|miss_resrv|altsyncram:addr_table[0][23]__63" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Info (19000): Inferred 1 megafunctions from design logic
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[0].core|mem_unit|dcache|[1].bank|miss_resrv|altsyncram:addr_table[0][23]__63"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 24
|
|
Info (286033): Parameter WIDTHAD_A set to 3
|
|
Info (286033): Parameter NUMWORDS_A set to 8
|
|
Info (286033): Parameter WIDTH_B set to 24
|
|
Info (286033): Parameter WIDTHAD_B set to 3
|
|
Info (286033): Parameter NUMWORDS_B set to 8
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[0].core|mem_unit|dcache|[2].bank|miss_resrv|altsyncram:addr_table[0][23]__64" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Info (19000): Inferred 1 megafunctions from design logic
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[0].core|mem_unit|dcache|[2].bank|miss_resrv|altsyncram:addr_table[0][23]__64"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 24
|
|
Info (286033): Parameter WIDTHAD_A set to 3
|
|
Info (286033): Parameter NUMWORDS_A set to 8
|
|
Info (286033): Parameter WIDTH_B set to 24
|
|
Info (286033): Parameter WIDTHAD_B set to 3
|
|
Info (286033): Parameter NUMWORDS_B set to 8
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[0].core|mem_unit|dcache|[3].bank|miss_resrv|altsyncram:addr_table[0][23]__65" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Info (19000): Inferred 1 megafunctions from design logic
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[0].core|mem_unit|dcache|[3].bank|miss_resrv|altsyncram:addr_table[0][23]__65"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 24
|
|
Info (286033): Parameter WIDTHAD_A set to 3
|
|
Info (286033): Parameter NUMWORDS_A set to 8
|
|
Info (286033): Parameter WIDTH_B set to 24
|
|
Info (286033): Parameter WIDTHAD_B set to 3
|
|
Info (286033): Parameter NUMWORDS_B set to 8
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[1].core|mem_unit|icache|[0].bank|miss_resrv|altsyncram:addr_table[0][25]__66" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Info (19000): Inferred 1 megafunctions from design logic
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[1].core|mem_unit|icache|[0].bank|miss_resrv|altsyncram:addr_table[0][25]__66"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 26
|
|
Info (286033): Parameter WIDTHAD_A set to 2
|
|
Info (286033): Parameter NUMWORDS_A set to 4
|
|
Info (286033): Parameter WIDTH_B set to 26
|
|
Info (286033): Parameter WIDTHAD_B set to 2
|
|
Info (286033): Parameter NUMWORDS_B set to 4
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[1].core|mem_unit|dcache|[0].bank|miss_resrv|altsyncram:addr_table[0][23]__67" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Info (19000): Inferred 1 megafunctions from design logic
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[1].core|mem_unit|dcache|[0].bank|miss_resrv|altsyncram:addr_table[0][23]__67"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 24
|
|
Info (286033): Parameter WIDTHAD_A set to 3
|
|
Info (286033): Parameter NUMWORDS_A set to 8
|
|
Info (286033): Parameter WIDTH_B set to 24
|
|
Info (286033): Parameter WIDTHAD_B set to 3
|
|
Info (286033): Parameter NUMWORDS_B set to 8
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[1].core|mem_unit|dcache|[1].bank|miss_resrv|altsyncram:addr_table[0][23]__68" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Info (19000): Inferred 1 megafunctions from design logic
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[1].core|mem_unit|dcache|[1].bank|miss_resrv|altsyncram:addr_table[0][23]__68"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 24
|
|
Info (286033): Parameter WIDTHAD_A set to 3
|
|
Info (286033): Parameter NUMWORDS_A set to 8
|
|
Info (286033): Parameter WIDTH_B set to 24
|
|
Info (286033): Parameter WIDTHAD_B set to 3
|
|
Info (286033): Parameter NUMWORDS_B set to 8
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[1].core|mem_unit|dcache|[2].bank|miss_resrv|altsyncram:addr_table[0][23]__69" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Info (19000): Inferred 1 megafunctions from design logic
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[1].core|mem_unit|dcache|[2].bank|miss_resrv|altsyncram:addr_table[0][23]__69"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 24
|
|
Info (286033): Parameter WIDTHAD_A set to 3
|
|
Info (286033): Parameter NUMWORDS_A set to 8
|
|
Info (286033): Parameter WIDTH_B set to 24
|
|
Info (286033): Parameter WIDTHAD_B set to 3
|
|
Info (286033): Parameter NUMWORDS_B set to 8
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[1].core|mem_unit|dcache|[3].bank|miss_resrv|altsyncram:addr_table[0][23]__70" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Info (19000): Inferred 1 megafunctions from design logic
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[1].core|mem_unit|dcache|[3].bank|miss_resrv|altsyncram:addr_table[0][23]__70"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 24
|
|
Info (286033): Parameter WIDTHAD_A set to 3
|
|
Info (286033): Parameter NUMWORDS_A set to 8
|
|
Info (286033): Parameter WIDTH_B set to 24
|
|
Info (286033): Parameter WIDTHAD_B set to 3
|
|
Info (286033): Parameter NUMWORDS_B set to 8
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[2].core|mem_unit|icache|[0].bank|miss_resrv|altsyncram:addr_table[0][25]__71" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Info (19000): Inferred 1 megafunctions from design logic
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[2].core|mem_unit|icache|[0].bank|miss_resrv|altsyncram:addr_table[0][25]__71"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 26
|
|
Info (286033): Parameter WIDTHAD_A set to 2
|
|
Info (286033): Parameter NUMWORDS_A set to 4
|
|
Info (286033): Parameter WIDTH_B set to 26
|
|
Info (286033): Parameter WIDTHAD_B set to 2
|
|
Info (286033): Parameter NUMWORDS_B set to 4
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[2].core|mem_unit|dcache|[0].bank|miss_resrv|altsyncram:addr_table[0][23]__72" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Info (19000): Inferred 1 megafunctions from design logic
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[2].core|mem_unit|dcache|[0].bank|miss_resrv|altsyncram:addr_table[0][23]__72"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 24
|
|
Info (286033): Parameter WIDTHAD_A set to 3
|
|
Info (286033): Parameter NUMWORDS_A set to 8
|
|
Info (286033): Parameter WIDTH_B set to 24
|
|
Info (286033): Parameter WIDTHAD_B set to 3
|
|
Info (286033): Parameter NUMWORDS_B set to 8
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[2].core|mem_unit|dcache|[1].bank|miss_resrv|altsyncram:addr_table[0][23]__73" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Info (19000): Inferred 1 megafunctions from design logic
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[2].core|mem_unit|dcache|[1].bank|miss_resrv|altsyncram:addr_table[0][23]__73"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 24
|
|
Info (286033): Parameter WIDTHAD_A set to 3
|
|
Info (286033): Parameter NUMWORDS_A set to 8
|
|
Info (286033): Parameter WIDTH_B set to 24
|
|
Info (286033): Parameter WIDTHAD_B set to 3
|
|
Info (286033): Parameter NUMWORDS_B set to 8
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[2].core|mem_unit|dcache|[2].bank|miss_resrv|altsyncram:addr_table[0][23]__74" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Info (19000): Inferred 1 megafunctions from design logic
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[2].core|mem_unit|dcache|[2].bank|miss_resrv|altsyncram:addr_table[0][23]__74"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 24
|
|
Info (286033): Parameter WIDTHAD_A set to 3
|
|
Info (286033): Parameter NUMWORDS_A set to 8
|
|
Info (286033): Parameter WIDTH_B set to 24
|
|
Info (286033): Parameter WIDTHAD_B set to 3
|
|
Info (286033): Parameter NUMWORDS_B set to 8
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[2].core|mem_unit|dcache|[3].bank|miss_resrv|altsyncram:addr_table[0][23]__75" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Info (19000): Inferred 1 megafunctions from design logic
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[2].core|mem_unit|dcache|[3].bank|miss_resrv|altsyncram:addr_table[0][23]__75"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 24
|
|
Info (286033): Parameter WIDTHAD_A set to 3
|
|
Info (286033): Parameter NUMWORDS_A set to 8
|
|
Info (286033): Parameter WIDTH_B set to 24
|
|
Info (286033): Parameter WIDTHAD_B set to 3
|
|
Info (286033): Parameter NUMWORDS_B set to 8
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[3].core|mem_unit|icache|[0].bank|miss_resrv|altsyncram:addr_table[0][25]__76" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Info (19000): Inferred 1 megafunctions from design logic
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[3].core|mem_unit|icache|[0].bank|miss_resrv|altsyncram:addr_table[0][25]__76"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 26
|
|
Info (286033): Parameter WIDTHAD_A set to 2
|
|
Info (286033): Parameter NUMWORDS_A set to 4
|
|
Info (286033): Parameter WIDTH_B set to 26
|
|
Info (286033): Parameter WIDTHAD_B set to 2
|
|
Info (286033): Parameter NUMWORDS_B set to 4
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[3].core|mem_unit|dcache|[0].bank|miss_resrv|altsyncram:addr_table[0][23]__77" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Info (19000): Inferred 1 megafunctions from design logic
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[3].core|mem_unit|dcache|[0].bank|miss_resrv|altsyncram:addr_table[0][23]__77"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 24
|
|
Info (286033): Parameter WIDTHAD_A set to 3
|
|
Info (286033): Parameter NUMWORDS_A set to 8
|
|
Info (286033): Parameter WIDTH_B set to 24
|
|
Info (286033): Parameter WIDTHAD_B set to 3
|
|
Info (286033): Parameter NUMWORDS_B set to 8
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[3].core|mem_unit|dcache|[1].bank|miss_resrv|altsyncram:addr_table[0][23]__78" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Info (19000): Inferred 1 megafunctions from design logic
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[3].core|mem_unit|dcache|[1].bank|miss_resrv|altsyncram:addr_table[0][23]__78"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 24
|
|
Info (286033): Parameter WIDTHAD_A set to 3
|
|
Info (286033): Parameter NUMWORDS_A set to 8
|
|
Info (286033): Parameter WIDTH_B set to 24
|
|
Info (286033): Parameter WIDTHAD_B set to 3
|
|
Info (286033): Parameter NUMWORDS_B set to 8
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[3].core|mem_unit|dcache|[2].bank|miss_resrv|altsyncram:addr_table[0][23]__79" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Info (19000): Inferred 1 megafunctions from design logic
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[3].core|mem_unit|dcache|[2].bank|miss_resrv|altsyncram:addr_table[0][23]__79"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 24
|
|
Info (286033): Parameter WIDTHAD_A set to 3
|
|
Info (286033): Parameter NUMWORDS_A set to 8
|
|
Info (286033): Parameter WIDTH_B set to 24
|
|
Info (286033): Parameter WIDTHAD_B set to 3
|
|
Info (286033): Parameter NUMWORDS_B set to 8
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[3].core|mem_unit|dcache|[3].bank|miss_resrv|altsyncram:addr_table[0][23]__80" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Info (19000): Inferred 1 megafunctions from design logic
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[3].core|mem_unit|dcache|[3].bank|miss_resrv|altsyncram:addr_table[0][23]__80"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 24
|
|
Info (286033): Parameter WIDTHAD_A set to 3
|
|
Info (286033): Parameter NUMWORDS_A set to 8
|
|
Info (286033): Parameter WIDTH_B set to 24
|
|
Info (286033): Parameter WIDTHAD_B set to 3
|
|
Info (286033): Parameter NUMWORDS_B set to 8
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info: Found 301 design entities
|
|
Info: There are 10021 partitions after elaboration.
|
|
Info: Creating instance-specific data models and dissolving soft partitions
|
|
Info (18299): Expanding entity and wildcard assignments.
|
|
Info (18300): Expanded entity and wildcard assignments. Elapsed time: 00:00:01
|
|
Warning (14284): Synthesized away the following node(s):
|
|
Warning (14285): Synthesized away the following RAM node(s):
|
|
Warning (14320): Synthesized away node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|fifo_ram|q_b[524]" File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/tmp-clearbox/afu_default/23127/altsyncram_8qf1.tdf Line: 16810
|
|
Warning (14320): Synthesized away node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|fifo_ram|q_b[525]" File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/tmp-clearbox/afu_default/23127/altsyncram_8qf1.tdf Line: 16842
|
|
Warning (14320): Synthesized away node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|fifo_ram|q_b[526]" File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/tmp-clearbox/afu_default/23127/altsyncram_8qf1.tdf Line: 16874
|
|
Warning (14320): Synthesized away node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|fifo_ram|q_b[0]" File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/tmp-clearbox/afu_default/23127/altsyncram_2nf1.tdf Line: 42
|
|
Warning (14320): Synthesized away node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|fifo_ram|q_b[1]" File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/tmp-clearbox/afu_default/23127/altsyncram_2nf1.tdf Line: 74
|
|
Warning (14320): Synthesized away node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|fifo_ram|q_b[2]" File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/tmp-clearbox/afu_default/23127/altsyncram_2nf1.tdf Line: 106
|
|
Warning (14320): Synthesized away node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|fifo_ram|q_b[3]" File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/tmp-clearbox/afu_default/23127/altsyncram_2nf1.tdf Line: 138
|
|
Warning (14320): Synthesized away node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|fifo_ram|q_b[4]" File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/tmp-clearbox/afu_default/23127/altsyncram_2nf1.tdf Line: 170
|
|
Warning (14320): Synthesized away node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|fifo_ram|q_b[5]" File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/tmp-clearbox/afu_default/23127/altsyncram_2nf1.tdf Line: 202
|
|
Warning (14320): Synthesized away node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|fifo_ram|q_b[6]" File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/tmp-clearbox/afu_default/23127/altsyncram_2nf1.tdf Line: 234
|
|
Warning (14320): Synthesized away node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|fifo_ram|q_b[7]" File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/tmp-clearbox/afu_default/23127/altsyncram_2nf1.tdf Line: 266
|
|
Warning (14320): Synthesized away node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|fifo_ram|q_b[8]" File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/tmp-clearbox/afu_default/23127/altsyncram_2nf1.tdf Line: 298
|
|
Warning (14320): Synthesized away node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|fifo_ram|q_b[9]" File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/tmp-clearbox/afu_default/23127/altsyncram_2nf1.tdf Line: 330
|
|
Warning (14320): Synthesized away node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|fifo_ram|q_b[10]" File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/tmp-clearbox/afu_default/23127/altsyncram_2nf1.tdf Line: 362
|
|
Warning (14320): Synthesized away node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|fifo_ram|q_b[11]" File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/tmp-clearbox/afu_default/23127/altsyncram_2nf1.tdf Line: 394
|
|
Warning (14320): Synthesized away node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|fifo_ram|q_b[12]" File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/tmp-clearbox/afu_default/23127/altsyncram_2nf1.tdf Line: 426
|
|
Warning (14320): Synthesized away node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|fifo_ram|q_b[13]" File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/tmp-clearbox/afu_default/23127/altsyncram_2nf1.tdf Line: 458
|
|
Warning (14320): Synthesized away node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|fifo_ram|q_b[14]" File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/tmp-clearbox/afu_default/23127/altsyncram_2nf1.tdf Line: 490
|
|
Warning (14320): Synthesized away node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|fifo_ram|q_b[15]" File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/tmp-clearbox/afu_default/23127/altsyncram_2nf1.tdf Line: 522
|
|
Warning (14320): Synthesized away node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|fifo_ram|q_b[22]" File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/tmp-clearbox/afu_default/23127/altsyncram_2nf1.tdf Line: 746
|
|
Warning (14320): Synthesized away node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|fifo_ram|q_b[24]" File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/tmp-clearbox/afu_default/23127/altsyncram_2nf1.tdf Line: 810
|
|
Warning (14320): Synthesized away node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|fifo_ram|q_b[25]" File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/tmp-clearbox/afu_default/23127/altsyncram_2nf1.tdf Line: 842
|
|
Warning (14320): Synthesized away node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|fifo_ram|q_b[26]" File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/tmp-clearbox/afu_default/23127/altsyncram_2nf1.tdf Line: 874
|
|
Warning (14320): Synthesized away node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|fifo_ram|q_b[27]" File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/tmp-clearbox/afu_default/23127/altsyncram_2nf1.tdf Line: 906
|
|
Critical Warning (20580): Imported Partition 'green_region' has type 'PARTIAL_RECONFIGURATION_PARTITION' but it is not specified in the current project.
|
|
Info: found pre-synthesis snapshots for 3 partition(s)
|
|
Info: Synthesizing partition "root_partition"
|
|
Info: Successfully synthesized partition
|
|
Info: Synthesizing partition "root_partition_2cedade0"
|
|
Info: Successfully synthesized partition
|
|
Info: Synthesizing partition "green_region"
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[0].core|pipeline|issue|gpr_stage|[0].gpr_ram_f|mem_0_30_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[0].core|pipeline|issue|gpr_stage|[0].gpr_ram_f|mem_0_31_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[0].core|pipeline|issue|gpr_stage|[1].gpr_ram_f|mem_0_30_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[0].core|pipeline|issue|gpr_stage|[1].gpr_ram_f|mem_0_31_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[0].core|pipeline|issue|gpr_stage|[2].gpr_ram_f|mem_0_30_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[0].core|pipeline|issue|gpr_stage|[2].gpr_ram_f|mem_0_31_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[0].core|pipeline|issue|gpr_stage|[3].gpr_ram_f|mem_0_30_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[0].core|pipeline|issue|gpr_stage|[3].gpr_ram_f|mem_0_31_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[0].core|mem_unit|icache|[0].bank|tag_access|tag_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[0].core|mem_unit|icache|[0].bank|data_access|data_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[0].core|mem_unit|dcache|[0].bank|tag_access|tag_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[0].core|mem_unit|dcache|[0].bank|data_access|data_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[0].core|mem_unit|dcache|[1].bank|tag_access|tag_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[0].core|mem_unit|dcache|[1].bank|data_access|data_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[0].core|mem_unit|dcache|[2].bank|tag_access|tag_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[0].core|mem_unit|dcache|[2].bank|data_access|data_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[0].core|mem_unit|dcache|[3].bank|tag_access|tag_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[0].core|mem_unit|dcache|[3].bank|data_access|data_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[0].core|mem_unit|smem|[0].data|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[0].core|mem_unit|smem|[1].data|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[0].core|mem_unit|smem|[2].data|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[0].core|mem_unit|smem|[3].data|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[1].core|pipeline|issue|gpr_stage|[0].gpr_ram_f|mem_0_30_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[1].core|pipeline|issue|gpr_stage|[0].gpr_ram_f|mem_0_31_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[1].core|pipeline|issue|gpr_stage|[1].gpr_ram_f|mem_0_30_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[1].core|pipeline|issue|gpr_stage|[1].gpr_ram_f|mem_0_31_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[1].core|pipeline|issue|gpr_stage|[2].gpr_ram_f|mem_0_30_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[1].core|pipeline|issue|gpr_stage|[2].gpr_ram_f|mem_0_31_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[1].core|pipeline|issue|gpr_stage|[3].gpr_ram_f|mem_0_30_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[1].core|pipeline|issue|gpr_stage|[3].gpr_ram_f|mem_0_31_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[1].core|mem_unit|icache|[0].bank|tag_access|tag_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[1].core|mem_unit|icache|[0].bank|data_access|data_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[1].core|mem_unit|dcache|[0].bank|tag_access|tag_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[1].core|mem_unit|dcache|[0].bank|data_access|data_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[1].core|mem_unit|dcache|[1].bank|tag_access|tag_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[1].core|mem_unit|dcache|[1].bank|data_access|data_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[1].core|mem_unit|dcache|[2].bank|tag_access|tag_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[1].core|mem_unit|dcache|[2].bank|data_access|data_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[1].core|mem_unit|dcache|[3].bank|tag_access|tag_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[1].core|mem_unit|dcache|[3].bank|data_access|data_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[1].core|mem_unit|smem|[0].data|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[1].core|mem_unit|smem|[1].data|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[1].core|mem_unit|smem|[2].data|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[1].core|mem_unit|smem|[3].data|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[2].core|pipeline|issue|gpr_stage|[0].gpr_ram_f|mem_0_30_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[2].core|pipeline|issue|gpr_stage|[0].gpr_ram_f|mem_0_31_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[2].core|pipeline|issue|gpr_stage|[1].gpr_ram_f|mem_0_30_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[2].core|pipeline|issue|gpr_stage|[1].gpr_ram_f|mem_0_31_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[2].core|pipeline|issue|gpr_stage|[2].gpr_ram_f|mem_0_30_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[2].core|pipeline|issue|gpr_stage|[2].gpr_ram_f|mem_0_31_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[2].core|pipeline|issue|gpr_stage|[3].gpr_ram_f|mem_0_30_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[2].core|pipeline|issue|gpr_stage|[3].gpr_ram_f|mem_0_31_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[2].core|mem_unit|icache|[0].bank|tag_access|tag_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[2].core|mem_unit|icache|[0].bank|data_access|data_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[2].core|mem_unit|dcache|[0].bank|tag_access|tag_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[2].core|mem_unit|dcache|[0].bank|data_access|data_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[2].core|mem_unit|dcache|[1].bank|tag_access|tag_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[2].core|mem_unit|dcache|[1].bank|data_access|data_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[2].core|mem_unit|dcache|[2].bank|tag_access|tag_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[2].core|mem_unit|dcache|[2].bank|data_access|data_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[2].core|mem_unit|dcache|[3].bank|tag_access|tag_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[2].core|mem_unit|dcache|[3].bank|data_access|data_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[2].core|mem_unit|smem|[0].data|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[2].core|mem_unit|smem|[1].data|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[2].core|mem_unit|smem|[2].data|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[2].core|mem_unit|smem|[3].data|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[3].core|pipeline|issue|gpr_stage|[0].gpr_ram_f|mem_0_30_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[3].core|pipeline|issue|gpr_stage|[0].gpr_ram_f|mem_0_31_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[3].core|pipeline|issue|gpr_stage|[1].gpr_ram_f|mem_0_30_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[3].core|pipeline|issue|gpr_stage|[1].gpr_ram_f|mem_0_31_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[3].core|pipeline|issue|gpr_stage|[2].gpr_ram_f|mem_0_30_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[3].core|pipeline|issue|gpr_stage|[2].gpr_ram_f|mem_0_31_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[3].core|pipeline|issue|gpr_stage|[3].gpr_ram_f|mem_0_30_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[3].core|pipeline|issue|gpr_stage|[3].gpr_ram_f|mem_0_31_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[3].core|mem_unit|icache|[0].bank|tag_access|tag_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[3].core|mem_unit|icache|[0].bank|data_access|data_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[3].core|mem_unit|dcache|[0].bank|tag_access|tag_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[3].core|mem_unit|dcache|[0].bank|data_access|data_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[3].core|mem_unit|dcache|[1].bank|tag_access|tag_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[3].core|mem_unit|dcache|[1].bank|data_access|data_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[3].core|mem_unit|dcache|[2].bank|tag_access|tag_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[3].core|mem_unit|dcache|[2].bank|data_access|data_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[3].core|mem_unit|dcache|[3].bank|tag_access|tag_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[3].core|mem_unit|dcache|[3].bank|data_access|data_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[3].core|mem_unit|smem|[0].data|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[3].core|mem_unit|smem|[1].data|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[3].core|mem_unit|smem|[2].data|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[3].core|mem_unit|smem|[3].data|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[0].core|pipeline|issue|gpr_stage|[0].gpr_ram_f|mem_0_30_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[0].core|pipeline|issue|gpr_stage|[0].gpr_ram_f|mem_0_31_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[0].core|pipeline|issue|gpr_stage|[1].gpr_ram_f|mem_0_30_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[0].core|pipeline|issue|gpr_stage|[1].gpr_ram_f|mem_0_31_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[0].core|pipeline|issue|gpr_stage|[2].gpr_ram_f|mem_0_30_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[0].core|pipeline|issue|gpr_stage|[2].gpr_ram_f|mem_0_31_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[0].core|pipeline|issue|gpr_stage|[3].gpr_ram_f|mem_0_30_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[0].core|pipeline|issue|gpr_stage|[3].gpr_ram_f|mem_0_31_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[0].core|mem_unit|icache|[0].bank|tag_access|tag_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[0].core|mem_unit|icache|[0].bank|data_access|data_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[0].core|mem_unit|dcache|[0].bank|tag_access|tag_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[0].core|mem_unit|dcache|[0].bank|data_access|data_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[0].core|mem_unit|dcache|[1].bank|tag_access|tag_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[0].core|mem_unit|dcache|[1].bank|data_access|data_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[0].core|mem_unit|dcache|[2].bank|tag_access|tag_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[0].core|mem_unit|dcache|[2].bank|data_access|data_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[0].core|mem_unit|dcache|[3].bank|tag_access|tag_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[0].core|mem_unit|dcache|[3].bank|data_access|data_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[0].core|mem_unit|smem|[0].data|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[0].core|mem_unit|smem|[1].data|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[0].core|mem_unit|smem|[2].data|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[0].core|mem_unit|smem|[3].data|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[1].core|pipeline|issue|gpr_stage|[0].gpr_ram_f|mem_0_30_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[1].core|pipeline|issue|gpr_stage|[0].gpr_ram_f|mem_0_31_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[1].core|pipeline|issue|gpr_stage|[1].gpr_ram_f|mem_0_30_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[1].core|pipeline|issue|gpr_stage|[1].gpr_ram_f|mem_0_31_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[1].core|pipeline|issue|gpr_stage|[2].gpr_ram_f|mem_0_30_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[1].core|pipeline|issue|gpr_stage|[2].gpr_ram_f|mem_0_31_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[1].core|pipeline|issue|gpr_stage|[3].gpr_ram_f|mem_0_30_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[1].core|pipeline|issue|gpr_stage|[3].gpr_ram_f|mem_0_31_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[1].core|mem_unit|icache|[0].bank|tag_access|tag_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[1].core|mem_unit|icache|[0].bank|data_access|data_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[1].core|mem_unit|dcache|[0].bank|tag_access|tag_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[1].core|mem_unit|dcache|[0].bank|data_access|data_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[1].core|mem_unit|dcache|[1].bank|tag_access|tag_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[1].core|mem_unit|dcache|[1].bank|data_access|data_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[1].core|mem_unit|dcache|[2].bank|tag_access|tag_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[1].core|mem_unit|dcache|[2].bank|data_access|data_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[1].core|mem_unit|dcache|[3].bank|tag_access|tag_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[1].core|mem_unit|dcache|[3].bank|data_access|data_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[1].core|mem_unit|smem|[0].data|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[1].core|mem_unit|smem|[1].data|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[1].core|mem_unit|smem|[2].data|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[1].core|mem_unit|smem|[3].data|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[2].core|pipeline|issue|gpr_stage|[0].gpr_ram_f|mem_0_30_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[2].core|pipeline|issue|gpr_stage|[0].gpr_ram_f|mem_0_31_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[2].core|pipeline|issue|gpr_stage|[1].gpr_ram_f|mem_0_30_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[2].core|pipeline|issue|gpr_stage|[1].gpr_ram_f|mem_0_31_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[2].core|pipeline|issue|gpr_stage|[2].gpr_ram_f|mem_0_30_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[2].core|pipeline|issue|gpr_stage|[2].gpr_ram_f|mem_0_31_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[2].core|pipeline|issue|gpr_stage|[3].gpr_ram_f|mem_0_30_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[2].core|pipeline|issue|gpr_stage|[3].gpr_ram_f|mem_0_31_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[2].core|mem_unit|icache|[0].bank|tag_access|tag_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[2].core|mem_unit|icache|[0].bank|data_access|data_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[2].core|mem_unit|dcache|[0].bank|tag_access|tag_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[2].core|mem_unit|dcache|[0].bank|data_access|data_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[2].core|mem_unit|dcache|[1].bank|tag_access|tag_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[2].core|mem_unit|dcache|[1].bank|data_access|data_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[2].core|mem_unit|dcache|[2].bank|tag_access|tag_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[2].core|mem_unit|dcache|[2].bank|data_access|data_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[2].core|mem_unit|dcache|[3].bank|tag_access|tag_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[2].core|mem_unit|dcache|[3].bank|data_access|data_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[2].core|mem_unit|smem|[0].data|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[2].core|mem_unit|smem|[1].data|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[2].core|mem_unit|smem|[2].data|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[2].core|mem_unit|smem|[3].data|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[3].core|pipeline|issue|gpr_stage|[0].gpr_ram_f|mem_0_30_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[3].core|pipeline|issue|gpr_stage|[0].gpr_ram_f|mem_0_31_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[3].core|pipeline|issue|gpr_stage|[1].gpr_ram_f|mem_0_30_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[3].core|pipeline|issue|gpr_stage|[1].gpr_ram_f|mem_0_31_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[3].core|pipeline|issue|gpr_stage|[2].gpr_ram_f|mem_0_30_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[3].core|pipeline|issue|gpr_stage|[2].gpr_ram_f|mem_0_31_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[3].core|pipeline|issue|gpr_stage|[3].gpr_ram_f|mem_0_30_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[3].core|pipeline|issue|gpr_stage|[3].gpr_ram_f|mem_0_31_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[3].core|mem_unit|icache|[0].bank|tag_access|tag_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[3].core|mem_unit|icache|[0].bank|data_access|data_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[3].core|mem_unit|dcache|[0].bank|tag_access|tag_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[3].core|mem_unit|dcache|[0].bank|data_access|data_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[3].core|mem_unit|dcache|[1].bank|tag_access|tag_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[3].core|mem_unit|dcache|[1].bank|data_access|data_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[3].core|mem_unit|dcache|[2].bank|tag_access|tag_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[3].core|mem_unit|dcache|[2].bank|data_access|data_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[3].core|mem_unit|dcache|[3].bank|tag_access|tag_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[3].core|mem_unit|dcache|[3].bank|data_access|data_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[3].core|mem_unit|smem|[0].data|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[3].core|mem_unit|smem|[1].data|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[3].core|mem_unit|smem|[2].data|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[3].core|mem_unit|smem|[3].data|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|issue|gpr_stage|[0].gpr_ram_f|mem_0_30_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|issue|gpr_stage|[0].gpr_ram_f|mem_0_31_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|issue|gpr_stage|[1].gpr_ram_f|mem_0_30_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|issue|gpr_stage|[1].gpr_ram_f|mem_0_31_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|issue|gpr_stage|[2].gpr_ram_f|mem_0_30_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|issue|gpr_stage|[2].gpr_ram_f|mem_0_31_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|issue|gpr_stage|[3].gpr_ram_f|mem_0_30_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|issue|gpr_stage|[3].gpr_ram_f|mem_0_31_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|mem_unit|icache|[0].bank|tag_access|tag_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|mem_unit|icache|[0].bank|data_access|data_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|mem_unit|dcache|[0].bank|tag_access|tag_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|mem_unit|dcache|[0].bank|data_access|data_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|mem_unit|dcache|[1].bank|tag_access|tag_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|mem_unit|dcache|[1].bank|data_access|data_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|mem_unit|dcache|[2].bank|tag_access|tag_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|mem_unit|dcache|[2].bank|data_access|data_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|mem_unit|dcache|[3].bank|tag_access|tag_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|mem_unit|dcache|[3].bank|data_access|data_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|mem_unit|smem|[0].data|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|mem_unit|smem|[1].data|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|mem_unit|smem|[2].data|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|mem_unit|smem|[3].data|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[1].core|pipeline|issue|gpr_stage|[0].gpr_ram_f|mem_0_30_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[1].core|pipeline|issue|gpr_stage|[0].gpr_ram_f|mem_0_31_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[1].core|pipeline|issue|gpr_stage|[1].gpr_ram_f|mem_0_30_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[1].core|pipeline|issue|gpr_stage|[1].gpr_ram_f|mem_0_31_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[1].core|pipeline|issue|gpr_stage|[2].gpr_ram_f|mem_0_30_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[1].core|pipeline|issue|gpr_stage|[2].gpr_ram_f|mem_0_31_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[1].core|pipeline|issue|gpr_stage|[3].gpr_ram_f|mem_0_30_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[1].core|pipeline|issue|gpr_stage|[3].gpr_ram_f|mem_0_31_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[1].core|mem_unit|icache|[0].bank|tag_access|tag_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[1].core|mem_unit|icache|[0].bank|data_access|data_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[1].core|mem_unit|dcache|[0].bank|tag_access|tag_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[1].core|mem_unit|dcache|[0].bank|data_access|data_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[1].core|mem_unit|dcache|[1].bank|tag_access|tag_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[1].core|mem_unit|dcache|[1].bank|data_access|data_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[1].core|mem_unit|dcache|[2].bank|tag_access|tag_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[1].core|mem_unit|dcache|[2].bank|data_access|data_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[1].core|mem_unit|dcache|[3].bank|tag_access|tag_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[1].core|mem_unit|dcache|[3].bank|data_access|data_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[1].core|mem_unit|smem|[0].data|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[1].core|mem_unit|smem|[1].data|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[1].core|mem_unit|smem|[2].data|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[1].core|mem_unit|smem|[3].data|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[2].core|pipeline|issue|gpr_stage|[0].gpr_ram_f|mem_0_30_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[2].core|pipeline|issue|gpr_stage|[0].gpr_ram_f|mem_0_31_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[2].core|pipeline|issue|gpr_stage|[1].gpr_ram_f|mem_0_30_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[2].core|pipeline|issue|gpr_stage|[1].gpr_ram_f|mem_0_31_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[2].core|pipeline|issue|gpr_stage|[2].gpr_ram_f|mem_0_30_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[2].core|pipeline|issue|gpr_stage|[2].gpr_ram_f|mem_0_31_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[2].core|pipeline|issue|gpr_stage|[3].gpr_ram_f|mem_0_30_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[2].core|pipeline|issue|gpr_stage|[3].gpr_ram_f|mem_0_31_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[2].core|mem_unit|icache|[0].bank|tag_access|tag_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[2].core|mem_unit|icache|[0].bank|data_access|data_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[2].core|mem_unit|dcache|[0].bank|tag_access|tag_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[2].core|mem_unit|dcache|[0].bank|data_access|data_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[2].core|mem_unit|dcache|[1].bank|tag_access|tag_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[2].core|mem_unit|dcache|[1].bank|data_access|data_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[2].core|mem_unit|dcache|[2].bank|tag_access|tag_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[2].core|mem_unit|dcache|[2].bank|data_access|data_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[2].core|mem_unit|dcache|[3].bank|tag_access|tag_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[2].core|mem_unit|dcache|[3].bank|data_access|data_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[2].core|mem_unit|smem|[0].data|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[2].core|mem_unit|smem|[1].data|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[2].core|mem_unit|smem|[2].data|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[2].core|mem_unit|smem|[3].data|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[3].core|pipeline|issue|gpr_stage|[0].gpr_ram_f|mem_0_30_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[3].core|pipeline|issue|gpr_stage|[0].gpr_ram_f|mem_0_31_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[3].core|pipeline|issue|gpr_stage|[1].gpr_ram_f|mem_0_30_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[3].core|pipeline|issue|gpr_stage|[1].gpr_ram_f|mem_0_31_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[3].core|pipeline|issue|gpr_stage|[2].gpr_ram_f|mem_0_30_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[3].core|pipeline|issue|gpr_stage|[2].gpr_ram_f|mem_0_31_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[3].core|pipeline|issue|gpr_stage|[3].gpr_ram_f|mem_0_30_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[3].core|pipeline|issue|gpr_stage|[3].gpr_ram_f|mem_0_31_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[3].core|mem_unit|icache|[0].bank|tag_access|tag_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[3].core|mem_unit|icache|[0].bank|data_access|data_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[3].core|mem_unit|dcache|[0].bank|tag_access|tag_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[3].core|mem_unit|dcache|[0].bank|data_access|data_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[3].core|mem_unit|dcache|[1].bank|tag_access|tag_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[3].core|mem_unit|dcache|[1].bank|data_access|data_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[3].core|mem_unit|dcache|[2].bank|tag_access|tag_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[3].core|mem_unit|dcache|[2].bank|data_access|data_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[3].core|mem_unit|dcache|[3].bank|tag_access|tag_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[3].core|mem_unit|dcache|[3].bank|data_access|data_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[3].core|mem_unit|smem|[0].data|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[3].core|mem_unit|smem|[1].data|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[3].core|mem_unit|smem|[2].data|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[3].core|mem_unit|smem|[3].data|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[0].core|pipeline|issue|gpr_stage|[0].gpr_ram_f|mem_0_30_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[0].core|pipeline|issue|gpr_stage|[0].gpr_ram_f|mem_0_31_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[0].core|pipeline|issue|gpr_stage|[1].gpr_ram_f|mem_0_30_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[0].core|pipeline|issue|gpr_stage|[1].gpr_ram_f|mem_0_31_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[0].core|pipeline|issue|gpr_stage|[2].gpr_ram_f|mem_0_30_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[0].core|pipeline|issue|gpr_stage|[2].gpr_ram_f|mem_0_31_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[0].core|pipeline|issue|gpr_stage|[3].gpr_ram_f|mem_0_30_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[0].core|pipeline|issue|gpr_stage|[3].gpr_ram_f|mem_0_31_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[0].core|mem_unit|icache|[0].bank|tag_access|tag_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[0].core|mem_unit|icache|[0].bank|data_access|data_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[0].core|mem_unit|dcache|[0].bank|tag_access|tag_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[0].core|mem_unit|dcache|[0].bank|data_access|data_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[0].core|mem_unit|dcache|[1].bank|tag_access|tag_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[0].core|mem_unit|dcache|[1].bank|data_access|data_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[0].core|mem_unit|dcache|[2].bank|tag_access|tag_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[0].core|mem_unit|dcache|[2].bank|data_access|data_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[0].core|mem_unit|dcache|[3].bank|tag_access|tag_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[0].core|mem_unit|dcache|[3].bank|data_access|data_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[0].core|mem_unit|smem|[0].data|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[0].core|mem_unit|smem|[1].data|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[0].core|mem_unit|smem|[2].data|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[0].core|mem_unit|smem|[3].data|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[1].core|pipeline|issue|gpr_stage|[0].gpr_ram_f|mem_0_30_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[1].core|pipeline|issue|gpr_stage|[0].gpr_ram_f|mem_0_31_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[1].core|pipeline|issue|gpr_stage|[1].gpr_ram_f|mem_0_30_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[1].core|pipeline|issue|gpr_stage|[1].gpr_ram_f|mem_0_31_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[1].core|pipeline|issue|gpr_stage|[2].gpr_ram_f|mem_0_30_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[1].core|pipeline|issue|gpr_stage|[2].gpr_ram_f|mem_0_31_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[1].core|pipeline|issue|gpr_stage|[3].gpr_ram_f|mem_0_30_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[1].core|pipeline|issue|gpr_stage|[3].gpr_ram_f|mem_0_31_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[1].core|mem_unit|icache|[0].bank|tag_access|tag_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[1].core|mem_unit|icache|[0].bank|data_access|data_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[1].core|mem_unit|dcache|[0].bank|tag_access|tag_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[1].core|mem_unit|dcache|[0].bank|data_access|data_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[1].core|mem_unit|dcache|[1].bank|tag_access|tag_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[1].core|mem_unit|dcache|[1].bank|data_access|data_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[1].core|mem_unit|dcache|[2].bank|tag_access|tag_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[1].core|mem_unit|dcache|[2].bank|data_access|data_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[1].core|mem_unit|dcache|[3].bank|tag_access|tag_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[1].core|mem_unit|dcache|[3].bank|data_access|data_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[1].core|mem_unit|smem|[0].data|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[1].core|mem_unit|smem|[1].data|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[1].core|mem_unit|smem|[2].data|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[1].core|mem_unit|smem|[3].data|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[2].core|pipeline|issue|gpr_stage|[0].gpr_ram_f|mem_0_30_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[2].core|pipeline|issue|gpr_stage|[0].gpr_ram_f|mem_0_31_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[2].core|pipeline|issue|gpr_stage|[1].gpr_ram_f|mem_0_30_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[2].core|pipeline|issue|gpr_stage|[1].gpr_ram_f|mem_0_31_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[2].core|pipeline|issue|gpr_stage|[2].gpr_ram_f|mem_0_30_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[2].core|pipeline|issue|gpr_stage|[2].gpr_ram_f|mem_0_31_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[2].core|pipeline|issue|gpr_stage|[3].gpr_ram_f|mem_0_30_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[2].core|pipeline|issue|gpr_stage|[3].gpr_ram_f|mem_0_31_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[2].core|mem_unit|icache|[0].bank|tag_access|tag_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[2].core|mem_unit|icache|[0].bank|data_access|data_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[2].core|mem_unit|dcache|[0].bank|tag_access|tag_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[2].core|mem_unit|dcache|[0].bank|data_access|data_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[2].core|mem_unit|dcache|[1].bank|tag_access|tag_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[2].core|mem_unit|dcache|[1].bank|data_access|data_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[2].core|mem_unit|dcache|[2].bank|tag_access|tag_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[2].core|mem_unit|dcache|[2].bank|data_access|data_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[2].core|mem_unit|dcache|[3].bank|tag_access|tag_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[2].core|mem_unit|dcache|[3].bank|data_access|data_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[2].core|mem_unit|smem|[0].data|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[2].core|mem_unit|smem|[1].data|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[2].core|mem_unit|smem|[2].data|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[2].core|mem_unit|smem|[3].data|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[3].core|pipeline|issue|gpr_stage|[0].gpr_ram_f|mem_0_30_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[3].core|pipeline|issue|gpr_stage|[0].gpr_ram_f|mem_0_31_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[3].core|pipeline|issue|gpr_stage|[1].gpr_ram_f|mem_0_30_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[3].core|pipeline|issue|gpr_stage|[1].gpr_ram_f|mem_0_31_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[3].core|pipeline|issue|gpr_stage|[2].gpr_ram_f|mem_0_30_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[3].core|pipeline|issue|gpr_stage|[2].gpr_ram_f|mem_0_31_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[3].core|pipeline|issue|gpr_stage|[3].gpr_ram_f|mem_0_30_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[3].core|pipeline|issue|gpr_stage|[3].gpr_ram_f|mem_0_31_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[3].core|mem_unit|icache|[0].bank|tag_access|tag_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[3].core|mem_unit|icache|[0].bank|data_access|data_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[3].core|mem_unit|dcache|[0].bank|tag_access|tag_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[3].core|mem_unit|dcache|[0].bank|data_access|data_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[3].core|mem_unit|dcache|[1].bank|tag_access|tag_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[3].core|mem_unit|dcache|[1].bank|data_access|data_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[3].core|mem_unit|dcache|[2].bank|tag_access|tag_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[3].core|mem_unit|dcache|[2].bank|data_access|data_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[3].core|mem_unit|dcache|[3].bank|tag_access|tag_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[3].core|mem_unit|dcache|[3].bank|data_access|data_store|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[3].core|mem_unit|smem|[0].data|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[3].core|mem_unit|smem|[1].data|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[3].core|mem_unit|smem|[2].data|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Warning (276020): Inferred RAM node "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[3].core|mem_unit|smem|[3].data|mem_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
|
|
Info (19000): Inferred 821 megafunctions from design logic
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|avs_wrapper|rd_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 32
|
|
Info (286033): Parameter WIDTHAD set to 4
|
|
Info (286033): Parameter NUMWORDS set to 16
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|avs_wrapper|rd_rsp_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 512
|
|
Info (286033): Parameter WIDTHAD set to 4
|
|
Info (286033): Parameter NUMWORDS set to 16
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|cci_rd_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 515
|
|
Info (286033): Parameter WIDTHAD set to 4
|
|
Info (286033): Parameter NUMWORDS set to 16
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[0].core|pipeline|fetch|warp_sched|[0].ipdom_stack|store|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 41
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[0].core|pipeline|fetch|warp_sched|[1].ipdom_stack|store|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 41
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[0].core|pipeline|fetch|warp_sched|[2].ipdom_stack|store|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 41
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[0].core|pipeline|fetch|warp_sched|[3].ipdom_stack|store|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 41
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[0].core|pipeline|fetch|icache_stage|req_metadata|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 36
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[0].core|pipeline|execute|lsu_unit|req_metadata|data_table|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 21
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[0].core|pipeline|execute|fpu_unit|req_metadata|data_table|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 13
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[0].core|mem_unit|icache|dram_rsp_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 538
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[0].core|mem_unit|icache|[0].bank|core_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 69
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[0].core|mem_unit|icache|[0].bank|miss_resrv|entries|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 12
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[0].core|mem_unit|icache|[0].bank|dram_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 602
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[0].core|mem_unit|dcache|dram_rsp_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 538
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[0].core|mem_unit|dcache|[0].bank|core_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 71
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[0].core|mem_unit|dcache|[0].bank|miss_resrv|entries|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 14
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[0].core|mem_unit|dcache|[0].bank|dram_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 601
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[0].core|mem_unit|dcache|[1].bank|core_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 71
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[0].core|mem_unit|dcache|[1].bank|miss_resrv|entries|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 14
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[0].core|mem_unit|dcache|[1].bank|dram_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 601
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[0].core|mem_unit|dcache|[2].bank|core_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 71
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[0].core|mem_unit|dcache|[2].bank|miss_resrv|entries|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 14
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[0].core|mem_unit|dcache|[2].bank|dram_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 601
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[0].core|mem_unit|dcache|[3].bank|core_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 71
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[0].core|mem_unit|dcache|[3].bank|miss_resrv|entries|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 14
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[0].core|mem_unit|dcache|[3].bank|dram_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 601
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[0].core|mem_unit|smem|core_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 212
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[1].core|pipeline|fetch|warp_sched|[0].ipdom_stack|store|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 41
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[1].core|pipeline|fetch|warp_sched|[1].ipdom_stack|store|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 41
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[1].core|pipeline|fetch|warp_sched|[2].ipdom_stack|store|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 41
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[1].core|pipeline|fetch|warp_sched|[3].ipdom_stack|store|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 41
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[1].core|pipeline|fetch|icache_stage|req_metadata|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 36
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[1].core|pipeline|execute|lsu_unit|req_metadata|data_table|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 21
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[1].core|pipeline|execute|fpu_unit|req_metadata|data_table|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 13
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[1].core|mem_unit|icache|dram_rsp_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 538
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[1].core|mem_unit|icache|[0].bank|core_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 69
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[1].core|mem_unit|icache|[0].bank|miss_resrv|entries|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 12
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[1].core|mem_unit|icache|[0].bank|dram_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 602
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[1].core|mem_unit|dcache|dram_rsp_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 538
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[1].core|mem_unit|dcache|[0].bank|core_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 71
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[1].core|mem_unit|dcache|[0].bank|miss_resrv|entries|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 14
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[1].core|mem_unit|dcache|[0].bank|dram_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 601
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[1].core|mem_unit|dcache|[1].bank|core_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 71
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[1].core|mem_unit|dcache|[1].bank|miss_resrv|entries|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 14
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[1].core|mem_unit|dcache|[1].bank|dram_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 601
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[1].core|mem_unit|dcache|[2].bank|core_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 71
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[1].core|mem_unit|dcache|[2].bank|miss_resrv|entries|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 14
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[1].core|mem_unit|dcache|[2].bank|dram_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 601
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[1].core|mem_unit|dcache|[3].bank|core_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 71
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[1].core|mem_unit|dcache|[3].bank|miss_resrv|entries|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 14
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[1].core|mem_unit|dcache|[3].bank|dram_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 601
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[1].core|mem_unit|smem|core_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 212
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[2].core|pipeline|fetch|warp_sched|[0].ipdom_stack|store|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 41
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[2].core|pipeline|fetch|warp_sched|[1].ipdom_stack|store|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 41
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[2].core|pipeline|fetch|warp_sched|[2].ipdom_stack|store|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 41
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[2].core|pipeline|fetch|warp_sched|[3].ipdom_stack|store|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 41
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[2].core|pipeline|fetch|icache_stage|req_metadata|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 36
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[2].core|pipeline|execute|lsu_unit|req_metadata|data_table|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 21
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[2].core|pipeline|execute|fpu_unit|req_metadata|data_table|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 13
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[2].core|mem_unit|icache|dram_rsp_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 538
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[2].core|mem_unit|icache|[0].bank|core_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 69
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[2].core|mem_unit|icache|[0].bank|miss_resrv|entries|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 12
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[2].core|mem_unit|icache|[0].bank|dram_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 602
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[2].core|mem_unit|dcache|dram_rsp_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 538
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[2].core|mem_unit|dcache|[0].bank|core_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 71
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[2].core|mem_unit|dcache|[0].bank|miss_resrv|entries|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 14
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[2].core|mem_unit|dcache|[0].bank|dram_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 601
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[2].core|mem_unit|dcache|[1].bank|core_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 71
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[2].core|mem_unit|dcache|[1].bank|miss_resrv|entries|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 14
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[2].core|mem_unit|dcache|[1].bank|dram_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 601
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[2].core|mem_unit|dcache|[2].bank|core_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 71
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[2].core|mem_unit|dcache|[2].bank|miss_resrv|entries|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 14
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[2].core|mem_unit|dcache|[2].bank|dram_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 601
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[2].core|mem_unit|dcache|[3].bank|core_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 71
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[2].core|mem_unit|dcache|[3].bank|miss_resrv|entries|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 14
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[2].core|mem_unit|dcache|[3].bank|dram_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 601
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[2].core|mem_unit|smem|core_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 212
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[3].core|pipeline|fetch|warp_sched|[0].ipdom_stack|store|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 41
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[3].core|pipeline|fetch|warp_sched|[1].ipdom_stack|store|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 41
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[3].core|pipeline|fetch|warp_sched|[2].ipdom_stack|store|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 41
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[3].core|pipeline|fetch|warp_sched|[3].ipdom_stack|store|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 41
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[3].core|pipeline|fetch|icache_stage|req_metadata|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 36
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[3].core|pipeline|execute|lsu_unit|req_metadata|data_table|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 21
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[3].core|pipeline|execute|fpu_unit|req_metadata|data_table|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 13
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[3].core|mem_unit|icache|dram_rsp_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 538
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[3].core|mem_unit|icache|[0].bank|core_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 69
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[3].core|mem_unit|icache|[0].bank|miss_resrv|entries|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 12
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[3].core|mem_unit|icache|[0].bank|dram_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 602
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[3].core|mem_unit|dcache|dram_rsp_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 538
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[3].core|mem_unit|dcache|[0].bank|core_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 71
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[3].core|mem_unit|dcache|[0].bank|miss_resrv|entries|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 14
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[3].core|mem_unit|dcache|[0].bank|dram_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 601
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[3].core|mem_unit|dcache|[1].bank|core_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 71
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[3].core|mem_unit|dcache|[1].bank|miss_resrv|entries|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 14
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[3].core|mem_unit|dcache|[1].bank|dram_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 601
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[3].core|mem_unit|dcache|[2].bank|core_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 71
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[3].core|mem_unit|dcache|[2].bank|miss_resrv|entries|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 14
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[3].core|mem_unit|dcache|[2].bank|dram_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 601
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[3].core|mem_unit|dcache|[3].bank|core_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 71
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[3].core|mem_unit|dcache|[3].bank|miss_resrv|entries|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 14
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[3].core|mem_unit|dcache|[3].bank|dram_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 601
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[3].core|mem_unit|smem|core_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 212
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[0].core|pipeline|fetch|warp_sched|[0].ipdom_stack|store|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 41
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[0].core|pipeline|fetch|warp_sched|[1].ipdom_stack|store|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 41
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[0].core|pipeline|fetch|warp_sched|[2].ipdom_stack|store|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 41
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[0].core|pipeline|fetch|warp_sched|[3].ipdom_stack|store|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 41
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[0].core|pipeline|fetch|icache_stage|req_metadata|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 36
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[0].core|pipeline|execute|lsu_unit|req_metadata|data_table|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 21
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[0].core|pipeline|execute|fpu_unit|req_metadata|data_table|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 13
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[0].core|mem_unit|icache|dram_rsp_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 538
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[0].core|mem_unit|icache|[0].bank|core_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 69
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[0].core|mem_unit|icache|[0].bank|miss_resrv|entries|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 12
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[0].core|mem_unit|icache|[0].bank|dram_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 602
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[0].core|mem_unit|dcache|dram_rsp_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 538
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[0].core|mem_unit|dcache|[0].bank|core_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 71
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[0].core|mem_unit|dcache|[0].bank|miss_resrv|entries|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 14
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[0].core|mem_unit|dcache|[0].bank|dram_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 601
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[0].core|mem_unit|dcache|[1].bank|core_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 71
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[0].core|mem_unit|dcache|[1].bank|miss_resrv|entries|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 14
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[0].core|mem_unit|dcache|[1].bank|dram_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 601
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[0].core|mem_unit|dcache|[2].bank|core_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 71
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[0].core|mem_unit|dcache|[2].bank|miss_resrv|entries|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 14
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[0].core|mem_unit|dcache|[2].bank|dram_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 601
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[0].core|mem_unit|dcache|[3].bank|core_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 71
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[0].core|mem_unit|dcache|[3].bank|miss_resrv|entries|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 14
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[0].core|mem_unit|dcache|[3].bank|dram_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 601
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[0].core|mem_unit|smem|core_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 212
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[1].core|pipeline|fetch|warp_sched|[0].ipdom_stack|store|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 41
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[1].core|pipeline|fetch|warp_sched|[1].ipdom_stack|store|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 41
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[1].core|pipeline|fetch|warp_sched|[2].ipdom_stack|store|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 41
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[1].core|pipeline|fetch|warp_sched|[3].ipdom_stack|store|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 41
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[1].core|pipeline|fetch|icache_stage|req_metadata|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 36
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[1].core|pipeline|execute|lsu_unit|req_metadata|data_table|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 21
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[1].core|pipeline|execute|fpu_unit|req_metadata|data_table|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 13
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[1].core|mem_unit|icache|dram_rsp_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 538
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[1].core|mem_unit|icache|[0].bank|core_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 69
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[1].core|mem_unit|icache|[0].bank|miss_resrv|entries|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 12
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[1].core|mem_unit|icache|[0].bank|dram_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 602
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[1].core|mem_unit|dcache|dram_rsp_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 538
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[1].core|mem_unit|dcache|[0].bank|core_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 71
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[1].core|mem_unit|dcache|[0].bank|miss_resrv|entries|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 14
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[1].core|mem_unit|dcache|[0].bank|dram_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 601
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[1].core|mem_unit|dcache|[1].bank|core_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 71
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[1].core|mem_unit|dcache|[1].bank|miss_resrv|entries|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 14
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[1].core|mem_unit|dcache|[1].bank|dram_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 601
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[1].core|mem_unit|dcache|[2].bank|core_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 71
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[1].core|mem_unit|dcache|[2].bank|miss_resrv|entries|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 14
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[1].core|mem_unit|dcache|[2].bank|dram_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 601
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[1].core|mem_unit|dcache|[3].bank|core_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 71
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[1].core|mem_unit|dcache|[3].bank|miss_resrv|entries|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 14
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[1].core|mem_unit|dcache|[3].bank|dram_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 601
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[1].core|mem_unit|smem|core_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 212
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[2].core|pipeline|fetch|warp_sched|[0].ipdom_stack|store|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 41
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[2].core|pipeline|fetch|warp_sched|[1].ipdom_stack|store|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 41
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[2].core|pipeline|fetch|warp_sched|[2].ipdom_stack|store|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 41
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[2].core|pipeline|fetch|warp_sched|[3].ipdom_stack|store|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 41
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[2].core|pipeline|fetch|icache_stage|req_metadata|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 36
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[2].core|pipeline|execute|lsu_unit|req_metadata|data_table|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 21
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[2].core|pipeline|execute|fpu_unit|req_metadata|data_table|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 13
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[2].core|mem_unit|icache|dram_rsp_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 538
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[2].core|mem_unit|icache|[0].bank|core_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 69
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[2].core|mem_unit|icache|[0].bank|miss_resrv|entries|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 12
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[2].core|mem_unit|icache|[0].bank|dram_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 602
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[2].core|mem_unit|dcache|dram_rsp_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 538
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[2].core|mem_unit|dcache|[0].bank|core_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 71
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[2].core|mem_unit|dcache|[0].bank|miss_resrv|entries|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 14
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[2].core|mem_unit|dcache|[0].bank|dram_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 601
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[2].core|mem_unit|dcache|[1].bank|core_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 71
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[2].core|mem_unit|dcache|[1].bank|miss_resrv|entries|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 14
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[2].core|mem_unit|dcache|[1].bank|dram_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 601
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[2].core|mem_unit|dcache|[2].bank|core_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 71
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[2].core|mem_unit|dcache|[2].bank|miss_resrv|entries|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 14
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[2].core|mem_unit|dcache|[2].bank|dram_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 601
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[2].core|mem_unit|dcache|[3].bank|core_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 71
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[2].core|mem_unit|dcache|[3].bank|miss_resrv|entries|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 14
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[2].core|mem_unit|dcache|[3].bank|dram_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 601
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[2].core|mem_unit|smem|core_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 212
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[3].core|pipeline|fetch|warp_sched|[0].ipdom_stack|store|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 41
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[3].core|pipeline|fetch|warp_sched|[1].ipdom_stack|store|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 41
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[3].core|pipeline|fetch|warp_sched|[2].ipdom_stack|store|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 41
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[3].core|pipeline|fetch|warp_sched|[3].ipdom_stack|store|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 41
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[3].core|pipeline|fetch|icache_stage|req_metadata|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 36
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[3].core|pipeline|execute|lsu_unit|req_metadata|data_table|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 21
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[3].core|pipeline|execute|fpu_unit|req_metadata|data_table|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 13
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[3].core|mem_unit|icache|dram_rsp_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 538
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[3].core|mem_unit|icache|[0].bank|core_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 69
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[3].core|mem_unit|icache|[0].bank|miss_resrv|entries|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 12
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[3].core|mem_unit|icache|[0].bank|dram_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 602
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[3].core|mem_unit|dcache|dram_rsp_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 538
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[3].core|mem_unit|dcache|[0].bank|core_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 71
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[3].core|mem_unit|dcache|[0].bank|miss_resrv|entries|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 14
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[3].core|mem_unit|dcache|[0].bank|dram_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 601
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[3].core|mem_unit|dcache|[1].bank|core_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 71
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[3].core|mem_unit|dcache|[1].bank|miss_resrv|entries|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 14
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[3].core|mem_unit|dcache|[1].bank|dram_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 601
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[3].core|mem_unit|dcache|[2].bank|core_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 71
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[3].core|mem_unit|dcache|[2].bank|miss_resrv|entries|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 14
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[3].core|mem_unit|dcache|[2].bank|dram_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 601
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[3].core|mem_unit|dcache|[3].bank|core_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 71
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[3].core|mem_unit|dcache|[3].bank|miss_resrv|entries|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 14
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[3].core|mem_unit|dcache|[3].bank|dram_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 601
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[3].core|mem_unit|smem|core_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 212
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|fetch|warp_sched|[0].ipdom_stack|store|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 41
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|fetch|warp_sched|[1].ipdom_stack|store|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 41
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|fetch|warp_sched|[2].ipdom_stack|store|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 41
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|fetch|warp_sched|[3].ipdom_stack|store|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 41
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|fetch|icache_stage|req_metadata|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 36
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|execute|lsu_unit|req_metadata|data_table|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 21
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|execute|fpu_unit|req_metadata|data_table|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 13
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|mem_unit|icache|dram_rsp_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 538
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|mem_unit|icache|[0].bank|core_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 69
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|mem_unit|icache|[0].bank|miss_resrv|entries|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 12
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|mem_unit|icache|[0].bank|dram_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 602
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|mem_unit|dcache|dram_rsp_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 538
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|mem_unit|dcache|[0].bank|core_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 71
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|mem_unit|dcache|[0].bank|miss_resrv|entries|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 14
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|mem_unit|dcache|[0].bank|dram_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 601
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|mem_unit|dcache|[1].bank|core_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 71
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|mem_unit|dcache|[1].bank|miss_resrv|entries|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 14
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|mem_unit|dcache|[1].bank|dram_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 601
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|mem_unit|dcache|[2].bank|core_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 71
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|mem_unit|dcache|[2].bank|miss_resrv|entries|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 14
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|mem_unit|dcache|[2].bank|dram_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 601
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|mem_unit|dcache|[3].bank|core_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 71
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|mem_unit|dcache|[3].bank|miss_resrv|entries|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 14
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|mem_unit|dcache|[3].bank|dram_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 601
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|mem_unit|smem|core_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 212
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[1].core|pipeline|fetch|warp_sched|[0].ipdom_stack|store|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 41
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[1].core|pipeline|fetch|warp_sched|[1].ipdom_stack|store|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 41
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[1].core|pipeline|fetch|warp_sched|[2].ipdom_stack|store|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 41
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[1].core|pipeline|fetch|warp_sched|[3].ipdom_stack|store|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 41
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[1].core|pipeline|fetch|icache_stage|req_metadata|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 36
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[1].core|pipeline|execute|lsu_unit|req_metadata|data_table|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 21
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[1].core|pipeline|execute|fpu_unit|req_metadata|data_table|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 13
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[1].core|mem_unit|icache|dram_rsp_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 538
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[1].core|mem_unit|icache|[0].bank|core_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 69
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[1].core|mem_unit|icache|[0].bank|miss_resrv|entries|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 12
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[1].core|mem_unit|icache|[0].bank|dram_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 602
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[1].core|mem_unit|dcache|dram_rsp_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 538
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[1].core|mem_unit|dcache|[0].bank|core_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 71
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[1].core|mem_unit|dcache|[0].bank|miss_resrv|entries|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 14
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[1].core|mem_unit|dcache|[0].bank|dram_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 601
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[1].core|mem_unit|dcache|[1].bank|core_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 71
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[1].core|mem_unit|dcache|[1].bank|miss_resrv|entries|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 14
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[1].core|mem_unit|dcache|[1].bank|dram_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 601
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[1].core|mem_unit|dcache|[2].bank|core_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 71
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[1].core|mem_unit|dcache|[2].bank|miss_resrv|entries|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 14
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[1].core|mem_unit|dcache|[2].bank|dram_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 601
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[1].core|mem_unit|dcache|[3].bank|core_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 71
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[1].core|mem_unit|dcache|[3].bank|miss_resrv|entries|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 14
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[1].core|mem_unit|dcache|[3].bank|dram_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 601
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[1].core|mem_unit|smem|core_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 212
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[2].core|pipeline|fetch|warp_sched|[0].ipdom_stack|store|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 41
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[2].core|pipeline|fetch|warp_sched|[1].ipdom_stack|store|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 41
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[2].core|pipeline|fetch|warp_sched|[2].ipdom_stack|store|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 41
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[2].core|pipeline|fetch|warp_sched|[3].ipdom_stack|store|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 41
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[2].core|pipeline|fetch|icache_stage|req_metadata|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 36
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[2].core|pipeline|execute|lsu_unit|req_metadata|data_table|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 21
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[2].core|pipeline|execute|fpu_unit|req_metadata|data_table|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 13
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[2].core|mem_unit|icache|dram_rsp_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 538
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[2].core|mem_unit|icache|[0].bank|core_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 69
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[2].core|mem_unit|icache|[0].bank|miss_resrv|entries|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 12
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[2].core|mem_unit|icache|[0].bank|dram_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 602
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[2].core|mem_unit|dcache|dram_rsp_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 538
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[2].core|mem_unit|dcache|[0].bank|core_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 71
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[2].core|mem_unit|dcache|[0].bank|miss_resrv|entries|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 14
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[2].core|mem_unit|dcache|[0].bank|dram_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 601
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[2].core|mem_unit|dcache|[1].bank|core_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 71
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[2].core|mem_unit|dcache|[1].bank|miss_resrv|entries|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 14
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[2].core|mem_unit|dcache|[1].bank|dram_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 601
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[2].core|mem_unit|dcache|[2].bank|core_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 71
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[2].core|mem_unit|dcache|[2].bank|miss_resrv|entries|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 14
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[2].core|mem_unit|dcache|[2].bank|dram_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 601
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[2].core|mem_unit|dcache|[3].bank|core_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 71
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[2].core|mem_unit|dcache|[3].bank|miss_resrv|entries|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 14
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[2].core|mem_unit|dcache|[3].bank|dram_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 601
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[2].core|mem_unit|smem|core_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 212
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[3].core|pipeline|fetch|warp_sched|[0].ipdom_stack|store|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 41
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[3].core|pipeline|fetch|warp_sched|[1].ipdom_stack|store|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 41
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[3].core|pipeline|fetch|warp_sched|[2].ipdom_stack|store|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 41
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[3].core|pipeline|fetch|warp_sched|[3].ipdom_stack|store|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 41
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[3].core|pipeline|fetch|icache_stage|req_metadata|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 36
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[3].core|pipeline|execute|lsu_unit|req_metadata|data_table|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 21
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[3].core|pipeline|execute|fpu_unit|req_metadata|data_table|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 13
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[3].core|mem_unit|icache|dram_rsp_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 538
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[3].core|mem_unit|icache|[0].bank|core_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 69
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[3].core|mem_unit|icache|[0].bank|miss_resrv|entries|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 12
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[3].core|mem_unit|icache|[0].bank|dram_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 602
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[3].core|mem_unit|dcache|dram_rsp_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 538
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[3].core|mem_unit|dcache|[0].bank|core_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 71
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[3].core|mem_unit|dcache|[0].bank|miss_resrv|entries|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 14
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[3].core|mem_unit|dcache|[0].bank|dram_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 601
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[3].core|mem_unit|dcache|[1].bank|core_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 71
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[3].core|mem_unit|dcache|[1].bank|miss_resrv|entries|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 14
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[3].core|mem_unit|dcache|[1].bank|dram_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 601
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[3].core|mem_unit|dcache|[2].bank|core_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 71
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[3].core|mem_unit|dcache|[2].bank|miss_resrv|entries|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 14
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[3].core|mem_unit|dcache|[2].bank|dram_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 601
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[3].core|mem_unit|dcache|[3].bank|core_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 71
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[3].core|mem_unit|dcache|[3].bank|miss_resrv|entries|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 14
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[3].core|mem_unit|dcache|[3].bank|dram_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 601
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[3].core|mem_unit|smem|core_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 212
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[0].core|pipeline|fetch|warp_sched|[0].ipdom_stack|store|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 41
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[0].core|pipeline|fetch|warp_sched|[1].ipdom_stack|store|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 41
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[0].core|pipeline|fetch|warp_sched|[2].ipdom_stack|store|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 41
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[0].core|pipeline|fetch|warp_sched|[3].ipdom_stack|store|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 41
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[0].core|pipeline|fetch|icache_stage|req_metadata|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 36
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[0].core|pipeline|execute|lsu_unit|req_metadata|data_table|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 21
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[0].core|pipeline|execute|fpu_unit|req_metadata|data_table|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 13
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[0].core|mem_unit|icache|dram_rsp_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 538
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[0].core|mem_unit|icache|[0].bank|core_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 69
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[0].core|mem_unit|icache|[0].bank|miss_resrv|entries|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 12
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[0].core|mem_unit|icache|[0].bank|dram_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 602
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[0].core|mem_unit|dcache|dram_rsp_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 538
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[0].core|mem_unit|dcache|[0].bank|core_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 71
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[0].core|mem_unit|dcache|[0].bank|miss_resrv|entries|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 14
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[0].core|mem_unit|dcache|[0].bank|dram_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 601
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[0].core|mem_unit|dcache|[1].bank|core_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 71
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[0].core|mem_unit|dcache|[1].bank|miss_resrv|entries|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 14
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[0].core|mem_unit|dcache|[1].bank|dram_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 601
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[0].core|mem_unit|dcache|[2].bank|core_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 71
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[0].core|mem_unit|dcache|[2].bank|miss_resrv|entries|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 14
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[0].core|mem_unit|dcache|[2].bank|dram_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 601
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[0].core|mem_unit|dcache|[3].bank|core_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 71
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[0].core|mem_unit|dcache|[3].bank|miss_resrv|entries|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 14
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[0].core|mem_unit|dcache|[3].bank|dram_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 601
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[0].core|mem_unit|smem|core_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 212
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[1].core|pipeline|fetch|warp_sched|[0].ipdom_stack|store|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 41
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[1].core|pipeline|fetch|warp_sched|[1].ipdom_stack|store|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 41
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[1].core|pipeline|fetch|warp_sched|[2].ipdom_stack|store|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 41
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[1].core|pipeline|fetch|warp_sched|[3].ipdom_stack|store|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 41
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[1].core|pipeline|fetch|icache_stage|req_metadata|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 36
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[1].core|pipeline|execute|lsu_unit|req_metadata|data_table|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 21
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[1].core|pipeline|execute|fpu_unit|req_metadata|data_table|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 13
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[1].core|mem_unit|icache|dram_rsp_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 538
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[1].core|mem_unit|icache|[0].bank|core_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 69
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[1].core|mem_unit|icache|[0].bank|miss_resrv|entries|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 12
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[1].core|mem_unit|icache|[0].bank|dram_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 602
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[1].core|mem_unit|dcache|dram_rsp_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 538
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[1].core|mem_unit|dcache|[0].bank|core_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 71
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[1].core|mem_unit|dcache|[0].bank|miss_resrv|entries|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 14
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[1].core|mem_unit|dcache|[0].bank|dram_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 601
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[1].core|mem_unit|dcache|[1].bank|core_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 71
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[1].core|mem_unit|dcache|[1].bank|miss_resrv|entries|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 14
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[1].core|mem_unit|dcache|[1].bank|dram_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 601
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[1].core|mem_unit|dcache|[2].bank|core_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 71
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[1].core|mem_unit|dcache|[2].bank|miss_resrv|entries|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 14
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[1].core|mem_unit|dcache|[2].bank|dram_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 601
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[1].core|mem_unit|dcache|[3].bank|core_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 71
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[1].core|mem_unit|dcache|[3].bank|miss_resrv|entries|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 14
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[1].core|mem_unit|dcache|[3].bank|dram_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 601
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[1].core|mem_unit|smem|core_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 212
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[2].core|pipeline|fetch|warp_sched|[0].ipdom_stack|store|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 41
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[2].core|pipeline|fetch|warp_sched|[1].ipdom_stack|store|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 41
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[2].core|pipeline|fetch|warp_sched|[2].ipdom_stack|store|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 41
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[2].core|pipeline|fetch|warp_sched|[3].ipdom_stack|store|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 41
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[2].core|pipeline|fetch|icache_stage|req_metadata|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 36
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[2].core|pipeline|execute|lsu_unit|req_metadata|data_table|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 21
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[2].core|pipeline|execute|fpu_unit|req_metadata|data_table|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 13
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[2].core|mem_unit|icache|dram_rsp_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 538
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[2].core|mem_unit|icache|[0].bank|core_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 69
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[2].core|mem_unit|icache|[0].bank|miss_resrv|entries|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 12
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[2].core|mem_unit|icache|[0].bank|dram_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 602
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[2].core|mem_unit|dcache|dram_rsp_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 538
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[2].core|mem_unit|dcache|[0].bank|core_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 71
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[2].core|mem_unit|dcache|[0].bank|miss_resrv|entries|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 14
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[2].core|mem_unit|dcache|[0].bank|dram_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 601
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[2].core|mem_unit|dcache|[1].bank|core_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 71
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[2].core|mem_unit|dcache|[1].bank|miss_resrv|entries|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 14
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[2].core|mem_unit|dcache|[1].bank|dram_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 601
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[2].core|mem_unit|dcache|[2].bank|core_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 71
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[2].core|mem_unit|dcache|[2].bank|miss_resrv|entries|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 14
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[2].core|mem_unit|dcache|[2].bank|dram_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 601
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[2].core|mem_unit|dcache|[3].bank|core_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 71
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[2].core|mem_unit|dcache|[3].bank|miss_resrv|entries|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 14
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[2].core|mem_unit|dcache|[3].bank|dram_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 601
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[2].core|mem_unit|smem|core_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 212
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[3].core|pipeline|fetch|warp_sched|[0].ipdom_stack|store|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 41
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[3].core|pipeline|fetch|warp_sched|[1].ipdom_stack|store|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 41
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[3].core|pipeline|fetch|warp_sched|[2].ipdom_stack|store|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 41
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[3].core|pipeline|fetch|warp_sched|[3].ipdom_stack|store|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 41
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[3].core|pipeline|fetch|icache_stage|req_metadata|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 36
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[3].core|pipeline|execute|lsu_unit|req_metadata|data_table|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 21
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[3].core|pipeline|execute|fpu_unit|req_metadata|data_table|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 13
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[3].core|mem_unit|icache|dram_rsp_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 538
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[3].core|mem_unit|icache|[0].bank|core_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 69
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[3].core|mem_unit|icache|[0].bank|miss_resrv|entries|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 12
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[3].core|mem_unit|icache|[0].bank|dram_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 602
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[3].core|mem_unit|dcache|dram_rsp_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 538
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[3].core|mem_unit|dcache|[0].bank|core_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 71
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[3].core|mem_unit|dcache|[0].bank|miss_resrv|entries|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 14
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[3].core|mem_unit|dcache|[0].bank|dram_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 601
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[3].core|mem_unit|dcache|[1].bank|core_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 71
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[3].core|mem_unit|dcache|[1].bank|miss_resrv|entries|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 14
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[3].core|mem_unit|dcache|[1].bank|dram_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 601
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[3].core|mem_unit|dcache|[2].bank|core_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 71
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[3].core|mem_unit|dcache|[2].bank|miss_resrv|entries|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 14
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[3].core|mem_unit|dcache|[2].bank|dram_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 601
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[3].core|mem_unit|dcache|[3].bank|core_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 71
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[3].core|mem_unit|dcache|[3].bank|miss_resrv|entries|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 14
|
|
Info (286033): Parameter WIDTHAD set to 3
|
|
Info (286033): Parameter NUMWORDS set to 8
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[3].core|mem_unit|dcache|[3].bank|dram_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 601
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276038): Inferred altdpram megafunction from the following logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[3].core|mem_unit|smem|core_req_queue|dp_ram|mem_rtl_0"
|
|
Info (286033): Parameter WIDTH set to 212
|
|
Info (286033): Parameter WIDTHAD set to 2
|
|
Info (286033): Parameter NUMWORDS set to 4
|
|
Info (286033): Parameter WRADDRESS_REG set to INCLOCK
|
|
Info (286033): Parameter WRADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter WRCONTROL_REG set to INCLOCK
|
|
Info (286033): Parameter WRCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter RDADDRESS_REG set to OUTCLOCK
|
|
Info (286033): Parameter RDADDRESS_ACLR set to OFF
|
|
Info (286033): Parameter RDCONTROL_REG set to UNREGISTERED
|
|
Info (286033): Parameter RDCONTROL_ACLR set to OFF
|
|
Info (286033): Parameter INDATA_REG set to INCLOCK
|
|
Info (286033): Parameter INDATA_ACLR set to OFF
|
|
Info (286033): Parameter OUTDATA_REG set to UNREGISTERED
|
|
Info (286033): Parameter OUTDATA_ACLR set to OFF
|
|
Info (286033): Parameter LPM_FILE set to UNUSED
|
|
Info (286033): Parameter RAM_BLOCK_TYPE set to LUTRAM
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_avalon_mem_if|c.mm_async[0].mem_async_shim|avmm_cross|cmd_fifo|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 605
|
|
Info (286033): Parameter WIDTHAD_A set to 7
|
|
Info (286033): Parameter NUMWORDS_A set to 128
|
|
Info (286033): Parameter WIDTH_B set to 605
|
|
Info (286033): Parameter WIDTHAD_B set to 7
|
|
Info (286033): Parameter NUMWORDS_B set to 128
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK1
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_avalon_mem_if|c.mm_async[0].mem_async_shim|avmm_cross|rsp_fifo|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 512
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 512
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK1
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[0].core|pipeline|issue|gpr_stage|[0].gpr_ram_f|mem_0_30_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[0].core|pipeline|issue|gpr_stage|[0].gpr_ram_f|mem_0_31_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[0].core|pipeline|issue|gpr_stage|[0].gpr_ram_f|mem_0_31_rtl_1"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (286033): Parameter RDCONTROL_REG_B set to CLOCK0
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[0].core|pipeline|issue|gpr_stage|[1].gpr_ram_f|mem_0_30_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[0].core|pipeline|issue|gpr_stage|[1].gpr_ram_f|mem_0_31_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[0].core|pipeline|issue|gpr_stage|[1].gpr_ram_f|mem_0_31_rtl_1"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (286033): Parameter RDCONTROL_REG_B set to CLOCK0
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[0].core|pipeline|issue|gpr_stage|[2].gpr_ram_f|mem_0_30_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[0].core|pipeline|issue|gpr_stage|[2].gpr_ram_f|mem_0_31_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[0].core|pipeline|issue|gpr_stage|[2].gpr_ram_f|mem_0_31_rtl_1"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (286033): Parameter RDCONTROL_REG_B set to CLOCK0
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[0].core|pipeline|issue|gpr_stage|[3].gpr_ram_f|mem_0_30_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[0].core|pipeline|issue|gpr_stage|[3].gpr_ram_f|mem_0_31_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[0].core|pipeline|issue|gpr_stage|[3].gpr_ram_f|mem_0_31_rtl_1"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (286033): Parameter RDCONTROL_REG_B set to CLOCK0
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[0].core|mem_unit|icache|[0].bank|tag_access|tag_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 19
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 19
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter INIT_FILE set to qdb/_compiler/afu_default/green_region/19.2.0/final/1/mifs/ram0_VX_sp_ram_647fd9b1.hdl.mif
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[0].core|mem_unit|icache|[0].bank|data_access|data_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 512
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 512
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[0].core|mem_unit|dcache|[0].bank|tag_access|tag_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 19
|
|
Info (286033): Parameter WIDTHAD_A set to 6
|
|
Info (286033): Parameter NUMWORDS_A set to 64
|
|
Info (286033): Parameter WIDTH_B set to 19
|
|
Info (286033): Parameter WIDTHAD_B set to 6
|
|
Info (286033): Parameter NUMWORDS_B set to 64
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter INIT_FILE set to qdb/_compiler/afu_default/green_region/19.2.0/final/1/mifs/ram1_VX_sp_ram_647fd9b1.hdl.mif
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[0].core|mem_unit|dcache|[0].bank|data_access|data_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 512
|
|
Info (286033): Parameter WIDTHAD_A set to 6
|
|
Info (286033): Parameter NUMWORDS_A set to 64
|
|
Info (286033): Parameter WIDTH_B set to 512
|
|
Info (286033): Parameter WIDTHAD_B set to 6
|
|
Info (286033): Parameter NUMWORDS_B set to 64
|
|
Info (286033): Parameter WIDTH_BYTEENA_A set to 64
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[0].core|mem_unit|dcache|[1].bank|tag_access|tag_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 19
|
|
Info (286033): Parameter WIDTHAD_A set to 6
|
|
Info (286033): Parameter NUMWORDS_A set to 64
|
|
Info (286033): Parameter WIDTH_B set to 19
|
|
Info (286033): Parameter WIDTHAD_B set to 6
|
|
Info (286033): Parameter NUMWORDS_B set to 64
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter INIT_FILE set to qdb/_compiler/afu_default/green_region/19.2.0/final/1/mifs/ram1_VX_sp_ram_647fd9b1.hdl.mif
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[0].core|mem_unit|dcache|[1].bank|data_access|data_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 512
|
|
Info (286033): Parameter WIDTHAD_A set to 6
|
|
Info (286033): Parameter NUMWORDS_A set to 64
|
|
Info (286033): Parameter WIDTH_B set to 512
|
|
Info (286033): Parameter WIDTHAD_B set to 6
|
|
Info (286033): Parameter NUMWORDS_B set to 64
|
|
Info (286033): Parameter WIDTH_BYTEENA_A set to 64
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[0].core|mem_unit|dcache|[2].bank|tag_access|tag_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 19
|
|
Info (286033): Parameter WIDTHAD_A set to 6
|
|
Info (286033): Parameter NUMWORDS_A set to 64
|
|
Info (286033): Parameter WIDTH_B set to 19
|
|
Info (286033): Parameter WIDTHAD_B set to 6
|
|
Info (286033): Parameter NUMWORDS_B set to 64
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter INIT_FILE set to qdb/_compiler/afu_default/green_region/19.2.0/final/1/mifs/ram1_VX_sp_ram_647fd9b1.hdl.mif
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[0].core|mem_unit|dcache|[2].bank|data_access|data_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 512
|
|
Info (286033): Parameter WIDTHAD_A set to 6
|
|
Info (286033): Parameter NUMWORDS_A set to 64
|
|
Info (286033): Parameter WIDTH_B set to 512
|
|
Info (286033): Parameter WIDTHAD_B set to 6
|
|
Info (286033): Parameter NUMWORDS_B set to 64
|
|
Info (286033): Parameter WIDTH_BYTEENA_A set to 64
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[0].core|mem_unit|dcache|[3].bank|tag_access|tag_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 19
|
|
Info (286033): Parameter WIDTHAD_A set to 6
|
|
Info (286033): Parameter NUMWORDS_A set to 64
|
|
Info (286033): Parameter WIDTH_B set to 19
|
|
Info (286033): Parameter WIDTHAD_B set to 6
|
|
Info (286033): Parameter NUMWORDS_B set to 64
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter INIT_FILE set to qdb/_compiler/afu_default/green_region/19.2.0/final/1/mifs/ram1_VX_sp_ram_647fd9b1.hdl.mif
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[0].core|mem_unit|dcache|[3].bank|data_access|data_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 512
|
|
Info (286033): Parameter WIDTHAD_A set to 6
|
|
Info (286033): Parameter NUMWORDS_A set to 64
|
|
Info (286033): Parameter WIDTH_B set to 512
|
|
Info (286033): Parameter WIDTHAD_B set to 6
|
|
Info (286033): Parameter NUMWORDS_B set to 64
|
|
Info (286033): Parameter WIDTH_BYTEENA_A set to 64
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[0].core|mem_unit|smem|[0].data|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 10
|
|
Info (286033): Parameter NUMWORDS_A set to 1024
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 10
|
|
Info (286033): Parameter NUMWORDS_B set to 1024
|
|
Info (286033): Parameter WIDTH_BYTEENA_A set to 4
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[0].core|mem_unit|smem|[1].data|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 10
|
|
Info (286033): Parameter NUMWORDS_A set to 1024
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 10
|
|
Info (286033): Parameter NUMWORDS_B set to 1024
|
|
Info (286033): Parameter WIDTH_BYTEENA_A set to 4
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[0].core|mem_unit|smem|[2].data|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 10
|
|
Info (286033): Parameter NUMWORDS_A set to 1024
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 10
|
|
Info (286033): Parameter NUMWORDS_B set to 1024
|
|
Info (286033): Parameter WIDTH_BYTEENA_A set to 4
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[0].core|mem_unit|smem|[3].data|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 10
|
|
Info (286033): Parameter NUMWORDS_A set to 1024
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 10
|
|
Info (286033): Parameter NUMWORDS_B set to 1024
|
|
Info (286033): Parameter WIDTH_BYTEENA_A set to 4
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[1].core|pipeline|issue|gpr_stage|[0].gpr_ram_f|mem_0_30_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[1].core|pipeline|issue|gpr_stage|[0].gpr_ram_f|mem_0_31_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[1].core|pipeline|issue|gpr_stage|[0].gpr_ram_f|mem_0_31_rtl_1"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (286033): Parameter RDCONTROL_REG_B set to CLOCK0
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[1].core|pipeline|issue|gpr_stage|[1].gpr_ram_f|mem_0_30_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[1].core|pipeline|issue|gpr_stage|[1].gpr_ram_f|mem_0_31_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[1].core|pipeline|issue|gpr_stage|[1].gpr_ram_f|mem_0_31_rtl_1"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (286033): Parameter RDCONTROL_REG_B set to CLOCK0
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[1].core|pipeline|issue|gpr_stage|[2].gpr_ram_f|mem_0_30_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[1].core|pipeline|issue|gpr_stage|[2].gpr_ram_f|mem_0_31_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[1].core|pipeline|issue|gpr_stage|[2].gpr_ram_f|mem_0_31_rtl_1"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (286033): Parameter RDCONTROL_REG_B set to CLOCK0
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[1].core|pipeline|issue|gpr_stage|[3].gpr_ram_f|mem_0_30_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[1].core|pipeline|issue|gpr_stage|[3].gpr_ram_f|mem_0_31_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[1].core|pipeline|issue|gpr_stage|[3].gpr_ram_f|mem_0_31_rtl_1"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (286033): Parameter RDCONTROL_REG_B set to CLOCK0
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[1].core|mem_unit|icache|[0].bank|tag_access|tag_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 19
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 19
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter INIT_FILE set to qdb/_compiler/afu_default/green_region/19.2.0/final/1/mifs/ram0_VX_sp_ram_647fd9b1.hdl.mif
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[1].core|mem_unit|icache|[0].bank|data_access|data_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 512
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 512
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[1].core|mem_unit|dcache|[0].bank|tag_access|tag_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 19
|
|
Info (286033): Parameter WIDTHAD_A set to 6
|
|
Info (286033): Parameter NUMWORDS_A set to 64
|
|
Info (286033): Parameter WIDTH_B set to 19
|
|
Info (286033): Parameter WIDTHAD_B set to 6
|
|
Info (286033): Parameter NUMWORDS_B set to 64
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter INIT_FILE set to qdb/_compiler/afu_default/green_region/19.2.0/final/1/mifs/ram1_VX_sp_ram_647fd9b1.hdl.mif
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[1].core|mem_unit|dcache|[0].bank|data_access|data_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 512
|
|
Info (286033): Parameter WIDTHAD_A set to 6
|
|
Info (286033): Parameter NUMWORDS_A set to 64
|
|
Info (286033): Parameter WIDTH_B set to 512
|
|
Info (286033): Parameter WIDTHAD_B set to 6
|
|
Info (286033): Parameter NUMWORDS_B set to 64
|
|
Info (286033): Parameter WIDTH_BYTEENA_A set to 64
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[1].core|mem_unit|dcache|[1].bank|tag_access|tag_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 19
|
|
Info (286033): Parameter WIDTHAD_A set to 6
|
|
Info (286033): Parameter NUMWORDS_A set to 64
|
|
Info (286033): Parameter WIDTH_B set to 19
|
|
Info (286033): Parameter WIDTHAD_B set to 6
|
|
Info (286033): Parameter NUMWORDS_B set to 64
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter INIT_FILE set to qdb/_compiler/afu_default/green_region/19.2.0/final/1/mifs/ram1_VX_sp_ram_647fd9b1.hdl.mif
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[1].core|mem_unit|dcache|[1].bank|data_access|data_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 512
|
|
Info (286033): Parameter WIDTHAD_A set to 6
|
|
Info (286033): Parameter NUMWORDS_A set to 64
|
|
Info (286033): Parameter WIDTH_B set to 512
|
|
Info (286033): Parameter WIDTHAD_B set to 6
|
|
Info (286033): Parameter NUMWORDS_B set to 64
|
|
Info (286033): Parameter WIDTH_BYTEENA_A set to 64
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[1].core|mem_unit|dcache|[2].bank|tag_access|tag_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 19
|
|
Info (286033): Parameter WIDTHAD_A set to 6
|
|
Info (286033): Parameter NUMWORDS_A set to 64
|
|
Info (286033): Parameter WIDTH_B set to 19
|
|
Info (286033): Parameter WIDTHAD_B set to 6
|
|
Info (286033): Parameter NUMWORDS_B set to 64
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter INIT_FILE set to qdb/_compiler/afu_default/green_region/19.2.0/final/1/mifs/ram1_VX_sp_ram_647fd9b1.hdl.mif
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[1].core|mem_unit|dcache|[2].bank|data_access|data_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 512
|
|
Info (286033): Parameter WIDTHAD_A set to 6
|
|
Info (286033): Parameter NUMWORDS_A set to 64
|
|
Info (286033): Parameter WIDTH_B set to 512
|
|
Info (286033): Parameter WIDTHAD_B set to 6
|
|
Info (286033): Parameter NUMWORDS_B set to 64
|
|
Info (286033): Parameter WIDTH_BYTEENA_A set to 64
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[1].core|mem_unit|dcache|[3].bank|tag_access|tag_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 19
|
|
Info (286033): Parameter WIDTHAD_A set to 6
|
|
Info (286033): Parameter NUMWORDS_A set to 64
|
|
Info (286033): Parameter WIDTH_B set to 19
|
|
Info (286033): Parameter WIDTHAD_B set to 6
|
|
Info (286033): Parameter NUMWORDS_B set to 64
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter INIT_FILE set to qdb/_compiler/afu_default/green_region/19.2.0/final/1/mifs/ram1_VX_sp_ram_647fd9b1.hdl.mif
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[1].core|mem_unit|dcache|[3].bank|data_access|data_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 512
|
|
Info (286033): Parameter WIDTHAD_A set to 6
|
|
Info (286033): Parameter NUMWORDS_A set to 64
|
|
Info (286033): Parameter WIDTH_B set to 512
|
|
Info (286033): Parameter WIDTHAD_B set to 6
|
|
Info (286033): Parameter NUMWORDS_B set to 64
|
|
Info (286033): Parameter WIDTH_BYTEENA_A set to 64
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[1].core|mem_unit|smem|[0].data|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 10
|
|
Info (286033): Parameter NUMWORDS_A set to 1024
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 10
|
|
Info (286033): Parameter NUMWORDS_B set to 1024
|
|
Info (286033): Parameter WIDTH_BYTEENA_A set to 4
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[1].core|mem_unit|smem|[1].data|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 10
|
|
Info (286033): Parameter NUMWORDS_A set to 1024
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 10
|
|
Info (286033): Parameter NUMWORDS_B set to 1024
|
|
Info (286033): Parameter WIDTH_BYTEENA_A set to 4
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[1].core|mem_unit|smem|[2].data|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 10
|
|
Info (286033): Parameter NUMWORDS_A set to 1024
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 10
|
|
Info (286033): Parameter NUMWORDS_B set to 1024
|
|
Info (286033): Parameter WIDTH_BYTEENA_A set to 4
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[1].core|mem_unit|smem|[3].data|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 10
|
|
Info (286033): Parameter NUMWORDS_A set to 1024
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 10
|
|
Info (286033): Parameter NUMWORDS_B set to 1024
|
|
Info (286033): Parameter WIDTH_BYTEENA_A set to 4
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[2].core|pipeline|issue|gpr_stage|[0].gpr_ram_f|mem_0_30_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[2].core|pipeline|issue|gpr_stage|[0].gpr_ram_f|mem_0_31_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[2].core|pipeline|issue|gpr_stage|[0].gpr_ram_f|mem_0_31_rtl_1"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (286033): Parameter RDCONTROL_REG_B set to CLOCK0
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[2].core|pipeline|issue|gpr_stage|[1].gpr_ram_f|mem_0_30_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[2].core|pipeline|issue|gpr_stage|[1].gpr_ram_f|mem_0_31_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[2].core|pipeline|issue|gpr_stage|[1].gpr_ram_f|mem_0_31_rtl_1"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (286033): Parameter RDCONTROL_REG_B set to CLOCK0
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[2].core|pipeline|issue|gpr_stage|[2].gpr_ram_f|mem_0_30_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[2].core|pipeline|issue|gpr_stage|[2].gpr_ram_f|mem_0_31_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[2].core|pipeline|issue|gpr_stage|[2].gpr_ram_f|mem_0_31_rtl_1"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (286033): Parameter RDCONTROL_REG_B set to CLOCK0
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[2].core|pipeline|issue|gpr_stage|[3].gpr_ram_f|mem_0_30_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[2].core|pipeline|issue|gpr_stage|[3].gpr_ram_f|mem_0_31_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[2].core|pipeline|issue|gpr_stage|[3].gpr_ram_f|mem_0_31_rtl_1"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (286033): Parameter RDCONTROL_REG_B set to CLOCK0
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[2].core|mem_unit|icache|[0].bank|tag_access|tag_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 19
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 19
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter INIT_FILE set to qdb/_compiler/afu_default/green_region/19.2.0/final/1/mifs/ram0_VX_sp_ram_647fd9b1.hdl.mif
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[2].core|mem_unit|icache|[0].bank|data_access|data_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 512
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 512
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[2].core|mem_unit|dcache|[0].bank|tag_access|tag_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 19
|
|
Info (286033): Parameter WIDTHAD_A set to 6
|
|
Info (286033): Parameter NUMWORDS_A set to 64
|
|
Info (286033): Parameter WIDTH_B set to 19
|
|
Info (286033): Parameter WIDTHAD_B set to 6
|
|
Info (286033): Parameter NUMWORDS_B set to 64
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter INIT_FILE set to qdb/_compiler/afu_default/green_region/19.2.0/final/1/mifs/ram1_VX_sp_ram_647fd9b1.hdl.mif
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[2].core|mem_unit|dcache|[0].bank|data_access|data_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 512
|
|
Info (286033): Parameter WIDTHAD_A set to 6
|
|
Info (286033): Parameter NUMWORDS_A set to 64
|
|
Info (286033): Parameter WIDTH_B set to 512
|
|
Info (286033): Parameter WIDTHAD_B set to 6
|
|
Info (286033): Parameter NUMWORDS_B set to 64
|
|
Info (286033): Parameter WIDTH_BYTEENA_A set to 64
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[2].core|mem_unit|dcache|[1].bank|tag_access|tag_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 19
|
|
Info (286033): Parameter WIDTHAD_A set to 6
|
|
Info (286033): Parameter NUMWORDS_A set to 64
|
|
Info (286033): Parameter WIDTH_B set to 19
|
|
Info (286033): Parameter WIDTHAD_B set to 6
|
|
Info (286033): Parameter NUMWORDS_B set to 64
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter INIT_FILE set to qdb/_compiler/afu_default/green_region/19.2.0/final/1/mifs/ram1_VX_sp_ram_647fd9b1.hdl.mif
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[2].core|mem_unit|dcache|[1].bank|data_access|data_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 512
|
|
Info (286033): Parameter WIDTHAD_A set to 6
|
|
Info (286033): Parameter NUMWORDS_A set to 64
|
|
Info (286033): Parameter WIDTH_B set to 512
|
|
Info (286033): Parameter WIDTHAD_B set to 6
|
|
Info (286033): Parameter NUMWORDS_B set to 64
|
|
Info (286033): Parameter WIDTH_BYTEENA_A set to 64
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[2].core|mem_unit|dcache|[2].bank|tag_access|tag_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 19
|
|
Info (286033): Parameter WIDTHAD_A set to 6
|
|
Info (286033): Parameter NUMWORDS_A set to 64
|
|
Info (286033): Parameter WIDTH_B set to 19
|
|
Info (286033): Parameter WIDTHAD_B set to 6
|
|
Info (286033): Parameter NUMWORDS_B set to 64
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter INIT_FILE set to qdb/_compiler/afu_default/green_region/19.2.0/final/1/mifs/ram1_VX_sp_ram_647fd9b1.hdl.mif
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[2].core|mem_unit|dcache|[2].bank|data_access|data_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 512
|
|
Info (286033): Parameter WIDTHAD_A set to 6
|
|
Info (286033): Parameter NUMWORDS_A set to 64
|
|
Info (286033): Parameter WIDTH_B set to 512
|
|
Info (286033): Parameter WIDTHAD_B set to 6
|
|
Info (286033): Parameter NUMWORDS_B set to 64
|
|
Info (286033): Parameter WIDTH_BYTEENA_A set to 64
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[2].core|mem_unit|dcache|[3].bank|tag_access|tag_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 19
|
|
Info (286033): Parameter WIDTHAD_A set to 6
|
|
Info (286033): Parameter NUMWORDS_A set to 64
|
|
Info (286033): Parameter WIDTH_B set to 19
|
|
Info (286033): Parameter WIDTHAD_B set to 6
|
|
Info (286033): Parameter NUMWORDS_B set to 64
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter INIT_FILE set to qdb/_compiler/afu_default/green_region/19.2.0/final/1/mifs/ram1_VX_sp_ram_647fd9b1.hdl.mif
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[2].core|mem_unit|dcache|[3].bank|data_access|data_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 512
|
|
Info (286033): Parameter WIDTHAD_A set to 6
|
|
Info (286033): Parameter NUMWORDS_A set to 64
|
|
Info (286033): Parameter WIDTH_B set to 512
|
|
Info (286033): Parameter WIDTHAD_B set to 6
|
|
Info (286033): Parameter NUMWORDS_B set to 64
|
|
Info (286033): Parameter WIDTH_BYTEENA_A set to 64
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[2].core|mem_unit|smem|[0].data|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 10
|
|
Info (286033): Parameter NUMWORDS_A set to 1024
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 10
|
|
Info (286033): Parameter NUMWORDS_B set to 1024
|
|
Info (286033): Parameter WIDTH_BYTEENA_A set to 4
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[2].core|mem_unit|smem|[1].data|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 10
|
|
Info (286033): Parameter NUMWORDS_A set to 1024
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 10
|
|
Info (286033): Parameter NUMWORDS_B set to 1024
|
|
Info (286033): Parameter WIDTH_BYTEENA_A set to 4
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[2].core|mem_unit|smem|[2].data|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 10
|
|
Info (286033): Parameter NUMWORDS_A set to 1024
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 10
|
|
Info (286033): Parameter NUMWORDS_B set to 1024
|
|
Info (286033): Parameter WIDTH_BYTEENA_A set to 4
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[2].core|mem_unit|smem|[3].data|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 10
|
|
Info (286033): Parameter NUMWORDS_A set to 1024
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 10
|
|
Info (286033): Parameter NUMWORDS_B set to 1024
|
|
Info (286033): Parameter WIDTH_BYTEENA_A set to 4
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[3].core|pipeline|issue|gpr_stage|[0].gpr_ram_f|mem_0_30_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[3].core|pipeline|issue|gpr_stage|[0].gpr_ram_f|mem_0_31_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[3].core|pipeline|issue|gpr_stage|[0].gpr_ram_f|mem_0_31_rtl_1"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (286033): Parameter RDCONTROL_REG_B set to CLOCK0
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[3].core|pipeline|issue|gpr_stage|[1].gpr_ram_f|mem_0_30_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[3].core|pipeline|issue|gpr_stage|[1].gpr_ram_f|mem_0_31_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[3].core|pipeline|issue|gpr_stage|[1].gpr_ram_f|mem_0_31_rtl_1"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (286033): Parameter RDCONTROL_REG_B set to CLOCK0
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[3].core|pipeline|issue|gpr_stage|[2].gpr_ram_f|mem_0_30_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[3].core|pipeline|issue|gpr_stage|[2].gpr_ram_f|mem_0_31_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[3].core|pipeline|issue|gpr_stage|[2].gpr_ram_f|mem_0_31_rtl_1"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (286033): Parameter RDCONTROL_REG_B set to CLOCK0
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[3].core|pipeline|issue|gpr_stage|[3].gpr_ram_f|mem_0_30_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[3].core|pipeline|issue|gpr_stage|[3].gpr_ram_f|mem_0_31_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[3].core|pipeline|issue|gpr_stage|[3].gpr_ram_f|mem_0_31_rtl_1"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (286033): Parameter RDCONTROL_REG_B set to CLOCK0
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[3].core|mem_unit|icache|[0].bank|tag_access|tag_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 19
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 19
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter INIT_FILE set to qdb/_compiler/afu_default/green_region/19.2.0/final/1/mifs/ram0_VX_sp_ram_647fd9b1.hdl.mif
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[3].core|mem_unit|icache|[0].bank|data_access|data_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 512
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 512
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[3].core|mem_unit|dcache|[0].bank|tag_access|tag_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 19
|
|
Info (286033): Parameter WIDTHAD_A set to 6
|
|
Info (286033): Parameter NUMWORDS_A set to 64
|
|
Info (286033): Parameter WIDTH_B set to 19
|
|
Info (286033): Parameter WIDTHAD_B set to 6
|
|
Info (286033): Parameter NUMWORDS_B set to 64
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter INIT_FILE set to qdb/_compiler/afu_default/green_region/19.2.0/final/1/mifs/ram1_VX_sp_ram_647fd9b1.hdl.mif
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[3].core|mem_unit|dcache|[0].bank|data_access|data_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 512
|
|
Info (286033): Parameter WIDTHAD_A set to 6
|
|
Info (286033): Parameter NUMWORDS_A set to 64
|
|
Info (286033): Parameter WIDTH_B set to 512
|
|
Info (286033): Parameter WIDTHAD_B set to 6
|
|
Info (286033): Parameter NUMWORDS_B set to 64
|
|
Info (286033): Parameter WIDTH_BYTEENA_A set to 64
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[3].core|mem_unit|dcache|[1].bank|tag_access|tag_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 19
|
|
Info (286033): Parameter WIDTHAD_A set to 6
|
|
Info (286033): Parameter NUMWORDS_A set to 64
|
|
Info (286033): Parameter WIDTH_B set to 19
|
|
Info (286033): Parameter WIDTHAD_B set to 6
|
|
Info (286033): Parameter NUMWORDS_B set to 64
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter INIT_FILE set to qdb/_compiler/afu_default/green_region/19.2.0/final/1/mifs/ram1_VX_sp_ram_647fd9b1.hdl.mif
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[3].core|mem_unit|dcache|[1].bank|data_access|data_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 512
|
|
Info (286033): Parameter WIDTHAD_A set to 6
|
|
Info (286033): Parameter NUMWORDS_A set to 64
|
|
Info (286033): Parameter WIDTH_B set to 512
|
|
Info (286033): Parameter WIDTHAD_B set to 6
|
|
Info (286033): Parameter NUMWORDS_B set to 64
|
|
Info (286033): Parameter WIDTH_BYTEENA_A set to 64
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[3].core|mem_unit|dcache|[2].bank|tag_access|tag_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 19
|
|
Info (286033): Parameter WIDTHAD_A set to 6
|
|
Info (286033): Parameter NUMWORDS_A set to 64
|
|
Info (286033): Parameter WIDTH_B set to 19
|
|
Info (286033): Parameter WIDTHAD_B set to 6
|
|
Info (286033): Parameter NUMWORDS_B set to 64
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter INIT_FILE set to qdb/_compiler/afu_default/green_region/19.2.0/final/1/mifs/ram1_VX_sp_ram_647fd9b1.hdl.mif
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[3].core|mem_unit|dcache|[2].bank|data_access|data_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 512
|
|
Info (286033): Parameter WIDTHAD_A set to 6
|
|
Info (286033): Parameter NUMWORDS_A set to 64
|
|
Info (286033): Parameter WIDTH_B set to 512
|
|
Info (286033): Parameter WIDTHAD_B set to 6
|
|
Info (286033): Parameter NUMWORDS_B set to 64
|
|
Info (286033): Parameter WIDTH_BYTEENA_A set to 64
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[3].core|mem_unit|dcache|[3].bank|tag_access|tag_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 19
|
|
Info (286033): Parameter WIDTHAD_A set to 6
|
|
Info (286033): Parameter NUMWORDS_A set to 64
|
|
Info (286033): Parameter WIDTH_B set to 19
|
|
Info (286033): Parameter WIDTHAD_B set to 6
|
|
Info (286033): Parameter NUMWORDS_B set to 64
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter INIT_FILE set to qdb/_compiler/afu_default/green_region/19.2.0/final/1/mifs/ram1_VX_sp_ram_647fd9b1.hdl.mif
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[3].core|mem_unit|dcache|[3].bank|data_access|data_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 512
|
|
Info (286033): Parameter WIDTHAD_A set to 6
|
|
Info (286033): Parameter NUMWORDS_A set to 64
|
|
Info (286033): Parameter WIDTH_B set to 512
|
|
Info (286033): Parameter WIDTHAD_B set to 6
|
|
Info (286033): Parameter NUMWORDS_B set to 64
|
|
Info (286033): Parameter WIDTH_BYTEENA_A set to 64
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[3].core|mem_unit|smem|[0].data|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 10
|
|
Info (286033): Parameter NUMWORDS_A set to 1024
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 10
|
|
Info (286033): Parameter NUMWORDS_B set to 1024
|
|
Info (286033): Parameter WIDTH_BYTEENA_A set to 4
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[3].core|mem_unit|smem|[1].data|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 10
|
|
Info (286033): Parameter NUMWORDS_A set to 1024
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 10
|
|
Info (286033): Parameter NUMWORDS_B set to 1024
|
|
Info (286033): Parameter WIDTH_BYTEENA_A set to 4
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[3].core|mem_unit|smem|[2].data|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 10
|
|
Info (286033): Parameter NUMWORDS_A set to 1024
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 10
|
|
Info (286033): Parameter NUMWORDS_B set to 1024
|
|
Info (286033): Parameter WIDTH_BYTEENA_A set to 4
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[3].core|mem_unit|smem|[3].data|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 10
|
|
Info (286033): Parameter NUMWORDS_A set to 1024
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 10
|
|
Info (286033): Parameter NUMWORDS_B set to 1024
|
|
Info (286033): Parameter WIDTH_BYTEENA_A set to 4
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[0].core|pipeline|issue|gpr_stage|[0].gpr_ram_f|mem_0_30_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[0].core|pipeline|issue|gpr_stage|[0].gpr_ram_f|mem_0_31_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[0].core|pipeline|issue|gpr_stage|[0].gpr_ram_f|mem_0_31_rtl_1"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (286033): Parameter RDCONTROL_REG_B set to CLOCK0
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[0].core|pipeline|issue|gpr_stage|[1].gpr_ram_f|mem_0_30_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[0].core|pipeline|issue|gpr_stage|[1].gpr_ram_f|mem_0_31_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[0].core|pipeline|issue|gpr_stage|[1].gpr_ram_f|mem_0_31_rtl_1"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (286033): Parameter RDCONTROL_REG_B set to CLOCK0
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[0].core|pipeline|issue|gpr_stage|[2].gpr_ram_f|mem_0_30_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[0].core|pipeline|issue|gpr_stage|[2].gpr_ram_f|mem_0_31_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[0].core|pipeline|issue|gpr_stage|[2].gpr_ram_f|mem_0_31_rtl_1"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (286033): Parameter RDCONTROL_REG_B set to CLOCK0
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[0].core|pipeline|issue|gpr_stage|[3].gpr_ram_f|mem_0_30_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[0].core|pipeline|issue|gpr_stage|[3].gpr_ram_f|mem_0_31_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[0].core|pipeline|issue|gpr_stage|[3].gpr_ram_f|mem_0_31_rtl_1"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (286033): Parameter RDCONTROL_REG_B set to CLOCK0
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[0].core|mem_unit|icache|[0].bank|tag_access|tag_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 19
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 19
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter INIT_FILE set to qdb/_compiler/afu_default/green_region/19.2.0/final/1/mifs/ram0_VX_sp_ram_647fd9b1.hdl.mif
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[0].core|mem_unit|icache|[0].bank|data_access|data_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 512
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 512
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[0].core|mem_unit|dcache|[0].bank|tag_access|tag_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 19
|
|
Info (286033): Parameter WIDTHAD_A set to 6
|
|
Info (286033): Parameter NUMWORDS_A set to 64
|
|
Info (286033): Parameter WIDTH_B set to 19
|
|
Info (286033): Parameter WIDTHAD_B set to 6
|
|
Info (286033): Parameter NUMWORDS_B set to 64
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter INIT_FILE set to qdb/_compiler/afu_default/green_region/19.2.0/final/1/mifs/ram1_VX_sp_ram_647fd9b1.hdl.mif
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[0].core|mem_unit|dcache|[0].bank|data_access|data_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 512
|
|
Info (286033): Parameter WIDTHAD_A set to 6
|
|
Info (286033): Parameter NUMWORDS_A set to 64
|
|
Info (286033): Parameter WIDTH_B set to 512
|
|
Info (286033): Parameter WIDTHAD_B set to 6
|
|
Info (286033): Parameter NUMWORDS_B set to 64
|
|
Info (286033): Parameter WIDTH_BYTEENA_A set to 64
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[0].core|mem_unit|dcache|[1].bank|tag_access|tag_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 19
|
|
Info (286033): Parameter WIDTHAD_A set to 6
|
|
Info (286033): Parameter NUMWORDS_A set to 64
|
|
Info (286033): Parameter WIDTH_B set to 19
|
|
Info (286033): Parameter WIDTHAD_B set to 6
|
|
Info (286033): Parameter NUMWORDS_B set to 64
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter INIT_FILE set to qdb/_compiler/afu_default/green_region/19.2.0/final/1/mifs/ram1_VX_sp_ram_647fd9b1.hdl.mif
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[0].core|mem_unit|dcache|[1].bank|data_access|data_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 512
|
|
Info (286033): Parameter WIDTHAD_A set to 6
|
|
Info (286033): Parameter NUMWORDS_A set to 64
|
|
Info (286033): Parameter WIDTH_B set to 512
|
|
Info (286033): Parameter WIDTHAD_B set to 6
|
|
Info (286033): Parameter NUMWORDS_B set to 64
|
|
Info (286033): Parameter WIDTH_BYTEENA_A set to 64
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[0].core|mem_unit|dcache|[2].bank|tag_access|tag_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 19
|
|
Info (286033): Parameter WIDTHAD_A set to 6
|
|
Info (286033): Parameter NUMWORDS_A set to 64
|
|
Info (286033): Parameter WIDTH_B set to 19
|
|
Info (286033): Parameter WIDTHAD_B set to 6
|
|
Info (286033): Parameter NUMWORDS_B set to 64
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter INIT_FILE set to qdb/_compiler/afu_default/green_region/19.2.0/final/1/mifs/ram1_VX_sp_ram_647fd9b1.hdl.mif
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[0].core|mem_unit|dcache|[2].bank|data_access|data_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 512
|
|
Info (286033): Parameter WIDTHAD_A set to 6
|
|
Info (286033): Parameter NUMWORDS_A set to 64
|
|
Info (286033): Parameter WIDTH_B set to 512
|
|
Info (286033): Parameter WIDTHAD_B set to 6
|
|
Info (286033): Parameter NUMWORDS_B set to 64
|
|
Info (286033): Parameter WIDTH_BYTEENA_A set to 64
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[0].core|mem_unit|dcache|[3].bank|tag_access|tag_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 19
|
|
Info (286033): Parameter WIDTHAD_A set to 6
|
|
Info (286033): Parameter NUMWORDS_A set to 64
|
|
Info (286033): Parameter WIDTH_B set to 19
|
|
Info (286033): Parameter WIDTHAD_B set to 6
|
|
Info (286033): Parameter NUMWORDS_B set to 64
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter INIT_FILE set to qdb/_compiler/afu_default/green_region/19.2.0/final/1/mifs/ram1_VX_sp_ram_647fd9b1.hdl.mif
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[0].core|mem_unit|dcache|[3].bank|data_access|data_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 512
|
|
Info (286033): Parameter WIDTHAD_A set to 6
|
|
Info (286033): Parameter NUMWORDS_A set to 64
|
|
Info (286033): Parameter WIDTH_B set to 512
|
|
Info (286033): Parameter WIDTHAD_B set to 6
|
|
Info (286033): Parameter NUMWORDS_B set to 64
|
|
Info (286033): Parameter WIDTH_BYTEENA_A set to 64
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[0].core|mem_unit|smem|[0].data|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 10
|
|
Info (286033): Parameter NUMWORDS_A set to 1024
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 10
|
|
Info (286033): Parameter NUMWORDS_B set to 1024
|
|
Info (286033): Parameter WIDTH_BYTEENA_A set to 4
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[0].core|mem_unit|smem|[1].data|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 10
|
|
Info (286033): Parameter NUMWORDS_A set to 1024
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 10
|
|
Info (286033): Parameter NUMWORDS_B set to 1024
|
|
Info (286033): Parameter WIDTH_BYTEENA_A set to 4
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[0].core|mem_unit|smem|[2].data|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 10
|
|
Info (286033): Parameter NUMWORDS_A set to 1024
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 10
|
|
Info (286033): Parameter NUMWORDS_B set to 1024
|
|
Info (286033): Parameter WIDTH_BYTEENA_A set to 4
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[0].core|mem_unit|smem|[3].data|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 10
|
|
Info (286033): Parameter NUMWORDS_A set to 1024
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 10
|
|
Info (286033): Parameter NUMWORDS_B set to 1024
|
|
Info (286033): Parameter WIDTH_BYTEENA_A set to 4
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[1].core|pipeline|issue|gpr_stage|[0].gpr_ram_f|mem_0_30_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[1].core|pipeline|issue|gpr_stage|[0].gpr_ram_f|mem_0_31_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[1].core|pipeline|issue|gpr_stage|[0].gpr_ram_f|mem_0_31_rtl_1"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (286033): Parameter RDCONTROL_REG_B set to CLOCK0
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[1].core|pipeline|issue|gpr_stage|[1].gpr_ram_f|mem_0_30_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[1].core|pipeline|issue|gpr_stage|[1].gpr_ram_f|mem_0_31_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[1].core|pipeline|issue|gpr_stage|[1].gpr_ram_f|mem_0_31_rtl_1"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (286033): Parameter RDCONTROL_REG_B set to CLOCK0
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[1].core|pipeline|issue|gpr_stage|[2].gpr_ram_f|mem_0_30_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[1].core|pipeline|issue|gpr_stage|[2].gpr_ram_f|mem_0_31_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[1].core|pipeline|issue|gpr_stage|[2].gpr_ram_f|mem_0_31_rtl_1"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (286033): Parameter RDCONTROL_REG_B set to CLOCK0
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[1].core|pipeline|issue|gpr_stage|[3].gpr_ram_f|mem_0_30_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[1].core|pipeline|issue|gpr_stage|[3].gpr_ram_f|mem_0_31_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[1].core|pipeline|issue|gpr_stage|[3].gpr_ram_f|mem_0_31_rtl_1"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (286033): Parameter RDCONTROL_REG_B set to CLOCK0
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[1].core|mem_unit|icache|[0].bank|tag_access|tag_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 19
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 19
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter INIT_FILE set to qdb/_compiler/afu_default/green_region/19.2.0/final/1/mifs/ram0_VX_sp_ram_647fd9b1.hdl.mif
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[1].core|mem_unit|icache|[0].bank|data_access|data_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 512
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 512
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[1].core|mem_unit|dcache|[0].bank|tag_access|tag_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 19
|
|
Info (286033): Parameter WIDTHAD_A set to 6
|
|
Info (286033): Parameter NUMWORDS_A set to 64
|
|
Info (286033): Parameter WIDTH_B set to 19
|
|
Info (286033): Parameter WIDTHAD_B set to 6
|
|
Info (286033): Parameter NUMWORDS_B set to 64
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter INIT_FILE set to qdb/_compiler/afu_default/green_region/19.2.0/final/1/mifs/ram1_VX_sp_ram_647fd9b1.hdl.mif
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[1].core|mem_unit|dcache|[0].bank|data_access|data_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 512
|
|
Info (286033): Parameter WIDTHAD_A set to 6
|
|
Info (286033): Parameter NUMWORDS_A set to 64
|
|
Info (286033): Parameter WIDTH_B set to 512
|
|
Info (286033): Parameter WIDTHAD_B set to 6
|
|
Info (286033): Parameter NUMWORDS_B set to 64
|
|
Info (286033): Parameter WIDTH_BYTEENA_A set to 64
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[1].core|mem_unit|dcache|[1].bank|tag_access|tag_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 19
|
|
Info (286033): Parameter WIDTHAD_A set to 6
|
|
Info (286033): Parameter NUMWORDS_A set to 64
|
|
Info (286033): Parameter WIDTH_B set to 19
|
|
Info (286033): Parameter WIDTHAD_B set to 6
|
|
Info (286033): Parameter NUMWORDS_B set to 64
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter INIT_FILE set to qdb/_compiler/afu_default/green_region/19.2.0/final/1/mifs/ram1_VX_sp_ram_647fd9b1.hdl.mif
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[1].core|mem_unit|dcache|[1].bank|data_access|data_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 512
|
|
Info (286033): Parameter WIDTHAD_A set to 6
|
|
Info (286033): Parameter NUMWORDS_A set to 64
|
|
Info (286033): Parameter WIDTH_B set to 512
|
|
Info (286033): Parameter WIDTHAD_B set to 6
|
|
Info (286033): Parameter NUMWORDS_B set to 64
|
|
Info (286033): Parameter WIDTH_BYTEENA_A set to 64
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[1].core|mem_unit|dcache|[2].bank|tag_access|tag_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 19
|
|
Info (286033): Parameter WIDTHAD_A set to 6
|
|
Info (286033): Parameter NUMWORDS_A set to 64
|
|
Info (286033): Parameter WIDTH_B set to 19
|
|
Info (286033): Parameter WIDTHAD_B set to 6
|
|
Info (286033): Parameter NUMWORDS_B set to 64
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter INIT_FILE set to qdb/_compiler/afu_default/green_region/19.2.0/final/1/mifs/ram1_VX_sp_ram_647fd9b1.hdl.mif
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[1].core|mem_unit|dcache|[2].bank|data_access|data_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 512
|
|
Info (286033): Parameter WIDTHAD_A set to 6
|
|
Info (286033): Parameter NUMWORDS_A set to 64
|
|
Info (286033): Parameter WIDTH_B set to 512
|
|
Info (286033): Parameter WIDTHAD_B set to 6
|
|
Info (286033): Parameter NUMWORDS_B set to 64
|
|
Info (286033): Parameter WIDTH_BYTEENA_A set to 64
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[1].core|mem_unit|dcache|[3].bank|tag_access|tag_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 19
|
|
Info (286033): Parameter WIDTHAD_A set to 6
|
|
Info (286033): Parameter NUMWORDS_A set to 64
|
|
Info (286033): Parameter WIDTH_B set to 19
|
|
Info (286033): Parameter WIDTHAD_B set to 6
|
|
Info (286033): Parameter NUMWORDS_B set to 64
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter INIT_FILE set to qdb/_compiler/afu_default/green_region/19.2.0/final/1/mifs/ram1_VX_sp_ram_647fd9b1.hdl.mif
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[1].core|mem_unit|dcache|[3].bank|data_access|data_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 512
|
|
Info (286033): Parameter WIDTHAD_A set to 6
|
|
Info (286033): Parameter NUMWORDS_A set to 64
|
|
Info (286033): Parameter WIDTH_B set to 512
|
|
Info (286033): Parameter WIDTHAD_B set to 6
|
|
Info (286033): Parameter NUMWORDS_B set to 64
|
|
Info (286033): Parameter WIDTH_BYTEENA_A set to 64
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[1].core|mem_unit|smem|[0].data|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 10
|
|
Info (286033): Parameter NUMWORDS_A set to 1024
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 10
|
|
Info (286033): Parameter NUMWORDS_B set to 1024
|
|
Info (286033): Parameter WIDTH_BYTEENA_A set to 4
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[1].core|mem_unit|smem|[1].data|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 10
|
|
Info (286033): Parameter NUMWORDS_A set to 1024
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 10
|
|
Info (286033): Parameter NUMWORDS_B set to 1024
|
|
Info (286033): Parameter WIDTH_BYTEENA_A set to 4
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[1].core|mem_unit|smem|[2].data|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 10
|
|
Info (286033): Parameter NUMWORDS_A set to 1024
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 10
|
|
Info (286033): Parameter NUMWORDS_B set to 1024
|
|
Info (286033): Parameter WIDTH_BYTEENA_A set to 4
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[1].core|mem_unit|smem|[3].data|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 10
|
|
Info (286033): Parameter NUMWORDS_A set to 1024
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 10
|
|
Info (286033): Parameter NUMWORDS_B set to 1024
|
|
Info (286033): Parameter WIDTH_BYTEENA_A set to 4
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[2].core|pipeline|issue|gpr_stage|[0].gpr_ram_f|mem_0_30_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[2].core|pipeline|issue|gpr_stage|[0].gpr_ram_f|mem_0_31_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[2].core|pipeline|issue|gpr_stage|[0].gpr_ram_f|mem_0_31_rtl_1"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (286033): Parameter RDCONTROL_REG_B set to CLOCK0
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[2].core|pipeline|issue|gpr_stage|[1].gpr_ram_f|mem_0_30_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[2].core|pipeline|issue|gpr_stage|[1].gpr_ram_f|mem_0_31_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[2].core|pipeline|issue|gpr_stage|[1].gpr_ram_f|mem_0_31_rtl_1"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (286033): Parameter RDCONTROL_REG_B set to CLOCK0
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[2].core|pipeline|issue|gpr_stage|[2].gpr_ram_f|mem_0_30_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[2].core|pipeline|issue|gpr_stage|[2].gpr_ram_f|mem_0_31_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[2].core|pipeline|issue|gpr_stage|[2].gpr_ram_f|mem_0_31_rtl_1"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (286033): Parameter RDCONTROL_REG_B set to CLOCK0
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[2].core|pipeline|issue|gpr_stage|[3].gpr_ram_f|mem_0_30_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[2].core|pipeline|issue|gpr_stage|[3].gpr_ram_f|mem_0_31_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[2].core|pipeline|issue|gpr_stage|[3].gpr_ram_f|mem_0_31_rtl_1"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (286033): Parameter RDCONTROL_REG_B set to CLOCK0
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[2].core|mem_unit|icache|[0].bank|tag_access|tag_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 19
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 19
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter INIT_FILE set to qdb/_compiler/afu_default/green_region/19.2.0/final/1/mifs/ram0_VX_sp_ram_647fd9b1.hdl.mif
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[2].core|mem_unit|icache|[0].bank|data_access|data_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 512
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 512
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[2].core|mem_unit|dcache|[0].bank|tag_access|tag_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 19
|
|
Info (286033): Parameter WIDTHAD_A set to 6
|
|
Info (286033): Parameter NUMWORDS_A set to 64
|
|
Info (286033): Parameter WIDTH_B set to 19
|
|
Info (286033): Parameter WIDTHAD_B set to 6
|
|
Info (286033): Parameter NUMWORDS_B set to 64
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter INIT_FILE set to qdb/_compiler/afu_default/green_region/19.2.0/final/1/mifs/ram1_VX_sp_ram_647fd9b1.hdl.mif
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[2].core|mem_unit|dcache|[0].bank|data_access|data_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 512
|
|
Info (286033): Parameter WIDTHAD_A set to 6
|
|
Info (286033): Parameter NUMWORDS_A set to 64
|
|
Info (286033): Parameter WIDTH_B set to 512
|
|
Info (286033): Parameter WIDTHAD_B set to 6
|
|
Info (286033): Parameter NUMWORDS_B set to 64
|
|
Info (286033): Parameter WIDTH_BYTEENA_A set to 64
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[2].core|mem_unit|dcache|[1].bank|tag_access|tag_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 19
|
|
Info (286033): Parameter WIDTHAD_A set to 6
|
|
Info (286033): Parameter NUMWORDS_A set to 64
|
|
Info (286033): Parameter WIDTH_B set to 19
|
|
Info (286033): Parameter WIDTHAD_B set to 6
|
|
Info (286033): Parameter NUMWORDS_B set to 64
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter INIT_FILE set to qdb/_compiler/afu_default/green_region/19.2.0/final/1/mifs/ram1_VX_sp_ram_647fd9b1.hdl.mif
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[2].core|mem_unit|dcache|[1].bank|data_access|data_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 512
|
|
Info (286033): Parameter WIDTHAD_A set to 6
|
|
Info (286033): Parameter NUMWORDS_A set to 64
|
|
Info (286033): Parameter WIDTH_B set to 512
|
|
Info (286033): Parameter WIDTHAD_B set to 6
|
|
Info (286033): Parameter NUMWORDS_B set to 64
|
|
Info (286033): Parameter WIDTH_BYTEENA_A set to 64
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[2].core|mem_unit|dcache|[2].bank|tag_access|tag_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 19
|
|
Info (286033): Parameter WIDTHAD_A set to 6
|
|
Info (286033): Parameter NUMWORDS_A set to 64
|
|
Info (286033): Parameter WIDTH_B set to 19
|
|
Info (286033): Parameter WIDTHAD_B set to 6
|
|
Info (286033): Parameter NUMWORDS_B set to 64
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter INIT_FILE set to qdb/_compiler/afu_default/green_region/19.2.0/final/1/mifs/ram1_VX_sp_ram_647fd9b1.hdl.mif
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[2].core|mem_unit|dcache|[2].bank|data_access|data_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 512
|
|
Info (286033): Parameter WIDTHAD_A set to 6
|
|
Info (286033): Parameter NUMWORDS_A set to 64
|
|
Info (286033): Parameter WIDTH_B set to 512
|
|
Info (286033): Parameter WIDTHAD_B set to 6
|
|
Info (286033): Parameter NUMWORDS_B set to 64
|
|
Info (286033): Parameter WIDTH_BYTEENA_A set to 64
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[2].core|mem_unit|dcache|[3].bank|tag_access|tag_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 19
|
|
Info (286033): Parameter WIDTHAD_A set to 6
|
|
Info (286033): Parameter NUMWORDS_A set to 64
|
|
Info (286033): Parameter WIDTH_B set to 19
|
|
Info (286033): Parameter WIDTHAD_B set to 6
|
|
Info (286033): Parameter NUMWORDS_B set to 64
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter INIT_FILE set to qdb/_compiler/afu_default/green_region/19.2.0/final/1/mifs/ram1_VX_sp_ram_647fd9b1.hdl.mif
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[2].core|mem_unit|dcache|[3].bank|data_access|data_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 512
|
|
Info (286033): Parameter WIDTHAD_A set to 6
|
|
Info (286033): Parameter NUMWORDS_A set to 64
|
|
Info (286033): Parameter WIDTH_B set to 512
|
|
Info (286033): Parameter WIDTHAD_B set to 6
|
|
Info (286033): Parameter NUMWORDS_B set to 64
|
|
Info (286033): Parameter WIDTH_BYTEENA_A set to 64
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[2].core|mem_unit|smem|[0].data|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 10
|
|
Info (286033): Parameter NUMWORDS_A set to 1024
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 10
|
|
Info (286033): Parameter NUMWORDS_B set to 1024
|
|
Info (286033): Parameter WIDTH_BYTEENA_A set to 4
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[2].core|mem_unit|smem|[1].data|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 10
|
|
Info (286033): Parameter NUMWORDS_A set to 1024
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 10
|
|
Info (286033): Parameter NUMWORDS_B set to 1024
|
|
Info (286033): Parameter WIDTH_BYTEENA_A set to 4
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[2].core|mem_unit|smem|[2].data|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 10
|
|
Info (286033): Parameter NUMWORDS_A set to 1024
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 10
|
|
Info (286033): Parameter NUMWORDS_B set to 1024
|
|
Info (286033): Parameter WIDTH_BYTEENA_A set to 4
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[2].core|mem_unit|smem|[3].data|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 10
|
|
Info (286033): Parameter NUMWORDS_A set to 1024
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 10
|
|
Info (286033): Parameter NUMWORDS_B set to 1024
|
|
Info (286033): Parameter WIDTH_BYTEENA_A set to 4
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[3].core|pipeline|issue|gpr_stage|[0].gpr_ram_f|mem_0_30_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[3].core|pipeline|issue|gpr_stage|[0].gpr_ram_f|mem_0_31_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[3].core|pipeline|issue|gpr_stage|[0].gpr_ram_f|mem_0_31_rtl_1"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (286033): Parameter RDCONTROL_REG_B set to CLOCK0
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[3].core|pipeline|issue|gpr_stage|[1].gpr_ram_f|mem_0_30_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[3].core|pipeline|issue|gpr_stage|[1].gpr_ram_f|mem_0_31_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[3].core|pipeline|issue|gpr_stage|[1].gpr_ram_f|mem_0_31_rtl_1"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (286033): Parameter RDCONTROL_REG_B set to CLOCK0
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[3].core|pipeline|issue|gpr_stage|[2].gpr_ram_f|mem_0_30_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[3].core|pipeline|issue|gpr_stage|[2].gpr_ram_f|mem_0_31_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[3].core|pipeline|issue|gpr_stage|[2].gpr_ram_f|mem_0_31_rtl_1"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (286033): Parameter RDCONTROL_REG_B set to CLOCK0
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[3].core|pipeline|issue|gpr_stage|[3].gpr_ram_f|mem_0_30_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[3].core|pipeline|issue|gpr_stage|[3].gpr_ram_f|mem_0_31_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[3].core|pipeline|issue|gpr_stage|[3].gpr_ram_f|mem_0_31_rtl_1"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (286033): Parameter RDCONTROL_REG_B set to CLOCK0
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[3].core|mem_unit|icache|[0].bank|tag_access|tag_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 19
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 19
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter INIT_FILE set to qdb/_compiler/afu_default/green_region/19.2.0/final/1/mifs/ram0_VX_sp_ram_647fd9b1.hdl.mif
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[3].core|mem_unit|icache|[0].bank|data_access|data_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 512
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 512
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[3].core|mem_unit|dcache|[0].bank|tag_access|tag_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 19
|
|
Info (286033): Parameter WIDTHAD_A set to 6
|
|
Info (286033): Parameter NUMWORDS_A set to 64
|
|
Info (286033): Parameter WIDTH_B set to 19
|
|
Info (286033): Parameter WIDTHAD_B set to 6
|
|
Info (286033): Parameter NUMWORDS_B set to 64
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter INIT_FILE set to qdb/_compiler/afu_default/green_region/19.2.0/final/1/mifs/ram1_VX_sp_ram_647fd9b1.hdl.mif
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[3].core|mem_unit|dcache|[0].bank|data_access|data_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 512
|
|
Info (286033): Parameter WIDTHAD_A set to 6
|
|
Info (286033): Parameter NUMWORDS_A set to 64
|
|
Info (286033): Parameter WIDTH_B set to 512
|
|
Info (286033): Parameter WIDTHAD_B set to 6
|
|
Info (286033): Parameter NUMWORDS_B set to 64
|
|
Info (286033): Parameter WIDTH_BYTEENA_A set to 64
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[3].core|mem_unit|dcache|[1].bank|tag_access|tag_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 19
|
|
Info (286033): Parameter WIDTHAD_A set to 6
|
|
Info (286033): Parameter NUMWORDS_A set to 64
|
|
Info (286033): Parameter WIDTH_B set to 19
|
|
Info (286033): Parameter WIDTHAD_B set to 6
|
|
Info (286033): Parameter NUMWORDS_B set to 64
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter INIT_FILE set to qdb/_compiler/afu_default/green_region/19.2.0/final/1/mifs/ram1_VX_sp_ram_647fd9b1.hdl.mif
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[3].core|mem_unit|dcache|[1].bank|data_access|data_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 512
|
|
Info (286033): Parameter WIDTHAD_A set to 6
|
|
Info (286033): Parameter NUMWORDS_A set to 64
|
|
Info (286033): Parameter WIDTH_B set to 512
|
|
Info (286033): Parameter WIDTHAD_B set to 6
|
|
Info (286033): Parameter NUMWORDS_B set to 64
|
|
Info (286033): Parameter WIDTH_BYTEENA_A set to 64
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[3].core|mem_unit|dcache|[2].bank|tag_access|tag_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 19
|
|
Info (286033): Parameter WIDTHAD_A set to 6
|
|
Info (286033): Parameter NUMWORDS_A set to 64
|
|
Info (286033): Parameter WIDTH_B set to 19
|
|
Info (286033): Parameter WIDTHAD_B set to 6
|
|
Info (286033): Parameter NUMWORDS_B set to 64
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter INIT_FILE set to qdb/_compiler/afu_default/green_region/19.2.0/final/1/mifs/ram1_VX_sp_ram_647fd9b1.hdl.mif
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[3].core|mem_unit|dcache|[2].bank|data_access|data_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 512
|
|
Info (286033): Parameter WIDTHAD_A set to 6
|
|
Info (286033): Parameter NUMWORDS_A set to 64
|
|
Info (286033): Parameter WIDTH_B set to 512
|
|
Info (286033): Parameter WIDTHAD_B set to 6
|
|
Info (286033): Parameter NUMWORDS_B set to 64
|
|
Info (286033): Parameter WIDTH_BYTEENA_A set to 64
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[3].core|mem_unit|dcache|[3].bank|tag_access|tag_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 19
|
|
Info (286033): Parameter WIDTHAD_A set to 6
|
|
Info (286033): Parameter NUMWORDS_A set to 64
|
|
Info (286033): Parameter WIDTH_B set to 19
|
|
Info (286033): Parameter WIDTHAD_B set to 6
|
|
Info (286033): Parameter NUMWORDS_B set to 64
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter INIT_FILE set to qdb/_compiler/afu_default/green_region/19.2.0/final/1/mifs/ram1_VX_sp_ram_647fd9b1.hdl.mif
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[3].core|mem_unit|dcache|[3].bank|data_access|data_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 512
|
|
Info (286033): Parameter WIDTHAD_A set to 6
|
|
Info (286033): Parameter NUMWORDS_A set to 64
|
|
Info (286033): Parameter WIDTH_B set to 512
|
|
Info (286033): Parameter WIDTHAD_B set to 6
|
|
Info (286033): Parameter NUMWORDS_B set to 64
|
|
Info (286033): Parameter WIDTH_BYTEENA_A set to 64
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[3].core|mem_unit|smem|[0].data|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 10
|
|
Info (286033): Parameter NUMWORDS_A set to 1024
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 10
|
|
Info (286033): Parameter NUMWORDS_B set to 1024
|
|
Info (286033): Parameter WIDTH_BYTEENA_A set to 4
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[3].core|mem_unit|smem|[1].data|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 10
|
|
Info (286033): Parameter NUMWORDS_A set to 1024
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 10
|
|
Info (286033): Parameter NUMWORDS_B set to 1024
|
|
Info (286033): Parameter WIDTH_BYTEENA_A set to 4
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[3].core|mem_unit|smem|[2].data|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 10
|
|
Info (286033): Parameter NUMWORDS_A set to 1024
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 10
|
|
Info (286033): Parameter NUMWORDS_B set to 1024
|
|
Info (286033): Parameter WIDTH_BYTEENA_A set to 4
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[1].cluster|[3].core|mem_unit|smem|[3].data|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 10
|
|
Info (286033): Parameter NUMWORDS_A set to 1024
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 10
|
|
Info (286033): Parameter NUMWORDS_B set to 1024
|
|
Info (286033): Parameter WIDTH_BYTEENA_A set to 4
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|issue|gpr_stage|[0].gpr_ram_f|mem_0_30_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|issue|gpr_stage|[0].gpr_ram_f|mem_0_31_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|issue|gpr_stage|[0].gpr_ram_f|mem_0_31_rtl_1"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (286033): Parameter RDCONTROL_REG_B set to CLOCK0
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|issue|gpr_stage|[1].gpr_ram_f|mem_0_30_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|issue|gpr_stage|[1].gpr_ram_f|mem_0_31_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|issue|gpr_stage|[1].gpr_ram_f|mem_0_31_rtl_1"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (286033): Parameter RDCONTROL_REG_B set to CLOCK0
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|issue|gpr_stage|[2].gpr_ram_f|mem_0_30_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|issue|gpr_stage|[2].gpr_ram_f|mem_0_31_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|issue|gpr_stage|[2].gpr_ram_f|mem_0_31_rtl_1"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (286033): Parameter RDCONTROL_REG_B set to CLOCK0
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|issue|gpr_stage|[3].gpr_ram_f|mem_0_30_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|issue|gpr_stage|[3].gpr_ram_f|mem_0_31_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|issue|gpr_stage|[3].gpr_ram_f|mem_0_31_rtl_1"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (286033): Parameter RDCONTROL_REG_B set to CLOCK0
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|mem_unit|icache|[0].bank|tag_access|tag_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 19
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 19
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter INIT_FILE set to qdb/_compiler/afu_default/green_region/19.2.0/final/1/mifs/ram0_VX_sp_ram_647fd9b1.hdl.mif
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|mem_unit|icache|[0].bank|data_access|data_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 512
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 512
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|mem_unit|dcache|[0].bank|tag_access|tag_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 19
|
|
Info (286033): Parameter WIDTHAD_A set to 6
|
|
Info (286033): Parameter NUMWORDS_A set to 64
|
|
Info (286033): Parameter WIDTH_B set to 19
|
|
Info (286033): Parameter WIDTHAD_B set to 6
|
|
Info (286033): Parameter NUMWORDS_B set to 64
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter INIT_FILE set to qdb/_compiler/afu_default/green_region/19.2.0/final/1/mifs/ram1_VX_sp_ram_647fd9b1.hdl.mif
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|mem_unit|dcache|[0].bank|data_access|data_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 512
|
|
Info (286033): Parameter WIDTHAD_A set to 6
|
|
Info (286033): Parameter NUMWORDS_A set to 64
|
|
Info (286033): Parameter WIDTH_B set to 512
|
|
Info (286033): Parameter WIDTHAD_B set to 6
|
|
Info (286033): Parameter NUMWORDS_B set to 64
|
|
Info (286033): Parameter WIDTH_BYTEENA_A set to 64
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|mem_unit|dcache|[1].bank|tag_access|tag_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 19
|
|
Info (286033): Parameter WIDTHAD_A set to 6
|
|
Info (286033): Parameter NUMWORDS_A set to 64
|
|
Info (286033): Parameter WIDTH_B set to 19
|
|
Info (286033): Parameter WIDTHAD_B set to 6
|
|
Info (286033): Parameter NUMWORDS_B set to 64
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter INIT_FILE set to qdb/_compiler/afu_default/green_region/19.2.0/final/1/mifs/ram1_VX_sp_ram_647fd9b1.hdl.mif
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|mem_unit|dcache|[1].bank|data_access|data_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 512
|
|
Info (286033): Parameter WIDTHAD_A set to 6
|
|
Info (286033): Parameter NUMWORDS_A set to 64
|
|
Info (286033): Parameter WIDTH_B set to 512
|
|
Info (286033): Parameter WIDTHAD_B set to 6
|
|
Info (286033): Parameter NUMWORDS_B set to 64
|
|
Info (286033): Parameter WIDTH_BYTEENA_A set to 64
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|mem_unit|dcache|[2].bank|tag_access|tag_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 19
|
|
Info (286033): Parameter WIDTHAD_A set to 6
|
|
Info (286033): Parameter NUMWORDS_A set to 64
|
|
Info (286033): Parameter WIDTH_B set to 19
|
|
Info (286033): Parameter WIDTHAD_B set to 6
|
|
Info (286033): Parameter NUMWORDS_B set to 64
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter INIT_FILE set to qdb/_compiler/afu_default/green_region/19.2.0/final/1/mifs/ram1_VX_sp_ram_647fd9b1.hdl.mif
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|mem_unit|dcache|[2].bank|data_access|data_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 512
|
|
Info (286033): Parameter WIDTHAD_A set to 6
|
|
Info (286033): Parameter NUMWORDS_A set to 64
|
|
Info (286033): Parameter WIDTH_B set to 512
|
|
Info (286033): Parameter WIDTHAD_B set to 6
|
|
Info (286033): Parameter NUMWORDS_B set to 64
|
|
Info (286033): Parameter WIDTH_BYTEENA_A set to 64
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|mem_unit|dcache|[3].bank|tag_access|tag_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 19
|
|
Info (286033): Parameter WIDTHAD_A set to 6
|
|
Info (286033): Parameter NUMWORDS_A set to 64
|
|
Info (286033): Parameter WIDTH_B set to 19
|
|
Info (286033): Parameter WIDTHAD_B set to 6
|
|
Info (286033): Parameter NUMWORDS_B set to 64
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter INIT_FILE set to qdb/_compiler/afu_default/green_region/19.2.0/final/1/mifs/ram1_VX_sp_ram_647fd9b1.hdl.mif
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|mem_unit|dcache|[3].bank|data_access|data_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 512
|
|
Info (286033): Parameter WIDTHAD_A set to 6
|
|
Info (286033): Parameter NUMWORDS_A set to 64
|
|
Info (286033): Parameter WIDTH_B set to 512
|
|
Info (286033): Parameter WIDTHAD_B set to 6
|
|
Info (286033): Parameter NUMWORDS_B set to 64
|
|
Info (286033): Parameter WIDTH_BYTEENA_A set to 64
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|mem_unit|smem|[0].data|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 10
|
|
Info (286033): Parameter NUMWORDS_A set to 1024
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 10
|
|
Info (286033): Parameter NUMWORDS_B set to 1024
|
|
Info (286033): Parameter WIDTH_BYTEENA_A set to 4
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|mem_unit|smem|[1].data|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 10
|
|
Info (286033): Parameter NUMWORDS_A set to 1024
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 10
|
|
Info (286033): Parameter NUMWORDS_B set to 1024
|
|
Info (286033): Parameter WIDTH_BYTEENA_A set to 4
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|mem_unit|smem|[2].data|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 10
|
|
Info (286033): Parameter NUMWORDS_A set to 1024
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 10
|
|
Info (286033): Parameter NUMWORDS_B set to 1024
|
|
Info (286033): Parameter WIDTH_BYTEENA_A set to 4
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|mem_unit|smem|[3].data|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 10
|
|
Info (286033): Parameter NUMWORDS_A set to 1024
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 10
|
|
Info (286033): Parameter NUMWORDS_B set to 1024
|
|
Info (286033): Parameter WIDTH_BYTEENA_A set to 4
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[1].core|pipeline|issue|gpr_stage|[0].gpr_ram_f|mem_0_30_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[1].core|pipeline|issue|gpr_stage|[0].gpr_ram_f|mem_0_31_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[1].core|pipeline|issue|gpr_stage|[0].gpr_ram_f|mem_0_31_rtl_1"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (286033): Parameter RDCONTROL_REG_B set to CLOCK0
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[1].core|pipeline|issue|gpr_stage|[1].gpr_ram_f|mem_0_30_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[1].core|pipeline|issue|gpr_stage|[1].gpr_ram_f|mem_0_31_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[1].core|pipeline|issue|gpr_stage|[1].gpr_ram_f|mem_0_31_rtl_1"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (286033): Parameter RDCONTROL_REG_B set to CLOCK0
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[1].core|pipeline|issue|gpr_stage|[2].gpr_ram_f|mem_0_30_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[1].core|pipeline|issue|gpr_stage|[2].gpr_ram_f|mem_0_31_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[1].core|pipeline|issue|gpr_stage|[2].gpr_ram_f|mem_0_31_rtl_1"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (286033): Parameter RDCONTROL_REG_B set to CLOCK0
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[1].core|pipeline|issue|gpr_stage|[3].gpr_ram_f|mem_0_30_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[1].core|pipeline|issue|gpr_stage|[3].gpr_ram_f|mem_0_31_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[1].core|pipeline|issue|gpr_stage|[3].gpr_ram_f|mem_0_31_rtl_1"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (286033): Parameter RDCONTROL_REG_B set to CLOCK0
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[1].core|mem_unit|icache|[0].bank|tag_access|tag_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 19
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 19
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter INIT_FILE set to qdb/_compiler/afu_default/green_region/19.2.0/final/1/mifs/ram0_VX_sp_ram_647fd9b1.hdl.mif
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[1].core|mem_unit|icache|[0].bank|data_access|data_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 512
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 512
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[1].core|mem_unit|dcache|[0].bank|tag_access|tag_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 19
|
|
Info (286033): Parameter WIDTHAD_A set to 6
|
|
Info (286033): Parameter NUMWORDS_A set to 64
|
|
Info (286033): Parameter WIDTH_B set to 19
|
|
Info (286033): Parameter WIDTHAD_B set to 6
|
|
Info (286033): Parameter NUMWORDS_B set to 64
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter INIT_FILE set to qdb/_compiler/afu_default/green_region/19.2.0/final/1/mifs/ram1_VX_sp_ram_647fd9b1.hdl.mif
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[1].core|mem_unit|dcache|[0].bank|data_access|data_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 512
|
|
Info (286033): Parameter WIDTHAD_A set to 6
|
|
Info (286033): Parameter NUMWORDS_A set to 64
|
|
Info (286033): Parameter WIDTH_B set to 512
|
|
Info (286033): Parameter WIDTHAD_B set to 6
|
|
Info (286033): Parameter NUMWORDS_B set to 64
|
|
Info (286033): Parameter WIDTH_BYTEENA_A set to 64
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[1].core|mem_unit|dcache|[1].bank|tag_access|tag_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 19
|
|
Info (286033): Parameter WIDTHAD_A set to 6
|
|
Info (286033): Parameter NUMWORDS_A set to 64
|
|
Info (286033): Parameter WIDTH_B set to 19
|
|
Info (286033): Parameter WIDTHAD_B set to 6
|
|
Info (286033): Parameter NUMWORDS_B set to 64
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter INIT_FILE set to qdb/_compiler/afu_default/green_region/19.2.0/final/1/mifs/ram1_VX_sp_ram_647fd9b1.hdl.mif
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[1].core|mem_unit|dcache|[1].bank|data_access|data_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 512
|
|
Info (286033): Parameter WIDTHAD_A set to 6
|
|
Info (286033): Parameter NUMWORDS_A set to 64
|
|
Info (286033): Parameter WIDTH_B set to 512
|
|
Info (286033): Parameter WIDTHAD_B set to 6
|
|
Info (286033): Parameter NUMWORDS_B set to 64
|
|
Info (286033): Parameter WIDTH_BYTEENA_A set to 64
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[1].core|mem_unit|dcache|[2].bank|tag_access|tag_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 19
|
|
Info (286033): Parameter WIDTHAD_A set to 6
|
|
Info (286033): Parameter NUMWORDS_A set to 64
|
|
Info (286033): Parameter WIDTH_B set to 19
|
|
Info (286033): Parameter WIDTHAD_B set to 6
|
|
Info (286033): Parameter NUMWORDS_B set to 64
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter INIT_FILE set to qdb/_compiler/afu_default/green_region/19.2.0/final/1/mifs/ram1_VX_sp_ram_647fd9b1.hdl.mif
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[1].core|mem_unit|dcache|[2].bank|data_access|data_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 512
|
|
Info (286033): Parameter WIDTHAD_A set to 6
|
|
Info (286033): Parameter NUMWORDS_A set to 64
|
|
Info (286033): Parameter WIDTH_B set to 512
|
|
Info (286033): Parameter WIDTHAD_B set to 6
|
|
Info (286033): Parameter NUMWORDS_B set to 64
|
|
Info (286033): Parameter WIDTH_BYTEENA_A set to 64
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[1].core|mem_unit|dcache|[3].bank|tag_access|tag_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 19
|
|
Info (286033): Parameter WIDTHAD_A set to 6
|
|
Info (286033): Parameter NUMWORDS_A set to 64
|
|
Info (286033): Parameter WIDTH_B set to 19
|
|
Info (286033): Parameter WIDTHAD_B set to 6
|
|
Info (286033): Parameter NUMWORDS_B set to 64
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter INIT_FILE set to qdb/_compiler/afu_default/green_region/19.2.0/final/1/mifs/ram1_VX_sp_ram_647fd9b1.hdl.mif
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[1].core|mem_unit|dcache|[3].bank|data_access|data_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 512
|
|
Info (286033): Parameter WIDTHAD_A set to 6
|
|
Info (286033): Parameter NUMWORDS_A set to 64
|
|
Info (286033): Parameter WIDTH_B set to 512
|
|
Info (286033): Parameter WIDTHAD_B set to 6
|
|
Info (286033): Parameter NUMWORDS_B set to 64
|
|
Info (286033): Parameter WIDTH_BYTEENA_A set to 64
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[1].core|mem_unit|smem|[0].data|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 10
|
|
Info (286033): Parameter NUMWORDS_A set to 1024
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 10
|
|
Info (286033): Parameter NUMWORDS_B set to 1024
|
|
Info (286033): Parameter WIDTH_BYTEENA_A set to 4
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[1].core|mem_unit|smem|[1].data|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 10
|
|
Info (286033): Parameter NUMWORDS_A set to 1024
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 10
|
|
Info (286033): Parameter NUMWORDS_B set to 1024
|
|
Info (286033): Parameter WIDTH_BYTEENA_A set to 4
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[1].core|mem_unit|smem|[2].data|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 10
|
|
Info (286033): Parameter NUMWORDS_A set to 1024
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 10
|
|
Info (286033): Parameter NUMWORDS_B set to 1024
|
|
Info (286033): Parameter WIDTH_BYTEENA_A set to 4
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[1].core|mem_unit|smem|[3].data|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 10
|
|
Info (286033): Parameter NUMWORDS_A set to 1024
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 10
|
|
Info (286033): Parameter NUMWORDS_B set to 1024
|
|
Info (286033): Parameter WIDTH_BYTEENA_A set to 4
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[2].core|pipeline|issue|gpr_stage|[0].gpr_ram_f|mem_0_30_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[2].core|pipeline|issue|gpr_stage|[0].gpr_ram_f|mem_0_31_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[2].core|pipeline|issue|gpr_stage|[0].gpr_ram_f|mem_0_31_rtl_1"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (286033): Parameter RDCONTROL_REG_B set to CLOCK0
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[2].core|pipeline|issue|gpr_stage|[1].gpr_ram_f|mem_0_30_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[2].core|pipeline|issue|gpr_stage|[1].gpr_ram_f|mem_0_31_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[2].core|pipeline|issue|gpr_stage|[1].gpr_ram_f|mem_0_31_rtl_1"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (286033): Parameter RDCONTROL_REG_B set to CLOCK0
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[2].core|pipeline|issue|gpr_stage|[2].gpr_ram_f|mem_0_30_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[2].core|pipeline|issue|gpr_stage|[2].gpr_ram_f|mem_0_31_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[2].core|pipeline|issue|gpr_stage|[2].gpr_ram_f|mem_0_31_rtl_1"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (286033): Parameter RDCONTROL_REG_B set to CLOCK0
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[2].core|pipeline|issue|gpr_stage|[3].gpr_ram_f|mem_0_30_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[2].core|pipeline|issue|gpr_stage|[3].gpr_ram_f|mem_0_31_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[2].core|pipeline|issue|gpr_stage|[3].gpr_ram_f|mem_0_31_rtl_1"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (286033): Parameter RDCONTROL_REG_B set to CLOCK0
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[2].core|mem_unit|icache|[0].bank|tag_access|tag_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 19
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 19
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter INIT_FILE set to qdb/_compiler/afu_default/green_region/19.2.0/final/1/mifs/ram0_VX_sp_ram_647fd9b1.hdl.mif
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[2].core|mem_unit|icache|[0].bank|data_access|data_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 512
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 512
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[2].core|mem_unit|dcache|[0].bank|tag_access|tag_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 19
|
|
Info (286033): Parameter WIDTHAD_A set to 6
|
|
Info (286033): Parameter NUMWORDS_A set to 64
|
|
Info (286033): Parameter WIDTH_B set to 19
|
|
Info (286033): Parameter WIDTHAD_B set to 6
|
|
Info (286033): Parameter NUMWORDS_B set to 64
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter INIT_FILE set to qdb/_compiler/afu_default/green_region/19.2.0/final/1/mifs/ram1_VX_sp_ram_647fd9b1.hdl.mif
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[2].core|mem_unit|dcache|[0].bank|data_access|data_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 512
|
|
Info (286033): Parameter WIDTHAD_A set to 6
|
|
Info (286033): Parameter NUMWORDS_A set to 64
|
|
Info (286033): Parameter WIDTH_B set to 512
|
|
Info (286033): Parameter WIDTHAD_B set to 6
|
|
Info (286033): Parameter NUMWORDS_B set to 64
|
|
Info (286033): Parameter WIDTH_BYTEENA_A set to 64
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[2].core|mem_unit|dcache|[1].bank|tag_access|tag_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 19
|
|
Info (286033): Parameter WIDTHAD_A set to 6
|
|
Info (286033): Parameter NUMWORDS_A set to 64
|
|
Info (286033): Parameter WIDTH_B set to 19
|
|
Info (286033): Parameter WIDTHAD_B set to 6
|
|
Info (286033): Parameter NUMWORDS_B set to 64
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter INIT_FILE set to qdb/_compiler/afu_default/green_region/19.2.0/final/1/mifs/ram1_VX_sp_ram_647fd9b1.hdl.mif
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[2].core|mem_unit|dcache|[1].bank|data_access|data_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 512
|
|
Info (286033): Parameter WIDTHAD_A set to 6
|
|
Info (286033): Parameter NUMWORDS_A set to 64
|
|
Info (286033): Parameter WIDTH_B set to 512
|
|
Info (286033): Parameter WIDTHAD_B set to 6
|
|
Info (286033): Parameter NUMWORDS_B set to 64
|
|
Info (286033): Parameter WIDTH_BYTEENA_A set to 64
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[2].core|mem_unit|dcache|[2].bank|tag_access|tag_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 19
|
|
Info (286033): Parameter WIDTHAD_A set to 6
|
|
Info (286033): Parameter NUMWORDS_A set to 64
|
|
Info (286033): Parameter WIDTH_B set to 19
|
|
Info (286033): Parameter WIDTHAD_B set to 6
|
|
Info (286033): Parameter NUMWORDS_B set to 64
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter INIT_FILE set to qdb/_compiler/afu_default/green_region/19.2.0/final/1/mifs/ram1_VX_sp_ram_647fd9b1.hdl.mif
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[2].core|mem_unit|dcache|[2].bank|data_access|data_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 512
|
|
Info (286033): Parameter WIDTHAD_A set to 6
|
|
Info (286033): Parameter NUMWORDS_A set to 64
|
|
Info (286033): Parameter WIDTH_B set to 512
|
|
Info (286033): Parameter WIDTHAD_B set to 6
|
|
Info (286033): Parameter NUMWORDS_B set to 64
|
|
Info (286033): Parameter WIDTH_BYTEENA_A set to 64
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[2].core|mem_unit|dcache|[3].bank|tag_access|tag_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 19
|
|
Info (286033): Parameter WIDTHAD_A set to 6
|
|
Info (286033): Parameter NUMWORDS_A set to 64
|
|
Info (286033): Parameter WIDTH_B set to 19
|
|
Info (286033): Parameter WIDTHAD_B set to 6
|
|
Info (286033): Parameter NUMWORDS_B set to 64
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter INIT_FILE set to qdb/_compiler/afu_default/green_region/19.2.0/final/1/mifs/ram1_VX_sp_ram_647fd9b1.hdl.mif
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[2].core|mem_unit|dcache|[3].bank|data_access|data_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 512
|
|
Info (286033): Parameter WIDTHAD_A set to 6
|
|
Info (286033): Parameter NUMWORDS_A set to 64
|
|
Info (286033): Parameter WIDTH_B set to 512
|
|
Info (286033): Parameter WIDTHAD_B set to 6
|
|
Info (286033): Parameter NUMWORDS_B set to 64
|
|
Info (286033): Parameter WIDTH_BYTEENA_A set to 64
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[2].core|mem_unit|smem|[0].data|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 10
|
|
Info (286033): Parameter NUMWORDS_A set to 1024
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 10
|
|
Info (286033): Parameter NUMWORDS_B set to 1024
|
|
Info (286033): Parameter WIDTH_BYTEENA_A set to 4
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[2].core|mem_unit|smem|[1].data|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 10
|
|
Info (286033): Parameter NUMWORDS_A set to 1024
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 10
|
|
Info (286033): Parameter NUMWORDS_B set to 1024
|
|
Info (286033): Parameter WIDTH_BYTEENA_A set to 4
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[2].core|mem_unit|smem|[2].data|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 10
|
|
Info (286033): Parameter NUMWORDS_A set to 1024
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 10
|
|
Info (286033): Parameter NUMWORDS_B set to 1024
|
|
Info (286033): Parameter WIDTH_BYTEENA_A set to 4
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[2].core|mem_unit|smem|[3].data|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 10
|
|
Info (286033): Parameter NUMWORDS_A set to 1024
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 10
|
|
Info (286033): Parameter NUMWORDS_B set to 1024
|
|
Info (286033): Parameter WIDTH_BYTEENA_A set to 4
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[3].core|pipeline|issue|gpr_stage|[0].gpr_ram_f|mem_0_30_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[3].core|pipeline|issue|gpr_stage|[0].gpr_ram_f|mem_0_31_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[3].core|pipeline|issue|gpr_stage|[0].gpr_ram_f|mem_0_31_rtl_1"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (286033): Parameter RDCONTROL_REG_B set to CLOCK0
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[3].core|pipeline|issue|gpr_stage|[1].gpr_ram_f|mem_0_30_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[3].core|pipeline|issue|gpr_stage|[1].gpr_ram_f|mem_0_31_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[3].core|pipeline|issue|gpr_stage|[1].gpr_ram_f|mem_0_31_rtl_1"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (286033): Parameter RDCONTROL_REG_B set to CLOCK0
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[3].core|pipeline|issue|gpr_stage|[2].gpr_ram_f|mem_0_30_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[3].core|pipeline|issue|gpr_stage|[2].gpr_ram_f|mem_0_31_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[3].core|pipeline|issue|gpr_stage|[2].gpr_ram_f|mem_0_31_rtl_1"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (286033): Parameter RDCONTROL_REG_B set to CLOCK0
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[3].core|pipeline|issue|gpr_stage|[3].gpr_ram_f|mem_0_30_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[3].core|pipeline|issue|gpr_stage|[3].gpr_ram_f|mem_0_31_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[3].core|pipeline|issue|gpr_stage|[3].gpr_ram_f|mem_0_31_rtl_1"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (286033): Parameter RDCONTROL_REG_B set to CLOCK0
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[3].core|mem_unit|icache|[0].bank|tag_access|tag_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 19
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 19
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter INIT_FILE set to qdb/_compiler/afu_default/green_region/19.2.0/final/1/mifs/ram0_VX_sp_ram_647fd9b1.hdl.mif
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[3].core|mem_unit|icache|[0].bank|data_access|data_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 512
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 512
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[3].core|mem_unit|dcache|[0].bank|tag_access|tag_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 19
|
|
Info (286033): Parameter WIDTHAD_A set to 6
|
|
Info (286033): Parameter NUMWORDS_A set to 64
|
|
Info (286033): Parameter WIDTH_B set to 19
|
|
Info (286033): Parameter WIDTHAD_B set to 6
|
|
Info (286033): Parameter NUMWORDS_B set to 64
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter INIT_FILE set to qdb/_compiler/afu_default/green_region/19.2.0/final/1/mifs/ram1_VX_sp_ram_647fd9b1.hdl.mif
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[3].core|mem_unit|dcache|[0].bank|data_access|data_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 512
|
|
Info (286033): Parameter WIDTHAD_A set to 6
|
|
Info (286033): Parameter NUMWORDS_A set to 64
|
|
Info (286033): Parameter WIDTH_B set to 512
|
|
Info (286033): Parameter WIDTHAD_B set to 6
|
|
Info (286033): Parameter NUMWORDS_B set to 64
|
|
Info (286033): Parameter WIDTH_BYTEENA_A set to 64
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[3].core|mem_unit|dcache|[1].bank|tag_access|tag_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 19
|
|
Info (286033): Parameter WIDTHAD_A set to 6
|
|
Info (286033): Parameter NUMWORDS_A set to 64
|
|
Info (286033): Parameter WIDTH_B set to 19
|
|
Info (286033): Parameter WIDTHAD_B set to 6
|
|
Info (286033): Parameter NUMWORDS_B set to 64
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter INIT_FILE set to qdb/_compiler/afu_default/green_region/19.2.0/final/1/mifs/ram1_VX_sp_ram_647fd9b1.hdl.mif
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[3].core|mem_unit|dcache|[1].bank|data_access|data_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 512
|
|
Info (286033): Parameter WIDTHAD_A set to 6
|
|
Info (286033): Parameter NUMWORDS_A set to 64
|
|
Info (286033): Parameter WIDTH_B set to 512
|
|
Info (286033): Parameter WIDTHAD_B set to 6
|
|
Info (286033): Parameter NUMWORDS_B set to 64
|
|
Info (286033): Parameter WIDTH_BYTEENA_A set to 64
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[3].core|mem_unit|dcache|[2].bank|tag_access|tag_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 19
|
|
Info (286033): Parameter WIDTHAD_A set to 6
|
|
Info (286033): Parameter NUMWORDS_A set to 64
|
|
Info (286033): Parameter WIDTH_B set to 19
|
|
Info (286033): Parameter WIDTHAD_B set to 6
|
|
Info (286033): Parameter NUMWORDS_B set to 64
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter INIT_FILE set to qdb/_compiler/afu_default/green_region/19.2.0/final/1/mifs/ram1_VX_sp_ram_647fd9b1.hdl.mif
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[3].core|mem_unit|dcache|[2].bank|data_access|data_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 512
|
|
Info (286033): Parameter WIDTHAD_A set to 6
|
|
Info (286033): Parameter NUMWORDS_A set to 64
|
|
Info (286033): Parameter WIDTH_B set to 512
|
|
Info (286033): Parameter WIDTHAD_B set to 6
|
|
Info (286033): Parameter NUMWORDS_B set to 64
|
|
Info (286033): Parameter WIDTH_BYTEENA_A set to 64
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[3].core|mem_unit|dcache|[3].bank|tag_access|tag_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 19
|
|
Info (286033): Parameter WIDTHAD_A set to 6
|
|
Info (286033): Parameter NUMWORDS_A set to 64
|
|
Info (286033): Parameter WIDTH_B set to 19
|
|
Info (286033): Parameter WIDTHAD_B set to 6
|
|
Info (286033): Parameter NUMWORDS_B set to 64
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter INIT_FILE set to qdb/_compiler/afu_default/green_region/19.2.0/final/1/mifs/ram1_VX_sp_ram_647fd9b1.hdl.mif
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[3].core|mem_unit|dcache|[3].bank|data_access|data_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 512
|
|
Info (286033): Parameter WIDTHAD_A set to 6
|
|
Info (286033): Parameter NUMWORDS_A set to 64
|
|
Info (286033): Parameter WIDTH_B set to 512
|
|
Info (286033): Parameter WIDTHAD_B set to 6
|
|
Info (286033): Parameter NUMWORDS_B set to 64
|
|
Info (286033): Parameter WIDTH_BYTEENA_A set to 64
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[3].core|mem_unit|smem|[0].data|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 10
|
|
Info (286033): Parameter NUMWORDS_A set to 1024
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 10
|
|
Info (286033): Parameter NUMWORDS_B set to 1024
|
|
Info (286033): Parameter WIDTH_BYTEENA_A set to 4
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[3].core|mem_unit|smem|[1].data|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 10
|
|
Info (286033): Parameter NUMWORDS_A set to 1024
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 10
|
|
Info (286033): Parameter NUMWORDS_B set to 1024
|
|
Info (286033): Parameter WIDTH_BYTEENA_A set to 4
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[3].core|mem_unit|smem|[2].data|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 10
|
|
Info (286033): Parameter NUMWORDS_A set to 1024
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 10
|
|
Info (286033): Parameter NUMWORDS_B set to 1024
|
|
Info (286033): Parameter WIDTH_BYTEENA_A set to 4
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[3].core|mem_unit|smem|[3].data|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 10
|
|
Info (286033): Parameter NUMWORDS_A set to 1024
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 10
|
|
Info (286033): Parameter NUMWORDS_B set to 1024
|
|
Info (286033): Parameter WIDTH_BYTEENA_A set to 4
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[0].core|pipeline|issue|gpr_stage|[0].gpr_ram_f|mem_0_30_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[0].core|pipeline|issue|gpr_stage|[0].gpr_ram_f|mem_0_31_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[0].core|pipeline|issue|gpr_stage|[0].gpr_ram_f|mem_0_31_rtl_1"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (286033): Parameter RDCONTROL_REG_B set to CLOCK0
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[0].core|pipeline|issue|gpr_stage|[1].gpr_ram_f|mem_0_30_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[0].core|pipeline|issue|gpr_stage|[1].gpr_ram_f|mem_0_31_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[0].core|pipeline|issue|gpr_stage|[1].gpr_ram_f|mem_0_31_rtl_1"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (286033): Parameter RDCONTROL_REG_B set to CLOCK0
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[0].core|pipeline|issue|gpr_stage|[2].gpr_ram_f|mem_0_30_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[0].core|pipeline|issue|gpr_stage|[2].gpr_ram_f|mem_0_31_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[0].core|pipeline|issue|gpr_stage|[2].gpr_ram_f|mem_0_31_rtl_1"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (286033): Parameter RDCONTROL_REG_B set to CLOCK0
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[0].core|pipeline|issue|gpr_stage|[3].gpr_ram_f|mem_0_30_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[0].core|pipeline|issue|gpr_stage|[3].gpr_ram_f|mem_0_31_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[0].core|pipeline|issue|gpr_stage|[3].gpr_ram_f|mem_0_31_rtl_1"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (286033): Parameter RDCONTROL_REG_B set to CLOCK0
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[0].core|mem_unit|icache|[0].bank|tag_access|tag_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 19
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 19
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter INIT_FILE set to qdb/_compiler/afu_default/green_region/19.2.0/final/1/mifs/ram0_VX_sp_ram_647fd9b1.hdl.mif
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[0].core|mem_unit|icache|[0].bank|data_access|data_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 512
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 512
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[0].core|mem_unit|dcache|[0].bank|tag_access|tag_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 19
|
|
Info (286033): Parameter WIDTHAD_A set to 6
|
|
Info (286033): Parameter NUMWORDS_A set to 64
|
|
Info (286033): Parameter WIDTH_B set to 19
|
|
Info (286033): Parameter WIDTHAD_B set to 6
|
|
Info (286033): Parameter NUMWORDS_B set to 64
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter INIT_FILE set to qdb/_compiler/afu_default/green_region/19.2.0/final/1/mifs/ram1_VX_sp_ram_647fd9b1.hdl.mif
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[0].core|mem_unit|dcache|[0].bank|data_access|data_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 512
|
|
Info (286033): Parameter WIDTHAD_A set to 6
|
|
Info (286033): Parameter NUMWORDS_A set to 64
|
|
Info (286033): Parameter WIDTH_B set to 512
|
|
Info (286033): Parameter WIDTHAD_B set to 6
|
|
Info (286033): Parameter NUMWORDS_B set to 64
|
|
Info (286033): Parameter WIDTH_BYTEENA_A set to 64
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[0].core|mem_unit|dcache|[1].bank|tag_access|tag_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 19
|
|
Info (286033): Parameter WIDTHAD_A set to 6
|
|
Info (286033): Parameter NUMWORDS_A set to 64
|
|
Info (286033): Parameter WIDTH_B set to 19
|
|
Info (286033): Parameter WIDTHAD_B set to 6
|
|
Info (286033): Parameter NUMWORDS_B set to 64
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter INIT_FILE set to qdb/_compiler/afu_default/green_region/19.2.0/final/1/mifs/ram1_VX_sp_ram_647fd9b1.hdl.mif
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[0].core|mem_unit|dcache|[1].bank|data_access|data_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 512
|
|
Info (286033): Parameter WIDTHAD_A set to 6
|
|
Info (286033): Parameter NUMWORDS_A set to 64
|
|
Info (286033): Parameter WIDTH_B set to 512
|
|
Info (286033): Parameter WIDTHAD_B set to 6
|
|
Info (286033): Parameter NUMWORDS_B set to 64
|
|
Info (286033): Parameter WIDTH_BYTEENA_A set to 64
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[0].core|mem_unit|dcache|[2].bank|tag_access|tag_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 19
|
|
Info (286033): Parameter WIDTHAD_A set to 6
|
|
Info (286033): Parameter NUMWORDS_A set to 64
|
|
Info (286033): Parameter WIDTH_B set to 19
|
|
Info (286033): Parameter WIDTHAD_B set to 6
|
|
Info (286033): Parameter NUMWORDS_B set to 64
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter INIT_FILE set to qdb/_compiler/afu_default/green_region/19.2.0/final/1/mifs/ram1_VX_sp_ram_647fd9b1.hdl.mif
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[0].core|mem_unit|dcache|[2].bank|data_access|data_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 512
|
|
Info (286033): Parameter WIDTHAD_A set to 6
|
|
Info (286033): Parameter NUMWORDS_A set to 64
|
|
Info (286033): Parameter WIDTH_B set to 512
|
|
Info (286033): Parameter WIDTHAD_B set to 6
|
|
Info (286033): Parameter NUMWORDS_B set to 64
|
|
Info (286033): Parameter WIDTH_BYTEENA_A set to 64
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[0].core|mem_unit|dcache|[3].bank|tag_access|tag_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 19
|
|
Info (286033): Parameter WIDTHAD_A set to 6
|
|
Info (286033): Parameter NUMWORDS_A set to 64
|
|
Info (286033): Parameter WIDTH_B set to 19
|
|
Info (286033): Parameter WIDTHAD_B set to 6
|
|
Info (286033): Parameter NUMWORDS_B set to 64
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter INIT_FILE set to qdb/_compiler/afu_default/green_region/19.2.0/final/1/mifs/ram1_VX_sp_ram_647fd9b1.hdl.mif
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[0].core|mem_unit|dcache|[3].bank|data_access|data_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 512
|
|
Info (286033): Parameter WIDTHAD_A set to 6
|
|
Info (286033): Parameter NUMWORDS_A set to 64
|
|
Info (286033): Parameter WIDTH_B set to 512
|
|
Info (286033): Parameter WIDTHAD_B set to 6
|
|
Info (286033): Parameter NUMWORDS_B set to 64
|
|
Info (286033): Parameter WIDTH_BYTEENA_A set to 64
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[0].core|mem_unit|smem|[0].data|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 10
|
|
Info (286033): Parameter NUMWORDS_A set to 1024
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 10
|
|
Info (286033): Parameter NUMWORDS_B set to 1024
|
|
Info (286033): Parameter WIDTH_BYTEENA_A set to 4
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[0].core|mem_unit|smem|[1].data|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 10
|
|
Info (286033): Parameter NUMWORDS_A set to 1024
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 10
|
|
Info (286033): Parameter NUMWORDS_B set to 1024
|
|
Info (286033): Parameter WIDTH_BYTEENA_A set to 4
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[0].core|mem_unit|smem|[2].data|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 10
|
|
Info (286033): Parameter NUMWORDS_A set to 1024
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 10
|
|
Info (286033): Parameter NUMWORDS_B set to 1024
|
|
Info (286033): Parameter WIDTH_BYTEENA_A set to 4
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[0].core|mem_unit|smem|[3].data|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 10
|
|
Info (286033): Parameter NUMWORDS_A set to 1024
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 10
|
|
Info (286033): Parameter NUMWORDS_B set to 1024
|
|
Info (286033): Parameter WIDTH_BYTEENA_A set to 4
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[1].core|pipeline|issue|gpr_stage|[0].gpr_ram_f|mem_0_30_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[1].core|pipeline|issue|gpr_stage|[0].gpr_ram_f|mem_0_31_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[1].core|pipeline|issue|gpr_stage|[0].gpr_ram_f|mem_0_31_rtl_1"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (286033): Parameter RDCONTROL_REG_B set to CLOCK0
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[1].core|pipeline|issue|gpr_stage|[1].gpr_ram_f|mem_0_30_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[1].core|pipeline|issue|gpr_stage|[1].gpr_ram_f|mem_0_31_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[1].core|pipeline|issue|gpr_stage|[1].gpr_ram_f|mem_0_31_rtl_1"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (286033): Parameter RDCONTROL_REG_B set to CLOCK0
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[1].core|pipeline|issue|gpr_stage|[2].gpr_ram_f|mem_0_30_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[1].core|pipeline|issue|gpr_stage|[2].gpr_ram_f|mem_0_31_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[1].core|pipeline|issue|gpr_stage|[2].gpr_ram_f|mem_0_31_rtl_1"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (286033): Parameter RDCONTROL_REG_B set to CLOCK0
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[1].core|pipeline|issue|gpr_stage|[3].gpr_ram_f|mem_0_30_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[1].core|pipeline|issue|gpr_stage|[3].gpr_ram_f|mem_0_31_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[1].core|pipeline|issue|gpr_stage|[3].gpr_ram_f|mem_0_31_rtl_1"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (286033): Parameter RDCONTROL_REG_B set to CLOCK0
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[1].core|mem_unit|icache|[0].bank|tag_access|tag_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 19
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 19
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter INIT_FILE set to qdb/_compiler/afu_default/green_region/19.2.0/final/1/mifs/ram0_VX_sp_ram_647fd9b1.hdl.mif
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[1].core|mem_unit|icache|[0].bank|data_access|data_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 512
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 512
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[1].core|mem_unit|dcache|[0].bank|tag_access|tag_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 19
|
|
Info (286033): Parameter WIDTHAD_A set to 6
|
|
Info (286033): Parameter NUMWORDS_A set to 64
|
|
Info (286033): Parameter WIDTH_B set to 19
|
|
Info (286033): Parameter WIDTHAD_B set to 6
|
|
Info (286033): Parameter NUMWORDS_B set to 64
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter INIT_FILE set to qdb/_compiler/afu_default/green_region/19.2.0/final/1/mifs/ram1_VX_sp_ram_647fd9b1.hdl.mif
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[1].core|mem_unit|dcache|[0].bank|data_access|data_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 512
|
|
Info (286033): Parameter WIDTHAD_A set to 6
|
|
Info (286033): Parameter NUMWORDS_A set to 64
|
|
Info (286033): Parameter WIDTH_B set to 512
|
|
Info (286033): Parameter WIDTHAD_B set to 6
|
|
Info (286033): Parameter NUMWORDS_B set to 64
|
|
Info (286033): Parameter WIDTH_BYTEENA_A set to 64
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[1].core|mem_unit|dcache|[1].bank|tag_access|tag_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 19
|
|
Info (286033): Parameter WIDTHAD_A set to 6
|
|
Info (286033): Parameter NUMWORDS_A set to 64
|
|
Info (286033): Parameter WIDTH_B set to 19
|
|
Info (286033): Parameter WIDTHAD_B set to 6
|
|
Info (286033): Parameter NUMWORDS_B set to 64
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter INIT_FILE set to qdb/_compiler/afu_default/green_region/19.2.0/final/1/mifs/ram1_VX_sp_ram_647fd9b1.hdl.mif
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[1].core|mem_unit|dcache|[1].bank|data_access|data_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 512
|
|
Info (286033): Parameter WIDTHAD_A set to 6
|
|
Info (286033): Parameter NUMWORDS_A set to 64
|
|
Info (286033): Parameter WIDTH_B set to 512
|
|
Info (286033): Parameter WIDTHAD_B set to 6
|
|
Info (286033): Parameter NUMWORDS_B set to 64
|
|
Info (286033): Parameter WIDTH_BYTEENA_A set to 64
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[1].core|mem_unit|dcache|[2].bank|tag_access|tag_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 19
|
|
Info (286033): Parameter WIDTHAD_A set to 6
|
|
Info (286033): Parameter NUMWORDS_A set to 64
|
|
Info (286033): Parameter WIDTH_B set to 19
|
|
Info (286033): Parameter WIDTHAD_B set to 6
|
|
Info (286033): Parameter NUMWORDS_B set to 64
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter INIT_FILE set to qdb/_compiler/afu_default/green_region/19.2.0/final/1/mifs/ram1_VX_sp_ram_647fd9b1.hdl.mif
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[1].core|mem_unit|dcache|[2].bank|data_access|data_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 512
|
|
Info (286033): Parameter WIDTHAD_A set to 6
|
|
Info (286033): Parameter NUMWORDS_A set to 64
|
|
Info (286033): Parameter WIDTH_B set to 512
|
|
Info (286033): Parameter WIDTHAD_B set to 6
|
|
Info (286033): Parameter NUMWORDS_B set to 64
|
|
Info (286033): Parameter WIDTH_BYTEENA_A set to 64
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[1].core|mem_unit|dcache|[3].bank|tag_access|tag_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 19
|
|
Info (286033): Parameter WIDTHAD_A set to 6
|
|
Info (286033): Parameter NUMWORDS_A set to 64
|
|
Info (286033): Parameter WIDTH_B set to 19
|
|
Info (286033): Parameter WIDTHAD_B set to 6
|
|
Info (286033): Parameter NUMWORDS_B set to 64
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter INIT_FILE set to qdb/_compiler/afu_default/green_region/19.2.0/final/1/mifs/ram1_VX_sp_ram_647fd9b1.hdl.mif
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[1].core|mem_unit|dcache|[3].bank|data_access|data_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 512
|
|
Info (286033): Parameter WIDTHAD_A set to 6
|
|
Info (286033): Parameter NUMWORDS_A set to 64
|
|
Info (286033): Parameter WIDTH_B set to 512
|
|
Info (286033): Parameter WIDTHAD_B set to 6
|
|
Info (286033): Parameter NUMWORDS_B set to 64
|
|
Info (286033): Parameter WIDTH_BYTEENA_A set to 64
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[1].core|mem_unit|smem|[0].data|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 10
|
|
Info (286033): Parameter NUMWORDS_A set to 1024
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 10
|
|
Info (286033): Parameter NUMWORDS_B set to 1024
|
|
Info (286033): Parameter WIDTH_BYTEENA_A set to 4
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[1].core|mem_unit|smem|[1].data|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 10
|
|
Info (286033): Parameter NUMWORDS_A set to 1024
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 10
|
|
Info (286033): Parameter NUMWORDS_B set to 1024
|
|
Info (286033): Parameter WIDTH_BYTEENA_A set to 4
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[1].core|mem_unit|smem|[2].data|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 10
|
|
Info (286033): Parameter NUMWORDS_A set to 1024
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 10
|
|
Info (286033): Parameter NUMWORDS_B set to 1024
|
|
Info (286033): Parameter WIDTH_BYTEENA_A set to 4
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[1].core|mem_unit|smem|[3].data|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 10
|
|
Info (286033): Parameter NUMWORDS_A set to 1024
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 10
|
|
Info (286033): Parameter NUMWORDS_B set to 1024
|
|
Info (286033): Parameter WIDTH_BYTEENA_A set to 4
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[2].core|pipeline|issue|gpr_stage|[0].gpr_ram_f|mem_0_30_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[2].core|pipeline|issue|gpr_stage|[0].gpr_ram_f|mem_0_31_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[2].core|pipeline|issue|gpr_stage|[0].gpr_ram_f|mem_0_31_rtl_1"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (286033): Parameter RDCONTROL_REG_B set to CLOCK0
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[2].core|pipeline|issue|gpr_stage|[1].gpr_ram_f|mem_0_30_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[2].core|pipeline|issue|gpr_stage|[1].gpr_ram_f|mem_0_31_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[2].core|pipeline|issue|gpr_stage|[1].gpr_ram_f|mem_0_31_rtl_1"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (286033): Parameter RDCONTROL_REG_B set to CLOCK0
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[2].core|pipeline|issue|gpr_stage|[2].gpr_ram_f|mem_0_30_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[2].core|pipeline|issue|gpr_stage|[2].gpr_ram_f|mem_0_31_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[2].core|pipeline|issue|gpr_stage|[2].gpr_ram_f|mem_0_31_rtl_1"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (286033): Parameter RDCONTROL_REG_B set to CLOCK0
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[2].core|pipeline|issue|gpr_stage|[3].gpr_ram_f|mem_0_30_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[2].core|pipeline|issue|gpr_stage|[3].gpr_ram_f|mem_0_31_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[2].core|pipeline|issue|gpr_stage|[3].gpr_ram_f|mem_0_31_rtl_1"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (286033): Parameter RDCONTROL_REG_B set to CLOCK0
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[2].core|mem_unit|icache|[0].bank|tag_access|tag_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 19
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 19
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter INIT_FILE set to qdb/_compiler/afu_default/green_region/19.2.0/final/1/mifs/ram0_VX_sp_ram_647fd9b1.hdl.mif
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[2].core|mem_unit|icache|[0].bank|data_access|data_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 512
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 512
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[2].core|mem_unit|dcache|[0].bank|tag_access|tag_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 19
|
|
Info (286033): Parameter WIDTHAD_A set to 6
|
|
Info (286033): Parameter NUMWORDS_A set to 64
|
|
Info (286033): Parameter WIDTH_B set to 19
|
|
Info (286033): Parameter WIDTHAD_B set to 6
|
|
Info (286033): Parameter NUMWORDS_B set to 64
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter INIT_FILE set to qdb/_compiler/afu_default/green_region/19.2.0/final/1/mifs/ram1_VX_sp_ram_647fd9b1.hdl.mif
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[2].core|mem_unit|dcache|[0].bank|data_access|data_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 512
|
|
Info (286033): Parameter WIDTHAD_A set to 6
|
|
Info (286033): Parameter NUMWORDS_A set to 64
|
|
Info (286033): Parameter WIDTH_B set to 512
|
|
Info (286033): Parameter WIDTHAD_B set to 6
|
|
Info (286033): Parameter NUMWORDS_B set to 64
|
|
Info (286033): Parameter WIDTH_BYTEENA_A set to 64
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[2].core|mem_unit|dcache|[1].bank|tag_access|tag_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 19
|
|
Info (286033): Parameter WIDTHAD_A set to 6
|
|
Info (286033): Parameter NUMWORDS_A set to 64
|
|
Info (286033): Parameter WIDTH_B set to 19
|
|
Info (286033): Parameter WIDTHAD_B set to 6
|
|
Info (286033): Parameter NUMWORDS_B set to 64
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter INIT_FILE set to qdb/_compiler/afu_default/green_region/19.2.0/final/1/mifs/ram1_VX_sp_ram_647fd9b1.hdl.mif
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[2].core|mem_unit|dcache|[1].bank|data_access|data_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 512
|
|
Info (286033): Parameter WIDTHAD_A set to 6
|
|
Info (286033): Parameter NUMWORDS_A set to 64
|
|
Info (286033): Parameter WIDTH_B set to 512
|
|
Info (286033): Parameter WIDTHAD_B set to 6
|
|
Info (286033): Parameter NUMWORDS_B set to 64
|
|
Info (286033): Parameter WIDTH_BYTEENA_A set to 64
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[2].core|mem_unit|dcache|[2].bank|tag_access|tag_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 19
|
|
Info (286033): Parameter WIDTHAD_A set to 6
|
|
Info (286033): Parameter NUMWORDS_A set to 64
|
|
Info (286033): Parameter WIDTH_B set to 19
|
|
Info (286033): Parameter WIDTHAD_B set to 6
|
|
Info (286033): Parameter NUMWORDS_B set to 64
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter INIT_FILE set to qdb/_compiler/afu_default/green_region/19.2.0/final/1/mifs/ram1_VX_sp_ram_647fd9b1.hdl.mif
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[2].core|mem_unit|dcache|[2].bank|data_access|data_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 512
|
|
Info (286033): Parameter WIDTHAD_A set to 6
|
|
Info (286033): Parameter NUMWORDS_A set to 64
|
|
Info (286033): Parameter WIDTH_B set to 512
|
|
Info (286033): Parameter WIDTHAD_B set to 6
|
|
Info (286033): Parameter NUMWORDS_B set to 64
|
|
Info (286033): Parameter WIDTH_BYTEENA_A set to 64
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[2].core|mem_unit|dcache|[3].bank|tag_access|tag_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 19
|
|
Info (286033): Parameter WIDTHAD_A set to 6
|
|
Info (286033): Parameter NUMWORDS_A set to 64
|
|
Info (286033): Parameter WIDTH_B set to 19
|
|
Info (286033): Parameter WIDTHAD_B set to 6
|
|
Info (286033): Parameter NUMWORDS_B set to 64
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter INIT_FILE set to qdb/_compiler/afu_default/green_region/19.2.0/final/1/mifs/ram1_VX_sp_ram_647fd9b1.hdl.mif
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[2].core|mem_unit|dcache|[3].bank|data_access|data_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 512
|
|
Info (286033): Parameter WIDTHAD_A set to 6
|
|
Info (286033): Parameter NUMWORDS_A set to 64
|
|
Info (286033): Parameter WIDTH_B set to 512
|
|
Info (286033): Parameter WIDTHAD_B set to 6
|
|
Info (286033): Parameter NUMWORDS_B set to 64
|
|
Info (286033): Parameter WIDTH_BYTEENA_A set to 64
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[2].core|mem_unit|smem|[0].data|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 10
|
|
Info (286033): Parameter NUMWORDS_A set to 1024
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 10
|
|
Info (286033): Parameter NUMWORDS_B set to 1024
|
|
Info (286033): Parameter WIDTH_BYTEENA_A set to 4
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[2].core|mem_unit|smem|[1].data|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 10
|
|
Info (286033): Parameter NUMWORDS_A set to 1024
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 10
|
|
Info (286033): Parameter NUMWORDS_B set to 1024
|
|
Info (286033): Parameter WIDTH_BYTEENA_A set to 4
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[2].core|mem_unit|smem|[2].data|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 10
|
|
Info (286033): Parameter NUMWORDS_A set to 1024
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 10
|
|
Info (286033): Parameter NUMWORDS_B set to 1024
|
|
Info (286033): Parameter WIDTH_BYTEENA_A set to 4
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[2].core|mem_unit|smem|[3].data|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 10
|
|
Info (286033): Parameter NUMWORDS_A set to 1024
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 10
|
|
Info (286033): Parameter NUMWORDS_B set to 1024
|
|
Info (286033): Parameter WIDTH_BYTEENA_A set to 4
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[3].core|pipeline|issue|gpr_stage|[0].gpr_ram_f|mem_0_30_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[3].core|pipeline|issue|gpr_stage|[0].gpr_ram_f|mem_0_31_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[3].core|pipeline|issue|gpr_stage|[0].gpr_ram_f|mem_0_31_rtl_1"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (286033): Parameter RDCONTROL_REG_B set to CLOCK0
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[3].core|pipeline|issue|gpr_stage|[1].gpr_ram_f|mem_0_30_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[3].core|pipeline|issue|gpr_stage|[1].gpr_ram_f|mem_0_31_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[3].core|pipeline|issue|gpr_stage|[1].gpr_ram_f|mem_0_31_rtl_1"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (286033): Parameter RDCONTROL_REG_B set to CLOCK0
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[3].core|pipeline|issue|gpr_stage|[2].gpr_ram_f|mem_0_30_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[3].core|pipeline|issue|gpr_stage|[2].gpr_ram_f|mem_0_31_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[3].core|pipeline|issue|gpr_stage|[2].gpr_ram_f|mem_0_31_rtl_1"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (286033): Parameter RDCONTROL_REG_B set to CLOCK0
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[3].core|pipeline|issue|gpr_stage|[3].gpr_ram_f|mem_0_30_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[3].core|pipeline|issue|gpr_stage|[3].gpr_ram_f|mem_0_31_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[3].core|pipeline|issue|gpr_stage|[3].gpr_ram_f|mem_0_31_rtl_1"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (286033): Parameter RDCONTROL_REG_B set to CLOCK0
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[3].core|mem_unit|icache|[0].bank|tag_access|tag_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 19
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 19
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter INIT_FILE set to qdb/_compiler/afu_default/green_region/19.2.0/final/1/mifs/ram0_VX_sp_ram_647fd9b1.hdl.mif
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[3].core|mem_unit|icache|[0].bank|data_access|data_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 512
|
|
Info (286033): Parameter WIDTHAD_A set to 8
|
|
Info (286033): Parameter NUMWORDS_A set to 256
|
|
Info (286033): Parameter WIDTH_B set to 512
|
|
Info (286033): Parameter WIDTHAD_B set to 8
|
|
Info (286033): Parameter NUMWORDS_B set to 256
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[3].core|mem_unit|dcache|[0].bank|tag_access|tag_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 19
|
|
Info (286033): Parameter WIDTHAD_A set to 6
|
|
Info (286033): Parameter NUMWORDS_A set to 64
|
|
Info (286033): Parameter WIDTH_B set to 19
|
|
Info (286033): Parameter WIDTHAD_B set to 6
|
|
Info (286033): Parameter NUMWORDS_B set to 64
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter INIT_FILE set to qdb/_compiler/afu_default/green_region/19.2.0/final/1/mifs/ram1_VX_sp_ram_647fd9b1.hdl.mif
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[3].core|mem_unit|dcache|[0].bank|data_access|data_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 512
|
|
Info (286033): Parameter WIDTHAD_A set to 6
|
|
Info (286033): Parameter NUMWORDS_A set to 64
|
|
Info (286033): Parameter WIDTH_B set to 512
|
|
Info (286033): Parameter WIDTHAD_B set to 6
|
|
Info (286033): Parameter NUMWORDS_B set to 64
|
|
Info (286033): Parameter WIDTH_BYTEENA_A set to 64
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[3].core|mem_unit|dcache|[1].bank|tag_access|tag_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 19
|
|
Info (286033): Parameter WIDTHAD_A set to 6
|
|
Info (286033): Parameter NUMWORDS_A set to 64
|
|
Info (286033): Parameter WIDTH_B set to 19
|
|
Info (286033): Parameter WIDTHAD_B set to 6
|
|
Info (286033): Parameter NUMWORDS_B set to 64
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter INIT_FILE set to qdb/_compiler/afu_default/green_region/19.2.0/final/1/mifs/ram1_VX_sp_ram_647fd9b1.hdl.mif
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[3].core|mem_unit|dcache|[1].bank|data_access|data_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 512
|
|
Info (286033): Parameter WIDTHAD_A set to 6
|
|
Info (286033): Parameter NUMWORDS_A set to 64
|
|
Info (286033): Parameter WIDTH_B set to 512
|
|
Info (286033): Parameter WIDTHAD_B set to 6
|
|
Info (286033): Parameter NUMWORDS_B set to 64
|
|
Info (286033): Parameter WIDTH_BYTEENA_A set to 64
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[3].core|mem_unit|dcache|[2].bank|tag_access|tag_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 19
|
|
Info (286033): Parameter WIDTHAD_A set to 6
|
|
Info (286033): Parameter NUMWORDS_A set to 64
|
|
Info (286033): Parameter WIDTH_B set to 19
|
|
Info (286033): Parameter WIDTHAD_B set to 6
|
|
Info (286033): Parameter NUMWORDS_B set to 64
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter INIT_FILE set to qdb/_compiler/afu_default/green_region/19.2.0/final/1/mifs/ram1_VX_sp_ram_647fd9b1.hdl.mif
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[3].core|mem_unit|dcache|[2].bank|data_access|data_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 512
|
|
Info (286033): Parameter WIDTHAD_A set to 6
|
|
Info (286033): Parameter NUMWORDS_A set to 64
|
|
Info (286033): Parameter WIDTH_B set to 512
|
|
Info (286033): Parameter WIDTHAD_B set to 6
|
|
Info (286033): Parameter NUMWORDS_B set to 64
|
|
Info (286033): Parameter WIDTH_BYTEENA_A set to 64
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[3].core|mem_unit|dcache|[3].bank|tag_access|tag_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 19
|
|
Info (286033): Parameter WIDTHAD_A set to 6
|
|
Info (286033): Parameter NUMWORDS_A set to 64
|
|
Info (286033): Parameter WIDTH_B set to 19
|
|
Info (286033): Parameter WIDTHAD_B set to 6
|
|
Info (286033): Parameter NUMWORDS_B set to 64
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter INIT_FILE set to qdb/_compiler/afu_default/green_region/19.2.0/final/1/mifs/ram1_VX_sp_ram_647fd9b1.hdl.mif
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[3].core|mem_unit|dcache|[3].bank|data_access|data_store|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 512
|
|
Info (286033): Parameter WIDTHAD_A set to 6
|
|
Info (286033): Parameter NUMWORDS_A set to 64
|
|
Info (286033): Parameter WIDTH_B set to 512
|
|
Info (286033): Parameter WIDTHAD_B set to 6
|
|
Info (286033): Parameter NUMWORDS_B set to 64
|
|
Info (286033): Parameter WIDTH_BYTEENA_A set to 64
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[3].core|mem_unit|smem|[0].data|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 10
|
|
Info (286033): Parameter NUMWORDS_A set to 1024
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 10
|
|
Info (286033): Parameter NUMWORDS_B set to 1024
|
|
Info (286033): Parameter WIDTH_BYTEENA_A set to 4
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[3].core|mem_unit|smem|[1].data|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 10
|
|
Info (286033): Parameter NUMWORDS_A set to 1024
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 10
|
|
Info (286033): Parameter NUMWORDS_B set to 1024
|
|
Info (286033): Parameter WIDTH_BYTEENA_A set to 4
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[3].core|mem_unit|smem|[2].data|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 10
|
|
Info (286033): Parameter NUMWORDS_A set to 1024
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 10
|
|
Info (286033): Parameter NUMWORDS_B set to 1024
|
|
Info (286033): Parameter WIDTH_BYTEENA_A set to 4
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Info (276029): Inferred altsyncram megafunction from the following design logic: "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[3].cluster|[3].core|mem_unit|smem|[3].data|mem_rtl_0"
|
|
Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
|
|
Info (286033): Parameter WIDTH_A set to 32
|
|
Info (286033): Parameter WIDTHAD_A set to 10
|
|
Info (286033): Parameter NUMWORDS_A set to 1024
|
|
Info (286033): Parameter WIDTH_B set to 32
|
|
Info (286033): Parameter WIDTHAD_B set to 10
|
|
Info (286033): Parameter NUMWORDS_B set to 1024
|
|
Info (286033): Parameter WIDTH_BYTEENA_A set to 4
|
|
Info (286033): Parameter ADDRESS_ACLR_A set to NONE
|
|
Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
|
|
Info (286033): Parameter ADDRESS_ACLR_B set to NONE
|
|
Info (286033): Parameter OUTDATA_ACLR_B set to NONE
|
|
Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
|
|
Info (286033): Parameter INDATA_ACLR_A set to NONE
|
|
Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
|
|
Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
|
|
Critical Warning (19854): Discovered an explicitly defined initial values in Partition green_region. Initial values within partial reconfiguration or Reserved Core regions are not supported! Please refer to the green_region Partition report folder for more information.
|
|
Warning (13024): Output pins are stuck at VCC or GND
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4a_burstcount[1]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 67
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4a_burstcount[2]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 67
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4a_burstcount[3]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 67
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4a_burstcount[4]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 67
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4a_burstcount[5]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 67
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4a_burstcount[6]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 67
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4a_address[26]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_burstcount[0]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 77
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_burstcount[1]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 77
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_burstcount[2]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 77
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_burstcount[3]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 77
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_burstcount[4]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 77
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_burstcount[5]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 77
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_burstcount[6]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 77
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[0]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[1]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[2]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[3]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[4]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[5]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[6]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[7]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[8]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[9]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[10]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[11]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[12]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[13]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[14]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[15]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[16]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[17]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[18]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[19]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[20]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[21]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[22]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[23]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[24]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[25]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[26]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[27]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[28]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[29]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[30]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[31]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[32]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[33]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[34]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[35]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[36]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[37]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[38]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[39]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[40]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[41]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[42]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[43]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[44]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[45]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[46]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[47]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[48]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[49]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[50]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[51]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[52]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[53]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[54]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[55]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[56]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[57]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[58]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[59]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[60]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[61]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[62]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[63]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[64]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[65]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[66]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[67]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[68]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[69]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[70]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[71]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[72]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[73]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[74]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[75]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[76]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[77]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[78]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[79]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[80]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[81]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[82]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[83]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[84]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[85]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[86]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[87]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[88]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[89]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[90]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[91]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[92]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[93]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[94]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[95]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[96]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[97]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[98]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[99]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[100]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[101]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[102]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[103]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[104]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[105]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[106]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[107]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[108]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[109]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[110]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[111]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[112]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[113]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[114]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[115]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[116]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[117]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[118]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[119]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[120]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[121]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[122]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[123]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[124]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[125]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[126]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[127]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[128]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[129]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[130]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[131]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[132]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[133]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[134]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[135]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[136]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[137]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[138]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[139]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[140]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[141]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[142]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[143]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[144]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[145]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[146]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[147]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[148]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[149]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[150]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[151]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[152]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[153]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[154]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[155]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[156]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[157]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[158]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[159]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[160]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[161]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[162]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[163]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[164]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[165]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[166]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[167]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[168]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[169]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[170]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[171]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[172]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[173]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[174]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[175]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[176]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[177]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[178]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[179]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[180]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[181]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[182]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[183]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[184]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[185]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[186]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[187]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[188]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[189]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[190]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[191]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[192]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[193]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[194]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[195]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[196]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[197]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[198]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[199]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[200]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[201]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[202]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[203]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[204]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[205]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[206]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[207]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[208]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[209]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[210]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[211]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[212]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[213]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[214]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[215]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[216]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[217]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[218]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[219]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[220]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[221]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[222]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[223]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[224]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[225]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[226]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[227]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[228]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[229]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[230]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[231]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[232]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[233]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[234]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[235]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[236]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[237]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[238]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[239]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[240]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[241]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[242]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[243]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[244]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[245]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[246]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[247]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[248]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[249]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[250]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[251]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[252]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[253]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[254]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[255]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[256]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[257]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[258]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[259]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[260]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[261]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[262]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[263]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[264]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[265]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[266]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[267]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[268]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[269]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[270]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[271]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[272]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[273]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[274]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[275]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[276]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[277]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[278]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[279]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[280]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[281]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[282]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[283]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[284]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[285]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[286]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[287]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[288]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[289]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[290]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[291]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[292]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[293]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[294]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[295]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[296]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[297]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[298]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[299]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[300]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[301]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[302]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[303]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[304]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[305]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[306]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[307]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[308]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[309]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[310]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[311]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[312]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[313]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[314]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[315]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[316]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[317]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[318]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[319]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[320]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[321]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[322]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[323]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[324]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[325]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[326]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[327]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[328]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[329]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[330]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[331]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[332]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[333]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[334]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[335]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[336]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[337]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[338]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[339]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[340]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[341]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[342]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[343]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[344]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[345]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[346]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[347]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[348]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[349]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[350]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[351]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[352]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[353]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[354]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[355]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[356]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[357]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[358]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[359]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[360]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[361]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[362]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[363]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[364]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[365]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[366]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[367]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[368]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[369]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[370]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[371]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[372]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[373]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[374]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[375]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[376]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[377]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[378]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[379]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[380]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[381]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[382]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[383]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[384]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[385]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[386]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[387]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[388]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[389]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[390]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[391]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[392]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[393]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[394]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[395]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[396]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[397]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[398]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[399]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[400]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[401]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[402]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[403]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[404]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[405]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[406]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[407]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[408]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[409]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[410]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[411]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[412]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[413]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[414]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[415]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[416]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[417]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[418]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[419]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[420]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[421]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[422]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[423]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[424]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[425]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[426]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[427]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[428]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[429]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[430]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[431]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[432]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[433]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[434]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[435]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[436]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[437]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[438]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[439]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[440]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[441]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[442]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[443]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[444]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[445]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[446]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[447]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[448]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[449]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[450]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[451]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[452]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[453]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[454]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[455]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[456]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
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|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[457]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[458]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[459]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[460]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[461]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[462]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[463]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[464]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
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|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[465]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
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|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[466]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[467]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[468]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
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|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[469]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[470]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[471]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[472]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[473]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[474]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
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|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[475]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[476]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[477]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
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|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[478]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[479]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[480]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[481]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[482]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[483]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[484]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[485]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[486]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[487]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[488]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[489]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[490]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[491]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[492]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[493]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[494]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[495]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[496]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[497]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[498]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[499]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[500]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[501]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[502]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[503]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[504]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[505]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[506]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[507]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[508]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[509]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[510]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_writedata[511]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 78
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_address[0]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 79
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_address[1]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 79
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_address[2]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 79
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_address[3]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 79
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_address[4]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 79
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_address[5]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 79
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_address[6]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 79
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_address[7]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 79
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_address[8]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 79
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_address[9]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 79
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_address[10]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 79
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_address[11]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 79
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_address[12]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 79
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_address[13]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 79
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_address[14]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 79
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_address[15]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 79
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_address[16]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 79
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_address[17]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 79
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_address[18]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 79
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_address[19]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 79
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_address[20]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 79
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_address[21]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 79
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_address[22]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 79
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_address[23]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 79
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_address[24]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 79
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_address[25]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 79
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_address[26]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 79
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_write" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 80
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_read" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 81
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_byteenable[0]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 82
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_byteenable[1]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 82
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_byteenable[2]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 82
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|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_byteenable[3]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 82
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|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_byteenable[4]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 82
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|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_byteenable[5]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 82
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|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_byteenable[6]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 82
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|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_byteenable[7]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 82
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|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_byteenable[8]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 82
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|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_byteenable[9]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 82
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|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_byteenable[10]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 82
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|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_byteenable[11]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 82
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|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_byteenable[12]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 82
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|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_byteenable[13]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 82
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|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_byteenable[14]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 82
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|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_byteenable[15]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 82
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|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_byteenable[16]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 82
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|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_byteenable[17]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 82
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|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_byteenable[18]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 82
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|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_byteenable[19]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 82
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|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_byteenable[20]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 82
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|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_byteenable[21]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 82
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|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_byteenable[22]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 82
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|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_byteenable[23]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 82
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|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_byteenable[24]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 82
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|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_byteenable[25]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 82
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|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_byteenable[26]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 82
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|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_byteenable[27]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 82
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|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_byteenable[28]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 82
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|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_byteenable[29]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 82
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|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_byteenable[30]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 82
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|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_byteenable[31]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 82
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|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_byteenable[32]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 82
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|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_byteenable[33]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 82
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|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_byteenable[34]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 82
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|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_byteenable[35]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 82
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|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_byteenable[36]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 82
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|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_byteenable[37]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 82
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|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_byteenable[38]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 82
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|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_byteenable[39]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 82
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|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_byteenable[40]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 82
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|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_byteenable[41]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 82
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|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_byteenable[42]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 82
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|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_byteenable[43]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 82
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|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_byteenable[44]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 82
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|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_byteenable[45]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 82
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|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_byteenable[46]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 82
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|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_byteenable[47]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 82
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|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_byteenable[48]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 82
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|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_byteenable[49]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 82
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|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_byteenable[50]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 82
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|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_byteenable[51]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 82
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|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_byteenable[52]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 82
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_byteenable[53]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 82
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_byteenable[54]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 82
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_byteenable[55]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 82
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_byteenable[56]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 82
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_byteenable[57]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 82
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_byteenable[58]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 82
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_byteenable[59]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 82
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_byteenable[60]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 82
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_byteenable[61]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 82
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_byteenable[62]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 82
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|DDR4b_byteenable[63]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 82
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_analogreset[0]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 51
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_analogreset[1]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 51
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_analogreset[2]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 51
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_analogreset[3]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 51
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_digitalreset[0]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 52
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_digitalreset[1]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 52
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_digitalreset[2]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 52
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_digitalreset[3]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 52
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_rx_analogreset[0]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 53
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_rx_analogreset[1]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 53
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_rx_analogreset[2]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 53
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_rx_analogreset[3]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 53
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_rx_digitalreset[0]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 54
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_rx_digitalreset[1]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 54
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_rx_digitalreset[2]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 54
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_rx_digitalreset[3]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 54
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_rx_seriallpbken[0]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 57
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_rx_seriallpbken[1]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 57
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_rx_seriallpbken[2]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 57
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_rx_seriallpbken[3]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 57
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_rx_set_locktoref[0]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 58
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_rx_set_locktoref[1]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 58
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_rx_set_locktoref[2]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 58
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_rx_set_locktoref[3]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 58
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_rx_set_locktodata[0]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 59
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_rx_set_locktodata[1]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 59
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_rx_set_locktodata[2]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 59
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_rx_set_locktodata[3]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 59
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[0]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[1]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[2]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[3]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[4]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[5]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[6]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[7]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[8]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[9]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[10]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[11]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[12]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[13]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[14]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[15]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[16]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[17]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[18]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[19]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[20]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[21]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[22]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[23]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[24]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[25]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[26]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[27]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[28]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[29]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[30]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[31]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[32]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[33]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[34]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[35]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[36]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[37]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[38]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[39]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[40]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[41]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[42]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[43]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[44]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[45]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[46]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[47]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[48]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[49]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[50]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[51]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[52]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[53]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[54]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[55]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[56]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[57]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[58]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[59]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[60]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[61]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[62]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[63]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[64]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[65]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[66]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[67]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[68]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[69]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[70]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[71]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[72]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[73]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[74]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[75]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[76]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[77]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[78]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[79]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[80]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[81]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[82]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[83]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[84]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[85]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[86]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[87]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[88]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[89]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[90]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[91]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[92]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[93]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[94]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[95]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[96]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[97]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[98]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[99]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[100]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[101]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[102]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[103]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[104]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[105]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[106]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[107]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[108]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[109]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[110]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[111]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[112]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[113]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[114]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[115]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[116]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[117]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[118]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[119]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[120]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[121]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[122]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[123]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[124]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[125]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[126]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[127]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[128]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[129]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[130]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[131]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[132]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[133]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[134]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[135]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[136]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[137]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[138]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[139]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[140]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[141]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[142]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[143]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[144]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[145]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[146]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[147]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[148]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[149]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[150]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[151]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[152]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[153]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[154]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[155]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[156]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[157]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[158]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[159]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[160]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[161]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[162]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[163]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[164]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[165]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[166]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[167]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[168]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[169]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[170]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[171]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[172]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[173]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[174]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[175]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[176]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[177]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[178]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[179]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[180]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[181]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[182]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[183]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[184]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[185]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[186]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[187]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[188]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[189]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[190]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[191]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[192]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[193]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[194]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[195]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[196]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[197]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[198]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[199]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[200]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[201]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[202]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[203]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[204]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[205]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[206]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[207]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[208]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[209]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[210]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[211]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[212]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[213]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[214]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[215]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[216]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[217]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[218]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[219]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[220]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[221]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[222]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[223]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[224]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[225]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[226]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[227]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[228]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[229]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[230]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[231]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[232]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[233]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[234]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[235]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[236]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[237]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[238]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[239]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[240]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[241]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[242]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[243]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[244]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[245]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[246]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[247]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[248]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[249]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[250]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[251]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[252]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[253]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[254]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[255]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[256]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[257]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[258]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[259]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[260]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[261]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[262]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[263]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[264]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[265]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[266]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[267]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[268]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[269]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[270]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[271]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[272]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[273]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[274]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[275]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[276]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[277]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[278]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[279]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[280]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[281]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[282]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[283]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[284]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[285]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[286]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[287]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[288]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[289]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[290]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[291]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[292]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[293]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[294]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[295]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[296]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[297]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[298]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[299]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[300]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[301]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[302]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[303]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[304]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[305]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[306]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[307]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[308]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[309]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[310]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[311]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[312]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[313]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[314]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[315]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[316]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[317]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[318]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[319]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[320]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[321]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[322]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[323]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[324]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[325]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[326]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[327]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[328]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[329]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[330]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[331]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[332]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[333]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[334]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[335]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[336]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[337]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[338]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[339]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[340]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[341]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[342]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[343]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[344]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[345]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[346]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[347]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[348]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[349]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[350]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[351]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[352]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[353]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[354]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[355]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[356]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[357]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[358]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[359]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[360]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[361]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[362]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[363]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[364]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[365]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[366]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[367]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[368]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[369]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[370]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[371]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[372]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[373]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[374]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[375]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[376]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[377]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[378]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[379]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[380]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[381]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[382]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[383]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[384]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[385]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[386]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[387]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[388]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[389]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[390]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[391]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[392]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[393]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[394]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[395]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[396]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[397]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[398]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[399]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[400]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[401]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[402]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[403]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[404]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[405]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[406]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[407]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[408]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[409]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[410]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[411]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[412]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[413]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[414]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[415]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[416]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[417]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[418]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[419]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[420]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[421]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[422]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[423]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[424]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[425]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[426]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[427]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[428]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[429]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[430]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[431]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[432]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[433]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[434]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[435]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[436]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[437]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[438]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[439]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[440]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[441]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[442]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[443]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[444]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[445]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[446]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[447]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[448]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[449]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[450]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[451]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[452]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[453]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[454]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[455]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[456]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[457]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[458]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[459]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[460]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[461]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[462]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[463]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[464]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[465]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[466]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[467]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[468]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[469]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[470]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[471]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[472]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[473]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[474]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[475]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[476]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[477]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[478]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[479]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[480]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[481]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[482]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[483]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[484]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[485]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[486]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[487]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[488]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[489]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[490]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[491]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[492]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[493]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[494]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[495]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[496]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[497]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[498]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[499]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[500]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[501]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[502]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[503]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[504]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[505]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[506]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[507]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[508]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[509]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[510]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_parallel_data[511]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 69
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_control[0]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 70
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_control[1]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 70
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_control[2]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 70
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_control[3]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 70
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_control[4]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 70
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_control[5]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 70
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_control[6]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 70
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_control[7]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 70
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_control[8]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 70
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_control[9]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 70
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_control[10]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 70
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_control[11]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 70
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_control[12]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 70
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_control[13]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 70
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_control[14]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 70
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_control[15]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 70
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_control[16]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 70
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_control[17]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 70
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_control[18]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 70
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_control[19]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 70
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_control[20]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 70
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_control[21]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 70
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_control[22]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 70
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_control[23]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 70
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_control[24]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 70
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_control[25]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 70
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_control[26]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 70
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_control[27]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 70
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_control[28]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 70
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_control[29]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 70
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_control[30]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 70
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_control[31]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 70
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_control[32]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 70
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_control[33]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 70
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_control[34]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 70
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_control[35]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 70
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_control[36]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 70
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_control[37]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 70
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_control[38]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 70
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_control[39]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 70
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_control[40]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 70
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_control[41]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 70
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_control[42]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 70
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_control[43]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 70
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_control[44]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 70
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_control[45]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 70
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_control[46]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 70
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_control[47]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 70
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_control[48]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 70
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_control[49]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 70
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_control[50]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 70
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_control[51]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 70
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_control[52]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 70
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_control[53]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 70
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_control[54]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 70
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_control[55]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 70
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_control[56]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 70
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_control[57]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 70
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_control[58]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 70
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_control[59]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 70
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_control[60]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 70
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_control[61]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 70
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_control[62]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 70
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_control[63]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 70
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_control[64]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 70
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_control[65]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 70
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_control[66]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 70
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_control[67]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 70
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_control[68]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 70
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_control[69]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 70
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_control[70]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 70
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_control[71]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 70
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_rx_enh_fifo_rd_en[0]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 86
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_rx_enh_fifo_rd_en[1]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 86
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_rx_enh_fifo_rd_en[2]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 86
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_rx_enh_fifo_rd_en[3]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 86
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_enh_data_valid[0]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 87
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_enh_data_valid[1]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 87
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_enh_data_valid[2]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 87
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_tx_enh_data_valid[3]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 87
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_init_start" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 86
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_prmgmt_fatal_err" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 86
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_prmgmt_dout[0]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 94
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_prmgmt_dout[1]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 94
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_prmgmt_dout[2]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 94
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_prmgmt_dout[3]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 94
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_prmgmt_dout[4]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 94
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_prmgmt_dout[5]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 94
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_prmgmt_dout[6]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 94
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_prmgmt_dout[7]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 94
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_prmgmt_dout[8]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 94
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_prmgmt_dout[9]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 94
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_prmgmt_dout[10]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 94
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_prmgmt_dout[11]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 94
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_prmgmt_dout[12]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 94
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_prmgmt_dout[13]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 94
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_prmgmt_dout[14]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 94
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_prmgmt_dout[15]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 94
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_prmgmt_dout[16]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 94
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_prmgmt_dout[17]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 94
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_prmgmt_dout[18]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 94
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_prmgmt_dout[19]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 94
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_prmgmt_dout[20]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 94
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_prmgmt_dout[21]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 94
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_prmgmt_dout[22]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 94
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_prmgmt_dout[23]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 94
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_prmgmt_dout[24]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 94
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_prmgmt_dout[25]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 94
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_prmgmt_dout[26]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 94
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_prmgmt_dout[27]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 94
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_prmgmt_dout[28]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 94
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_prmgmt_dout[29]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 94
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_prmgmt_dout[30]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 94
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|
Warning (13410): Pin "fpga_top|inst_green_bs|hssi.a2f_prmgmt_dout[31]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/pr_hssi_if.vh Line: 94
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|tcm_mmio_waitreq" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 95
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|tcm_mmio_readdata[0]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 97
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|tcm_mmio_readdata[1]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 97
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|tcm_mmio_readdata[2]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 97
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|tcm_mmio_readdata[3]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 97
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|tcm_mmio_readdata[4]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 97
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|tcm_mmio_readdata[5]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 97
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|tcm_mmio_readdata[6]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 97
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|tcm_mmio_readdata[7]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 97
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|tcm_mmio_readdata[8]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 97
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|tcm_mmio_readdata[9]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 97
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|tcm_mmio_readdata[10]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 97
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|tcm_mmio_readdata[11]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 97
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|tcm_mmio_readdata[12]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 97
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|tcm_mmio_readdata[13]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 97
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|tcm_mmio_readdata[14]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 97
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|tcm_mmio_readdata[15]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 97
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|tcm_mmio_readdata[16]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 97
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|tcm_mmio_readdata[17]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 97
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|tcm_mmio_readdata[18]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 97
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|tcm_mmio_readdata[19]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 97
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|tcm_mmio_readdata[20]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 97
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|tcm_mmio_readdata[21]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 97
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|tcm_mmio_readdata[22]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 97
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|tcm_mmio_readdata[23]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 97
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|tcm_mmio_readdata[24]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 97
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|tcm_mmio_readdata[25]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 97
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|tcm_mmio_readdata[26]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 97
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|tcm_mmio_readdata[27]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 97
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|
Warning (13410): Pin "fpga_top|inst_green_bs|tcm_mmio_readdata[28]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 97
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|
Warning (13410): Pin "fpga_top|inst_green_bs|tcm_mmio_readdata[29]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 97
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|
Warning (13410): Pin "fpga_top|inst_green_bs|tcm_mmio_readdata[30]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 97
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|
Warning (13410): Pin "fpga_top|inst_green_bs|tcm_mmio_readdata[31]" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 97
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|tcm_mmio_readdatavalid" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 98
|
|
Warning (13410): Pin "fpga_top|inst_green_bs|pr2sr_tdo" is stuck at GND File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/platform/green_bs.sv Line: 104
|
|
Info (17049): 44415 registers lost all their fanouts during netlist optimizations.
|
|
Info (21057): Implemented 958754 device resources after synthesis - the final resource count might be different
|
|
Info (21058): Implemented 2386 input pins
|
|
Info (21059): Implemented 2655 output pins
|
|
Info (21061): Implemented 805691 logic cells
|
|
Info (21064): Implemented 147446 RAM segments
|
|
Info (21062): Implemented 512 DSP elements
|
|
Info: Successfully synthesized partition
|
|
Info: Saving post-synthesis snapshots for 3 partition(s)
|
|
Info: Quartus Prime Synthesis was successful. 0 errors, 1831 warnings
|
|
Info: Peak virtual memory: 14556 megabytes
|
|
Info: Processing ended: Sat Mar 6 05:12:50 2021
|
|
Info: Elapsed time: 00:30:13
|
|
Info (19538): Reading SDC files took 00:00:40 cumulatively in this process.
|
|
Info: *******************************************************************
|
|
Info: Running Quartus Prime Fitter
|
|
Info: Version 19.2.0 Build 57 06/24/2019 Patches 0.01rc SJ Pro Edition
|
|
Info: Processing started: Sat Mar 6 05:15:34 2021
|
|
Info: Command: quartus_fit --read_settings_files=on --write_settings_files=off dcp -c afu_default
|
|
Info: qfit2_default_script.tcl version: #1
|
|
Info: Project = dcp
|
|
Info: Revision = afu_default
|
|
Info (16677): Loading synthesized database
|
|
Info (16734): Loading "final" snapshot for partition "root_partition".
|
|
Info (16734): Loading "final" snapshot for partition "root_partition_2cedade0".
|
|
Info (16734): Loading "synthesized" snapshot for partition "green_region".
|
|
Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design contains file: "/opt/opae/1.1.2/share/opae/platform/platform_if/rtl/platform_shims/utils/quartus_ip/platform_utils_dc_fifo.sdc", assignment in base design does not contain file). Check that the assignment in the current design is correct.
|
|
Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design contains file: "/opt/opae/1.1.2/share/opae/platform/platform_if/rtl/platform_shims/utils/quartus_ip/platform_utils_avalon_dc_fifo.sdc", assignment in base design does not contain file). Check that the assignment in the current design is correct.
|
|
Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design contains file: "/opt/opae/1.1.2/share/opae/platform/platform_if/par/platform_if.sdc", assignment in base design does not contain file). Check that the assignment in the current design is correct.
|
|
Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design contains file: "dcp_bbs.sdc", assignment in base design does not contain file). Check that the assignment in the current design is correct.
|
|
Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design contains file: "platform/green_bs.sdc", assignment in base design does not contain file). Check that the assignment in the current design is correct.
|
|
Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design contains file: "dcp_user_clocks.sdc", assignment in base design does not contain file). Check that the assignment in the current design is correct.
|
|
Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/hssi_eth/e10/phy/altera_eth_10gbaser_phy/altera_xcvr_native_a10_191/synth/altera_xcvr_native_a10_false_paths.sdc"). Check that the assignment in the current design is correct.
|
|
Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/hssi_eth/native_xcvr/altera_xcvr_native_a10_191/synth/altera_xcvr_native_a10_false_paths.sdc"). Check that the assignment in the current design is correct.
|
|
Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/remote_stp/QSYS_IPs/PR_190/ip/SLD_HUB_CONT_SYS_WO_SLD_EP/SLD_HUB_CONT_SYS_WO_SLD_EP_sld_hub_controller_system_without_sldep_0/altera_streaming_sld_hub_controller_core_without_sldep_180/synth/altera_streaming_sld_hub_controller_without_sldep.sdc"). Check that the assignment in the current design is correct.
|
|
Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/fme/ptmgr/TEMPERATURE_SourceTree/ptmgr_temp_sensor/altera_temp_sense_191/synth/altera_temp_sense.sdc"). Check that the assignment in the current design is correct.
|
|
Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/top/dcp_top.sdc"). Check that the assignment in the current design is correct.
|
|
Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/sdc/fabric.sdc"). Check that the assignment in the current design is correct.
|
|
Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/sdc/fme.sdc"). Check that the assignment in the current design is correct.
|
|
Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/sdc/fiu.sdc"). Check that the assignment in the current design is correct.
|
|
Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/afu/green_bs.sdc"). Check that the assignment in the current design is correct.
|
|
Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/partial_reconfig/PR_IP/alt_pr_191/synth/rtl/alt_pr.sdc"). Check that the assignment in the current design is correct.
|
|
Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/pcie/ips/pcie_sriov_ep_g3x8/pcie_sriov_ep_g3x8/altera_xcvr_native_a10_191/synth/altera_xcvr_native_a10_false_paths.sdc"). Check that the assignment in the current design is correct.
|
|
Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/pcie/ips/pcie_sriov_ep_g3x8/pcie_sriov_ep_g3x8/altera_pcie_a10_hip_191/synth/altera_pci_express.sdc"). Check that the assignment in the current design is correct.
|
|
Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/afu/nlb_400/nlb_400.sdc"). Check that the assignment in the current design is correct.
|
|
Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/bmc_mailbox/ip/bmc_mailbox/bmc_mailbox_spi_slave_to_avalon_mm_master_bridge_1/spi_slave_to_avalon_mm_master_bridge_191/synth/spiphyslave.sdc"). Check that the assignment in the current design is correct.
|
|
Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/tcm/ip/tcm/tcm_alt_pr_0/alt_pr_191/synth/rtl/alt_pr.sdc"). Check that the assignment in the current design is correct.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_aeb", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|rdemp_eq_comp_msb_aeb", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|wrptr_g[0]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|wrptr_g[1]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|wrptr_g[2]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|wrptr_g[3]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|wrptr_g[4]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|wrptr_g[5]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|wrptr_g[6]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|rdptr_g1p|counter1a0", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_aeb", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|rdemp_eq_comp_msb_aeb", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|wrptr_g[0]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|wrptr_g[1]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|wrptr_g[2]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|wrptr_g[3]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|wrptr_g[4]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|wrptr_g[5]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|wrptr_g[6]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|rdptr_g1p|counter1a0", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_aeb", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|rdemp_eq_comp_msb_aeb", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|wrptr_g[0]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|wrptr_g[1]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|wrptr_g[2]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|wrptr_g[3]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|wrptr_g[4]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|wrptr_g[5]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|rdptr_g1p|counter1a0", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|wrptr_g1p|counter4a0", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|rdptr_g1p|parity2", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|wrptr_g1p|counter4a0", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|rdptr_g1p|parity2", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|wrptr_g1p|counter3a0", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|rdptr_g1p|parity2", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|wrptr_g1p|parity5", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|wrptr_g1p|parity5", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|wrptr_g1p|parity4", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_aeb", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|rdemp_eq_comp_msb_aeb", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|wrptr_g[0]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|wrptr_g[1]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|wrptr_g[2]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|wrptr_g[3]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|wrptr_g[4]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|wrptr_g[5]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|wrptr_g[6]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|wrptr_g[7]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|wrptr_g[8]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|wrptr_g[9]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|rdptr_g1p|counter1a0", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_aeb", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|rdemp_eq_comp_msb_aeb", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|wrptr_g[0]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|wrptr_g[1]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|wrptr_g[2]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|wrptr_g[3]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|wrptr_g[4]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|wrptr_g[5]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|wrptr_g[6]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|wrptr_g[7]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|wrptr_g[8]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|rdptr_g1p|counter1a0", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|wrptr_g1p|counter4a0", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|rdptr_g1p|parity2", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|wrptr_g1p|counter4a0", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|rdptr_g1p|parity2", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|wrptr_g1p|parity5", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|wrptr_g1p|parity5", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Info (16678): Successfully loaded synthesized database: elapsed time is 00:00:19
|
|
Info (16303): Superior Performance optimization mode selected -- timing performance will be prioritized at the potential cost of increased logic area and compilation time
|
|
Info (16304): Mode behavior is affected by advanced setting Restructure Multiplexers (default for this mode is Off)
|
|
Info (16304): Mode behavior is affected by advanced setting Placement Effort Multiplier (default for this mode is 4.0)
|
|
Info (20030): Parallel compilation is enabled and will use 16 of the 32 processors detected
|
|
Info (119006): Selected device 10AX115N2F40E2LG for design "afu_default"
|
|
Info (21076): Core supply voltage operating condition is not set. Assuming a default value of '0.9V'.
|
|
Info (21077): Low junction temperature is 0 degrees C
|
|
Info (21077): High junction temperature is 100 degrees C
|
|
Warning (18550): Found RAM instances implemented as ROM because the write logic is disabled. One instance is listed below as an example.
|
|
Info (119043): Atom "mem|ddr4b|ddr4b|cal_slave_component|ioaux_soft_ram|the_altsyncram|auto_generated|ram_block1a0" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled
|
|
Info (171004): Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance
|
|
Info (176045): Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements.
|
|
Warning (176050): Can't implement Global Signal option for node "DDR4_RefClk~input" that drives nodes that cannot change routing due to incremental compilation -- other nodes are not affected File: /nfs/site/disks/pac_build_1/psgpacbuild/SC/adapt/nightly/19.1/367/l64/work/platform/dcp_1.0-rc/design/top/dcp_top.v Line: 6
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|
Info (12262): Starting Fitter periphery placement operations
|
|
Info (12290): Loading the periphery placement data.
|
|
Info (12291): Periphery placement data loaded: elapsed time is 00:00:45
|
|
Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
|
|
Warning (12789): Real-time CRC ERROR_CHECK_FREQUENCY_DIVISOR value (1) in design does not match value (4) in the Quartus Prime Settings File
|
|
Info (19022): A default voltage has been automatically assigned to "PCIE_TX[0]". Refer to .pin report for more information. If this value is not valid, use the QSF assignment "set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE -to <to> -entity <entity name> <value>" to specify the desired voltage.
|
|
Info (19022): A default voltage has been automatically assigned to "PCIE_TX[1]". Refer to .pin report for more information. If this value is not valid, use the QSF assignment "set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE -to <to> -entity <entity name> <value>" to specify the desired voltage.
|
|
Info (19022): A default voltage has been automatically assigned to "PCIE_TX[2]". Refer to .pin report for more information. If this value is not valid, use the QSF assignment "set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE -to <to> -entity <entity name> <value>" to specify the desired voltage.
|
|
Info (19022): A default voltage has been automatically assigned to "PCIE_TX[3]". Refer to .pin report for more information. If this value is not valid, use the QSF assignment "set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE -to <to> -entity <entity name> <value>" to specify the desired voltage.
|
|
Info (19022): A default voltage has been automatically assigned to "PCIE_TX[4]". Refer to .pin report for more information. If this value is not valid, use the QSF assignment "set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE -to <to> -entity <entity name> <value>" to specify the desired voltage.
|
|
Info (19022): A default voltage has been automatically assigned to "PCIE_TX[5]". Refer to .pin report for more information. If this value is not valid, use the QSF assignment "set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE -to <to> -entity <entity name> <value>" to specify the desired voltage.
|
|
Info (19022): A default voltage has been automatically assigned to "PCIE_TX[6]". Refer to .pin report for more information. If this value is not valid, use the QSF assignment "set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE -to <to> -entity <entity name> <value>" to specify the desired voltage.
|
|
Info (19022): A default voltage has been automatically assigned to "PCIE_TX[7]". Refer to .pin report for more information. If this value is not valid, use the QSF assignment "set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE -to <to> -entity <entity name> <value>" to specify the desired voltage.
|
|
Info (176045): Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements.
|
|
Info (16210): Plan updated with currently enabled project assignments.
|
|
Info (12295): Periphery placement of all unplaced cells complete: elapsed time is 00:00:00
|
|
Critical Warning (17951): There are 36 unused RX channels in the design.
|
|
Info (19540): Add the QSF assignment 'set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to <pin_name>' for each unused channel that will be used in future.
|
|
Info (19541): The above QSF assignment will preserve the performance of specified channels over time, and works only if the design uses at least 1 transceiver channel.
|
|
Critical Warning (18655): There are 36 unused TX channels in the design.
|
|
Info (19540): Add the QSF assignment 'set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to <pin_name>' for each unused channel that will be used in future.
|
|
Info (19541): The above QSF assignment will preserve the performance of specified channels over time, and works only if the design uses at least 1 transceiver channel.
|
|
Warning (18708): ATX/FPLL < fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_pll.g_pll_g3n.lcpll_g3xn|lcpll_g3xn|a10_xcvr_atx_pll_inst|twentynm_atx_pll_inst > is not placed in the same bank as the reference clock.
|
|
Info (11178): Promoted 24 clocks (17 global, 3 regional, 4 periphery)
|
|
Info (13173): SYS_RefClk~inputCLKENA0 (3756 fanout) drives Global Clock Region, with the buffer placed at CLKCTRL_2A_G_I15
|
|
Info (13173): fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk0~CLKENA0 (3 fanout) drives Global Clock Region, with the buffer placed at CLKCTRL_1C_G_I12
|
|
Info (13173): fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk1~CLKENA0 (695057 fanout) drives Global Clock Region, with the buffer placed at CLKCTRL_1C_G_I13
|
|
Info (13173): fpga_top|inst_fiu_top|inst_hssi_ctrl|pll_r_0|xcvr_fpll_a10_0|outclk0~CLKENA0 (11 fanout) drives Global Clock Region, with the buffer placed at CLKCTRL_1I_G_I0
|
|
Info (13173): fpga_top|inst_fiu_top|inst_hssi_ctrl|pll_r_0|xcvr_fpll_a10_0|outclk1~CLKENA0 (7 fanout) drives Global Clock Region, with the buffer placed at CLKCTRL_1I_G_I1
|
|
Info (13173): fpga_top|inst_fiu_top|inst_hssi_ctrl|pll_t|xcvr_fpll_a10_0|outclk0~CLKENA0 (11 fanout) drives Global Clock Region, with the buffer placed at CLKCTRL_1H_G_I6
|
|
Info (13173): fpga_top|inst_fiu_top|inst_hssi_ctrl|pll_t|xcvr_fpll_a10_0|outclk1~CLKENA0 (7 fanout) drives Global Clock Region, with the buffer placed at CLKCTRL_1H_G_I7
|
|
Info (13173): mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|clk_gen_hmc.hr_qr.clk_gen_master.emif_usr_clk_buf (7247 fanout) drives Global Clock Region, with the buffer placed at CLKCTRL_3C_G_I19
|
|
Info (13173): u0|dcp_iopll|dcp_iopll|altera_iopll_i|twentynm_pll|outclk[1]~CLKENA0 (23823 fanout) drives Global Clock Region, with the buffer placed at CLKCTRL_2F_G_I5
|
|
Info (13173): u0|dcp_iopll|dcp_iopll|altera_iopll_i|twentynm_pll|outclk[2]~CLKENA0 (2 fanout) drives Global Clock Region, with the buffer placed at CLKCTRL_2F_G_I3
|
|
Info (13173): u0|dcp_iopll|dcp_iopll|altera_iopll_i|twentynm_pll|outclk[3]~CLKENA0 (1801 fanout) drives Global Clock Region, with the buffer placed at CLKCTRL_2F_G_I4
|
|
Info (13173): fspi_sclk~inputCLKENA0 (14 fanout) drives Global Clock Region, with the buffer placed at CLKCTRL_2K_G_I11
|
|
Info (13173): DDR4_RefClk~inputCLKENA0 (22 fanout) drives Global Clock Region, with the buffer placed at CLKCTRL_3C_G_I22
|
|
Info (13173): mem|ddr4a|ddr4a|arch|arch_inst|pll_inst|pll_c_counters[3]~CLKENA0 (185 fanout) drives Global Clock Region, with the buffer placed at CLKCTRL_3C_G_I18
|
|
Info (13173): u0|dcp_iopll|dcp_iopll|altera_iopll_i|twentynm_pll|outclk[4]~CLKENA0 (1756 fanout) drives Global Clock Region, with the buffer placed at CLKCTRL_2F_G_I14
|
|
Info (13173): fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~CORE_CLK_OUTCLKENA0 (14681 fanout) drives Global Clock Region, with the buffer placed at CLKCTRL_3A_G_I17
|
|
Info (13173): PCIE_REFCLK~inputFITTER_INSERTEDCLKENA0 (3800 fanout) drives Global Clock Region, with the buffer placed at CLKCTRL_1C_G_I2
|
|
Info (13173): ETH_RefClk~inputFITTER_INSERTEDCLKENA0 (7 fanout) drives Regional Clock Region 1, with the buffer placed at CLKCTRL_1E_R1_I0
|
|
Info (13173): fpga_top|inst_fiu_top|inst_hssi_ctrl|clkbuf_r_0 (8 fanout) drives Regional Clock Region 1, with the buffer placed at CLKCTRL_1E_R1_I1
|
|
Info (13173): fpga_top|inst_fiu_top|inst_hssi_ctrl|clkbuf_t (8 fanout) drives Regional Clock Region 2, with the buffer placed at CLKCTRL_1F_R2_I2
|
|
Info (13173): fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|out_pld_pcs_rx_clk_out~CLKENA0 (50 fanout) drives Periphery Clock Region 5, with the buffer placed at CLKCTRL_1E_P5_I9
|
|
Info (13173): fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|out_pld_pcs_rx_clk_out~CLKENA0 (42 fanout) drives Periphery Clock Region 5, with the buffer placed at CLKCTRL_1E_P5_I8
|
|
Info (13173): fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|out_pld_pcs_rx_clk_out~CLKENA0 (42 fanout) drives Periphery Clock Region 5, with the buffer placed at CLKCTRL_1E_P5_I6
|
|
Info (13173): fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|out_pld_pcs_rx_clk_out~CLKENA0 (41 fanout) drives Periphery Clock Region 5, with the buffer placed at CLKCTRL_1E_P5_I3
|
|
Info (11711): ===========================HSSI DESIGN INFO===========================
|
|
Info (11711): Reference Clocks: PCIE_REFCLK~pad
|
|
Info (11711): Transceiver Group fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm: type: duplex bond HIP, reference clk: PCIE_REFCLK~pad , 2 plls(ids): ff_pll(1937) (FPLL_1DB) lc(1938) (HSSIPMALCPLL_1DB)
|
|
Info (11711): pma_aux_ibuf:none(-1), avmm_id: -65537
|
|
Info (11711): Channel PCIE_TX[0](2105) PCIE_RX[0]
|
|
Info (11711): Channel PCIE_TX[1](2106) PCIE_RX[1]
|
|
Info (11711): Channel PCIE_TX[2](2107) PCIE_RX[2]
|
|
Info (11711): Channel PCIE_TX[3](2108) PCIE_RX[3]
|
|
Info (11711): Channel PCIE_TX[4](2109) PCIE_RX[4]
|
|
Info (11711): Channel PCIE_TX[5](2110) PCIE_RX[5]
|
|
Info (11711): Channel PCIE_TX[6](2111) PCIE_RX[6]
|
|
Info (11711): Channel PCIE_TX[7](2112) PCIE_RX[7]
|
|
Info (11711): fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_pll.fpll_g3|fpll_g3|fpll_inst
|
|
Info (11711): fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_pll.g_pll_g3n.lcpll_g3xn|lcpll_g3xn|a10_xcvr_atx_pll_inst|twentynm_atx_pll_inst
|
|
Info (11711): Reference Clocks: ETH_RefClk~pad
|
|
Info (11711): Transceiver Group fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm: type: duplex unbonded xN, reference clk: ETH_RefClk~pad , 1 pll(id): lc(1687) (HSSIPMALCPLL_1EB)
|
|
Info (11711): pma_aux_ibuf:none(-1), avmm_id: -65537
|
|
Info (11711): Channel QSFP1_TX_P_1(2101) QSFP1_RX_P_1
|
|
Info (11711): Channel QSFP1_TX_P_2(2102) QSFP1_RX_P_2
|
|
Info (11711): Channel QSFP1_TX_P_3(2103) QSFP1_RX_P_3
|
|
Info (11711): Channel QSFP1_TX_P_4(2104) QSFP1_RX_P_4
|
|
Info (11711): fpga_top|inst_fiu_top|inst_hssi_ctrl|atx0|altera_xcvr_atx_pll_ip_inst|a10_xcvr_atx_pll_inst|twentynm_atx_pll_inst
|
|
Info (11711): ===========================HSSI DESIGN INFO===========================
|
|
Info (11711): Reference Clocks: PCIE_REFCLK~pad
|
|
Info (11711): Transceiver Group fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm: type: duplex bond HIP, reference clk: PCIE_REFCLK~pad , 2 plls(ids): ff_pll(1937) (FPLL_1DB) lc(1938) (HSSIPMALCPLL_1DB)
|
|
Info (11711): pma_aux_ibuf:none(-1), avmm_id: -65537
|
|
Info (11711): Channel PCIE_TX[0](2105) PCIE_RX[0]
|
|
Info (11711): Channel PCIE_TX[1](2106) PCIE_RX[1]
|
|
Info (11711): Channel PCIE_TX[2](2107) PCIE_RX[2]
|
|
Info (11711): Channel PCIE_TX[3](2108) PCIE_RX[3]
|
|
Info (11711): Channel PCIE_TX[4](2109) PCIE_RX[4]
|
|
Info (11711): Channel PCIE_TX[5](2110) PCIE_RX[5]
|
|
Info (11711): Channel PCIE_TX[6](2111) PCIE_RX[6]
|
|
Info (11711): Channel PCIE_TX[7](2112) PCIE_RX[7]
|
|
Info (11711): fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_pll.fpll_g3|fpll_g3|fpll_inst
|
|
Info (11711): fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_pll.g_pll_g3n.lcpll_g3xn|lcpll_g3xn|a10_xcvr_atx_pll_inst|twentynm_atx_pll_inst
|
|
Info (11711): Reference Clocks: ETH_RefClk~pad
|
|
Info (11711): Transceiver Group fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm: type: duplex unbonded xN, reference clk: ETH_RefClk~pad , 1 pll(id): lc(1687) (HSSIPMALCPLL_1EB)
|
|
Info (11711): pma_aux_ibuf:none(-1), avmm_id: -65537
|
|
Info (11711): Channel QSFP1_TX_P_1(2101) QSFP1_RX_P_1
|
|
Info (11711): Channel QSFP1_TX_P_2(2102) QSFP1_RX_P_2
|
|
Info (11711): Channel QSFP1_TX_P_3(2103) QSFP1_RX_P_3
|
|
Info (11711): Channel QSFP1_TX_P_4(2104) QSFP1_RX_P_4
|
|
Info (11711): fpga_top|inst_fiu_top|inst_hssi_ctrl|atx0|altera_xcvr_atx_pll_ip_inst|a10_xcvr_atx_pll_inst|twentynm_atx_pll_inst
|
|
Info (332164): Evaluating HDL-embedded SDC commands
|
|
Info (332165): Entity MISOctl
|
|
Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *SPIPhy_altera_avalon_st_idle_inserter|received_esc*|*] -to [get_pins -no_case -compatibility_mode *|rdshiftreg*|*]
|
|
Info (332165): Entity MOSIctl
|
|
Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *]
|
|
Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *]
|
|
Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *]
|
|
Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *]
|
|
Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *]
|
|
Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *]
|
|
Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *]
|
|
Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *]
|
|
Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *]
|
|
Info (332165): Entity alt_jtag_atlantic
|
|
Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|jupdate}] -to [get_registers {*|alt_jtag_atlantic:*|jupdate1*}]
|
|
Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rdata[*]}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}]
|
|
Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|read}] -to [get_registers {*|alt_jtag_atlantic:*|read1*}]
|
|
Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|read_req}]
|
|
Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rvalid}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}]
|
|
Info (332166): set_false_path -from [get_registers {*|t_dav}] -to [get_registers {*|alt_jtag_atlantic:*|tck_t_dav}]
|
|
Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|user_saw_rvalid}] -to [get_registers {*|alt_jtag_atlantic:*|rvalid0*}]
|
|
Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|wdata[*]}] -to [get_registers {*}]
|
|
Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|write}] -to [get_registers {*|alt_jtag_atlantic:*|write1*}]
|
|
Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|write_stalled}] -to [get_registers {*|alt_jtag_atlantic:*|t_ena*}]
|
|
Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|write_stalled}] -to [get_registers {*|alt_jtag_atlantic:*|t_pause*}]
|
|
Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|write_valid}]
|
|
Info (332165): Entity alt_sync1r1
|
|
Info (332166): set_false_path -to [get_keepers *alt_sync1r1*ff_meta[*]]
|
|
Info (332165): Entity alt_sync_regs_m2
|
|
Info (332166): set_multicycle_path -to [get_keepers *sync_regs_m*din_meta[*]] 2
|
|
Info (332166): set_multicycle_path -to [get_keepers *sync_regs_m*din_meta[*]] 2
|
|
Info (332166): set_false_path -hold -to [get_keepers *sync_regs_m*din_meta[*]]
|
|
Info (332166): set_false_path -hold -to [get_keepers *sync_regs_m*din_meta[*]]
|
|
Info (332165): Entity alt_xcvr_resync
|
|
Info (332166): set regs [get_registers -nowarn *alt_xcvr_resync*sync_r[0]]; if {[llength [query_collection -report -all $regs]] > 0} {set_false_path -to $regs}
|
|
Info (332165): Entity altera_std_synchronizer
|
|
Info (332166): set_false_path -to [get_keepers {*altera_std_synchronizer:*|din_s1}]
|
|
Info (332165): Entity altpcie_reset_delay_sync
|
|
Info (332166): set_false_path -from [get_fanins -async *app_rstn_altpcie_reset_delay_sync_altpcie_a10_hip_hwtcl*rs_meta[*]] -to [get_keepers *app_rstn_altpcie_reset_delay_sync_altpcie_a10_hip_hwtcl*rs_meta[*]]
|
|
Info (332166): set_false_path -from [get_fanins -async *por_sync_altpcie_reset_delay_sync*rs_meta[*]] -to [get_keepers *por_sync_altpcie_reset_delay_sync*rs_meta[*]]
|
|
Info (332165): Entity altpcie_sc_bitsync
|
|
Info (332166): set_multicycle_path -to [get_keepers *pld_clk_in_use_altpcie_sc_bitsync*altpcie_sc_bitsync_meta_dff[*]] 3
|
|
Info (332166): set_false_path -hold -to [get_keepers *pld_clk_in_use_altpcie_sc_bitsync*altpcie_sc_bitsync_meta_dff[*]]
|
|
Info (332166): set_multicycle_path -to [get_keepers *reset_status_altpcie_sc_bitsync*altpcie_sc_bitsync_meta_dff[*]] 3
|
|
Info (332166): set_false_path -hold -to [get_keepers *reset_status_altpcie_sc_bitsync*altpcie_sc_bitsync_meta_dff[*]]
|
|
Info (332165): Entity dcfifo_tsr1
|
|
Info (332166): set_false_path -from *rdptr_g* -to *ws_dgrp|dffpipe_t5c:dffpipe16|dffe17a*
|
|
Info (332166): set_false_path -from *delayed_wrptr_g* -to *rs_dgwp|dffpipe_r5c:dffpipe12|dffe13a*
|
|
Info (332165): Entity alt_sld_fab_0_altera_a10_xcvr_reset_sequencer_191_yjmdoba
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|
Info (332166): if { [get_collection_size [get_pins -compatibility_mode -nowarn ~ALTERA_CLKUSR~~ibuf|o]] > 0 } { create_clock -name ~ALTERA_CLKUSR~ -period 8 [get_pins -compatibility_mode -nowarn ~ALTERA_CLKUSR~~ibuf|o] }
|
|
Info (19539): Reading the HDL-embedded SDC files elapsed 00:00:27.
|
|
Info (332104): Reading SDC File: '/opt/opae/1.1.2/share/opae/platform/platform_if/rtl/platform_shims/utils/quartus_ip/platform_utils_dc_fifo.sdc'
|
|
Info (332104): Reading SDC File: '/opt/opae/1.1.2/share/opae/platform/platform_if/rtl/platform_shims/utils/quartus_ip/platform_utils_avalon_dc_fifo.sdc'
|
|
Info (332104): Reading SDC File: '/opt/opae/1.1.2/share/opae/platform/platform_if/par/platform_if.sdc'
|
|
Warning (332174): Ignored filter at platform_if.sdc(10): *|platform_shim_ccip|c.ccip_async_shim|error[0] could not be matched with a keeper File: /opt/opae/1.1.2/share/opae/platform/platform_if/par/platform_if.sdc Line: 10
|
|
Warning (332049): Ignored set_false_path at platform_if.sdc(10): Argument <from> is an empty collection File: /opt/opae/1.1.2/share/opae/platform/platform_if/par/platform_if.sdc Line: 10
|
|
Info (332050): set_false_path -from [get_keepers *|platform_shim_ccip|c.ccip_async_shim|error[0]] File: /opt/opae/1.1.2/share/opae/platform/platform_if/par/platform_if.sdc Line: 10
|
|
Warning (332174): Ignored filter at platform_if.sdc(11): *|platform_shim_ccip|c.ccip_async_shim|pwrState[0]* could not be matched with a keeper File: /opt/opae/1.1.2/share/opae/platform/platform_if/par/platform_if.sdc Line: 11
|
|
Warning (332049): Ignored set_false_path at platform_if.sdc(11): Argument <from> is an empty collection File: /opt/opae/1.1.2/share/opae/platform/platform_if/par/platform_if.sdc Line: 11
|
|
Info (332050): set_false_path -from [get_keepers *|platform_shim_ccip|c.ccip_async_shim|pwrState[0]*] File: /opt/opae/1.1.2/share/opae/platform/platform_if/par/platform_if.sdc Line: 11
|
|
Info (332104): Reading SDC File: 'dcp_bbs.sdc'
|
|
Warning (332174): Ignored filter at dcp_bbs.sdc(2863): *aclr_filter*aclr_meta[*] could not be matched with a keeper File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 2863
|
|
Warning (332049): Ignored get_fanins at dcp_bbs.sdc(2863): Argument with value [get_keepers {*aclr_filter*aclr_meta[*]}] contains zero elements File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 2863
|
|
Info (332050): get_fanins -asynch [get_keepers {*aclr_filter*aclr_meta[*]}] File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 2863
|
|
Warning (332049): Ignored set_false_path at dcp_bbs.sdc(2863): Argument <from> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 2863
|
|
Info (332050): set_false_path -from [get_fanins -asynch [get_keepers {*aclr_filter*aclr_meta[*]}]] -to [get_keepers {*aclr_filter*aclr_meta[*]}] File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 2863
|
|
Warning (332049): Ignored set_false_path at dcp_bbs.sdc(2863): Argument <to> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 2863
|
|
Warning (332174): Ignored filter at dcp_bbs.sdc(2864): *flag_mx_meta[*] could not be matched with a keeper File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 2864
|
|
Warning (332049): Ignored set_false_path at dcp_bbs.sdc(2864): Argument <to> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 2864
|
|
Info (332050): set_false_path -to [get_keepers {*flag_mx_meta[*]}] File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 2864
|
|
Warning (332174): Ignored filter at dcp_bbs.sdc(3092): mem|ddr4b|ddr4b|arch|arch_inst|seq_if_inst|afi_cal_success_sync_inst|din_s1|d could not be matched with a pin File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3092
|
|
Warning (332174): Ignored filter at dcp_bbs.sdc(3094): mem|ddr4b|ddr4b|arch|arch_inst|seq_if_inst|afi_cal_fail_sync_inst|din_s1|*data could not be matched with a pin File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3094
|
|
Warning (332174): Ignored filter at dcp_bbs.sdc(3106): mem|ddr4a|ddr4a|arch|arch_inst|seq_if_inst|afi_cal_success_sync_inst|din_s1|d could not be matched with a pin File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3106
|
|
Warning (332174): Ignored filter at dcp_bbs.sdc(3108): mem|ddr4a|ddr4a|arch|arch_inst|seq_if_inst|afi_cal_fail_sync_inst|din_s1|d could not be matched with a pin File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3108
|
|
Warning (332174): Ignored filter at dcp_bbs.sdc(3153): fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g* could not be matched with a keeper File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3153
|
|
Warning (332174): Ignored filter at dcp_bbs.sdc(3153): fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe* could not be matched with a keeper File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3153
|
|
Warning (332049): Ignored set_max_delay at dcp_bbs.sdc(3153): Argument <from> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3153
|
|
Info (332050): set_max_delay -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] 100.000 File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3153
|
|
Warning (332049): Ignored set_max_delay at dcp_bbs.sdc(3153): Argument <to> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3153
|
|
Warning (332174): Ignored filter at dcp_bbs.sdc(3154): fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g* could not be matched with a keeper File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3154
|
|
Warning (332174): Ignored filter at dcp_bbs.sdc(3154): fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe* could not be matched with a keeper File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3154
|
|
Warning (332049): Ignored set_max_delay at dcp_bbs.sdc(3154): Argument <from> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3154
|
|
Info (332050): set_max_delay -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] 100.000 File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3154
|
|
Warning (332049): Ignored set_max_delay at dcp_bbs.sdc(3154): Argument <to> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3154
|
|
Warning (332174): Ignored filter at dcp_bbs.sdc(3155): fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g* could not be matched with a keeper File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3155
|
|
Warning (332174): Ignored filter at dcp_bbs.sdc(3155): fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe* could not be matched with a keeper File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3155
|
|
Warning (332049): Ignored set_max_delay at dcp_bbs.sdc(3155): Argument <from> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3155
|
|
Info (332050): set_max_delay -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] 100.000 File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3155
|
|
Warning (332049): Ignored set_max_delay at dcp_bbs.sdc(3155): Argument <to> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3155
|
|
Warning (332174): Ignored filter at dcp_bbs.sdc(3156): fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g* could not be matched with a keeper File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3156
|
|
Warning (332174): Ignored filter at dcp_bbs.sdc(3156): fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe* could not be matched with a keeper File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3156
|
|
Warning (332049): Ignored set_max_delay at dcp_bbs.sdc(3156): Argument <from> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3156
|
|
Info (332050): set_max_delay -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] 100.000 File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3156
|
|
Warning (332049): Ignored set_max_delay at dcp_bbs.sdc(3156): Argument <to> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3156
|
|
Warning (332174): Ignored filter at dcp_bbs.sdc(3157): fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g* could not be matched with a keeper File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3157
|
|
Warning (332174): Ignored filter at dcp_bbs.sdc(3157): fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe* could not be matched with a keeper File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3157
|
|
Warning (332049): Ignored set_max_delay at dcp_bbs.sdc(3157): Argument <from> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3157
|
|
Info (332050): set_max_delay -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] 100.000 File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3157
|
|
Warning (332049): Ignored set_max_delay at dcp_bbs.sdc(3157): Argument <to> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3157
|
|
Warning (332174): Ignored filter at dcp_bbs.sdc(3158): fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g* could not be matched with a keeper File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3158
|
|
Warning (332174): Ignored filter at dcp_bbs.sdc(3158): fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe* could not be matched with a keeper File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3158
|
|
Warning (332049): Ignored set_max_delay at dcp_bbs.sdc(3158): Argument <from> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3158
|
|
Info (332050): set_max_delay -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] 100.000 File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3158
|
|
Warning (332049): Ignored set_max_delay at dcp_bbs.sdc(3158): Argument <to> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3158
|
|
Warning (332174): Ignored filter at dcp_bbs.sdc(3159): fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g* could not be matched with a keeper File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3159
|
|
Warning (332174): Ignored filter at dcp_bbs.sdc(3159): fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe* could not be matched with a keeper File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3159
|
|
Warning (332049): Ignored set_max_delay at dcp_bbs.sdc(3159): Argument <from> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3159
|
|
Info (332050): set_max_delay -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] 100.000 File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3159
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|
Warning (332049): Ignored set_max_delay at dcp_bbs.sdc(3159): Argument <to> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3159
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|
Warning (332174): Ignored filter at dcp_bbs.sdc(3160): fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g* could not be matched with a keeper File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3160
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|
Warning (332174): Ignored filter at dcp_bbs.sdc(3160): fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe* could not be matched with a keeper File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3160
|
|
Warning (332049): Ignored set_max_delay at dcp_bbs.sdc(3160): Argument <from> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3160
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|
Info (332050): set_max_delay -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] 100.000 File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3160
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|
Warning (332049): Ignored set_max_delay at dcp_bbs.sdc(3160): Argument <to> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3160
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|
Warning (332174): Ignored filter at dcp_bbs.sdc(3161): fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|SoftReset_mem could not be matched with a keeper File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3161
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|
Warning (332174): Ignored filter at dcp_bbs.sdc(3161): fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4*_mem_if|ddr_reset_sync|resync_chains[0].synchronizer_nocut|*|clrn could not be matched with a pin File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3161
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|
Warning (332049): Ignored set_max_delay at dcp_bbs.sdc(3161): Argument <from> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3161
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|
Info (332050): set_max_delay -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|SoftReset_mem}] -to [get_pins {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4*_mem_if|ddr_reset_sync|resync_chains[0].synchronizer_nocut|*|clrn}] 100.000 File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3161
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|
Warning (332049): Ignored set_max_delay at dcp_bbs.sdc(3161): Argument <to> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3161
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|
Warning (332174): Ignored filter at dcp_bbs.sdc(3162): fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4*_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|wraclr|*|clrn could not be matched with a pin File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3162
|
|
Warning (332049): Ignored set_max_delay at dcp_bbs.sdc(3162): Argument <from> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3162
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|
Info (332050): set_max_delay -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|SoftReset_mem}] -to [get_pins {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4*_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|wraclr|*|clrn}] 100.000 File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3162
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|
Warning (332049): Ignored set_max_delay at dcp_bbs.sdc(3162): Argument <to> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3162
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|
Warning (332174): Ignored filter at dcp_bbs.sdc(3163): fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4*_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|rdaclr|*|clrn could not be matched with a pin File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3163
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|
Warning (332049): Ignored set_max_delay at dcp_bbs.sdc(3163): Argument <from> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3163
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|
Info (332050): set_max_delay -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|SoftReset_mem}] -to [get_pins {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4*_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|rdaclr|*|clrn}] 100.000 File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3163
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|
Warning (332049): Ignored set_max_delay at dcp_bbs.sdc(3163): Argument <to> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3163
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|
Warning (332174): Ignored filter at dcp_bbs.sdc(3164): fpga_top|inst_green_bs|inst_ccip_std_afu|inst_green_ccip_interface_reg|pck_cp2af_softReset_T0_q could not be matched with a keeper File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3164
|
|
Warning (332174): Ignored filter at dcp_bbs.sdc(3164): fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|Clk_100_reset_sync|resync_chains[0].synchronizer_nocut|*|clrn could not be matched with a pin File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3164
|
|
Warning (332049): Ignored set_max_delay at dcp_bbs.sdc(3164): Argument <from> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3164
|
|
Info (332050): set_max_delay -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|inst_green_ccip_interface_reg|pck_cp2af_softReset_T0_q}] -to [get_pins {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|Clk_100_reset_sync|resync_chains[0].synchronizer_nocut|*|clrn}] 100.000 File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3164
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|
Warning (332049): Ignored set_max_delay at dcp_bbs.sdc(3164): Argument <to> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3164
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|
Warning (332049): Ignored set_min_delay at dcp_bbs.sdc(3200): Argument <from> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3200
|
|
Info (332050): set_min_delay -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -100.000 File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3200
|
|
Warning (332049): Ignored set_min_delay at dcp_bbs.sdc(3200): Argument <to> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3200
|
|
Warning (332049): Ignored set_min_delay at dcp_bbs.sdc(3201): Argument <from> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3201
|
|
Info (332050): set_min_delay -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -100.000 File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3201
|
|
Warning (332049): Ignored set_min_delay at dcp_bbs.sdc(3201): Argument <to> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3201
|
|
Warning (332049): Ignored set_min_delay at dcp_bbs.sdc(3202): Argument <from> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3202
|
|
Info (332050): set_min_delay -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -100.000 File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3202
|
|
Warning (332049): Ignored set_min_delay at dcp_bbs.sdc(3202): Argument <to> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3202
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|
Warning (332049): Ignored set_min_delay at dcp_bbs.sdc(3203): Argument <from> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3203
|
|
Info (332050): set_min_delay -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -100.000 File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3203
|
|
Warning (332049): Ignored set_min_delay at dcp_bbs.sdc(3203): Argument <to> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3203
|
|
Warning (332049): Ignored set_min_delay at dcp_bbs.sdc(3204): Argument <from> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3204
|
|
Info (332050): set_min_delay -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -100.000 File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3204
|
|
Warning (332049): Ignored set_min_delay at dcp_bbs.sdc(3204): Argument <to> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3204
|
|
Warning (332049): Ignored set_min_delay at dcp_bbs.sdc(3205): Argument <from> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3205
|
|
Info (332050): set_min_delay -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -100.000 File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3205
|
|
Warning (332049): Ignored set_min_delay at dcp_bbs.sdc(3205): Argument <to> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3205
|
|
Warning (332049): Ignored set_min_delay at dcp_bbs.sdc(3206): Argument <from> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3206
|
|
Info (332050): set_min_delay -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -100.000 File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3206
|
|
Warning (332049): Ignored set_min_delay at dcp_bbs.sdc(3206): Argument <to> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3206
|
|
Warning (332049): Ignored set_min_delay at dcp_bbs.sdc(3207): Argument <from> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3207
|
|
Info (332050): set_min_delay -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -100.000 File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3207
|
|
Warning (332049): Ignored set_min_delay at dcp_bbs.sdc(3207): Argument <to> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3207
|
|
Warning (332049): Ignored set_min_delay at dcp_bbs.sdc(3208): Argument <from> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3208
|
|
Info (332050): set_min_delay -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|SoftReset_mem}] -to [get_pins {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4*_mem_if|ddr_reset_sync|resync_chains[0].synchronizer_nocut|*|clrn}] -100.000 File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3208
|
|
Warning (332049): Ignored set_min_delay at dcp_bbs.sdc(3208): Argument <to> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3208
|
|
Warning (332049): Ignored set_min_delay at dcp_bbs.sdc(3209): Argument <from> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3209
|
|
Info (332050): set_min_delay -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|SoftReset_mem}] -to [get_pins {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4*_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|wraclr|*|clrn}] -100.000 File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3209
|
|
Warning (332049): Ignored set_min_delay at dcp_bbs.sdc(3209): Argument <to> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3209
|
|
Warning (332049): Ignored set_min_delay at dcp_bbs.sdc(3210): Argument <from> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3210
|
|
Info (332050): set_min_delay -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|SoftReset_mem}] -to [get_pins {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4*_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|rdaclr|*|clrn}] -100.000 File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3210
|
|
Warning (332049): Ignored set_min_delay at dcp_bbs.sdc(3210): Argument <to> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3210
|
|
Warning (332049): Ignored set_min_delay at dcp_bbs.sdc(3211): Argument <from> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3211
|
|
Info (332050): set_min_delay -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|inst_green_ccip_interface_reg|pck_cp2af_softReset_T0_q}] -to [get_pins {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|Clk_100_reset_sync|resync_chains[0].synchronizer_nocut|*|clrn}] -100.000 File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3211
|
|
Warning (332049): Ignored set_min_delay at dcp_bbs.sdc(3211): Argument <to> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3211
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|
Warning (332049): Ignored set_net_delay at dcp_bbs.sdc(3252): argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] contains zero elements File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3252
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Info (332050): set_net_delay -max -value_multiplier 0.800 -get_value_from_clock_period dst_clock_period -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3252
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Warning (332049): Ignored set_net_delay at dcp_bbs.sdc(3253): argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] contains zero elements File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3253
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Info (332050): set_net_delay -max -value_multiplier 0.800 -get_value_from_clock_period dst_clock_period -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3253
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Warning (332049): Ignored set_net_delay at dcp_bbs.sdc(3254): argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] contains zero elements File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3254
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Info (332050): set_net_delay -max -value_multiplier 0.800 -get_value_from_clock_period dst_clock_period -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3254
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Warning (332049): Ignored set_net_delay at dcp_bbs.sdc(3255): argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] contains zero elements File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3255
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Info (332050): set_net_delay -max -value_multiplier 0.800 -get_value_from_clock_period dst_clock_period -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3255
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Warning (332049): Ignored set_net_delay at dcp_bbs.sdc(3256): argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] contains zero elements File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3256
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Info (332050): set_net_delay -max -value_multiplier 0.800 -get_value_from_clock_period dst_clock_period -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3256
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Warning (332049): Ignored set_net_delay at dcp_bbs.sdc(3257): argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] contains zero elements File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3257
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Info (332050): set_net_delay -max -value_multiplier 0.800 -get_value_from_clock_period dst_clock_period -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3257
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Warning (332049): Ignored set_net_delay at dcp_bbs.sdc(3258): argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] contains zero elements File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3258
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Info (332050): set_net_delay -max -value_multiplier 0.800 -get_value_from_clock_period dst_clock_period -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3258
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Warning (332049): Ignored set_net_delay at dcp_bbs.sdc(3259): argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] contains zero elements File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3259
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Info (332050): set_net_delay -max -value_multiplier 0.800 -get_value_from_clock_period dst_clock_period -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3259
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Warning (332049): Ignored set_net_delay at dcp_bbs.sdc(3260): argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] contains zero elements File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3260
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Info (332050): set_net_delay -max -value_multiplier 0.800 -get_value_from_clock_period dst_clock_period -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3260
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Warning (332049): Ignored set_net_delay at dcp_bbs.sdc(3261): argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] contains zero elements File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3261
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Info (332050): set_net_delay -max -value_multiplier 0.800 -get_value_from_clock_period dst_clock_period -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3261
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Warning (332049): Ignored set_net_delay at dcp_bbs.sdc(3262): argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] contains zero elements File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3262
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Info (332050): set_net_delay -max -value_multiplier 0.800 -get_value_from_clock_period dst_clock_period -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3262
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Warning (332049): Ignored set_net_delay at dcp_bbs.sdc(3263): argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] contains zero elements File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3263
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Info (332050): set_net_delay -max -value_multiplier 0.800 -get_value_from_clock_period dst_clock_period -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3263
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Warning (332049): Ignored set_net_delay at dcp_bbs.sdc(3264): argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] contains zero elements File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3264
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Info (332050): set_net_delay -max -value_multiplier 0.800 -get_value_from_clock_period dst_clock_period -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3264
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Warning (332049): Ignored set_net_delay at dcp_bbs.sdc(3265): argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] contains zero elements File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3265
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Info (332050): set_net_delay -max -value_multiplier 0.800 -get_value_from_clock_period dst_clock_period -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3265
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Warning (332049): Ignored set_net_delay at dcp_bbs.sdc(3266): argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] contains zero elements File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3266
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Info (332050): set_net_delay -max -value_multiplier 0.800 -get_value_from_clock_period dst_clock_period -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3266
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Warning (332049): Ignored set_net_delay at dcp_bbs.sdc(3267): argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] contains zero elements File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3267
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Info (332050): set_net_delay -max -value_multiplier 0.800 -get_value_from_clock_period dst_clock_period -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3267
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Warning (332049): Ignored set_max_skew at dcp_bbs.sdc(3316): Argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] contains zero elements File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3316
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Info (332050): set_max_skew -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3316
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Warning (332049): Ignored set_max_skew at dcp_bbs.sdc(3316): Argument -to with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] contains zero elements File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3316
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Warning (332049): Ignored set_max_skew at dcp_bbs.sdc(3317): Argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] contains zero elements File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3317
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Info (332050): set_max_skew -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3317
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Warning (332049): Ignored set_max_skew at dcp_bbs.sdc(3317): Argument -to with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] contains zero elements File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3317
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Warning (332049): Ignored set_max_skew at dcp_bbs.sdc(3318): Argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] contains zero elements File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3318
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Info (332050): set_max_skew -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3318
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Warning (332049): Ignored set_max_skew at dcp_bbs.sdc(3318): Argument -to with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] contains zero elements File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3318
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Warning (332049): Ignored set_max_skew at dcp_bbs.sdc(3319): Argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] contains zero elements File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3319
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Info (332050): set_max_skew -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3319
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Warning (332049): Ignored set_max_skew at dcp_bbs.sdc(3319): Argument -to with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] contains zero elements File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3319
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Warning (332049): Ignored set_max_skew at dcp_bbs.sdc(3320): Argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] contains zero elements File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3320
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|
Info (332050): set_max_skew -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3320
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Warning (332049): Ignored set_max_skew at dcp_bbs.sdc(3320): Argument -to with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] contains zero elements File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3320
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Warning (332049): Ignored set_max_skew at dcp_bbs.sdc(3321): Argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] contains zero elements File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3321
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Info (332050): set_max_skew -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3321
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Warning (332049): Ignored set_max_skew at dcp_bbs.sdc(3321): Argument -to with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] contains zero elements File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3321
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Warning (332049): Ignored set_max_skew at dcp_bbs.sdc(3322): Argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] contains zero elements File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3322
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Info (332050): set_max_skew -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3322
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Warning (332049): Ignored set_max_skew at dcp_bbs.sdc(3322): Argument -to with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] contains zero elements File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3322
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Warning (332049): Ignored set_max_skew at dcp_bbs.sdc(3323): Argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] contains zero elements File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3323
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|
Info (332050): set_max_skew -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3323
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Warning (332049): Ignored set_max_skew at dcp_bbs.sdc(3323): Argument -to with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] contains zero elements File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3323
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Warning (332049): Ignored set_max_skew at dcp_bbs.sdc(3324): Argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|SoftReset_mem}] contains zero elements File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3324
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Info (332050): set_max_skew -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|SoftReset_mem}] -to [get_pins {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4*_mem_if|ddr_reset_sync|resync_chains[0].synchronizer_nocut|*|clrn}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3324
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Warning (332049): Ignored set_max_skew at dcp_bbs.sdc(3324): Argument -to with value [get_pins {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4*_mem_if|ddr_reset_sync|resync_chains[0].synchronizer_nocut|*|clrn}] contains zero elements File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3324
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Warning (332049): Ignored set_max_skew at dcp_bbs.sdc(3325): Argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|SoftReset_mem}] contains zero elements File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3325
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Info (332050): set_max_skew -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|SoftReset_mem}] -to [get_pins {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4*_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|wraclr|*|clrn}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3325
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Warning (332049): Ignored set_max_skew at dcp_bbs.sdc(3325): Argument -to with value [get_pins {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4*_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|wraclr|*|clrn}] contains zero elements File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3325
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Warning (332049): Ignored set_max_skew at dcp_bbs.sdc(3326): Argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|SoftReset_mem}] contains zero elements File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3326
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Info (332050): set_max_skew -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|SoftReset_mem}] -to [get_pins {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4*_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|rdaclr|*|clrn}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3326
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Warning (332049): Ignored set_max_skew at dcp_bbs.sdc(3326): Argument -to with value [get_pins {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4*_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|rdaclr|*|clrn}] contains zero elements File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3326
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Warning (332049): Ignored set_max_skew at dcp_bbs.sdc(3327): Argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|inst_green_ccip_interface_reg|pck_cp2af_softReset_T0_q}] contains zero elements File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3327
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Info (332050): set_max_skew -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|inst_green_ccip_interface_reg|pck_cp2af_softReset_T0_q}] -to [get_pins {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|Clk_100_reset_sync|resync_chains[0].synchronizer_nocut|*|clrn}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3327
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Warning (332049): Ignored set_max_skew at dcp_bbs.sdc(3327): Argument -to with value [get_pins {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|Clk_100_reset_sync|resync_chains[0].synchronizer_nocut|*|clrn}] contains zero elements File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3327
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Info (332104): Reading SDC File: 'platform/green_bs.sdc'
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Info (332104): Reading SDC File: 'dcp_user_clocks.sdc'
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Info: Target user clock high: auto (220)
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Info: Target user clock low: auto (110.0)
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Warning (332043): Overwriting existing clock: fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk0
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Warning (332043): Overwriting existing clock: fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk1
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Info (332104): Reading SDC File: '../design/bmc_mailbox/bmc_mailbox/altera_reset_controller_191/synth/altera_reset_controller.sdc'
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Info (332104): Reading SDC File: '../design/hssi_eth/e10/address_decoder/address_decode/altera_reset_controller_191/synth/altera_reset_controller.sdc'
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Info (332104): Reading SDC File: '../design/hssi_eth/e10/address_decoder/ip/address_decode/address_decode_master_0/altera_reset_controller_191/synth/altera_reset_controller.sdc'
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Info (332104): Reading SDC File: '../design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_reset_controller_191/synth/altera_reset_controller.sdc'
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Info (332104): Reading SDC File: '../design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_reset_controller_191/synth/altera_reset_controller.sdc'
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Info (332104): Reading SDC File: '../design/tcm/ip/tcm/tcm_generic_quad_spi_controller2_0/altera_reset_controller_191/synth/altera_reset_controller.sdc'
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Info (332104): Reading SDC File: '../design/tcm/tcm/altera_reset_controller_191/synth/altera_reset_controller.sdc'
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Info (332104): Reading SDC File: '../design/fabric/lib/async_C0Rx_fifo/fifo_191/synth/async_C0Rx_fifo_fifo_191_wkfew6y.sdc'
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Info (332104): Reading SDC File: '../design/fabric/lib/async_C0Tx_fifo/fifo_191/synth/async_C0Tx_fifo_fifo_191_zdnyzji.sdc'
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Info (332104): Reading SDC File: '../design/fabric/lib/async_C1Rx_fifo/fifo_191/synth/async_C1Rx_fifo_fifo_191_fh7xhkq.sdc'
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Info (332104): Reading SDC File: '../design/fabric/lib/async_C1Tx_fifo/fifo_191/synth/async_C1Tx_fifo_fifo_191_6m7yegq.sdc'
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Info (332104): Reading SDC File: '../design/fabric/lib/async_CfgTx_fifo/fifo_191/synth/async_CfgTx_fifo_fifo_191_aug4t4i.sdc'
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Info (332104): Reading SDC File: '../design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc'
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Info (332151): Clock uncertainty is not calculated until you update the timing netlist.
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(633): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_A[0]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 633
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Info (332050): set_output_delay -clock $pins(ref_clock_name) 0 $pins(ac_sync) File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 633
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(633): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_A[1]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 633
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(633): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_A[2]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 633
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(633): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_A[3]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 633
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(633): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_A[4]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 633
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(633): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_A[5]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 633
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(633): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_A[6]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 633
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(633): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_A[7]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 633
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(633): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_A[8]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 633
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(633): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_A[9]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 633
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(633): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_A[10]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 633
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(633): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_A[11]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 633
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(633): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_A[12]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 633
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(633): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_A[13]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 633
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(633): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_A[14]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 633
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(633): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_A[15]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 633
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(633): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_A[16]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 633
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(633): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_ACT_L". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 633
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(633): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_BA[0]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 633
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(633): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_BA[1]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 633
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(633): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_BG". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 633
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(633): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_CKE". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 633
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(633): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_CS_L". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 633
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(633): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_ODT". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 633
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(633): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_PAR". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 633
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Warning (332043): Overwriting existing clock: DDR4A_DQS_P[0]_IN
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Warning (332043): Overwriting existing clock: DDR4A_DQS_P[1]_IN
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Warning (332043): Overwriting existing clock: DDR4A_DQS_P[2]_IN
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Warning (332043): Overwriting existing clock: DDR4A_DQS_P[3]_IN
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Warning (332043): Overwriting existing clock: DDR4A_DQS_P[4]_IN
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Warning (332043): Overwriting existing clock: DDR4A_DQS_P[5]_IN
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Warning (332043): Overwriting existing clock: DDR4A_DQS_P[6]_IN
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Warning (332043): Overwriting existing clock: DDR4A_DQS_P[7]_IN
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(795): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[0]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 795
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Info (332050): set_output_delay -clock $pins(ref_clock_name) 0 $pins(wdata) File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 795
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(795): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[1]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 795
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(795): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[2]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 795
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(795): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[3]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 795
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(795): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[4]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 795
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(795): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[5]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 795
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(795): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[6]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 795
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(795): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[7]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 795
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(795): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[8]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 795
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(795): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[9]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 795
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(795): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[10]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 795
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(795): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[11]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 795
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(795): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[12]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 795
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(795): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[13]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 795
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(795): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[14]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 795
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(795): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[15]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 795
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(795): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[16]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 795
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(795): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[17]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 795
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(795): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[18]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 795
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(795): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[19]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 795
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(795): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[20]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 795
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(795): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[21]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 795
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(795): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[22]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 795
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(795): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[23]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 795
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(795): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[24]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 795
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(795): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[25]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 795
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(795): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[26]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 795
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(795): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[27]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 795
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(795): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[28]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 795
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(795): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[29]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 795
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(795): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[30]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 795
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(795): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[31]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 795
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(795): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[32]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 795
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(795): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[33]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 795
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(795): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[34]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 795
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(795): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[35]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 795
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(795): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[36]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 795
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(795): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[37]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 795
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(795): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[38]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 795
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(795): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[39]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 795
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(795): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[40]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 795
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(795): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[41]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 795
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(795): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[42]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 795
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(795): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[43]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 795
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(795): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[44]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 795
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(795): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[45]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 795
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(795): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[46]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 795
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(795): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[47]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 795
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(795): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[48]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 795
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(795): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[49]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 795
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(795): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[50]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 795
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(795): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[51]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 795
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(795): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[52]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 795
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(795): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[53]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 795
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(795): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[54]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 795
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(795): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[55]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 795
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(795): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[56]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 795
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(795): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[57]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 795
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(795): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[58]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 795
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(795): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[59]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 795
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(795): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[60]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 795
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(795): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[61]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 795
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(795): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[62]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 795
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(795): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[63]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 795
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(796): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[0]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 796
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Info (332050): set_input_delay -clock $pins(ref_clock_name) 0 $pins(rdata) File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 796
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(796): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[1]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 796
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(796): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[2]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 796
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(796): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[3]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 796
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(796): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[4]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 796
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(796): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[5]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 796
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(796): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[6]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 796
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(796): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[7]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 796
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(796): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[8]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 796
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(796): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[9]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 796
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(796): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[10]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 796
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(796): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[11]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 796
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(796): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[12]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 796
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(796): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[13]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 796
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(796): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[14]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 796
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(796): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[15]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 796
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(796): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[16]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 796
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(796): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[17]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 796
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(796): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[18]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 796
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(796): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[19]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 796
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(796): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[20]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 796
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(796): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[21]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 796
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(796): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[22]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 796
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(796): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[23]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 796
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(796): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[24]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 796
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(796): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[25]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 796
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(796): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[26]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 796
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(796): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[27]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 796
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(796): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[28]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 796
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(796): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[29]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 796
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(796): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[30]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 796
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(796): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[31]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 796
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(796): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[32]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 796
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(796): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[33]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 796
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(796): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[34]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 796
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(796): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[35]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 796
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(796): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[36]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 796
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(796): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[37]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 796
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(796): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[38]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 796
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(796): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[39]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 796
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(796): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[40]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 796
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(796): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[41]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 796
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(796): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[42]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 796
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(796): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[43]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 796
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(796): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[44]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 796
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(796): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[45]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 796
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(796): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[46]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 796
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(796): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[47]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 796
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(796): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[48]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 796
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(796): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[49]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 796
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(796): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[50]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 796
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(796): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[51]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 796
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(796): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[52]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 796
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(796): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[53]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 796
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(796): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[54]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 796
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(796): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[55]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 796
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(796): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[56]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 796
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(796): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[57]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 796
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(796): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[58]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 796
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(796): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[59]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 796
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(796): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[60]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 796
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(796): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[61]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 796
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(796): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[62]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 796
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(796): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQ[63]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 796
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(804): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DBI_L[0]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 804
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Info (332050): set_output_delay -clock $pins(ref_clock_name) 0 $pins(dbi) File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 804
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(804): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DBI_L[1]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 804
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(804): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DBI_L[2]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 804
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(804): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DBI_L[3]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 804
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(804): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DBI_L[4]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 804
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(804): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DBI_L[5]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 804
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(804): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DBI_L[6]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 804
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(804): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DBI_L[7]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 804
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(805): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DBI_L[0]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 805
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Info (332050): set_input_delay -clock $pins(ref_clock_name) 0 $pins(dbi) File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 805
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(805): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DBI_L[1]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 805
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(805): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DBI_L[2]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 805
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(805): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DBI_L[3]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 805
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(805): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DBI_L[4]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 805
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(805): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DBI_L[5]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 805
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(805): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DBI_L[6]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 805
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(805): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DBI_L[7]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 805
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(808): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQS_P[0]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 808
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Info (332050): set_output_delay -clock $pins(ref_clock_name) 0 $pins(wclk) File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 808
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(808): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQS_P[1]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 808
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(808): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQS_P[2]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 808
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(808): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQS_P[3]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 808
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(808): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQS_P[4]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 808
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(808): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQS_P[5]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 808
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(808): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQS_P[6]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 808
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(808): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQS_P[7]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 808
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(811): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQS_N[0]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 811
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Info (332050): set_output_delay -clock $pins(ref_clock_name) 0 $pins(wclk_n) File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 811
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(811): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQS_N[1]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 811
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(811): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQS_N[2]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 811
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(811): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQS_N[3]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 811
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(811): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQS_N[4]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 811
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(811): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQS_N[5]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 811
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(811): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQS_N[6]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 811
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(811): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_DQS_N[7]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 811
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(834): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_RESET_L". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 834
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Info (332050): set_output_delay -clock $pins(ref_clock_name) 0 $ac_async File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 834
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc(831): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4A_ALERT_L". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 831
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Info (332050): set_input_delay -clock $pins(ref_clock_name) 0 $ac_async File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4a/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4a_altera_emif_arch_nf_191_4vzb73y.sdc Line: 831
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Info (332104): Reading SDC File: '../design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc'
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Info (332151): Clock uncertainty is not calculated until you update the timing netlist.
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(633): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_A[0]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 633
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Info (332050): set_output_delay -clock $pins(ref_clock_name) 0 $pins(ac_sync) File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 633
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(633): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_A[1]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 633
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(633): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_A[2]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 633
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(633): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_A[3]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 633
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(633): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_A[4]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 633
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(633): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_A[5]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 633
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(633): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_A[6]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 633
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(633): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_A[7]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 633
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(633): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_A[8]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 633
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(633): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_A[9]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 633
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(633): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_A[10]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 633
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(633): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_A[11]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 633
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(633): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_A[12]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 633
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(633): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_A[13]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 633
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(633): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_A[14]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 633
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(633): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_A[15]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 633
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(633): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_A[16]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 633
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(633): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_ACT_L". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 633
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(633): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_BA[0]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 633
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(633): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_BA[1]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 633
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(633): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_BG". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 633
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(633): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_CKE". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 633
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(633): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_CS_L". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 633
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(633): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_ODT". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 633
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(633): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_PAR". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 633
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Warning (332043): Overwriting existing clock: DDR4B_DQS_P[0]_IN
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Warning (332043): Overwriting existing clock: DDR4B_DQS_P[1]_IN
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Warning (332043): Overwriting existing clock: DDR4B_DQS_P[2]_IN
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Warning (332043): Overwriting existing clock: DDR4B_DQS_P[3]_IN
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Warning (332043): Overwriting existing clock: DDR4B_DQS_P[4]_IN
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Warning (332043): Overwriting existing clock: DDR4B_DQS_P[5]_IN
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Warning (332043): Overwriting existing clock: DDR4B_DQS_P[6]_IN
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Warning (332043): Overwriting existing clock: DDR4B_DQS_P[7]_IN
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(795): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[0]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 795
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Info (332050): set_output_delay -clock $pins(ref_clock_name) 0 $pins(wdata) File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 795
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(795): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[1]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 795
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(795): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[2]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 795
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(795): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[3]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 795
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(795): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[4]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 795
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(795): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[5]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 795
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(795): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[6]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 795
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(795): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[7]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 795
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(795): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[8]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 795
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(795): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[9]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 795
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(795): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[10]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 795
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(795): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[11]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 795
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(795): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[12]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 795
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(795): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[13]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 795
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(795): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[14]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 795
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(795): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[15]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 795
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(795): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[16]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 795
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(795): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[17]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 795
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(795): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[18]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 795
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(795): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[19]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 795
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(795): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[20]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 795
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(795): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[21]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 795
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(795): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[22]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 795
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(795): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[23]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 795
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(795): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[24]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 795
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(795): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[25]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 795
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(795): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[26]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 795
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(795): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[27]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 795
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(795): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[28]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 795
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(795): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[29]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 795
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(795): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[30]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 795
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(795): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[31]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 795
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(795): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[32]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 795
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(795): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[33]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 795
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(795): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[34]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 795
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(795): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[35]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 795
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(795): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[36]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 795
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(795): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[37]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 795
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(795): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[38]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 795
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(795): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[39]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 795
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(795): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[40]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 795
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(795): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[41]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 795
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(795): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[42]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 795
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(795): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[43]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 795
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(795): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[44]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 795
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(795): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[45]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 795
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(795): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[46]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 795
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(795): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[47]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 795
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(795): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[48]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 795
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(795): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[49]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 795
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(795): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[50]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 795
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(795): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[51]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 795
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(795): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[52]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 795
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(795): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[53]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 795
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(795): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[54]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 795
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(795): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[55]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 795
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(795): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[56]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 795
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(795): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[57]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 795
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(795): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[58]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 795
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(795): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[59]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 795
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(795): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[60]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 795
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(795): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[61]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 795
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(795): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[62]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 795
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(795): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[63]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 795
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(796): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[0]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 796
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Info (332050): set_input_delay -clock $pins(ref_clock_name) 0 $pins(rdata) File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 796
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(796): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[1]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 796
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(796): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[2]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 796
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(796): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[3]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 796
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(796): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[4]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 796
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(796): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[5]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 796
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(796): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[6]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 796
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(796): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[7]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 796
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(796): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[8]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 796
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(796): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[9]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 796
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(796): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[10]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 796
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(796): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[11]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 796
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(796): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[12]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 796
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(796): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[13]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 796
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(796): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[14]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 796
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(796): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[15]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 796
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(796): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[16]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 796
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(796): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[17]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 796
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(796): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[18]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 796
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(796): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[19]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 796
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(796): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[20]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 796
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(796): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[21]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 796
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(796): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[22]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 796
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(796): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[23]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 796
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(796): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[24]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 796
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(796): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[25]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 796
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(796): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[26]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 796
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(796): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[27]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 796
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(796): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[28]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 796
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(796): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[29]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 796
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(796): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[30]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 796
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(796): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[31]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 796
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(796): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[32]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 796
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(796): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[33]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 796
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(796): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[34]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 796
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(796): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[35]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 796
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(796): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[36]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 796
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(796): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[37]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 796
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(796): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[38]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 796
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(796): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[39]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 796
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(796): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[40]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 796
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(796): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[41]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 796
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(796): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[42]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 796
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(796): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[43]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 796
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(796): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[44]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 796
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(796): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[45]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 796
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(796): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[46]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 796
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(796): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[47]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 796
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(796): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[48]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 796
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(796): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[49]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 796
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(796): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[50]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 796
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(796): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[51]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 796
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(796): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[52]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 796
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(796): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[53]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 796
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(796): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[54]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 796
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(796): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[55]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 796
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(796): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[56]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 796
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(796): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[57]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 796
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(796): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[58]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 796
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(796): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[59]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 796
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(796): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[60]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 796
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(796): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[61]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 796
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(796): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[62]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 796
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(796): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQ[63]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 796
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(804): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DBI_L[0]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 804
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Info (332050): set_output_delay -clock $pins(ref_clock_name) 0 $pins(dbi) File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 804
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(804): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DBI_L[1]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 804
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(804): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DBI_L[2]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 804
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(804): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DBI_L[3]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 804
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(804): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DBI_L[4]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 804
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(804): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DBI_L[5]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 804
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(804): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DBI_L[6]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 804
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(804): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DBI_L[7]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 804
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(805): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DBI_L[0]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 805
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Info (332050): set_input_delay -clock $pins(ref_clock_name) 0 $pins(dbi) File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 805
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(805): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DBI_L[1]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 805
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(805): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DBI_L[2]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 805
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(805): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DBI_L[3]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 805
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(805): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DBI_L[4]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 805
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(805): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DBI_L[5]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 805
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(805): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DBI_L[6]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 805
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(805): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DBI_L[7]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 805
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(808): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQS_P[0]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 808
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Info (332050): set_output_delay -clock $pins(ref_clock_name) 0 $pins(wclk) File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 808
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(808): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQS_P[1]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 808
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(808): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQS_P[2]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 808
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(808): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQS_P[3]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 808
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(808): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQS_P[4]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 808
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(808): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQS_P[5]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 808
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(808): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQS_P[6]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 808
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(808): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQS_P[7]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 808
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(811): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQS_N[0]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 811
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Info (332050): set_output_delay -clock $pins(ref_clock_name) 0 $pins(wclk_n) File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 811
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(811): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQS_N[1]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 811
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(811): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQS_N[2]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 811
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(811): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQS_N[3]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 811
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(811): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQS_N[4]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 811
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(811): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQS_N[5]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 811
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(811): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQS_N[6]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 811
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(811): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_DQS_N[7]". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 811
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Warning (332054): Assignment set_output_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(834): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_RESET_L". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 834
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Info (332050): set_output_delay -clock $pins(ref_clock_name) 0 $ac_async File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 834
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Warning (332054): Assignment set_input_delay is accepted but has some problems at emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc(831): Set_input_delay/set_output_delay has replaced one or more delays on port "DDR4B_ALERT_L". Please use -add_delay option if you meant to add additional constraints. File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 831
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Info (332050): set_input_delay -clock $pins(ref_clock_name) 0 $ac_async File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/design/memory/emif_ddr4_rc/ip/emif_ddr4/emif_ddr4_ddr4b/altera_emif_arch_nf_191/synth/emif_ddr4_ddr4b_altera_emif_arch_nf_191_4xsx6xa.sdc Line: 831
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Info (332104): Reading SDC File: '../design/interrupts/msix_dcfifo/fifo_191/synth/msix_dcfifo_fifo_191_abngbqq.sdc'
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Info (332104): Reading SDC File: '../design/tcm/tcm/altera_avalon_st_handshake_clock_crosser_191/synth/altera_avalon_st_handshake_clock_crosser.sdc'
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Info (332104): Reading SDC File: '../design/tcm/ip/tcm/tcm_mm_clock_crossing_bridge_0/altera_avalon_mm_clock_crossing_bridge_191/synth/altera_avalon_dc_fifo.sdc'
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Info (332104): Reading SDC File: '../design/tcm/ip/tcm/tcm_nios2_gen2_0/altera_nios2_gen2_unit_191/synth/tcm_nios2_gen2_0_altera_nios2_gen2_unit_191_dbuc52a.sdc'
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Critical Warning (19294): Synopsys Design Constraints File file not found for instance '': '/nfs/site/disks/pac_build_1/psgpacbuild/SC/adapt/nightly/19.1/367/l64/work/platform/dcp_1.0-rc/build/qdb/_compiler/dcp/_flat/19.2.0/partitioned/1/.temp/sld_fabrics/ipgen/alt_sld_fab_0/alt_sld_fab_0/altera_avalon_dc_fifo_191/synth/alt_sld_fab_0_altera_avalon_dc_fifo_191_27jzy3q.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
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Critical Warning (19294): Synopsys Design Constraints File file not found for instance '': '/nfs/site/disks/pac_build_1/psgpacbuild/SC/adapt/nightly/19.1/367/l64/work/platform/dcp_1.0-rc/build/qdb/_compiler/dcp/_flat/19.2.0/partitioned/1/.temp/sld_fabrics/ipgen/alt_sld_fab_0/alt_sld_fab_0/altera_jtag_dc_streaming_191/synth/altera_avalon_st_jtag_interface.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
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Critical Warning (19294): Synopsys Design Constraints File file not found for instance '': '/nfs/site/disks/pac_build_1/psgpacbuild/SC/adapt/nightly/19.1/367/l64/work/platform/dcp_1.0-rc/build/qdb/_compiler/dcp/_flat/19.2.0/partitioned/1/.temp/sld_fabrics/ipgen/alt_sld_fab_0/alt_sld_fab_0/altera_reset_controller_191/synth/altera_reset_controller.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
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Critical Warning (19294): Synopsys Design Constraints File file not found for instance '': '/p/psg/swip/releases/acds/19.2/57/linux64/ip/altera/sld/jtag/altera_jtag_wys_atom/default_jtag.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
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Info (19449): Reading SDC files elapsed 00:00:32.
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Info (332097): The following timing edges are non-unate. The Timing Analyzer will assume pos-unate behavior for these edges in the clock network.
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Info (332098): Cell: mem|ddr4a|ddr4a|arch|arch_inst|bufs_inst|gen_mem_dqs.inst[0].b|cal_oct.obuf from: oe to: o
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Info (332098): Cell: mem|ddr4a|ddr4a|arch|arch_inst|bufs_inst|gen_mem_dqs.inst[1].b|cal_oct.obuf from: oe to: o
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Info (332098): Cell: mem|ddr4a|ddr4a|arch|arch_inst|bufs_inst|gen_mem_dqs.inst[2].b|cal_oct.obuf from: oe to: o
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Info (332098): Cell: mem|ddr4a|ddr4a|arch|arch_inst|bufs_inst|gen_mem_dqs.inst[3].b|cal_oct.obuf from: oe to: o
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Info (332098): Cell: mem|ddr4a|ddr4a|arch|arch_inst|bufs_inst|gen_mem_dqs.inst[4].b|cal_oct.obuf from: oe to: o
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Info (332098): Cell: mem|ddr4a|ddr4a|arch|arch_inst|bufs_inst|gen_mem_dqs.inst[5].b|cal_oct.obuf from: oe to: o
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Info (332098): Cell: mem|ddr4a|ddr4a|arch|arch_inst|bufs_inst|gen_mem_dqs.inst[6].b|cal_oct.obuf from: oe to: o
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Info (332098): Cell: mem|ddr4a|ddr4a|arch|arch_inst|bufs_inst|gen_mem_dqs.inst[7].b|cal_oct.obuf from: oe to: o
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Info (332098): Cell: mem|ddr4b|ddr4b|arch|arch_inst|bufs_inst|gen_mem_dqs.inst[0].b|cal_oct.obuf from: oe to: o
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Info (332098): Cell: mem|ddr4b|ddr4b|arch|arch_inst|bufs_inst|gen_mem_dqs.inst[1].b|cal_oct.obuf from: oe to: o
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Info (332098): Cell: mem|ddr4b|ddr4b|arch|arch_inst|bufs_inst|gen_mem_dqs.inst[2].b|cal_oct.obuf from: oe to: o
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Info (332098): Cell: mem|ddr4b|ddr4b|arch|arch_inst|bufs_inst|gen_mem_dqs.inst[3].b|cal_oct.obuf from: oe to: o
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Info (332098): Cell: mem|ddr4b|ddr4b|arch|arch_inst|bufs_inst|gen_mem_dqs.inst[4].b|cal_oct.obuf from: oe to: o
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Info (332098): Cell: mem|ddr4b|ddr4b|arch|arch_inst|bufs_inst|gen_mem_dqs.inst[5].b|cal_oct.obuf from: oe to: o
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Info (332098): Cell: mem|ddr4b|ddr4b|arch|arch_inst|bufs_inst|gen_mem_dqs.inst[6].b|cal_oct.obuf from: oe to: o
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Info (332098): Cell: mem|ddr4b|ddr4b|arch|arch_inst|bufs_inst|gen_mem_dqs.inst[7].b|cal_oct.obuf from: oe to: o
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Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties.
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Info (332152): The following assignments are ignored by the derive_clock_uncertainty command
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Warning (332056): PLL cross checking found inconsistent PLL clock settings:
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Warning (332056): Clock: fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk0 was found on node: fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|fpll_inst|outclk[0] with settings that do not match the following PLL specifications:
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Warning (332056): -multiply_by (expected: 25, found: 1100), -divide_by (expected: 16, found: 1000)
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Warning (332056): Clock: fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk1 was found on node: fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|fpll_inst|outclk[1] with settings that do not match the following PLL specifications:
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Warning (332056): -multiply_by (expected: 25, found: 2200), -divide_by (expected: 8, found: 1000)
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Warning (332056): Clock: hssi_pll_t_outclk0 with period: 3.200 found on PLL node: fpga_top|inst_fiu_top|inst_hssi_ctrl|pll_t|xcvr_fpll_a10_0|fpll_inst|outclk[0] does not match the period requirement: 6.400
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Warning (332056): Clock: hssi_pll_t_outclk1 with period: 3.800 found on PLL node: fpga_top|inst_fiu_top|inst_hssi_ctrl|pll_t|xcvr_fpll_a10_0|fpll_inst|outclk[1] does not match the period requirement: 6.400
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Warning (332056): Clock: hssi_pll_r_0_outclk0 with period: 3.200 found on PLL node: fpga_top|inst_fiu_top|inst_hssi_ctrl|pll_r_0|xcvr_fpll_a10_0|fpll_inst|outclk[0] does not match the period requirement: 6.400
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Warning (332056): Clock: hssi_pll_r_0_outclk1 with period: 3.800 found on PLL node: fpga_top|inst_fiu_top|inst_hssi_ctrl|pll_r_0|xcvr_fpll_a10_0|fpll_inst|outclk[1] does not match the period requirement: 6.400
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Warning (332088): No paths exist between clock target "fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MOSIctl|filtered_sclk_negedge|q" of clock "filtered_sclk_negedge" and its clock source. Assuming zero source clock latency.
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Info (332129): Detected timing requirements -- optimizing circuit to achieve only the specified requirements
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Info (332111): Found 189 clocks
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Info (332111): Period Clock Name
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Info (332111): ======== ============
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Info (332111): 100.000 altera_reserved_tck
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Info (332111): 1000.000 altera_ts_clk
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Info (332111): 3.752 DDR4_RefClk
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Info (332111): 0.937 DDR4A_DQS_P[0]_IN
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Info (332111): 0.937 DDR4A_DQS_P[1]_IN
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Info (332111): 0.937 DDR4A_DQS_P[2]_IN
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Info (332111): 0.937 DDR4A_DQS_P[3]_IN
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Info (332111): 0.937 DDR4A_DQS_P[4]_IN
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Info (332111): 0.937 DDR4A_DQS_P[5]_IN
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Info (332111): 0.937 DDR4A_DQS_P[6]_IN
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Info (332111): 0.937 DDR4A_DQS_P[7]_IN
|
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Info (332111): 0.937 DDR4B_DQS_P[0]_IN
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Info (332111): 0.937 DDR4B_DQS_P[1]_IN
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Info (332111): 0.937 DDR4B_DQS_P[2]_IN
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Info (332111): 0.937 DDR4B_DQS_P[3]_IN
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|
Info (332111): 0.937 DDR4B_DQS_P[4]_IN
|
|
Info (332111): 0.937 DDR4B_DQS_P[5]_IN
|
|
Info (332111): 0.937 DDR4B_DQS_P[6]_IN
|
|
Info (332111): 0.937 DDR4B_DQS_P[7]_IN
|
|
Info (332111): 3.103 ETH_RefClk
|
|
Info (332111): 250.000 filtered_sclk_negedge
|
|
Info (332111): 40.000 flash_oe_clk
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|
Info (332111): 9.090 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk0
|
|
Info (332111): 4.545 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk1
|
|
Info (332111): 0.193 fpga_top|inst_fiu_top|inst_hssi_ctrl|atx0|altera_xcvr_atx_pll_ip_inst|mcgb_serial_clk
|
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Info (332111): 10.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|avmmclk
|
|
Info (332111): 3.200 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_coreclkin
|
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Info (332111): 3.878 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_clk
|
|
Info (332111): 6.399 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_div_clk
|
|
Info (332111): 3.200 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|tx_coreclkin
|
|
Info (332111): 3.878 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|tx_pma_clk
|
|
Info (332111): 6.399 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|tx_pma_div_clk
|
|
Info (332111): 10.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|avmmclk
|
|
Info (332111): 3.200 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|rx_coreclkin
|
|
Info (332111): 3.878 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|rx_pma_clk
|
|
Info (332111): 6.399 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|rx_pma_div_clk
|
|
Info (332111): 3.200 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|tx_coreclkin
|
|
Info (332111): 3.878 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|tx_pma_clk
|
|
Info (332111): 6.399 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|tx_pma_div_clk
|
|
Info (332111): 10.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|avmmclk
|
|
Info (332111): 3.200 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|rx_coreclkin
|
|
Info (332111): 3.878 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|rx_pma_clk
|
|
Info (332111): 6.399 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|rx_pma_div_clk
|
|
Info (332111): 3.200 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|tx_coreclkin
|
|
Info (332111): 3.878 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|tx_pma_clk
|
|
Info (332111): 6.399 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|tx_pma_div_clk
|
|
Info (332111): 10.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|avmmclk
|
|
Info (332111): 3.200 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|rx_coreclkin
|
|
Info (332111): 3.878 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|rx_pma_clk
|
|
Info (332111): 6.399 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|rx_pma_div_clk
|
|
Info (332111): 3.200 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|tx_coreclkin
|
|
Info (332111): 3.878 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|tx_pma_clk
|
|
Info (332111): 6.399 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|tx_pma_div_clk
|
|
Info (332111): 10.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|avmmclk
|
|
Info (332111): 4.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|pma_hclk_by2
|
|
Info (332111): 2.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_clk
|
|
Info (332111): 2.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_clkout
|
|
Info (332111): 10.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332111): 2.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_pma_clk
|
|
Info (332111): 8.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|tx_clk
|
|
Info (332111): 10.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|avmmclk
|
|
Info (332111): 4.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|pma_hclk_by2
|
|
Info (332111): 2.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|rx_clk
|
|
Info (332111): 2.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|rx_clkout
|
|
Info (332111): 10.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|rx_fref
|
|
Info (332111): 2.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|rx_pma_clk
|
|
Info (332111): 8.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|tx_clk
|
|
Info (332111): 10.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|avmmclk
|
|
Info (332111): 4.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|pma_hclk_by2
|
|
Info (332111): 2.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|rx_clk
|
|
Info (332111): 2.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|rx_clkout
|
|
Info (332111): 10.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|rx_fref
|
|
Info (332111): 2.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|rx_pma_clk
|
|
Info (332111): 8.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|tx_clk
|
|
Info (332111): 10.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|avmmclk
|
|
Info (332111): 4.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|pma_hclk_by2
|
|
Info (332111): 2.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|rx_clk
|
|
Info (332111): 2.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|rx_clkout
|
|
Info (332111): 10.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|rx_fref
|
|
Info (332111): 2.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|rx_pma_clk
|
|
Info (332111): 8.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|tx_clk
|
|
Info (332111): 10.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|avmmclk
|
|
Info (332111): 4.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|pma_hclk_by2
|
|
Info (332111): 2.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|rx_clk
|
|
Info (332111): 2.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|rx_clkout
|
|
Info (332111): 10.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|rx_fref
|
|
Info (332111): 2.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|rx_pma_clk
|
|
Info (332111): 8.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|tx_clk
|
|
Info (332111): 10.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|avmmclk
|
|
Info (332111): 4.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|pma_hclk_by2
|
|
Info (332111): 2.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|rx_clk
|
|
Info (332111): 2.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|rx_clkout
|
|
Info (332111): 10.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|rx_fref
|
|
Info (332111): 2.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|rx_pma_clk
|
|
Info (332111): 8.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|tx_clk
|
|
Info (332111): 10.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|avmmclk
|
|
Info (332111): 4.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|pma_hclk_by2
|
|
Info (332111): 2.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|rx_clk
|
|
Info (332111): 2.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|rx_clkout
|
|
Info (332111): 10.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|rx_fref
|
|
Info (332111): 2.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|rx_pma_clk
|
|
Info (332111): 8.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|tx_clk
|
|
Info (332111): 10.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|avmmclk
|
|
Info (332111): 4.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|pma_hclk_by2
|
|
Info (332111): 2.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|rx_clk
|
|
Info (332111): 2.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|rx_clkout
|
|
Info (332111): 10.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|rx_fref
|
|
Info (332111): 2.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|rx_pma_clk
|
|
Info (332111): 8.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|tx_clk
|
|
Info (332111): 2.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|hip_cmn_clk[0]
|
|
Info (332111): 4.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|pld_clk
|
|
Info (332111): 2.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|pll_pcie_clk
|
|
Info (332111): 2.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|rx_pcs_clk_div_by_4[0]
|
|
Info (332111): 2.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|rx_pcs_clk_div_by_4[1]
|
|
Info (332111): 2.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|rx_pcs_clk_div_by_4[2]
|
|
Info (332111): 2.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|rx_pcs_clk_div_by_4[3]
|
|
Info (332111): 2.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|rx_pcs_clk_div_by_4[4]
|
|
Info (332111): 2.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|rx_pcs_clk_div_by_4[5]
|
|
Info (332111): 2.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|rx_pcs_clk_div_by_4[6]
|
|
Info (332111): 2.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|rx_pcs_clk_div_by_4[7]
|
|
Info (332111): 0.250 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|twentynm_atx_pll_inst~O_CLK0_8G
|
|
Info (332111): 2.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_bonding_clocks[0]
|
|
Info (332111): 8.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_clkout
|
|
Info (332111): 2.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_pcs_clk_div_by_4[0]
|
|
Info (332111): 2.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_pcs_clk_div_by_4[1]
|
|
Info (332111): 2.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_pcs_clk_div_by_4[2]
|
|
Info (332111): 2.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_pcs_clk_div_by_4[3]
|
|
Info (332111): 2.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_pcs_clk_div_by_4[4]
|
|
Info (332111): 2.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_pcs_clk_div_by_4[5]
|
|
Info (332111): 2.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_pcs_clk_div_by_4[6]
|
|
Info (332111): 2.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_pcs_clk_div_by_4[7]
|
|
Info (332111): 0.400 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_serial_clk
|
|
Info (332111): 4.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|wys~CORE_CLK_OUT
|
|
Info (332111): 250.000 fspi_sclk
|
|
Info (332111): 3.200 hssi_pll_r_0_outclk0
|
|
Info (332111): 3.800 hssi_pll_r_0_outclk1
|
|
Info (332111): 3.200 hssi_pll_t_outclk0
|
|
Info (332111): 3.800 hssi_pll_t_outclk1
|
|
Info (332111): 6.566 mem|ddr4a|ddr4a_core_cal_slave_clk
|
|
Info (332111): 3.752 mem|ddr4a|ddr4a_core_usr_clk
|
|
Info (332111): 1.876 mem|ddr4a|ddr4a_phy_clk_0
|
|
Info (332111): 1.876 mem|ddr4a|ddr4a_phy_clk_1
|
|
Info (332111): 1.876 mem|ddr4a|ddr4a_phy_clk_2
|
|
Info (332111): 3.752 mem|ddr4a|ddr4a_phy_clk_l_0
|
|
Info (332111): 3.752 mem|ddr4a|ddr4a_phy_clk_l_1
|
|
Info (332111): 3.752 mem|ddr4a|ddr4a_phy_clk_l_2
|
|
Info (332111): 0.938 mem|ddr4a|ddr4a_vco_clk
|
|
Info (332111): 0.938 mem|ddr4a|ddr4a_vco_clk_1
|
|
Info (332111): 0.938 mem|ddr4a|ddr4a_vco_clk_2
|
|
Info (332111): 0.938 mem|ddr4a|ddr4a_wf_clk_0
|
|
Info (332111): 0.938 mem|ddr4a|ddr4a_wf_clk_1
|
|
Info (332111): 0.938 mem|ddr4a|ddr4a_wf_clk_2
|
|
Info (332111): 0.938 mem|ddr4a|ddr4a_wf_clk_3
|
|
Info (332111): 0.938 mem|ddr4a|ddr4a_wf_clk_4
|
|
Info (332111): 0.938 mem|ddr4a|ddr4a_wf_clk_5
|
|
Info (332111): 0.938 mem|ddr4a|ddr4a_wf_clk_6
|
|
Info (332111): 0.938 mem|ddr4a|ddr4a_wf_clk_7
|
|
Info (332111): 0.938 mem|ddr4a|ddr4a_wf_clk_8
|
|
Info (332111): 0.938 mem|ddr4a|ddr4a_wf_clk_9
|
|
Info (332111): 0.938 mem|ddr4a|ddr4a_wf_clk_10
|
|
Info (332111): 1.876 mem|ddr4b|ddr4b_phy_clk_0
|
|
Info (332111): 1.876 mem|ddr4b|ddr4b_phy_clk_1
|
|
Info (332111): 1.876 mem|ddr4b|ddr4b_phy_clk_2
|
|
Info (332111): 3.752 mem|ddr4b|ddr4b_phy_clk_l_0
|
|
Info (332111): 3.752 mem|ddr4b|ddr4b_phy_clk_l_1
|
|
Info (332111): 3.752 mem|ddr4b|ddr4b_phy_clk_l_2
|
|
Info (332111): 0.938 mem|ddr4b|ddr4b_vco_clk_0
|
|
Info (332111): 0.938 mem|ddr4b|ddr4b_vco_clk_1
|
|
Info (332111): 0.938 mem|ddr4b|ddr4b_vco_clk_2
|
|
Info (332111): 0.938 mem|ddr4b|ddr4b_wf_clk_0
|
|
Info (332111): 0.938 mem|ddr4b|ddr4b_wf_clk_1
|
|
Info (332111): 0.938 mem|ddr4b|ddr4b_wf_clk_2
|
|
Info (332111): 0.938 mem|ddr4b|ddr4b_wf_clk_3
|
|
Info (332111): 0.938 mem|ddr4b|ddr4b_wf_clk_4
|
|
Info (332111): 0.938 mem|ddr4b|ddr4b_wf_clk_5
|
|
Info (332111): 0.938 mem|ddr4b|ddr4b_wf_clk_6
|
|
Info (332111): 0.938 mem|ddr4b|ddr4b_wf_clk_7
|
|
Info (332111): 0.938 mem|ddr4b|ddr4b_wf_clk_8
|
|
Info (332111): 0.938 mem|ddr4b|ddr4b_wf_clk_9
|
|
Info (332111): 0.938 mem|ddr4b|ddr4b_wf_clk_10
|
|
Info (332111): 10.000 PCIE_REFCLK
|
|
Info (332111): 10.000 pr_clk_enable_dclk_reg2_user_clk
|
|
Info (332111): 10.000 SYS_RefClk
|
|
Info (332111): 5.000 u0|dcp_iopll|dcp_iopll|clk1x
|
|
Info (332111): 40.000 u0|dcp_iopll|dcp_iopll|clk25
|
|
Info (332111): 20.000 u0|dcp_iopll|dcp_iopll|clk50
|
|
Info (332111): 10.000 u0|dcp_iopll|dcp_iopll|clk100
|
|
Info (332111): 9.090 vl_qph_user_clk_clkpsc_clk0
|
|
Info (332111): 4.545 vl_qph_user_clk_clkpsc_clk1
|
|
Info (176233): Starting register packing
|
|
Info: Target user clock high: auto (220)
|
|
Info: Target user clock low: auto (110.0)
|
|
Info (176235): Finished register packing
|
|
Extra Info (176218): Packed 1117 registers into blocks of type Block RAM
|
|
Extra Info (176218): Packed 49408 registers into blocks of type DSP block
|
|
Extra Info (176218): Packed 4480 registers into blocks of type MLAB cell
|
|
Extra Info (176220): Created 4224 register duplicates
|
|
Info (20273): Intermediate fitter snapshots will not be committed because ENABLE_INTERMEDIATE_SNAPSHOTS QSF assignment is disabled during compilation.
|
|
Info (12517): Periphery placement operations ending: elapsed time is 00:11:03
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_aeb", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|rdemp_eq_comp_msb_aeb", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|wrptr_g[0]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|wrptr_g[1]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|wrptr_g[2]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|wrptr_g[3]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|wrptr_g[4]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|wrptr_g[5]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|wrptr_g[6]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|rdptr_g1p|counter1a0", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_aeb", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|rdemp_eq_comp_msb_aeb", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|wrptr_g[0]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|wrptr_g[1]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|wrptr_g[2]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|wrptr_g[3]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|wrptr_g[4]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|wrptr_g[5]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|wrptr_g[6]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|rdptr_g1p|counter1a0", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_aeb", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|rdemp_eq_comp_msb_aeb", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|wrptr_g[0]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|wrptr_g[1]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|wrptr_g[2]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|wrptr_g[3]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|wrptr_g[4]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|wrptr_g[5]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|rdptr_g1p|counter1a0", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|wrptr_g1p|counter4a0", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|rdptr_g1p|parity2", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|wrptr_g1p|counter4a0", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|rdptr_g1p|parity2", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|wrptr_g1p|counter3a0", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|rdptr_g1p|parity2", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|wrptr_g1p|parity5", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|wrptr_g1p|parity5", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|wrptr_g1p|parity4", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_aeb", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|rdemp_eq_comp_msb_aeb", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|wrptr_g[0]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|wrptr_g[1]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|wrptr_g[2]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|wrptr_g[3]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|wrptr_g[4]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|wrptr_g[5]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|wrptr_g[6]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|wrptr_g[7]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|wrptr_g[8]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|wrptr_g[9]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|rdptr_g1p|counter1a0", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_aeb", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|rdemp_eq_comp_msb_aeb", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|wrptr_g[0]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|wrptr_g[1]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|wrptr_g[2]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|wrptr_g[3]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|wrptr_g[4]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|wrptr_g[5]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|wrptr_g[6]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|wrptr_g[7]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|wrptr_g[8]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|rdptr_g1p|counter1a0", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|wrptr_g1p|counter4a0", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|rdptr_g1p|parity2", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|wrptr_g1p|counter4a0", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|rdptr_g1p|parity2", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|wrptr_g1p|parity5", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|wrptr_g1p|parity5", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Info (11165): Fitter preparation operations ending: elapsed time is 00:10:40
|
|
Info (18252): The Fitter is using Physical Synthesis.
|
|
Info (170189): Fitter placement preparation operations beginning
|
|
Info (20288): The Fitter could not convert one or more RAM instances into MLABs automatically because auto MLAB conversion requires the Read-During-Write mode set to Don't Care. Change the Read-During-Write mode to Don't Care in the affected RAMS. Alternatively, to keep the current Read-During-Write mode, change the RAM type to MLAB instead of AUTO. For information on which RAM instances are affected, refer to the 'Fitter RAM Summary' table in the Fitter Report.
|
|
Info: Target user clock high: auto (220)
|
|
Info: Target user clock low: auto (110.0)
|
|
Info (14951): The Fitter is using Advanced Physical Optimization.
|
|
Info (170190): Fitter placement preparation operations ending: elapsed time is 00:31:59
|
|
Info (11888): Total time spent on timing analysis during Global Placement is 116.14 seconds.
|
|
Info (18258): Fitter Physical Synthesis operations beginning
|
|
Info (18709): Fitter Physical Synthesis has detected a Partial Reconfiguration or Reserved Core partition in the design. The registers inside this region or partition will not be retimed.
|
|
Info (18259): Fitter Physical Synthesis operations ending: elapsed time is 00:00:29
|
|
Info (11888): Total time spent on timing analysis during Physical Synthesis is 0.00 seconds.
|
|
Info (170189): Fitter placement preparation operations beginning
|
|
Info (14951): The Fitter is using Advanced Physical Optimization.
|
|
Info (19727): Fitter will now perform the packing at high effort level
|
|
Info (19727): Fitter will now perform the packing at the highest effort level
|
|
Info (170190): Fitter placement preparation operations ending: elapsed time is 00:25:56
|
|
Info (170191): Fitter placement operations beginning
|
|
Info (170137): Fitter placement was successful
|
|
Info (170192): Fitter placement operations ending: elapsed time is 00:26:33
|
|
Info (11888): Total time spent on timing analysis during Global Placement is 0.73 seconds.
|
|
Info (18258): Fitter Physical Synthesis operations beginning
|
|
Info (18259): Fitter Physical Synthesis operations ending: elapsed time is 00:01:12
|
|
Info (11888): Total time spent on timing analysis during Physical Synthesis is 0.00 seconds.
|
|
Info (170189): Fitter placement preparation operations beginning
|
|
Info (170191): Fitter placement operations beginning
|
|
Info (170137): Fitter placement was successful
|
|
Info (170192): Fitter placement operations ending: elapsed time is 00:00:14
|
|
Info: Target user clock high: auto (220)
|
|
Info: Target user clock low: auto (110.0)
|
|
Info (11888): Total time spent on timing analysis during Placement is 0.02 seconds.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_aeb", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|rdemp_eq_comp_msb_aeb", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|wrptr_g[0]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|wrptr_g[1]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|wrptr_g[2]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|wrptr_g[3]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|wrptr_g[4]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|wrptr_g[5]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|wrptr_g[6]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|rdptr_g1p|counter1a0", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_aeb", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|rdemp_eq_comp_msb_aeb", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|wrptr_g[0]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|wrptr_g[1]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|wrptr_g[2]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|wrptr_g[3]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|wrptr_g[4]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|wrptr_g[5]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|wrptr_g[6]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|rdptr_g1p|counter1a0", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_aeb", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|rdemp_eq_comp_msb_aeb", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|wrptr_g[0]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|wrptr_g[1]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|wrptr_g[2]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|wrptr_g[3]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|wrptr_g[4]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|wrptr_g[5]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|rdptr_g1p|counter1a0", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|wrptr_g1p|counter4a0", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|rdptr_g1p|parity2", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|wrptr_g1p|counter4a0", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|rdptr_g1p|parity2", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|wrptr_g1p|counter3a0", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|rdptr_g1p|parity2", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|wrptr_g1p|parity5", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|wrptr_g1p|parity5", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|wrptr_g1p|parity4", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_aeb", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|rdemp_eq_comp_msb_aeb", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|wrptr_g[0]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|wrptr_g[1]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|wrptr_g[2]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|wrptr_g[3]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|wrptr_g[4]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|wrptr_g[5]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|wrptr_g[6]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|wrptr_g[7]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|wrptr_g[8]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|wrptr_g[9]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|rdptr_g1p|counter1a0", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_aeb", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|rdemp_eq_comp_msb_aeb", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|wrptr_g[0]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|wrptr_g[1]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|wrptr_g[2]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|wrptr_g[3]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|wrptr_g[4]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|wrptr_g[5]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|wrptr_g[6]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|wrptr_g[7]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|wrptr_g[8]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|rdptr_g1p|counter1a0", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|wrptr_g1p|counter4a0", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|rdptr_g1p|parity2", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|wrptr_g1p|counter4a0", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|rdptr_g1p|parity2", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|wrptr_g1p|parity5", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|wrptr_g1p|parity5", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Info (170193): Fitter routing operations beginning
|
|
Info (170089): 4e+04 ns of routing delay (approximately 3.3% of available device routing delay) has been added to meet hold timing. For more information, refer to the Estimated Delay Added for Hold Timing section in the Fitter report.
|
|
Info (20215): Router estimated peak short interconnect utilization : 103% of right directional wire in region X72_Y140 to X79_Y146
|
|
Info (20265): Estimated peak short right directional wire utilization : 103% in region X72_Y140 to X79_Y146
|
|
Info (20265): Estimated peak short left directional wire utilization : 100% in region X8_Y77 to X15_Y83
|
|
Info (20265): Estimated peak short up directional wire utilization : 79% in region X96_Y49 to X103_Y55
|
|
Info (20265): Estimated peak short down directional wire utilization : 100% in region X0_Y77 to X7_Y83
|
|
Info (20215): Router estimated peak long high speed interconnect utilization : 150% of right directional wire in region X72_Y14 to X79_Y20
|
|
Info (20265): Estimated peak long high speed right directional wire utilization : 150% in region X72_Y14 to X79_Y20
|
|
Info (20265): Estimated peak long high speed left directional wire utilization : 125% in region X32_Y7 to X39_Y13
|
|
Info (20265): Estimated peak long high speed up directional wire utilization : 140% in region X136_Y91 to X143_Y97
|
|
Info (20265): Estimated peak long high speed down directional wire utilization : 150% in region X120_Y98 to X127_Y104
|
|
Info (20315): Note that the router may use short wires to implement long connections at higher delay
|
|
Info (170239): Router is attempting to preserve 6.80 percent of routes from an earlier compilation, a user specified Routing Constraints File, or internal routing requirements.
|
|
Info (170236): Routing optimizations have been running for 1 hour(s)
|
|
Info (170242): 940630 out of 940632 signals have been routed.
|
|
Info (170238): 1 interconnect resources are used by multiple signals.
|
|
Info: Target user clock high: auto (220)
|
|
Info: Target user clock low: auto (110.0)
|
|
Info (11888): Total time spent on timing analysis during Routing is 304.85 seconds.
|
|
Info (16607): Fitter routing operations ending: elapsed time is 01:14:15
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_aeb", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|rdemp_eq_comp_msb_aeb", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|wrptr_g[0]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|wrptr_g[1]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|wrptr_g[2]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|wrptr_g[3]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|wrptr_g[4]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|wrptr_g[5]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|wrptr_g[6]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|rdptr_g1p|counter1a0", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_aeb", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|rdemp_eq_comp_msb_aeb", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|wrptr_g[0]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|wrptr_g[1]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|wrptr_g[2]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|wrptr_g[3]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|wrptr_g[4]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|wrptr_g[5]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|wrptr_g[6]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|rdptr_g1p|counter1a0", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_aeb", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|rdemp_eq_comp_msb_aeb", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|wrptr_g[0]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|wrptr_g[1]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|wrptr_g[2]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|wrptr_g[3]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|wrptr_g[4]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|wrptr_g[5]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|rdptr_g1p|counter1a0", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|wrptr_g1p|counter4a0", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|rdptr_g1p|parity2", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|wrptr_g1p|counter4a0", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|rdptr_g1p|parity2", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|wrptr_g1p|counter3a0", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|rdptr_g1p|parity2", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|wrptr_g1p|parity5", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|wrptr_g1p|parity5", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|wrptr_g1p|parity4", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_aeb", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|rdemp_eq_comp_msb_aeb", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|wrptr_g[0]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|wrptr_g[1]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|wrptr_g[2]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|wrptr_g[3]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|wrptr_g[4]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|wrptr_g[5]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|wrptr_g[6]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|wrptr_g[7]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|wrptr_g[8]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|wrptr_g[9]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|rdptr_g1p|counter1a0", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_aeb", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|rdemp_eq_comp_msb_aeb", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|wrptr_g[0]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|wrptr_g[1]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|wrptr_g[2]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|wrptr_g[3]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|wrptr_g[4]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|wrptr_g[5]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|wrptr_g[6]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|wrptr_g[7]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|wrptr_g[8]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|rdptr_g1p|counter1a0", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|wrptr_g1p|counter4a0", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|rdptr_g1p|parity2", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|wrptr_g1p|counter4a0", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|rdptr_g1p|parity2", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|wrptr_g1p|parity5", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|wrptr_g1p|parity5", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|wrptr_g1p|counter4a0~DUPLICATE", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|wrptr_g1p|parity5~DUPLICATE", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Info (11888): Total time spent on timing analysis during Post-Routing is 0.50 seconds.
|
|
Info (16557): Fitter post-fit operations ending: elapsed time is 00:15:56
|
|
Info (20274): Successfully committed final database.
|
|
Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
|
|
Info: Quartus Prime Fitter was successful. 0 errors, 837 warnings
|
|
Info: Peak virtual memory: 28775 megabytes
|
|
Info: Processing ended: Sat Mar 6 08:45:58 2021
|
|
Info: Elapsed time: 03:30:24
|
|
Info (19538): Reading SDC files took 00:01:05 cumulatively in this process.
|
|
Info (293026): Skipped module Fast Forward due to the assignment FLOW_ENABLE_HYPER_RETIMER_FAST_FORWARD
|
|
Info: *******************************************************************
|
|
Info: Running Quartus Prime Timing Analyzer
|
|
Info: Version 19.2.0 Build 57 06/24/2019 Patches 0.01rc SJ Pro Edition
|
|
Info: Processing started: Sat Mar 6 08:46:14 2021
|
|
Info: Command: quartus_sta dcp -c afu_default --mode=finalize
|
|
Info: qsta_default_script.tcl version: #1
|
|
Info (16677): Loading final database
|
|
Info (16734): Loading "final" snapshot for partition "root_partition".
|
|
Info (16734): Loading "final" snapshot for partition "root_partition_2cedade0".
|
|
Info (16734): Loading "final" snapshot for partition "green_region".
|
|
Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design contains file: "/opt/opae/1.1.2/share/opae/platform/platform_if/rtl/platform_shims/utils/quartus_ip/platform_utils_dc_fifo.sdc", assignment in base design does not contain file). Check that the assignment in the current design is correct.
|
|
Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design contains file: "/opt/opae/1.1.2/share/opae/platform/platform_if/rtl/platform_shims/utils/quartus_ip/platform_utils_avalon_dc_fifo.sdc", assignment in base design does not contain file). Check that the assignment in the current design is correct.
|
|
Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design contains file: "/opt/opae/1.1.2/share/opae/platform/platform_if/par/platform_if.sdc", assignment in base design does not contain file). Check that the assignment in the current design is correct.
|
|
Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design contains file: "dcp_bbs.sdc", assignment in base design does not contain file). Check that the assignment in the current design is correct.
|
|
Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design contains file: "platform/green_bs.sdc", assignment in base design does not contain file). Check that the assignment in the current design is correct.
|
|
Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design contains file: "dcp_user_clocks.sdc", assignment in base design does not contain file). Check that the assignment in the current design is correct.
|
|
Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/hssi_eth/e10/phy/altera_eth_10gbaser_phy/altera_xcvr_native_a10_191/synth/altera_xcvr_native_a10_false_paths.sdc"). Check that the assignment in the current design is correct.
|
|
Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/hssi_eth/native_xcvr/altera_xcvr_native_a10_191/synth/altera_xcvr_native_a10_false_paths.sdc"). Check that the assignment in the current design is correct.
|
|
Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/remote_stp/QSYS_IPs/PR_190/ip/SLD_HUB_CONT_SYS_WO_SLD_EP/SLD_HUB_CONT_SYS_WO_SLD_EP_sld_hub_controller_system_without_sldep_0/altera_streaming_sld_hub_controller_core_without_sldep_180/synth/altera_streaming_sld_hub_controller_without_sldep.sdc"). Check that the assignment in the current design is correct.
|
|
Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/fme/ptmgr/TEMPERATURE_SourceTree/ptmgr_temp_sensor/altera_temp_sense_191/synth/altera_temp_sense.sdc"). Check that the assignment in the current design is correct.
|
|
Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/top/dcp_top.sdc"). Check that the assignment in the current design is correct.
|
|
Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/sdc/fabric.sdc"). Check that the assignment in the current design is correct.
|
|
Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/sdc/fme.sdc"). Check that the assignment in the current design is correct.
|
|
Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/sdc/fiu.sdc"). Check that the assignment in the current design is correct.
|
|
Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/afu/green_bs.sdc"). Check that the assignment in the current design is correct.
|
|
Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/partial_reconfig/PR_IP/alt_pr_191/synth/rtl/alt_pr.sdc"). Check that the assignment in the current design is correct.
|
|
Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/pcie/ips/pcie_sriov_ep_g3x8/pcie_sriov_ep_g3x8/altera_xcvr_native_a10_191/synth/altera_xcvr_native_a10_false_paths.sdc"). Check that the assignment in the current design is correct.
|
|
Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/pcie/ips/pcie_sriov_ep_g3x8/pcie_sriov_ep_g3x8/altera_pcie_a10_hip_191/synth/altera_pci_express.sdc"). Check that the assignment in the current design is correct.
|
|
Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/afu/nlb_400/nlb_400.sdc"). Check that the assignment in the current design is correct.
|
|
Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/bmc_mailbox/ip/bmc_mailbox/bmc_mailbox_spi_slave_to_avalon_mm_master_bridge_1/spi_slave_to_avalon_mm_master_bridge_191/synth/spiphyslave.sdc"). Check that the assignment in the current design is correct.
|
|
Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/tcm/ip/tcm/tcm_alt_pr_0/alt_pr_191/synth/rtl/alt_pr.sdc"). Check that the assignment in the current design is correct.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_aeb", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|rdemp_eq_comp_msb_aeb", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|wrptr_g[0]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|wrptr_g[1]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|wrptr_g[2]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|wrptr_g[3]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|wrptr_g[4]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|wrptr_g[5]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|wrptr_g[6]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|rdptr_g1p|counter1a0", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_aeb", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|rdemp_eq_comp_msb_aeb", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|wrptr_g[0]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|wrptr_g[1]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|wrptr_g[2]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|wrptr_g[3]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|wrptr_g[4]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|wrptr_g[5]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|wrptr_g[6]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|rdptr_g1p|counter1a0", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_aeb", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|rdemp_eq_comp_msb_aeb", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|wrptr_g[0]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|wrptr_g[1]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|wrptr_g[2]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|wrptr_g[3]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|wrptr_g[4]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|wrptr_g[5]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|rdptr_g1p|counter1a0", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|wrptr_g1p|counter4a0", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|rdptr_g1p|parity2", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|wrptr_g1p|counter4a0", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|rdptr_g1p|parity2", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|wrptr_g1p|counter3a0", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|rdptr_g1p|parity2", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|wrptr_g1p|parity5", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|wrptr_g1p|parity5", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|wrptr_g1p|parity4", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_aeb", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|rdemp_eq_comp_msb_aeb", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|wrptr_g[0]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|wrptr_g[1]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|wrptr_g[2]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|wrptr_g[3]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|wrptr_g[4]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|wrptr_g[5]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|wrptr_g[6]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|wrptr_g[7]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|wrptr_g[8]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|wrptr_g[9]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|rdptr_g1p|counter1a0", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_aeb", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|rdemp_eq_comp_msb_aeb", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|wrptr_g[0]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|wrptr_g[1]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|wrptr_g[2]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|wrptr_g[3]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|wrptr_g[4]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|wrptr_g[5]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|wrptr_g[6]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|wrptr_g[7]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|wrptr_g[8]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|rdptr_g1p|counter1a0", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|wrptr_g1p|counter4a0", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|rdptr_g1p|parity2", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|wrptr_g1p|counter4a0", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|rdptr_g1p|parity2", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|wrptr_g1p|parity5", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|wrptr_g1p|parity5", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|wrptr_g1p|counter4a0~DUPLICATE", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|wrptr_g1p|parity5~DUPLICATE", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Info (16678): Successfully loaded final database: elapsed time is 00:00:55
|
|
Info (20030): Parallel compilation is enabled and will use 16 of the 32 processors detected
|
|
Info (21076): Core supply voltage operating condition is not set. Assuming a default value of '0.9V'.
|
|
Info (21077): Low junction temperature is 0 degrees C
|
|
Info (21077): High junction temperature is 100 degrees C
|
|
Info (332164): Evaluating HDL-embedded SDC commands
|
|
Info (332165): Entity MISOctl
|
|
Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *SPIPhy_altera_avalon_st_idle_inserter|received_esc*|*] -to [get_pins -no_case -compatibility_mode *|rdshiftreg*|*]
|
|
Info (332165): Entity MOSIctl
|
|
Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *]
|
|
Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *]
|
|
Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *]
|
|
Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *]
|
|
Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *]
|
|
Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *]
|
|
Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *]
|
|
Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *]
|
|
Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *]
|
|
Info (332165): Entity alt_jtag_atlantic
|
|
Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|jupdate}] -to [get_registers {*|alt_jtag_atlantic:*|jupdate1*}]
|
|
Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rdata[*]}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}]
|
|
Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|read}] -to [get_registers {*|alt_jtag_atlantic:*|read1*}]
|
|
Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|read_req}]
|
|
Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rvalid}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}]
|
|
Info (332166): set_false_path -from [get_registers {*|t_dav}] -to [get_registers {*|alt_jtag_atlantic:*|tck_t_dav}]
|
|
Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|user_saw_rvalid}] -to [get_registers {*|alt_jtag_atlantic:*|rvalid0*}]
|
|
Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|wdata[*]}] -to [get_registers {*}]
|
|
Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|write}] -to [get_registers {*|alt_jtag_atlantic:*|write1*}]
|
|
Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|write_stalled}] -to [get_registers {*|alt_jtag_atlantic:*|t_ena*}]
|
|
Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|write_stalled}] -to [get_registers {*|alt_jtag_atlantic:*|t_pause*}]
|
|
Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|write_valid}]
|
|
Info (332165): Entity alt_sync1r1
|
|
Info (332166): set_false_path -to [get_keepers *alt_sync1r1*ff_meta[*]]
|
|
Info (332165): Entity alt_sync_regs_m2
|
|
Info (332166): set_multicycle_path -to [get_keepers *sync_regs_m*din_meta[*]] 2
|
|
Info (332166): set_multicycle_path -to [get_keepers *sync_regs_m*din_meta[*]] 2
|
|
Info (332166): set_false_path -hold -to [get_keepers *sync_regs_m*din_meta[*]]
|
|
Info (332166): set_false_path -hold -to [get_keepers *sync_regs_m*din_meta[*]]
|
|
Info (332165): Entity alt_xcvr_resync
|
|
Info (332166): set regs [get_registers -nowarn *alt_xcvr_resync*sync_r[0]]; if {[llength [query_collection -report -all $regs]] > 0} {set_false_path -to $regs}
|
|
Info (332165): Entity altera_std_synchronizer
|
|
Info (332166): set_false_path -to [get_keepers {*altera_std_synchronizer:*|din_s1}]
|
|
Info (332165): Entity altpcie_reset_delay_sync
|
|
Info (332166): set_false_path -from [get_fanins -async *app_rstn_altpcie_reset_delay_sync_altpcie_a10_hip_hwtcl*rs_meta[*]] -to [get_keepers *app_rstn_altpcie_reset_delay_sync_altpcie_a10_hip_hwtcl*rs_meta[*]]
|
|
Info (332166): set_false_path -from [get_fanins -async *por_sync_altpcie_reset_delay_sync*rs_meta[*]] -to [get_keepers *por_sync_altpcie_reset_delay_sync*rs_meta[*]]
|
|
Info (332165): Entity altpcie_sc_bitsync
|
|
Info (332166): set_multicycle_path -to [get_keepers *pld_clk_in_use_altpcie_sc_bitsync*altpcie_sc_bitsync_meta_dff[*]] 3
|
|
Info (332166): set_false_path -hold -to [get_keepers *pld_clk_in_use_altpcie_sc_bitsync*altpcie_sc_bitsync_meta_dff[*]]
|
|
Info (332166): set_multicycle_path -to [get_keepers *reset_status_altpcie_sc_bitsync*altpcie_sc_bitsync_meta_dff[*]] 3
|
|
Info (332166): set_false_path -hold -to [get_keepers *reset_status_altpcie_sc_bitsync*altpcie_sc_bitsync_meta_dff[*]]
|
|
Info (332165): Entity dcfifo_tsr1
|
|
Info (332166): set_false_path -from *rdptr_g* -to *ws_dgrp|dffpipe_t5c:dffpipe16|dffe17a*
|
|
Info (332166): set_false_path -from *delayed_wrptr_g* -to *rs_dgwp|dffpipe_r5c:dffpipe12|dffe13a*
|
|
Info (332165): Entity alt_sld_fab_0_altera_a10_xcvr_reset_sequencer_191_yjmdoba
|
|
Info (332166): if { [get_collection_size [get_pins -compatibility_mode -nowarn ~ALTERA_CLKUSR~~ibuf|o]] > 0 } { create_clock -name ~ALTERA_CLKUSR~ -period 8 [get_pins -compatibility_mode -nowarn ~ALTERA_CLKUSR~~ibuf|o] }
|
|
Info (19539): Reading the HDL-embedded SDC files elapsed 00:00:26.
|
|
Info (332104): Reading SDC File: '/opt/opae/1.1.2/share/opae/platform/platform_if/rtl/platform_shims/utils/quartus_ip/platform_utils_dc_fifo.sdc'
|
|
Info (332104): Reading SDC File: '/opt/opae/1.1.2/share/opae/platform/platform_if/rtl/platform_shims/utils/quartus_ip/platform_utils_avalon_dc_fifo.sdc'
|
|
Info (332104): Reading SDC File: '/opt/opae/1.1.2/share/opae/platform/platform_if/par/platform_if.sdc'
|
|
Warning (332174): Ignored filter at platform_if.sdc(10): *|platform_shim_ccip|c.ccip_async_shim|error[0] could not be matched with a keeper File: /opt/opae/1.1.2/share/opae/platform/platform_if/par/platform_if.sdc Line: 10
|
|
Warning (332049): Ignored set_false_path at platform_if.sdc(10): Argument <from> is an empty collection File: /opt/opae/1.1.2/share/opae/platform/platform_if/par/platform_if.sdc Line: 10
|
|
Info (332050): set_false_path -from [get_keepers *|platform_shim_ccip|c.ccip_async_shim|error[0]] File: /opt/opae/1.1.2/share/opae/platform/platform_if/par/platform_if.sdc Line: 10
|
|
Warning (332174): Ignored filter at platform_if.sdc(11): *|platform_shim_ccip|c.ccip_async_shim|pwrState[0]* could not be matched with a keeper File: /opt/opae/1.1.2/share/opae/platform/platform_if/par/platform_if.sdc Line: 11
|
|
Warning (332049): Ignored set_false_path at platform_if.sdc(11): Argument <from> is an empty collection File: /opt/opae/1.1.2/share/opae/platform/platform_if/par/platform_if.sdc Line: 11
|
|
Info (332050): set_false_path -from [get_keepers *|platform_shim_ccip|c.ccip_async_shim|pwrState[0]*] File: /opt/opae/1.1.2/share/opae/platform/platform_if/par/platform_if.sdc Line: 11
|
|
Info (332104): Reading SDC File: 'dcp_bbs.sdc'
|
|
Warning (332174): Ignored filter at dcp_bbs.sdc(2863): *aclr_filter*aclr_meta[*] could not be matched with a keeper File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 2863
|
|
Warning (332049): Ignored get_fanins at dcp_bbs.sdc(2863): Argument with value [get_keepers {*aclr_filter*aclr_meta[*]}] contains zero elements File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 2863
|
|
Info (332050): get_fanins -asynch [get_keepers {*aclr_filter*aclr_meta[*]}] File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 2863
|
|
Warning (332049): Ignored set_false_path at dcp_bbs.sdc(2863): Argument <from> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 2863
|
|
Info (332050): set_false_path -from [get_fanins -asynch [get_keepers {*aclr_filter*aclr_meta[*]}]] -to [get_keepers {*aclr_filter*aclr_meta[*]}] File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 2863
|
|
Warning (332049): Ignored set_false_path at dcp_bbs.sdc(2863): Argument <to> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 2863
|
|
Warning (332174): Ignored filter at dcp_bbs.sdc(2864): *flag_mx_meta[*] could not be matched with a keeper File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 2864
|
|
Warning (332049): Ignored set_false_path at dcp_bbs.sdc(2864): Argument <to> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 2864
|
|
Info (332050): set_false_path -to [get_keepers {*flag_mx_meta[*]}] File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 2864
|
|
Warning (332174): Ignored filter at dcp_bbs.sdc(3092): mem|ddr4b|ddr4b|arch|arch_inst|seq_if_inst|afi_cal_success_sync_inst|din_s1|d could not be matched with a pin File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3092
|
|
Warning (332174): Ignored filter at dcp_bbs.sdc(3094): mem|ddr4b|ddr4b|arch|arch_inst|seq_if_inst|afi_cal_fail_sync_inst|din_s1|*data could not be matched with a pin File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3094
|
|
Warning (332174): Ignored filter at dcp_bbs.sdc(3106): mem|ddr4a|ddr4a|arch|arch_inst|seq_if_inst|afi_cal_success_sync_inst|din_s1|d could not be matched with a pin File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3106
|
|
Warning (332174): Ignored filter at dcp_bbs.sdc(3108): mem|ddr4a|ddr4a|arch|arch_inst|seq_if_inst|afi_cal_fail_sync_inst|din_s1|d could not be matched with a pin File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3108
|
|
Warning (332174): Ignored filter at dcp_bbs.sdc(3153): fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g* could not be matched with a keeper File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3153
|
|
Warning (332174): Ignored filter at dcp_bbs.sdc(3153): fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe* could not be matched with a keeper File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3153
|
|
Warning (332049): Ignored set_max_delay at dcp_bbs.sdc(3153): Argument <from> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3153
|
|
Info (332050): set_max_delay -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] 100.000 File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3153
|
|
Warning (332049): Ignored set_max_delay at dcp_bbs.sdc(3153): Argument <to> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3153
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Warning (332174): Ignored filter at dcp_bbs.sdc(3154): fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g* could not be matched with a keeper File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3154
|
|
Warning (332174): Ignored filter at dcp_bbs.sdc(3154): fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe* could not be matched with a keeper File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3154
|
|
Warning (332049): Ignored set_max_delay at dcp_bbs.sdc(3154): Argument <from> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3154
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|
Info (332050): set_max_delay -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] 100.000 File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3154
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|
Warning (332049): Ignored set_max_delay at dcp_bbs.sdc(3154): Argument <to> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3154
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|
Warning (332174): Ignored filter at dcp_bbs.sdc(3155): fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g* could not be matched with a keeper File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3155
|
|
Warning (332174): Ignored filter at dcp_bbs.sdc(3155): fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe* could not be matched with a keeper File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3155
|
|
Warning (332049): Ignored set_max_delay at dcp_bbs.sdc(3155): Argument <from> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3155
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|
Info (332050): set_max_delay -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] 100.000 File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3155
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|
Warning (332049): Ignored set_max_delay at dcp_bbs.sdc(3155): Argument <to> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3155
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|
Warning (332174): Ignored filter at dcp_bbs.sdc(3156): fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g* could not be matched with a keeper File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3156
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|
Warning (332174): Ignored filter at dcp_bbs.sdc(3156): fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe* could not be matched with a keeper File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3156
|
|
Warning (332049): Ignored set_max_delay at dcp_bbs.sdc(3156): Argument <from> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3156
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|
Info (332050): set_max_delay -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] 100.000 File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3156
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|
Warning (332049): Ignored set_max_delay at dcp_bbs.sdc(3156): Argument <to> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3156
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|
Warning (332174): Ignored filter at dcp_bbs.sdc(3157): fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g* could not be matched with a keeper File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3157
|
|
Warning (332174): Ignored filter at dcp_bbs.sdc(3157): fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe* could not be matched with a keeper File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3157
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|
Warning (332049): Ignored set_max_delay at dcp_bbs.sdc(3157): Argument <from> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3157
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|
Info (332050): set_max_delay -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] 100.000 File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3157
|
|
Warning (332049): Ignored set_max_delay at dcp_bbs.sdc(3157): Argument <to> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3157
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|
Warning (332174): Ignored filter at dcp_bbs.sdc(3158): fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g* could not be matched with a keeper File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3158
|
|
Warning (332174): Ignored filter at dcp_bbs.sdc(3158): fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe* could not be matched with a keeper File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3158
|
|
Warning (332049): Ignored set_max_delay at dcp_bbs.sdc(3158): Argument <from> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3158
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|
Info (332050): set_max_delay -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] 100.000 File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3158
|
|
Warning (332049): Ignored set_max_delay at dcp_bbs.sdc(3158): Argument <to> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3158
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|
Warning (332174): Ignored filter at dcp_bbs.sdc(3159): fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g* could not be matched with a keeper File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3159
|
|
Warning (332174): Ignored filter at dcp_bbs.sdc(3159): fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe* could not be matched with a keeper File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3159
|
|
Warning (332049): Ignored set_max_delay at dcp_bbs.sdc(3159): Argument <from> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3159
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|
Info (332050): set_max_delay -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] 100.000 File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3159
|
|
Warning (332049): Ignored set_max_delay at dcp_bbs.sdc(3159): Argument <to> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3159
|
|
Warning (332174): Ignored filter at dcp_bbs.sdc(3160): fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g* could not be matched with a keeper File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3160
|
|
Warning (332174): Ignored filter at dcp_bbs.sdc(3160): fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe* could not be matched with a keeper File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3160
|
|
Warning (332049): Ignored set_max_delay at dcp_bbs.sdc(3160): Argument <from> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3160
|
|
Info (332050): set_max_delay -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] 100.000 File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3160
|
|
Warning (332049): Ignored set_max_delay at dcp_bbs.sdc(3160): Argument <to> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3160
|
|
Warning (332174): Ignored filter at dcp_bbs.sdc(3161): fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|SoftReset_mem could not be matched with a keeper File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3161
|
|
Warning (332174): Ignored filter at dcp_bbs.sdc(3161): fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4*_mem_if|ddr_reset_sync|resync_chains[0].synchronizer_nocut|*|clrn could not be matched with a pin File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3161
|
|
Warning (332049): Ignored set_max_delay at dcp_bbs.sdc(3161): Argument <from> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3161
|
|
Info (332050): set_max_delay -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|SoftReset_mem}] -to [get_pins {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4*_mem_if|ddr_reset_sync|resync_chains[0].synchronizer_nocut|*|clrn}] 100.000 File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3161
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|
Warning (332049): Ignored set_max_delay at dcp_bbs.sdc(3161): Argument <to> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3161
|
|
Warning (332174): Ignored filter at dcp_bbs.sdc(3162): fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4*_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|wraclr|*|clrn could not be matched with a pin File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3162
|
|
Warning (332049): Ignored set_max_delay at dcp_bbs.sdc(3162): Argument <from> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3162
|
|
Info (332050): set_max_delay -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|SoftReset_mem}] -to [get_pins {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4*_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|wraclr|*|clrn}] 100.000 File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3162
|
|
Warning (332049): Ignored set_max_delay at dcp_bbs.sdc(3162): Argument <to> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3162
|
|
Warning (332174): Ignored filter at dcp_bbs.sdc(3163): fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4*_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|rdaclr|*|clrn could not be matched with a pin File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3163
|
|
Warning (332049): Ignored set_max_delay at dcp_bbs.sdc(3163): Argument <from> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3163
|
|
Info (332050): set_max_delay -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|SoftReset_mem}] -to [get_pins {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4*_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|rdaclr|*|clrn}] 100.000 File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3163
|
|
Warning (332049): Ignored set_max_delay at dcp_bbs.sdc(3163): Argument <to> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3163
|
|
Warning (332174): Ignored filter at dcp_bbs.sdc(3164): fpga_top|inst_green_bs|inst_ccip_std_afu|inst_green_ccip_interface_reg|pck_cp2af_softReset_T0_q could not be matched with a keeper File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3164
|
|
Warning (332174): Ignored filter at dcp_bbs.sdc(3164): fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|Clk_100_reset_sync|resync_chains[0].synchronizer_nocut|*|clrn could not be matched with a pin File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3164
|
|
Warning (332049): Ignored set_max_delay at dcp_bbs.sdc(3164): Argument <from> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3164
|
|
Info (332050): set_max_delay -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|inst_green_ccip_interface_reg|pck_cp2af_softReset_T0_q}] -to [get_pins {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|Clk_100_reset_sync|resync_chains[0].synchronizer_nocut|*|clrn}] 100.000 File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3164
|
|
Warning (332049): Ignored set_max_delay at dcp_bbs.sdc(3164): Argument <to> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3164
|
|
Warning (332049): Ignored set_min_delay at dcp_bbs.sdc(3200): Argument <from> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3200
|
|
Info (332050): set_min_delay -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -100.000 File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3200
|
|
Warning (332049): Ignored set_min_delay at dcp_bbs.sdc(3200): Argument <to> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3200
|
|
Warning (332049): Ignored set_min_delay at dcp_bbs.sdc(3201): Argument <from> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3201
|
|
Info (332050): set_min_delay -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -100.000 File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3201
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|
Warning (332049): Ignored set_min_delay at dcp_bbs.sdc(3201): Argument <to> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3201
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|
Warning (332049): Ignored set_min_delay at dcp_bbs.sdc(3202): Argument <from> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3202
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|
Info (332050): set_min_delay -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -100.000 File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3202
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|
Warning (332049): Ignored set_min_delay at dcp_bbs.sdc(3202): Argument <to> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3202
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|
Warning (332049): Ignored set_min_delay at dcp_bbs.sdc(3203): Argument <from> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3203
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|
Info (332050): set_min_delay -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -100.000 File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3203
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|
Warning (332049): Ignored set_min_delay at dcp_bbs.sdc(3203): Argument <to> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3203
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|
Warning (332049): Ignored set_min_delay at dcp_bbs.sdc(3204): Argument <from> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3204
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|
Info (332050): set_min_delay -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -100.000 File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3204
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|
Warning (332049): Ignored set_min_delay at dcp_bbs.sdc(3204): Argument <to> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3204
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|
Warning (332049): Ignored set_min_delay at dcp_bbs.sdc(3205): Argument <from> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3205
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|
Info (332050): set_min_delay -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -100.000 File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3205
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|
Warning (332049): Ignored set_min_delay at dcp_bbs.sdc(3205): Argument <to> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3205
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|
Warning (332049): Ignored set_min_delay at dcp_bbs.sdc(3206): Argument <from> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3206
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|
Info (332050): set_min_delay -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -100.000 File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3206
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|
Warning (332049): Ignored set_min_delay at dcp_bbs.sdc(3206): Argument <to> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3206
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Warning (332049): Ignored set_min_delay at dcp_bbs.sdc(3207): Argument <from> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3207
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Info (332050): set_min_delay -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -100.000 File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3207
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|
Warning (332049): Ignored set_min_delay at dcp_bbs.sdc(3207): Argument <to> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3207
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|
Warning (332049): Ignored set_min_delay at dcp_bbs.sdc(3208): Argument <from> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3208
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Info (332050): set_min_delay -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|SoftReset_mem}] -to [get_pins {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4*_mem_if|ddr_reset_sync|resync_chains[0].synchronizer_nocut|*|clrn}] -100.000 File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3208
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Warning (332049): Ignored set_min_delay at dcp_bbs.sdc(3208): Argument <to> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3208
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Warning (332049): Ignored set_min_delay at dcp_bbs.sdc(3209): Argument <from> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3209
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|
Info (332050): set_min_delay -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|SoftReset_mem}] -to [get_pins {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4*_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|wraclr|*|clrn}] -100.000 File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3209
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|
Warning (332049): Ignored set_min_delay at dcp_bbs.sdc(3209): Argument <to> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3209
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|
Warning (332049): Ignored set_min_delay at dcp_bbs.sdc(3210): Argument <from> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3210
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|
Info (332050): set_min_delay -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|SoftReset_mem}] -to [get_pins {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4*_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|rdaclr|*|clrn}] -100.000 File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3210
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Warning (332049): Ignored set_min_delay at dcp_bbs.sdc(3210): Argument <to> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3210
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Warning (332049): Ignored set_min_delay at dcp_bbs.sdc(3211): Argument <from> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3211
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Info (332050): set_min_delay -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|inst_green_ccip_interface_reg|pck_cp2af_softReset_T0_q}] -to [get_pins {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|Clk_100_reset_sync|resync_chains[0].synchronizer_nocut|*|clrn}] -100.000 File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3211
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Warning (332049): Ignored set_min_delay at dcp_bbs.sdc(3211): Argument <to> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3211
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Warning (332049): Ignored set_net_delay at dcp_bbs.sdc(3252): argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] contains zero elements File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3252
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|
Info (332050): set_net_delay -max -value_multiplier 0.800 -get_value_from_clock_period dst_clock_period -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3252
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|
Warning (332049): Ignored set_net_delay at dcp_bbs.sdc(3253): argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] contains zero elements File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3253
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|
Info (332050): set_net_delay -max -value_multiplier 0.800 -get_value_from_clock_period dst_clock_period -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3253
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Warning (332049): Ignored set_net_delay at dcp_bbs.sdc(3254): argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] contains zero elements File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3254
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|
Info (332050): set_net_delay -max -value_multiplier 0.800 -get_value_from_clock_period dst_clock_period -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3254
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|
Warning (332049): Ignored set_net_delay at dcp_bbs.sdc(3255): argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] contains zero elements File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3255
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|
Info (332050): set_net_delay -max -value_multiplier 0.800 -get_value_from_clock_period dst_clock_period -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3255
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|
Warning (332049): Ignored set_net_delay at dcp_bbs.sdc(3256): argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] contains zero elements File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3256
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|
Info (332050): set_net_delay -max -value_multiplier 0.800 -get_value_from_clock_period dst_clock_period -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3256
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|
Warning (332049): Ignored set_net_delay at dcp_bbs.sdc(3257): argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] contains zero elements File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3257
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|
Info (332050): set_net_delay -max -value_multiplier 0.800 -get_value_from_clock_period dst_clock_period -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3257
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|
Warning (332049): Ignored set_net_delay at dcp_bbs.sdc(3258): argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] contains zero elements File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3258
|
|
Info (332050): set_net_delay -max -value_multiplier 0.800 -get_value_from_clock_period dst_clock_period -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3258
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|
Warning (332049): Ignored set_net_delay at dcp_bbs.sdc(3259): argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] contains zero elements File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3259
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|
Info (332050): set_net_delay -max -value_multiplier 0.800 -get_value_from_clock_period dst_clock_period -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3259
|
|
Warning (332049): Ignored set_net_delay at dcp_bbs.sdc(3260): argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] contains zero elements File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3260
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Info (332050): set_net_delay -max -value_multiplier 0.800 -get_value_from_clock_period dst_clock_period -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3260
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Warning (332049): Ignored set_net_delay at dcp_bbs.sdc(3261): argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] contains zero elements File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3261
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Info (332050): set_net_delay -max -value_multiplier 0.800 -get_value_from_clock_period dst_clock_period -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3261
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Warning (332049): Ignored set_net_delay at dcp_bbs.sdc(3262): argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] contains zero elements File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3262
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Info (332050): set_net_delay -max -value_multiplier 0.800 -get_value_from_clock_period dst_clock_period -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3262
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Warning (332049): Ignored set_net_delay at dcp_bbs.sdc(3263): argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] contains zero elements File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3263
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Info (332050): set_net_delay -max -value_multiplier 0.800 -get_value_from_clock_period dst_clock_period -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3263
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Warning (332049): Ignored set_net_delay at dcp_bbs.sdc(3264): argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] contains zero elements File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3264
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Info (332050): set_net_delay -max -value_multiplier 0.800 -get_value_from_clock_period dst_clock_period -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3264
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Warning (332049): Ignored set_net_delay at dcp_bbs.sdc(3265): argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] contains zero elements File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3265
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Info (332050): set_net_delay -max -value_multiplier 0.800 -get_value_from_clock_period dst_clock_period -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3265
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Warning (332049): Ignored set_net_delay at dcp_bbs.sdc(3266): argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] contains zero elements File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3266
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Info (332050): set_net_delay -max -value_multiplier 0.800 -get_value_from_clock_period dst_clock_period -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3266
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Warning (332049): Ignored set_net_delay at dcp_bbs.sdc(3267): argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] contains zero elements File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3267
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Info (332050): set_net_delay -max -value_multiplier 0.800 -get_value_from_clock_period dst_clock_period -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3267
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Warning (332049): Ignored set_max_skew at dcp_bbs.sdc(3316): Argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] contains zero elements File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3316
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Info (332050): set_max_skew -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3316
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Warning (332049): Ignored set_max_skew at dcp_bbs.sdc(3316): Argument -to with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] contains zero elements File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3316
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Warning (332049): Ignored set_max_skew at dcp_bbs.sdc(3317): Argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] contains zero elements File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3317
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Info (332050): set_max_skew -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3317
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Warning (332049): Ignored set_max_skew at dcp_bbs.sdc(3317): Argument -to with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] contains zero elements File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3317
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Warning (332049): Ignored set_max_skew at dcp_bbs.sdc(3318): Argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] contains zero elements File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3318
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Info (332050): set_max_skew -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3318
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Warning (332049): Ignored set_max_skew at dcp_bbs.sdc(3318): Argument -to with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] contains zero elements File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3318
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Warning (332049): Ignored set_max_skew at dcp_bbs.sdc(3319): Argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] contains zero elements File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3319
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Info (332050): set_max_skew -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3319
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Warning (332049): Ignored set_max_skew at dcp_bbs.sdc(3319): Argument -to with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] contains zero elements File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3319
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Warning (332049): Ignored set_max_skew at dcp_bbs.sdc(3320): Argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] contains zero elements File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3320
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Info (332050): set_max_skew -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3320
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Warning (332049): Ignored set_max_skew at dcp_bbs.sdc(3320): Argument -to with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] contains zero elements File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3320
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Warning (332049): Ignored set_max_skew at dcp_bbs.sdc(3321): Argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] contains zero elements File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3321
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Info (332050): set_max_skew -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3321
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Warning (332049): Ignored set_max_skew at dcp_bbs.sdc(3321): Argument -to with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] contains zero elements File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3321
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Warning (332049): Ignored set_max_skew at dcp_bbs.sdc(3322): Argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] contains zero elements File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3322
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|
Info (332050): set_max_skew -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3322
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Warning (332049): Ignored set_max_skew at dcp_bbs.sdc(3322): Argument -to with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] contains zero elements File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3322
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Warning (332049): Ignored set_max_skew at dcp_bbs.sdc(3323): Argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] contains zero elements File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3323
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Info (332050): set_max_skew -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3323
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|
Warning (332049): Ignored set_max_skew at dcp_bbs.sdc(3323): Argument -to with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] contains zero elements File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3323
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|
Warning (332049): Ignored set_max_skew at dcp_bbs.sdc(3324): Argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|SoftReset_mem}] contains zero elements File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3324
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|
Info (332050): set_max_skew -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|SoftReset_mem}] -to [get_pins {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4*_mem_if|ddr_reset_sync|resync_chains[0].synchronizer_nocut|*|clrn}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3324
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|
Warning (332049): Ignored set_max_skew at dcp_bbs.sdc(3324): Argument -to with value [get_pins {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4*_mem_if|ddr_reset_sync|resync_chains[0].synchronizer_nocut|*|clrn}] contains zero elements File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3324
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|
Warning (332049): Ignored set_max_skew at dcp_bbs.sdc(3325): Argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|SoftReset_mem}] contains zero elements File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3325
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|
Info (332050): set_max_skew -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|SoftReset_mem}] -to [get_pins {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4*_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|wraclr|*|clrn}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3325
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Warning (332049): Ignored set_max_skew at dcp_bbs.sdc(3325): Argument -to with value [get_pins {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4*_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|wraclr|*|clrn}] contains zero elements File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3325
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|
Warning (332049): Ignored set_max_skew at dcp_bbs.sdc(3326): Argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|SoftReset_mem}] contains zero elements File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3326
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|
Info (332050): set_max_skew -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|SoftReset_mem}] -to [get_pins {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4*_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|rdaclr|*|clrn}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3326
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|
Warning (332049): Ignored set_max_skew at dcp_bbs.sdc(3326): Argument -to with value [get_pins {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4*_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|rdaclr|*|clrn}] contains zero elements File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3326
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|
Warning (332049): Ignored set_max_skew at dcp_bbs.sdc(3327): Argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|inst_green_ccip_interface_reg|pck_cp2af_softReset_T0_q}] contains zero elements File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3327
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|
Info (332050): set_max_skew -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|inst_green_ccip_interface_reg|pck_cp2af_softReset_T0_q}] -to [get_pins {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|Clk_100_reset_sync|resync_chains[0].synchronizer_nocut|*|clrn}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3327
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|
Warning (332049): Ignored set_max_skew at dcp_bbs.sdc(3327): Argument -to with value [get_pins {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|Clk_100_reset_sync|resync_chains[0].synchronizer_nocut|*|clrn}] contains zero elements File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3327
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|
Info (332104): Reading SDC File: 'platform/green_bs.sdc'
|
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Info (332104): Reading SDC File: 'dcp_user_clocks.sdc'
|
|
Info: Target user clock high: auto (220)
|
|
Info: Target user clock low: auto (110.0)
|
|
Warning (332043): Overwriting existing clock: fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk0
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|
Warning (332043): Overwriting existing clock: fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk1
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|
Critical Warning (19294): Synopsys Design Constraints File file not found for instance '': '/nfs/site/disks/pac_build_1/psgpacbuild/SC/adapt/nightly/19.1/367/l64/work/platform/dcp_1.0-rc/build/qdb/_compiler/dcp/_flat/19.2.0/partitioned/1/.temp/sld_fabrics/ipgen/alt_sld_fab_0/alt_sld_fab_0/altera_avalon_dc_fifo_191/synth/alt_sld_fab_0_altera_avalon_dc_fifo_191_27jzy3q.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
|
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Critical Warning (19294): Synopsys Design Constraints File file not found for instance '': '/nfs/site/disks/pac_build_1/psgpacbuild/SC/adapt/nightly/19.1/367/l64/work/platform/dcp_1.0-rc/build/qdb/_compiler/dcp/_flat/19.2.0/partitioned/1/.temp/sld_fabrics/ipgen/alt_sld_fab_0/alt_sld_fab_0/altera_jtag_dc_streaming_191/synth/altera_avalon_st_jtag_interface.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
|
|
Critical Warning (19294): Synopsys Design Constraints File file not found for instance '': '/nfs/site/disks/pac_build_1/psgpacbuild/SC/adapt/nightly/19.1/367/l64/work/platform/dcp_1.0-rc/build/qdb/_compiler/dcp/_flat/19.2.0/partitioned/1/.temp/sld_fabrics/ipgen/alt_sld_fab_0/alt_sld_fab_0/altera_reset_controller_191/synth/altera_reset_controller.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
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Critical Warning (19294): Synopsys Design Constraints File file not found for instance '': '/p/psg/swip/releases/acds/19.2/57/linux64/ip/altera/sld/jtag/altera_jtag_wys_atom/default_jtag.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
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Info (19449): Reading SDC files elapsed 00:00:10.
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Info (332097): The following timing edges are non-unate. The Timing Analyzer will assume pos-unate behavior for these edges in the clock network.
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Info (332098): Cell: mem|ddr4a|ddr4a|arch|arch_inst|bufs_inst|gen_mem_dqs.inst[0].b|cal_oct.obuf from: oe to: o
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Info (332098): Cell: mem|ddr4a|ddr4a|arch|arch_inst|bufs_inst|gen_mem_dqs.inst[1].b|cal_oct.obuf from: oe to: o
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Info (332098): Cell: mem|ddr4a|ddr4a|arch|arch_inst|bufs_inst|gen_mem_dqs.inst[2].b|cal_oct.obuf from: oe to: o
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Info (332098): Cell: mem|ddr4a|ddr4a|arch|arch_inst|bufs_inst|gen_mem_dqs.inst[3].b|cal_oct.obuf from: oe to: o
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Info (332098): Cell: mem|ddr4a|ddr4a|arch|arch_inst|bufs_inst|gen_mem_dqs.inst[4].b|cal_oct.obuf from: oe to: o
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Info (332098): Cell: mem|ddr4a|ddr4a|arch|arch_inst|bufs_inst|gen_mem_dqs.inst[5].b|cal_oct.obuf from: oe to: o
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Info (332098): Cell: mem|ddr4a|ddr4a|arch|arch_inst|bufs_inst|gen_mem_dqs.inst[6].b|cal_oct.obuf from: oe to: o
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Info (332098): Cell: mem|ddr4a|ddr4a|arch|arch_inst|bufs_inst|gen_mem_dqs.inst[7].b|cal_oct.obuf from: oe to: o
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Info (332098): Cell: mem|ddr4b|ddr4b|arch|arch_inst|bufs_inst|gen_mem_dqs.inst[0].b|cal_oct.obuf from: oe to: o
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Info (332098): Cell: mem|ddr4b|ddr4b|arch|arch_inst|bufs_inst|gen_mem_dqs.inst[1].b|cal_oct.obuf from: oe to: o
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Info (332098): Cell: mem|ddr4b|ddr4b|arch|arch_inst|bufs_inst|gen_mem_dqs.inst[2].b|cal_oct.obuf from: oe to: o
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Info (332098): Cell: mem|ddr4b|ddr4b|arch|arch_inst|bufs_inst|gen_mem_dqs.inst[3].b|cal_oct.obuf from: oe to: o
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Info (332098): Cell: mem|ddr4b|ddr4b|arch|arch_inst|bufs_inst|gen_mem_dqs.inst[4].b|cal_oct.obuf from: oe to: o
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Info (332098): Cell: mem|ddr4b|ddr4b|arch|arch_inst|bufs_inst|gen_mem_dqs.inst[5].b|cal_oct.obuf from: oe to: o
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Info (332098): Cell: mem|ddr4b|ddr4b|arch|arch_inst|bufs_inst|gen_mem_dqs.inst[6].b|cal_oct.obuf from: oe to: o
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Info (332098): Cell: mem|ddr4b|ddr4b|arch|arch_inst|bufs_inst|gen_mem_dqs.inst[7].b|cal_oct.obuf from: oe to: o
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Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties.
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Info (332152): The following assignments are ignored by the derive_clock_uncertainty command
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Warning (332056): PLL cross checking found inconsistent PLL clock settings:
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Warning (332056): Clock: fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk0 was found on node: fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|fpll_inst|outclk[0] with settings that do not match the following PLL specifications:
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Warning (332056): -multiply_by (expected: 25, found: 1100), -divide_by (expected: 16, found: 1000)
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Warning (332056): Clock: fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk1 was found on node: fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|fpll_inst|outclk[1] with settings that do not match the following PLL specifications:
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Warning (332056): -multiply_by (expected: 25, found: 2200), -divide_by (expected: 8, found: 1000)
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Warning (332056): Clock: hssi_pll_t_outclk0 with period: 3.200 found on PLL node: fpga_top|inst_fiu_top|inst_hssi_ctrl|pll_t|xcvr_fpll_a10_0|fpll_inst|outclk[0] does not match the period requirement: 6.400
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Warning (332056): Clock: hssi_pll_t_outclk1 with period: 3.800 found on PLL node: fpga_top|inst_fiu_top|inst_hssi_ctrl|pll_t|xcvr_fpll_a10_0|fpll_inst|outclk[1] does not match the period requirement: 6.400
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Warning (332056): Clock: hssi_pll_r_0_outclk0 with period: 3.200 found on PLL node: fpga_top|inst_fiu_top|inst_hssi_ctrl|pll_r_0|xcvr_fpll_a10_0|fpll_inst|outclk[0] does not match the period requirement: 6.400
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Warning (332056): Clock: hssi_pll_r_0_outclk1 with period: 3.800 found on PLL node: fpga_top|inst_fiu_top|inst_hssi_ctrl|pll_r_0|xcvr_fpll_a10_0|fpll_inst|outclk[1] does not match the period requirement: 6.400
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Info (332171): The following clock uncertainty values are less than the recommended values that would be applied by the derive_clock_uncertainty command
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Info (332172): Setup clock transfer from mem|ddr4b|ddr4b_phy_clk_0 (Rise) to mem|ddr4a|ddr4a_core_usr_clk (Rise) has uncertainty 0.268 that is less than the recommended uncertainty 0.360
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Info (332172): Hold clock transfer from mem|ddr4b|ddr4b_phy_clk_0 (Rise) to mem|ddr4a|ddr4a_core_usr_clk (Rise) has uncertainty 0.272 that is less than the recommended uncertainty 0.360
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Info (332172): Setup clock transfer from mem|ddr4b|ddr4b_phy_clk_l_0 (Rise) to mem|ddr4a|ddr4a_core_usr_clk (Rise) has uncertainty 0.268 that is less than the recommended uncertainty 0.360
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Info (332172): Hold clock transfer from mem|ddr4b|ddr4b_phy_clk_l_0 (Rise) to mem|ddr4a|ddr4a_core_usr_clk (Rise) has uncertainty 0.272 that is less than the recommended uncertainty 0.360
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Info (332172): Setup clock transfer from mem|ddr4b|ddr4b_phy_clk_l_1 (Rise) to mem|ddr4a|ddr4a_core_usr_clk (Rise) has uncertainty 0.268 that is less than the recommended uncertainty 0.360
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Info (332172): Hold clock transfer from mem|ddr4b|ddr4b_phy_clk_l_1 (Rise) to mem|ddr4a|ddr4a_core_usr_clk (Rise) has uncertainty 0.272 that is less than the recommended uncertainty 0.360
|
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Info (332172): Setup clock transfer from mem|ddr4b|ddr4b_phy_clk_l_2 (Rise) to mem|ddr4a|ddr4a_core_usr_clk (Rise) has uncertainty 0.268 that is less than the recommended uncertainty 0.360
|
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Info (332172): Hold clock transfer from mem|ddr4b|ddr4b_phy_clk_l_2 (Rise) to mem|ddr4a|ddr4a_core_usr_clk (Rise) has uncertainty 0.272 that is less than the recommended uncertainty 0.360
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Info (332172): Setup clock transfer from mem|ddr4a|ddr4a_phy_clk_l_1 (Rise) to mem|ddr4a|ddr4a_core_usr_clk (Rise) has uncertainty 0.268 that is less than the recommended uncertainty 0.360
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Info (332172): Hold clock transfer from mem|ddr4a|ddr4a_phy_clk_l_1 (Rise) to mem|ddr4a|ddr4a_core_usr_clk (Rise) has uncertainty 0.272 that is less than the recommended uncertainty 0.360
|
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Info (332172): Setup clock transfer from mem|ddr4a|ddr4a_phy_clk_l_2 (Rise) to mem|ddr4a|ddr4a_core_usr_clk (Rise) has uncertainty 0.268 that is less than the recommended uncertainty 0.360
|
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Info (332172): Hold clock transfer from mem|ddr4a|ddr4a_phy_clk_l_2 (Rise) to mem|ddr4a|ddr4a_core_usr_clk (Rise) has uncertainty 0.272 that is less than the recommended uncertainty 0.360
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Info (332172): Setup clock transfer from mem|ddr4a|ddr4a_core_usr_clk (Rise) to mem|ddr4b|ddr4b_phy_clk_l_0 (Rise) has uncertainty 0.289 that is less than the recommended uncertainty 0.360
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Info (332172): Hold clock transfer from mem|ddr4a|ddr4a_core_usr_clk (Rise) to mem|ddr4b|ddr4b_phy_clk_l_0 (Rise) has uncertainty 0.320 that is less than the recommended uncertainty 0.360
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Info (332172): Setup clock transfer from mem|ddr4a|ddr4a_core_usr_clk (Rise) to mem|ddr4b|ddr4b_phy_clk_l_1 (Rise) has uncertainty 0.289 that is less than the recommended uncertainty 0.360
|
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Info (332172): Hold clock transfer from mem|ddr4a|ddr4a_core_usr_clk (Rise) to mem|ddr4b|ddr4b_phy_clk_l_1 (Rise) has uncertainty 0.320 that is less than the recommended uncertainty 0.360
|
|
Info (332172): Setup clock transfer from mem|ddr4a|ddr4a_core_usr_clk (Rise) to mem|ddr4b|ddr4b_phy_clk_l_2 (Rise) has uncertainty 0.289 that is less than the recommended uncertainty 0.360
|
|
Info (332172): Hold clock transfer from mem|ddr4a|ddr4a_core_usr_clk (Rise) to mem|ddr4b|ddr4b_phy_clk_l_2 (Rise) has uncertainty 0.320 that is less than the recommended uncertainty 0.360
|
|
Info (332172): Setup clock transfer from mem|ddr4a|ddr4a_core_usr_clk (Rise) to mem|ddr4a|ddr4a_phy_clk_l_1 (Rise) has uncertainty 0.289 that is less than the recommended uncertainty 0.360
|
|
Info (332172): Hold clock transfer from mem|ddr4a|ddr4a_core_usr_clk (Rise) to mem|ddr4a|ddr4a_phy_clk_l_1 (Rise) has uncertainty 0.320 that is less than the recommended uncertainty 0.360
|
|
Info (332172): Setup clock transfer from mem|ddr4a|ddr4a_core_usr_clk (Rise) to mem|ddr4a|ddr4a_phy_clk_l_2 (Rise) has uncertainty 0.289 that is less than the recommended uncertainty 0.360
|
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Info (332172): Hold clock transfer from mem|ddr4a|ddr4a_core_usr_clk (Rise) to mem|ddr4a|ddr4a_phy_clk_l_2 (Rise) has uncertainty 0.320 that is less than the recommended uncertainty 0.360
|
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Warning (332088): No paths exist between clock target "fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MOSIctl|filtered_sclk_negedge|q" of clock "filtered_sclk_negedge" and its clock source. Assuming zero source clock latency.
|
|
Info: Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
|
|
Info: Analyzing Slow 900mV 100C Model
|
|
Critical Warning (332148): Timing requirements not met
|
|
Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer.
|
|
Info (332146): Worst-case setup slack is -1.430
|
|
Info (332119): Slack End Point TNS Clock
|
|
Info (332119): ========= =================== =====================
|
|
Info (332119): -1.430 -28274.639 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk1
|
|
Info (332119): 0.028 0.000 mem|ddr4a|ddr4a_phy_clk_l_2
|
|
Info (332119): 0.079 0.000 mem|ddr4a|ddr4a_phy_clk_l_1
|
|
Info (332119): 0.084 0.000 mem|ddr4b|ddr4b_phy_clk_l_1
|
|
Info (332119): 0.097 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|wys~CORE_CLK_OUT
|
|
Info (332119): 0.126 0.000 mem|ddr4b|ddr4b_phy_clk_l_0
|
|
Info (332119): 0.186 0.000 mem|ddr4a|ddr4a_core_usr_clk
|
|
Info (332119): 0.294 0.000 mem|ddr4b|ddr4b_phy_clk_l_2
|
|
Info (332119): 0.506 0.000 u0|dcp_iopll|dcp_iopll|clk1x
|
|
Info (332119): 0.539 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_bonding_clocks[0]
|
|
Info (332119): 0.565 0.000 u0|dcp_iopll|dcp_iopll|clk100
|
|
Info (332119): 0.603 0.000 mem|ddr4a|ddr4a_phy_clk_l_0
|
|
Info (332119): 0.636 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|pld_clk
|
|
Info (332119): 1.057 0.000 PCIE_REFCLK
|
|
Info (332119): 1.217 0.000 mem|ddr4a|ddr4a_core_cal_slave_clk
|
|
Info (332119): 1.585 0.000 SYS_RefClk
|
|
Info (332119): 2.294 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_clk
|
|
Info (332119): 2.305 0.000 ETH_RefClk
|
|
Info (332119): 2.305 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|rx_pma_clk
|
|
Info (332119): 2.308 0.000 DDR4_RefClk
|
|
Info (332119): 2.315 0.000 hssi_pll_r_0_outclk0
|
|
Info (332119): 2.357 0.000 hssi_pll_t_outclk0
|
|
Info (332119): 2.439 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|rx_pma_clk
|
|
Info (332119): 2.532 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|rx_pma_clk
|
|
Info (332119): 2.944 0.000 hssi_pll_r_0_outclk1
|
|
Info (332119): 2.986 0.000 hssi_pll_t_outclk1
|
|
Info (332119): 3.210 0.000 vl_qph_user_clk_clkpsc_clk1
|
|
Info (332119): 3.381 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|avmmclk
|
|
Info (332119): 3.496 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|avmmclk
|
|
Info (332119): 3.675 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|avmmclk
|
|
Info (332119): 4.499 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|avmmclk
|
|
Info (332119): 4.502 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|avmmclk
|
|
Info (332119): 4.768 0.000 fspi_sclk
|
|
Info (332119): 4.946 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|avmmclk
|
|
Info (332119): 5.231 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|avmmclk
|
|
Info (332119): 5.508 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|avmmclk
|
|
Info (332119): 5.547 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|tx_pma_div_clk
|
|
Info (332119): 5.666 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_div_clk
|
|
Info (332119): 5.834 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|avmmclk
|
|
Info (332119): 6.158 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|avmmclk
|
|
Info (332119): 6.426 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|avmmclk
|
|
Info (332119): 7.436 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|avmmclk
|
|
Info (332119): 7.755 0.000 vl_qph_user_clk_clkpsc_clk0
|
|
Info (332119): 8.557 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk0
|
|
Info (332119): 10.498 0.000 pr_clk_enable_dclk_reg2_user_clk
|
|
Info (332119): 18.260 0.000 u0|dcp_iopll|dcp_iopll|clk25
|
|
Info (332119): 19.306 0.000 u0|dcp_iopll|dcp_iopll|clk50
|
|
Info (332119): 19.717 0.000 filtered_sclk_negedge
|
|
Info (332119): 40.325 0.000 altera_reserved_tck
|
|
Info (332146): Worst-case hold slack is 0.033
|
|
Info (332119): Slack End Point TNS Clock
|
|
Info (332119): ========= =================== =====================
|
|
Info (332119): 0.033 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk1
|
|
Info (332119): 0.044 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|wys~CORE_CLK_OUT
|
|
Info (332119): 0.047 0.000 u0|dcp_iopll|dcp_iopll|clk1x
|
|
Info (332119): 0.048 0.000 SYS_RefClk
|
|
Info (332119): 0.051 0.000 u0|dcp_iopll|dcp_iopll|clk25
|
|
Info (332119): 0.052 0.000 altera_reserved_tck
|
|
Info (332119): 0.053 0.000 mem|ddr4a|ddr4a_core_usr_clk
|
|
Info (332119): 0.054 0.000 PCIE_REFCLK
|
|
Info (332119): 0.055 0.000 u0|dcp_iopll|dcp_iopll|clk100
|
|
Info (332119): 0.057 0.000 DDR4_RefClk
|
|
Info (332119): 0.059 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|rx_pma_clk
|
|
Info (332119): 0.059 0.000 mem|ddr4a|ddr4a_core_cal_slave_clk
|
|
Info (332119): 0.060 0.000 filtered_sclk_negedge
|
|
Info (332119): 0.064 0.000 hssi_pll_t_outclk1
|
|
Info (332119): 0.068 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_clk
|
|
Info (332119): 0.069 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_div_clk
|
|
Info (332119): 0.077 0.000 hssi_pll_r_0_outclk0
|
|
Info (332119): 0.078 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|tx_pma_div_clk
|
|
Info (332119): 0.087 0.000 hssi_pll_r_0_outclk1
|
|
Info (332119): 0.090 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|rx_pma_clk
|
|
Info (332119): 0.095 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk0
|
|
Info (332119): 0.097 0.000 ETH_RefClk
|
|
Info (332119): 0.097 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|rx_pma_clk
|
|
Info (332119): 0.097 0.000 hssi_pll_t_outclk0
|
|
Info (332119): 0.114 0.000 u0|dcp_iopll|dcp_iopll|clk50
|
|
Info (332119): 0.141 0.000 fspi_sclk
|
|
Info (332119): 0.220 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_bonding_clocks[0]
|
|
Info (332119): 0.241 0.000 mem|ddr4a|ddr4a_phy_clk_l_2
|
|
Info (332119): 0.264 0.000 mem|ddr4a|ddr4a_phy_clk_l_1
|
|
Info (332119): 0.296 0.000 mem|ddr4a|ddr4a_phy_clk_l_0
|
|
Info (332119): 0.304 0.000 mem|ddr4b|ddr4b_phy_clk_l_0
|
|
Info (332119): 0.304 0.000 mem|ddr4b|ddr4b_phy_clk_l_1
|
|
Info (332119): 0.318 0.000 mem|ddr4b|ddr4b_phy_clk_l_2
|
|
Info (332119): 0.446 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|pld_clk
|
|
Info (332119): 0.639 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|avmmclk
|
|
Info (332119): 0.680 0.000 vl_qph_user_clk_clkpsc_clk0
|
|
Info (332119): 0.680 0.000 vl_qph_user_clk_clkpsc_clk1
|
|
Info (332119): 0.742 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|avmmclk
|
|
Info (332119): 0.826 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|avmmclk
|
|
Info (332119): 0.871 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|avmmclk
|
|
Info (332119): 0.980 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|avmmclk
|
|
Info (332119): 0.995 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|avmmclk
|
|
Info (332119): 1.061 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|avmmclk
|
|
Info (332119): 1.174 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|avmmclk
|
|
Info (332119): 1.257 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|avmmclk
|
|
Info (332119): 1.437 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|avmmclk
|
|
Info (332119): 1.552 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|avmmclk
|
|
Info (332119): 1.795 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|avmmclk
|
|
Info (332119): 6.829 0.000 pr_clk_enable_dclk_reg2_user_clk
|
|
Info (332146): Worst-case recovery slack is 0.254
|
|
Info (332119): Slack End Point TNS Clock
|
|
Info (332119): ========= =================== =====================
|
|
Info (332119): 0.254 0.000 mem|ddr4a|ddr4a_core_usr_clk
|
|
Info (332119): 0.554 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|wys~CORE_CLK_OUT
|
|
Info (332119): 0.855 0.000 u0|dcp_iopll|dcp_iopll|clk1x
|
|
Info (332119): 1.183 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk1
|
|
Info (332119): 1.215 0.000 u0|dcp_iopll|dcp_iopll|clk100
|
|
Info (332119): 1.954 0.000 SYS_RefClk
|
|
Info (332119): 2.123 0.000 mem|ddr4a|ddr4a_core_cal_slave_clk
|
|
Info (332119): 2.130 0.000 filtered_sclk_negedge
|
|
Info (332119): 2.565 0.000 u0|dcp_iopll|dcp_iopll|clk25
|
|
Info (332119): 2.859 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|rx_pma_clk
|
|
Info (332119): 2.863 0.000 DDR4_RefClk
|
|
Info (332119): 2.940 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_clk
|
|
Info (332119): 2.948 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|rx_pma_clk
|
|
Info (332119): 3.036 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|rx_pma_clk
|
|
Info (332119): 4.660 0.000 fspi_sclk
|
|
Info (332119): 4.939 0.000 PCIE_REFCLK
|
|
Info (332119): 14.727 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|rx_fref
|
|
Info (332119): 15.188 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|rx_fref
|
|
Info (332119): 15.297 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|rx_fref
|
|
Info (332119): 15.322 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|rx_fref
|
|
Info (332119): 15.355 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|rx_fref
|
|
Info (332119): 15.588 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|rx_fref
|
|
Info (332119): 15.607 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|rx_fref
|
|
Info (332119): 16.480 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|rx_pma_clk
|
|
Info (332119): 16.805 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332119): 16.944 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|rx_pma_clk
|
|
Info (332119): 17.053 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|rx_pma_clk
|
|
Info (332119): 17.078 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|rx_pma_clk
|
|
Info (332119): 17.082 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_pma_clk
|
|
Info (332119): 17.111 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|rx_pma_clk
|
|
Info (332119): 17.344 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|rx_pma_clk
|
|
Info (332119): 17.363 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|rx_pma_clk
|
|
Info (332119): 39.729 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|tx_pma_clk
|
|
Info (332119): 39.994 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|tx_pma_clk
|
|
Info (332119): 40.022 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|tx_pma_clk
|
|
Info (332119): 40.582 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|tx_pma_clk
|
|
Info (332119): 41.854 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|tx_coreclkin
|
|
Info (332119): 42.349 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|tx_coreclkin
|
|
Info (332119): 42.379 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|tx_coreclkin
|
|
Info (332119): 42.614 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|tx_coreclkin
|
|
Info (332119): 97.252 0.000 altera_reserved_tck
|
|
Info (332146): Worst-case removal slack is 0.201
|
|
Info (332119): Slack End Point TNS Clock
|
|
Info (332119): ========= =================== =====================
|
|
Info (332119): 0.201 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk1
|
|
Info (332119): 0.315 0.000 u0|dcp_iopll|dcp_iopll|clk1x
|
|
Info (332119): 0.322 0.000 SYS_RefClk
|
|
Info (332119): 0.343 0.000 mem|ddr4a|ddr4a_core_usr_clk
|
|
Info (332119): 0.347 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_clk
|
|
Info (332119): 0.375 0.000 mem|ddr4a|ddr4a_core_cal_slave_clk
|
|
Info (332119): 0.378 0.000 PCIE_REFCLK
|
|
Info (332119): 0.395 0.000 DDR4_RefClk
|
|
Info (332119): 0.412 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|wys~CORE_CLK_OUT
|
|
Info (332119): 0.422 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|rx_pma_clk
|
|
Info (332119): 0.432 0.000 u0|dcp_iopll|dcp_iopll|clk100
|
|
Info (332119): 0.452 0.000 u0|dcp_iopll|dcp_iopll|clk25
|
|
Info (332119): 0.462 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|rx_pma_clk
|
|
Info (332119): 0.479 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|rx_pma_clk
|
|
Info (332119): 0.928 0.000 altera_reserved_tck
|
|
Info (332119): 2.050 0.000 fspi_sclk
|
|
Info (332119): 4.987 0.000 filtered_sclk_negedge
|
|
Info (332119): 8.470 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|rx_pma_clk
|
|
Info (332119): 8.473 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|rx_pma_clk
|
|
Info (332119): 8.730 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|rx_pma_clk
|
|
Info (332119): 8.768 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|rx_pma_clk
|
|
Info (332119): 8.782 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|rx_pma_clk
|
|
Info (332119): 8.835 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|rx_pma_clk
|
|
Info (332119): 9.306 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|rx_pma_clk
|
|
Info (332119): 9.383 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_pma_clk
|
|
Info (332119): 10.089 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|rx_fref
|
|
Info (332119): 10.106 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|rx_fref
|
|
Info (332119): 10.310 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|rx_fref
|
|
Info (332119): 10.337 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|rx_fref
|
|
Info (332119): 10.377 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|rx_fref
|
|
Info (332119): 10.433 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|rx_fref
|
|
Info (332119): 10.837 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|rx_fref
|
|
Info (332119): 12.463 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332119): 52.212 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|tx_coreclkin
|
|
Info (332119): 52.569 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|tx_coreclkin
|
|
Info (332119): 52.721 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|tx_coreclkin
|
|
Info (332119): 52.779 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|tx_coreclkin
|
|
Info (332119): 53.594 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|tx_pma_clk
|
|
Info (332119): 53.775 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|tx_pma_clk
|
|
Info (332119): 53.964 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|tx_pma_clk
|
|
Info (332119): 54.008 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|tx_pma_clk
|
|
Info (332146): Worst-case minimum pulse width slack is 0.092
|
|
Info (332119): Slack End Point TNS Clock
|
|
Info (332119): ========= =================== =====================
|
|
Info (332119): 0.092 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|atx0|altera_xcvr_atx_pll_ip_inst|mcgb_serial_clk
|
|
Info (332119): 0.124 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|twentynm_atx_pll_inst~O_CLK0_8G
|
|
Info (332119): 0.181 0.000 DDR4A_DQS_P[1]_IN
|
|
Info (332119): 0.181 0.000 DDR4A_DQS_P[2]_IN
|
|
Info (332119): 0.181 0.000 DDR4A_DQS_P[5]_IN
|
|
Info (332119): 0.181 0.000 DDR4A_DQS_P[6]_IN
|
|
Info (332119): 0.181 0.000 DDR4B_DQS_P[1]_IN
|
|
Info (332119): 0.181 0.000 DDR4B_DQS_P[2]_IN
|
|
Info (332119): 0.181 0.000 DDR4B_DQS_P[5]_IN
|
|
Info (332119): 0.181 0.000 DDR4B_DQS_P[6]_IN
|
|
Info (332119): 0.182 0.000 DDR4A_DQS_P[0]_IN
|
|
Info (332119): 0.182 0.000 DDR4A_DQS_P[3]_IN
|
|
Info (332119): 0.182 0.000 DDR4A_DQS_P[4]_IN
|
|
Info (332119): 0.182 0.000 DDR4A_DQS_P[7]_IN
|
|
Info (332119): 0.182 0.000 DDR4B_DQS_P[0]_IN
|
|
Info (332119): 0.182 0.000 DDR4B_DQS_P[3]_IN
|
|
Info (332119): 0.182 0.000 DDR4B_DQS_P[4]_IN
|
|
Info (332119): 0.182 0.000 DDR4B_DQS_P[7]_IN
|
|
Info (332119): 0.200 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_serial_clk
|
|
Info (332119): 0.439 0.000 mem|ddr4a|ddr4a_vco_clk
|
|
Info (332119): 0.456 0.000 mem|ddr4a|ddr4a_wf_clk_0
|
|
Info (332119): 0.456 0.000 mem|ddr4b|ddr4b_wf_clk_0
|
|
Info (332119): 0.461 0.000 mem|ddr4a|ddr4a_wf_clk_2
|
|
Info (332119): 0.461 0.000 mem|ddr4b|ddr4b_wf_clk_2
|
|
Info (332119): 0.462 0.000 mem|ddr4a|ddr4a_wf_clk_1
|
|
Info (332119): 0.462 0.000 mem|ddr4b|ddr4b_wf_clk_1
|
|
Info (332119): 0.464 0.000 mem|ddr4a|ddr4a_vco_clk_1
|
|
Info (332119): 0.464 0.000 mem|ddr4a|ddr4a_vco_clk_2
|
|
Info (332119): 0.464 0.000 mem|ddr4a|ddr4a_wf_clk_10
|
|
Info (332119): 0.464 0.000 mem|ddr4a|ddr4a_wf_clk_3
|
|
Info (332119): 0.464 0.000 mem|ddr4a|ddr4a_wf_clk_4
|
|
Info (332119): 0.464 0.000 mem|ddr4a|ddr4a_wf_clk_5
|
|
Info (332119): 0.464 0.000 mem|ddr4a|ddr4a_wf_clk_6
|
|
Info (332119): 0.464 0.000 mem|ddr4a|ddr4a_wf_clk_7
|
|
Info (332119): 0.464 0.000 mem|ddr4a|ddr4a_wf_clk_8
|
|
Info (332119): 0.464 0.000 mem|ddr4a|ddr4a_wf_clk_9
|
|
Info (332119): 0.464 0.000 mem|ddr4b|ddr4b_vco_clk_0
|
|
Info (332119): 0.464 0.000 mem|ddr4b|ddr4b_vco_clk_1
|
|
Info (332119): 0.464 0.000 mem|ddr4b|ddr4b_vco_clk_2
|
|
Info (332119): 0.464 0.000 mem|ddr4b|ddr4b_wf_clk_10
|
|
Info (332119): 0.464 0.000 mem|ddr4b|ddr4b_wf_clk_3
|
|
Info (332119): 0.464 0.000 mem|ddr4b|ddr4b_wf_clk_4
|
|
Info (332119): 0.464 0.000 mem|ddr4b|ddr4b_wf_clk_5
|
|
Info (332119): 0.464 0.000 mem|ddr4b|ddr4b_wf_clk_6
|
|
Info (332119): 0.464 0.000 mem|ddr4b|ddr4b_wf_clk_7
|
|
Info (332119): 0.464 0.000 mem|ddr4b|ddr4b_wf_clk_8
|
|
Info (332119): 0.464 0.000 mem|ddr4b|ddr4b_wf_clk_9
|
|
Info (332119): 0.606 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_bonding_clocks[0]
|
|
Info (332119): 0.795 0.000 mem|ddr4a|ddr4a_phy_clk_0
|
|
Info (332119): 0.795 0.000 mem|ddr4a|ddr4a_phy_clk_1
|
|
Info (332119): 0.795 0.000 mem|ddr4a|ddr4a_phy_clk_2
|
|
Info (332119): 0.795 0.000 mem|ddr4b|ddr4b_phy_clk_0
|
|
Info (332119): 0.795 0.000 mem|ddr4b|ddr4b_phy_clk_1
|
|
Info (332119): 0.795 0.000 mem|ddr4b|ddr4b_phy_clk_2
|
|
Info (332119): 0.833 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_pma_clk
|
|
Info (332119): 0.833 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|rx_pma_clk
|
|
Info (332119): 0.833 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|rx_pma_clk
|
|
Info (332119): 0.833 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|rx_pma_clk
|
|
Info (332119): 0.833 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|rx_pma_clk
|
|
Info (332119): 0.833 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|rx_pma_clk
|
|
Info (332119): 0.833 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|rx_pma_clk
|
|
Info (332119): 0.833 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|rx_pma_clk
|
|
Info (332119): 0.852 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_clk
|
|
Info (332119): 0.852 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|rx_clk
|
|
Info (332119): 0.852 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|rx_clk
|
|
Info (332119): 0.852 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|rx_clk
|
|
Info (332119): 0.852 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|rx_clk
|
|
Info (332119): 0.852 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|rx_clk
|
|
Info (332119): 0.852 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|rx_clk
|
|
Info (332119): 0.852 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|rx_clk
|
|
Info (332119): 0.854 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_pcs_clk_div_by_4[0]
|
|
Info (332119): 0.854 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_pcs_clk_div_by_4[1]
|
|
Info (332119): 0.854 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_pcs_clk_div_by_4[2]
|
|
Info (332119): 0.854 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_pcs_clk_div_by_4[3]
|
|
Info (332119): 0.854 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_pcs_clk_div_by_4[4]
|
|
Info (332119): 0.854 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_pcs_clk_div_by_4[5]
|
|
Info (332119): 0.854 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_pcs_clk_div_by_4[6]
|
|
Info (332119): 0.854 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_pcs_clk_div_by_4[7]
|
|
Info (332119): 0.863 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|rx_pcs_clk_div_by_4[0]
|
|
Info (332119): 0.863 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|rx_pcs_clk_div_by_4[1]
|
|
Info (332119): 0.863 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|rx_pcs_clk_div_by_4[2]
|
|
Info (332119): 0.863 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|rx_pcs_clk_div_by_4[3]
|
|
Info (332119): 0.863 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|rx_pcs_clk_div_by_4[4]
|
|
Info (332119): 0.863 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|rx_pcs_clk_div_by_4[5]
|
|
Info (332119): 0.863 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|rx_pcs_clk_div_by_4[6]
|
|
Info (332119): 0.863 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|rx_pcs_clk_div_by_4[7]
|
|
Info (332119): 0.892 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|pll_pcie_clk
|
|
Info (332119): 0.901 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|hip_cmn_clk[0]
|
|
Info (332119): 1.250 0.000 ETH_RefClk
|
|
Info (332119): 1.436 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|tx_coreclkin
|
|
Info (332119): 1.436 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|tx_coreclkin
|
|
Info (332119): 1.436 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|tx_coreclkin
|
|
Info (332119): 1.436 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|tx_coreclkin
|
|
Info (332119): 1.478 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_coreclkin
|
|
Info (332119): 1.478 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|rx_coreclkin
|
|
Info (332119): 1.478 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|rx_coreclkin
|
|
Info (332119): 1.478 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|rx_coreclkin
|
|
Info (332119): 1.480 0.000 mem|ddr4a|ddr4a_core_usr_clk
|
|
Info (332119): 1.510 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|wys~CORE_CLK_OUT
|
|
Info (332119): 1.563 0.000 hssi_pll_r_0_outclk0
|
|
Info (332119): 1.568 0.000 hssi_pll_t_outclk0
|
|
Info (332119): 1.595 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|tx_pma_clk
|
|
Info (332119): 1.595 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|tx_pma_clk
|
|
Info (332119): 1.595 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|tx_pma_clk
|
|
Info (332119): 1.595 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|tx_pma_clk
|
|
Info (332119): 1.697 0.000 DDR4_RefClk
|
|
Info (332119): 1.736 0.000 mem|ddr4a|ddr4a_phy_clk_l_0
|
|
Info (332119): 1.736 0.000 mem|ddr4a|ddr4a_phy_clk_l_1
|
|
Info (332119): 1.736 0.000 mem|ddr4a|ddr4a_phy_clk_l_2
|
|
Info (332119): 1.736 0.000 mem|ddr4b|ddr4b_phy_clk_l_0
|
|
Info (332119): 1.736 0.000 mem|ddr4b|ddr4b_phy_clk_l_1
|
|
Info (332119): 1.736 0.000 mem|ddr4b|ddr4b_phy_clk_l_2
|
|
Info (332119): 1.772 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_clk
|
|
Info (332119): 1.772 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|rx_pma_clk
|
|
Info (332119): 1.772 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|rx_pma_clk
|
|
Info (332119): 1.772 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|rx_pma_clk
|
|
Info (332119): 1.836 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|pld_clk
|
|
Info (332119): 1.855 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|pma_hclk_by2
|
|
Info (332119): 1.855 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|pma_hclk_by2
|
|
Info (332119): 1.855 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|pma_hclk_by2
|
|
Info (332119): 1.855 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|pma_hclk_by2
|
|
Info (332119): 1.855 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|pma_hclk_by2
|
|
Info (332119): 1.855 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|pma_hclk_by2
|
|
Info (332119): 1.855 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|pma_hclk_by2
|
|
Info (332119): 1.855 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|pma_hclk_by2
|
|
Info (332119): 1.862 0.000 hssi_pll_r_0_outclk1
|
|
Info (332119): 1.867 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk1
|
|
Info (332119): 1.867 0.000 hssi_pll_t_outclk1
|
|
Info (332119): 2.055 0.000 u0|dcp_iopll|dcp_iopll|clk1x
|
|
Info (332119): 2.227 0.000 vl_qph_user_clk_clkpsc_clk1
|
|
Info (332119): 2.915 0.000 mem|ddr4a|ddr4a_core_cal_slave_clk
|
|
Info (332119): 3.103 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_div_clk
|
|
Info (332119): 3.106 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|tx_pma_div_clk
|
|
Info (332119): 3.826 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_clkout
|
|
Info (332119): 3.879 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|tx_clk
|
|
Info (332119): 3.879 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|tx_clk
|
|
Info (332119): 3.879 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|tx_clk
|
|
Info (332119): 3.879 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|tx_clk
|
|
Info (332119): 3.879 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|tx_clk
|
|
Info (332119): 3.879 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|tx_clk
|
|
Info (332119): 3.879 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|tx_clk
|
|
Info (332119): 3.879 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|tx_clk
|
|
Info (332119): 4.478 0.000 vl_qph_user_clk_clkpsc_clk0
|
|
Info (332119): 4.511 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk0
|
|
Info (332119): 4.560 0.000 SYS_RefClk
|
|
Info (332119): 4.566 0.000 u0|dcp_iopll|dcp_iopll|clk100
|
|
Info (332119): 4.618 0.000 PCIE_REFCLK
|
|
Info (332119): 4.849 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332119): 4.861 0.000 pr_clk_enable_dclk_reg2_user_clk
|
|
Info (332119): 4.863 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|rx_fref
|
|
Info (332119): 4.863 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|rx_fref
|
|
Info (332119): 4.863 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|rx_fref
|
|
Info (332119): 4.863 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|rx_fref
|
|
Info (332119): 4.863 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|rx_fref
|
|
Info (332119): 4.863 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|rx_fref
|
|
Info (332119): 4.863 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|rx_fref
|
|
Info (332119): 4.879 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|avmmclk
|
|
Info (332119): 4.879 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|avmmclk
|
|
Info (332119): 4.879 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|avmmclk
|
|
Info (332119): 4.879 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|avmmclk
|
|
Info (332119): 4.879 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|avmmclk
|
|
Info (332119): 4.879 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|avmmclk
|
|
Info (332119): 4.879 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|avmmclk
|
|
Info (332119): 4.879 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|avmmclk
|
|
Info (332119): 4.879 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|avmmclk
|
|
Info (332119): 4.879 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|avmmclk
|
|
Info (332119): 4.879 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|avmmclk
|
|
Info (332119): 4.879 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|avmmclk
|
|
Info (332119): 4.931 0.000 filtered_sclk_negedge
|
|
Info (332119): 9.966 0.000 u0|dcp_iopll|dcp_iopll|clk50
|
|
Info (332119): 19.582 0.000 u0|dcp_iopll|dcp_iopll|clk25
|
|
Info (332119): 19.868 0.000 flash_oe_clk
|
|
Info (332119): 49.870 0.000 altera_reserved_tck
|
|
Info (332119): 124.829 0.000 fspi_sclk
|
|
Info (332119): 500.000 0.000 altera_ts_clk
|
|
Warning (332182): No path is found satisfying assignment "set_max_skew -from [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|tcm_control_out|pio_0|data_out[0]}] -to [get_pins {fpga_top|inst_green_bs|ddr4*_reset_sync|resync_chains[0].synchronizer_nocut|*|clrn}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 ". This assignment will be ignored.
|
|
Info (332115): Worst-case slack is 2.412 for "set_max_skew -from [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Tx_fifo|C1Tx_fifo.inst_async_C1Tx_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Tx_fifo|C1Tx_fifo.inst_async_C1Tx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 "
|
|
Info (332115): Worst-case slack is 2.467 for "set_max_skew -from [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Tx_fifo|C0Tx_fifo.inst_async_C0Tx_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Tx_fifo|C0Tx_fifo.inst_async_C0Tx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 "
|
|
Info (332115): Worst-case slack is 2.615 for "set_max_skew -from [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_CfgTx_fifo|CfgTx_fifo.inst_async_CfgTx_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_CfgTx_fifo|CfgTx_fifo.inst_async_CfgTx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 "
|
|
Info (332115): Worst-case slack is 2.666 for "set_max_skew -from [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Rx_fifo|C0Rx_fifo.inst_async_C0Rx_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Rx_fifo|C0Rx_fifo.inst_async_C0Rx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 "
|
|
Info (332115): Worst-case slack is 2.683 for "set_max_skew -from [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Rx_fifo|C1Rx_fifo.inst_async_C1Rx_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Rx_fifo|C1Rx_fifo.inst_async_C1Rx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 "
|
|
Info (332115): Worst-case slack is 2.779 for "set_max_skew -from [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_msix_top|msix_brid|msix_dcfifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_msix_top|msix_brid|msix_dcfifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 "
|
|
Info (332115): Worst-case slack is 2.960 for "set_max_skew -from [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 "
|
|
Info (332115): Worst-case slack is 2.992 for "set_max_skew -from [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Tx_fifo|C0Tx_fifo.inst_async_C0Tx_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Tx_fifo|C0Tx_fifo.inst_async_C0Tx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 "
|
|
Info (332115): Worst-case slack is 3.021 for "set_max_skew -from [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 "
|
|
Info (332115): Worst-case slack is 3.037 for "set_max_skew -from [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 "
|
|
Info (332115): Worst-case slack is 3.042 for "set_max_skew -from [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 "
|
|
Info (332115): Worst-case slack is 3.094 for "set_max_skew -from [get_keepers {fpga_top|inst_blue_ccip_interface_reg|pck_cp2af_softReset_T0_q}] -to [get_pins {fpga_top|inst_green_bs|ddr4*_reset_sync|resync_chains[0].synchronizer_nocut|*|clrn}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 "
|
|
Info (332115): Worst-case slack is 3.111 for "set_max_skew -from [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 "
|
|
Info (332115): Worst-case slack is 3.115 for "set_max_skew -from [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 "
|
|
Info (332115): Worst-case slack is 3.229 for "set_max_skew -from [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 "
|
|
Info (332115): Worst-case slack is 3.235 for "set_max_skew -from [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Rx_fifo|C0Rx_fifo.inst_async_C0Rx_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Rx_fifo|C0Rx_fifo.inst_async_C0Rx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 "
|
|
Info (332115): Worst-case slack is 3.256 for "set_max_skew -from [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 "
|
|
Info (332115): Worst-case slack is 3.322 for "set_max_skew -from [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Tx_fifo|C1Tx_fifo.inst_async_C1Tx_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Tx_fifo|C1Tx_fifo.inst_async_C1Tx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 "
|
|
Info (332115): Worst-case slack is 3.329 for "set_max_skew -from [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_CfgTx_fifo|CfgTx_fifo.inst_async_CfgTx_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_CfgTx_fifo|CfgTx_fifo.inst_async_CfgTx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 "
|
|
Info (332115): Worst-case slack is 3.357 for "set_max_skew -from [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 "
|
|
Info (332115): Worst-case slack is 3.424 for "set_max_skew -from [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Rx_fifo|C1Rx_fifo.inst_async_C1Rx_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Rx_fifo|C1Rx_fifo.inst_async_C1Rx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 "
|
|
Info (332115): Worst-case slack is 3.426 for "set_max_skew -from [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_msix_top|msix_brid|msix_dcfifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_msix_top|msix_brid|msix_dcfifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 "
|
|
Info (332115): Worst-case slack is 3.453 for "set_max_skew -from [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 "
|
|
Info (332115): Worst-case slack is 3.470 for "set_max_skew -from [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|ddr_backchannel|mm_clock_crossing_bridge_0|rsp_fifo|out_rd_ptr_gray[*]}] -to [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|ddr_backchannel|mm_clock_crossing_bridge_0|rsp_fifo|read_crosser|sync[*].u|din_s1}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 "
|
|
Info (332115): Worst-case slack is 3.476 for "set_max_skew -from [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|ddr_backchannel|mm_clock_crossing_bridge_0|cmd_fifo|in_wr_ptr_gray[*]}] -to [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|ddr_backchannel|mm_clock_crossing_bridge_0|cmd_fifo|write_crosser|sync[*].u|din_s1}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 "
|
|
Info (332115): Worst-case slack is 7.418 for "set_max_skew -from [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|ddr_backchannel|mm_clock_crossing_bridge_0|cmd_fifo|out_rd_ptr_gray[*]}] -to [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|ddr_backchannel|mm_clock_crossing_bridge_0|cmd_fifo|read_crosser|sync[*].u|din_s1}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 "
|
|
Info (332115): Worst-case slack is 7.420 for "set_max_skew -from [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|ddr_backchannel|mm_clock_crossing_bridge_0|rsp_fifo|in_wr_ptr_gray[*]}] -to [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|ddr_backchannel|mm_clock_crossing_bridge_0|rsp_fifo|write_crosser|sync[*].u|din_s1}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 "
|
|
Info (332115): Worst-case slack is 7.427 for "set_max_skew -from [get_registers {auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|stfabric|t2h0_fifo|in_wr_ptr_gray[*]}] -to [get_registers {auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|stfabric|t2h0_fifo|write_crosser|sync[*].u|din_s1}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 "
|
|
Info (332115): Worst-case slack is 7.475 for "set_max_skew -from [get_registers {auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|stfabric|t2h0_fifo|out_rd_ptr_gray[*]}] -to [get_registers {auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|stfabric|t2h0_fifo|read_crosser|sync[*].u|din_s1}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 "
|
|
Info (332115): Worst-case slack is 7.498 for "set_max_skew -from [get_registers {auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|stfabric|h2t0_fifo|in_wr_ptr_gray[*]}] -to [get_registers {auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|stfabric|h2t0_fifo|write_crosser|sync[*].u|din_s1}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 "
|
|
Info (332115): Worst-case slack is 7.525 for "set_max_skew -from [get_registers {auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|stfabric|h2t0_fifo|out_rd_ptr_gray[*]}] -to [get_registers {auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|stfabric|h2t0_fifo|read_crosser|sync[*].u|din_s1}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 "
|
|
Info (332163): Slow 900mV 100C Model Net Delay Summary
|
|
Info (332163): Name Slack Req Actual From To Type
|
|
Info (332163): ============= ====== ====== ====== =============== =============== ====
|
|
Info (332163): set_net_delay 1.412 3.001 1.589 [get_pins -compatibility_mode {*|out_rd_ptr_gray[*]*}]
|
|
Info (332163): [get_registers {*|platform_utils_dcfifo_synchronizer_bundle:read_crosser|platform_utils_std_synchronizer_nocut:sync[*].u|din_s1}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 2.196 3.636 1.440 [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 2.198 4.000 1.802 [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser|async_clock_crosser.clock_xer|out_data_toggle_flopped}]
|
|
Info (332163): [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser|async_clock_crosser.clock_xer|out_to_in_synchronizer|din_s1}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 2.202 3.200 0.998 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Rx_fifo|C1Rx_fifo.inst_async_C1Rx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Rx_fifo|C1Rx_fifo.inst_async_C1Rx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 2.224 3.200 0.976 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Tx_fifo|C1Tx_fifo.inst_async_C1Tx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Tx_fifo|C1Tx_fifo.inst_async_C1Tx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 2.250 3.200 0.950 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Tx_fifo|C0Tx_fifo.inst_async_C0Tx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Tx_fifo|C0Tx_fifo.inst_async_C0Tx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 2.420 3.001 0.581 [get_pins -compatibility_mode {*|in_wr_ptr_gray[*]*}]
|
|
Info (332163): [get_registers {*|platform_utils_dcfifo_synchronizer_bundle:write_crosser|platform_utils_std_synchronizer_nocut:sync[*].u|din_s1}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 2.433 3.200 0.767 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Rx_fifo|C0Rx_fifo.inst_async_C0Rx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Rx_fifo|C0Rx_fifo.inst_async_C0Rx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 2.450 3.200 0.750 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_CfgTx_fifo|CfgTx_fifo.inst_async_CfgTx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_CfgTx_fifo|CfgTx_fifo.inst_async_CfgTx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 2.514 3.636 1.122 [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 2.520 4.000 1.480 [get_registers {*altera_avalon_st_clock_crosser:*|in_data_buffer*}]
|
|
Info (332163): [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_004|async_clock_crosser.clock_xer|out_data_buffer*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 2.529 3.200 0.671 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_msix_top|msix_brid|msix_dcfifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_msix_top|msix_brid|msix_dcfifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 2.531 3.200 0.669 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Tx_fifo|C0Tx_fifo.inst_async_C0Tx_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Tx_fifo|C0Tx_fifo.inst_async_C0Tx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 2.550 3.200 0.650 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Rx_fifo|C0Rx_fifo.inst_async_C0Rx_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Rx_fifo|C0Rx_fifo.inst_async_C0Rx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 2.583 4.000 1.417 [get_registers {*altera_avalon_st_clock_crosser:*|in_data_buffer*}]
|
|
Info (332163): [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_005|async_clock_crosser.clock_xer|out_data_buffer*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 2.596 3.636 1.040 [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 2.632 3.200 0.568 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_CfgTx_fifo|CfgTx_fifo.inst_async_CfgTx_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_CfgTx_fifo|CfgTx_fifo.inst_async_CfgTx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 2.632 3.636 1.004 [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 2.635 3.200 0.565 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Tx_fifo|C1Tx_fifo.inst_async_C1Tx_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Tx_fifo|C1Tx_fifo.inst_async_C1Tx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 2.674 3.200 0.526 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Rx_fifo|C1Rx_fifo.inst_async_C1Rx_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Rx_fifo|C1Rx_fifo.inst_async_C1Rx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 2.682 3.200 0.518 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_msix_top|msix_brid|msix_dcfifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_msix_top|msix_brid|msix_dcfifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 2.691 3.636 0.945 [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 2.738 4.000 1.262 [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_003|async_clock_crosser.clock_xer|out_data_toggle_flopped}]
|
|
Info (332163): [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_003|async_clock_crosser.clock_xer|out_to_in_synchronizer|din_s1}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 2.865 4.000 1.135 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Tx_fifo|C1Tx_fifo.inst_async_C1Tx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Tx_fifo|C1Tx_fifo.inst_async_C1Tx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 2.870 4.000 1.130 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Rx_fifo|C0Rx_fifo.inst_async_C0Rx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Rx_fifo|C0Rx_fifo.inst_async_C0Rx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 2.873 3.636 0.763 [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|delayed_wrptr_g*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 2.875 4.000 1.125 [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_001|async_clock_crosser.clock_xer|out_data_toggle_flopped}]
|
|
Info (332163): [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_001|async_clock_crosser.clock_xer|out_to_in_synchronizer|din_s1}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 2.897 4.000 1.103 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Tx_fifo|C0Tx_fifo.inst_async_C0Tx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Tx_fifo|C0Tx_fifo.inst_async_C0Tx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 2.902 4.000 1.098 [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 2.920 4.000 1.080 [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_004|async_clock_crosser.clock_xer|in_data_toggle}]
|
|
Info (332163): [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_004|async_clock_crosser.clock_xer|in_to_out_synchronizer|din_s1}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 2.975 4.000 1.025 [get_registers {*altera_avalon_st_clock_crosser:*|in_data_buffer*}]
|
|
Info (332163): [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_006|async_clock_crosser.clock_xer|out_data_buffer*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 2.980 3.636 0.656 [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|*rdptr_g*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 3.023 4.000 0.977 [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 3.042 3.636 0.594 [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|delayed_wrptr_g*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 3.052 3.636 0.584 [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|*rdptr_g*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 3.126 3.636 0.510 [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|*rdptr_g*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 3.142 4.000 0.858 [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 3.172 4.000 0.828 [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 3.213 4.000 0.787 [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 3.234 4.000 0.766 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Rx_fifo|C1Rx_fifo.inst_async_C1Rx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Rx_fifo|C1Rx_fifo.inst_async_C1Rx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 3.247 4.000 0.753 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_CfgTx_fifo|CfgTx_fifo.inst_async_CfgTx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_CfgTx_fifo|CfgTx_fifo.inst_async_CfgTx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 3.250 4.000 0.750 [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|delayed_wrptr_g*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 3.292 4.000 0.708 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Tx_fifo|C1Tx_fifo.inst_async_C1Tx_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Tx_fifo|C1Tx_fifo.inst_async_C1Tx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 3.317 4.000 0.683 [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_002|async_clock_crosser.clock_xer|out_data_toggle_flopped}]
|
|
Info (332163): [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_002|async_clock_crosser.clock_xer|out_to_in_synchronizer|din_s1}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 3.337 4.000 0.663 [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|*rdptr_g*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 3.343 4.000 0.657 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_msix_top|msix_brid|msix_dcfifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_msix_top|msix_brid|msix_dcfifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 3.357 4.000 0.643 [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_005|async_clock_crosser.clock_xer|in_data_toggle}]
|
|
Info (332163): [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_005|async_clock_crosser.clock_xer|in_to_out_synchronizer|din_s1}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 3.378 4.000 0.622 [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|*rdptr_g*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 3.382 4.000 0.618 [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_007|async_clock_crosser.clock_xer|in_data_toggle}]
|
|
Info (332163): [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_007|async_clock_crosser.clock_xer|in_to_out_synchronizer|din_s1}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 3.429 4.000 0.571 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_CfgTx_fifo|CfgTx_fifo.inst_async_CfgTx_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_CfgTx_fifo|CfgTx_fifo.inst_async_CfgTx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 3.432 4.000 0.568 [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|delayed_wrptr_g*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 3.438 4.000 0.562 [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|delayed_wrptr_g*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 3.463 4.000 0.537 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Rx_fifo|C0Rx_fifo.inst_async_C0Rx_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Rx_fifo|C0Rx_fifo.inst_async_C0Rx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 3.479 4.000 0.521 [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_006|async_clock_crosser.clock_xer|in_data_toggle}]
|
|
Info (332163): [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_006|async_clock_crosser.clock_xer|in_to_out_synchronizer|din_s1}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 3.493 4.000 0.507 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Tx_fifo|C0Tx_fifo.inst_async_C0Tx_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Tx_fifo|C0Tx_fifo.inst_async_C0Tx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 3.497 4.000 0.503 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_msix_top|msix_brid|msix_dcfifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_msix_top|msix_brid|msix_dcfifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 3.556 4.000 0.444 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Rx_fifo|C1Rx_fifo.inst_async_C1Rx_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Rx_fifo|C1Rx_fifo.inst_async_C1Rx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 3.652 4.000 0.348 [get_pins -compatibility_mode {*|out_rd_ptr_gray[*]*}]
|
|
Info (332163): [get_registers {*|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer_nocut:sync[*].u|din_s1}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 3.686 4.000 0.314 [get_pins -compatibility_mode {*|in_wr_ptr_gray[*]*}]
|
|
Info (332163): [get_registers {*|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer_nocut:sync[*].u|din_s1}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 5.599 8.000 2.401 [get_registers {*altera_avalon_st_clock_crosser:*|in_data_buffer*}]
|
|
Info (332163): [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_003|async_clock_crosser.clock_xer|out_data_buffer*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 5.771 8.000 2.229 [get_registers {*altera_avalon_st_clock_crosser:*|in_data_buffer*}]
|
|
Info (332163): [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_002|async_clock_crosser.clock_xer|out_data_buffer*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 6.521 8.000 1.479 [get_registers {auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|host_link_jtag|jtag|normal.jtag_dc_streaming|sink_crosser|out_data_toggle_flopped}]
|
|
Info (332163): [get_registers {auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|host_link_jtag|jtag|normal.jtag_dc_streaming|sink_crosser|out_to_in_synchronizer|din_s1}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 7.065 8.000 0.935 [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_002|async_clock_crosser.clock_xer|in_data_toggle}]
|
|
Info (332163): [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_002|async_clock_crosser.clock_xer|in_to_out_synchronizer|din_s1}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 7.070 8.000 0.930 [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_006|async_clock_crosser.clock_xer|out_data_toggle_flopped}]
|
|
Info (332163): [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_006|async_clock_crosser.clock_xer|out_to_in_synchronizer|din_s1}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 7.381 8.000 0.619 [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_003|async_clock_crosser.clock_xer|in_data_toggle}]
|
|
Info (332163): [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_003|async_clock_crosser.clock_xer|in_to_out_synchronizer|din_s1}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 7.481 8.000 0.519 [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_007|async_clock_crosser.clock_xer|out_data_toggle_flopped}]
|
|
Info (332163): [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_007|async_clock_crosser.clock_xer|out_to_in_synchronizer|din_s1}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 30.384 32.000 1.616 [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_005|async_clock_crosser.clock_xer|out_data_toggle_flopped}]
|
|
Info (332163): [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_005|async_clock_crosser.clock_xer|out_to_in_synchronizer|din_s1}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 30.426 32.000 1.574 [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser|async_clock_crosser.clock_xer|in_data_toggle}]
|
|
Info (332163): [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser|async_clock_crosser.clock_xer|in_to_out_synchronizer|din_s1}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 30.729 32.000 1.271 [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_004|async_clock_crosser.clock_xer|out_data_toggle_flopped}]
|
|
Info (332163): [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_004|async_clock_crosser.clock_xer|out_to_in_synchronizer|din_s1}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 30.838 32.000 1.162 [get_registers {*altera_avalon_st_clock_crosser:*|in_data_buffer*}]
|
|
Info (332163): [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_001|async_clock_crosser.clock_xer|out_data_buffer*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 30.961 32.000 1.039 [get_registers {*altera_avalon_st_clock_crosser:*|in_data_buffer*}]
|
|
Info (332163): [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser|async_clock_crosser.clock_xer|out_data_buffer*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 31.288 32.000 0.712 [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_001|async_clock_crosser.clock_xer|in_data_toggle}]
|
|
Info (332163): [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_001|async_clock_crosser.clock_xer|in_to_out_synchronizer|din_s1}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 74.085 80.000 5.915 [get_registers {auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|host_link_jtag|jtag|normal.jtag_dc_streaming|sink_crosser|in_data_toggle}]
|
|
Info (332163): [get_registers {auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|host_link_jtag|jtag|normal.jtag_dc_streaming|sink_crosser|in_to_out_synchronizer|din_s1}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 78.927 80.000 1.073 [get_registers {*altera_avalon_st_clock_crosser:*|in_data_buffer*}]
|
|
Info (332163): [get_registers {auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|host_link_jtag|jtag|normal.jtag_dc_streaming|sink_crosser|out_data_buffer*}]
|
|
Info (332163): max
|
|
Info (332114): Report Metastability: Found 403 synchronizer chains.
|
|
Info (332114): Design MTBF is not calculated because the design doesn't meet its timing requirements.
|
|
Info (332115): Report Timing: Found 1 setup paths (1 violated). Worst case slack is -1.430
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk1}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is -1.430 (VIOLATED)
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|mem_unit|icache|[0].bank|core_rsp_req|shift_reg[0][28]
|
|
Info (332115): To Node : fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|issue|ibuffer|q_data_out[2][8]
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk1
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk1
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 6.353 6.353 R clock network delay
|
|
Info (332115): 6.353 0.000 fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|mem_unit|icache|[0].bank|core_rsp_req|shift_reg[0][28]
|
|
Info (332115): 6.567 0.214 RR uTco fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|mem_unit|icache|[0].bank|core_rsp_req|shift_reg[0][28]|q
|
|
Info (332115): 6.682 0.115 RR CELL High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|mem_unit|icache|[0].bank|core_rsp_req|shift_reg[0][28]~la_lab/laboutt[17]
|
|
Info (332115): 7.430 0.748 RR IC High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|mem_unit|icache|[0].bank|core_rsp_req|data_out[28]~14|datad
|
|
Info (332115): 7.565 0.135 RR CELL High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|mem_unit|icache|[0].bank|core_rsp_req|data_out[28]~14|combout
|
|
Info (332115): 7.570 0.005 RR CELL High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|mem_unit|icache|[0].bank|core_rsp_req|data_out[28]~14~la_lab/laboutb[11]
|
|
Info (332115): 8.958 1.388 RR IC High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|decode|reduce_or_12~0|datab
|
|
Info (332115): 9.215 0.257 RR CELL High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|decode|reduce_or_12~0|combout
|
|
Info (332115): 9.220 0.005 RR CELL High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|decode|reduce_or_12~0~la_lab/laboutt[11]
|
|
Info (332115): 9.405 0.185 RR IC High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|decode|Select_52~3|dataf
|
|
Info (332115): 9.449 0.044 RR CELL High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|decode|Select_52~3|combout
|
|
Info (332115): 9.453 0.004 RR CELL High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|decode|Select_52~3~la_lab/laboutb[4]
|
|
Info (332115): 9.661 0.208 RR IC High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|decode|shift_left_0~20|dataf
|
|
Info (332115): 9.711 0.050 RF CELL High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|decode|shift_left_0~20|combout
|
|
Info (332115): 9.715 0.004 FF CELL High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|decode|shift_left_0~20~la_lab/laboutt[8]
|
|
Info (332115): 10.963 1.248 FF IC High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|decode|i571~1|dataf
|
|
Info (332115): 11.007 0.044 FF CELL High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|decode|i571~1|combout
|
|
Info (332115): 11.012 0.005 FF CELL High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|decode|i571~1~la_mlab/laboutb[12]
|
|
Info (332115): 11.209 0.197 FF IC High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|decode|i571~0|dataf
|
|
Info (332115): 11.249 0.040 FF CELL High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|decode|i571~0|combout
|
|
Info (332115): 11.254 0.005 FF CELL High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|decode|i571~0~la_mlab/laboutt[10]
|
|
Info (332115): 12.469 1.215 FF IC High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|issue|ibuffer|q_data_out[2][8]|asdata
|
|
Info (332115): 12.469 0.000 FF CELL High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|issue|ibuffer|q_data_out[2][8]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 4.545 4.545 latch edge time
|
|
Info (332115): 9.846 5.301 R clock network delay
|
|
Info (332115): 10.908 1.062 clock pessimism removed
|
|
Info (332115): 10.878 -0.030 clock uncertainty
|
|
Info (332115): 11.039 0.161 uTsu fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|issue|ibuffer|q_data_out[2][8]
|
|
Info (332115): Data Arrival Time : 12.469
|
|
Info (332115): Data Required Time : 11.039
|
|
Info (332115): Slack : -1.430 (VIOLATED)
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 0.028
|
|
Info (20696): -to_clock [get_clocks {mem|ddr4a|ddr4a_phy_clk_l_2}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 0.028
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : mem|ddr4a_avmm_chkr|clearing
|
|
Info (332115): To Node : mem|ddr4a|ddr4a|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[0].lane_gen[0].lane_inst~phy_reg1
|
|
Info (332115): Launch Clock : mem|ddr4a|ddr4a_core_usr_clk
|
|
Info (332115): Latch Clock : mem|ddr4a|ddr4a_phy_clk_l_2
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.117 0.117 launch edge time
|
|
Info (332115): 3.673 3.556 R clock network delay
|
|
Info (332115): 3.673 0.000 mem|ddr4a_avmm_chkr|clearing
|
|
Info (332115): 3.890 0.217 FF uTco mem|ddr4a_avmm_chkr|clearing|q
|
|
Info (332115): 3.975 0.085 FF CELL High Speed mem|ddr4a_avmm_chkr|clearing~la_mlab/laboutt[13]
|
|
Info (332115): 4.678 0.703 FF IC High Speed mem|ddr4a_avmm_chkr|avm_writedata[131]~26|datad
|
|
Info (332115): 4.830 0.152 FR CELL High Speed mem|ddr4a_avmm_chkr|avm_writedata[131]~26|combout
|
|
Info (332115): 4.834 0.004 RR CELL High Speed mem|ddr4a_avmm_chkr|avm_writedata[131]~26~la_lab/laboutt[16]
|
|
Info (332115): 6.647 1.813 RR IC High Speed mem|ddr4a|ddr4a|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[0].lane_gen[0].lane_inst|data_from_core[50]
|
|
Info (332115): 6.647 0.000 RR CELL mem|ddr4a|ddr4a|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[0].lane_gen[0].lane_inst~phy_reg1
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 3.869 3.869 latch edge time
|
|
Info (332115): 6.461 2.592 R clock network delay
|
|
Info (332115): 6.634 0.173 clock pessimism removed
|
|
Info (332115): 6.345 -0.289 clock uncertainty
|
|
Info (332115): 6.675 0.330 uTsu mem|ddr4a|ddr4a|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[0].lane_gen[0].lane_inst~phy_reg1
|
|
Info (332115): Data Arrival Time : 6.647
|
|
Info (332115): Data Required Time : 6.675
|
|
Info (332115): Slack : 0.028
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 0.079
|
|
Info (20696): -to_clock [get_clocks {mem|ddr4a|ddr4a_phy_clk_l_1}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 0.079
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : mem|ddr4a_avmm_chkr|clearing
|
|
Info (332115): To Node : mem|ddr4a|ddr4a|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[1].lane_gen[3].lane_inst~phy_reg1
|
|
Info (332115): Launch Clock : mem|ddr4a|ddr4a_core_usr_clk
|
|
Info (332115): Latch Clock : mem|ddr4a|ddr4a_phy_clk_l_1
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.117 0.117 launch edge time
|
|
Info (332115): 3.673 3.556 R clock network delay
|
|
Info (332115): 3.673 0.000 mem|ddr4a_avmm_chkr|clearing
|
|
Info (332115): 3.890 0.217 RR uTco mem|ddr4a_avmm_chkr|clearing|q
|
|
Info (332115): 4.027 0.137 RR CELL High Speed mem|ddr4a_avmm_chkr|clearing~la_mlab/laboutt[13]
|
|
Info (332115): 5.194 1.167 RR IC High Speed mem|ddr4a_avmm_chkr|avm_writedata[416]~262|dataf
|
|
Info (332115): 5.246 0.052 RF CELL High Speed mem|ddr4a_avmm_chkr|avm_writedata[416]~262|combout
|
|
Info (332115): 5.251 0.005 FF CELL High Speed mem|ddr4a_avmm_chkr|avm_writedata[416]~262~la_lab/laboutb[9]
|
|
Info (332115): 6.605 1.354 FF IC High Speed mem|ddr4a|ddr4a|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[1].lane_gen[3].lane_inst|data_from_core[78]
|
|
Info (332115): 6.605 0.000 FF CELL mem|ddr4a|ddr4a|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[1].lane_gen[3].lane_inst~phy_reg1
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 3.869 3.869 latch edge time
|
|
Info (332115): 6.463 2.594 R clock network delay
|
|
Info (332115): 6.636 0.173 clock pessimism removed
|
|
Info (332115): 6.347 -0.289 clock uncertainty
|
|
Info (332115): 6.684 0.337 uTsu mem|ddr4a|ddr4a|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[1].lane_gen[3].lane_inst~phy_reg1
|
|
Info (332115): Data Arrival Time : 6.605
|
|
Info (332115): Data Required Time : 6.684
|
|
Info (332115): Slack : 0.079
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 0.084
|
|
Info (20696): -to_clock [get_clocks {mem|ddr4b|ddr4b_phy_clk_l_1}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 0.084
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : mem|ddr4b_avmm_chkr|clearing
|
|
Info (332115): To Node : mem|ddr4b|ddr4b|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[1].lane_gen[3].lane_inst~phy_reg1
|
|
Info (332115): Launch Clock : mem|ddr4a|ddr4a_core_usr_clk
|
|
Info (332115): Latch Clock : mem|ddr4b|ddr4b_phy_clk_l_1
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.117 0.117 launch edge time
|
|
Info (332115): 3.531 3.414 R clock network delay
|
|
Info (332115): 3.531 0.000 mem|ddr4b_avmm_chkr|clearing
|
|
Info (332115): 3.747 0.216 RR uTco mem|ddr4b_avmm_chkr|clearing|q
|
|
Info (332115): 3.877 0.130 RR CELL High Speed mem|ddr4b_avmm_chkr|clearing~la_lab/laboutb[17]
|
|
Info (332115): 5.164 1.287 RR IC High Speed mem|ddr4b_avmm_chkr|avm_writedata[0]~260|dataf
|
|
Info (332115): 5.217 0.053 RF CELL High Speed mem|ddr4b_avmm_chkr|avm_writedata[0]~260|combout
|
|
Info (332115): 5.222 0.005 FF CELL High Speed mem|ddr4b_avmm_chkr|avm_writedata[0]~260~la_lab/laboutb[5]
|
|
Info (332115): 6.420 1.198 FF IC High Speed mem|ddr4b|ddr4b|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[1].lane_gen[3].lane_inst|data_from_core[76]
|
|
Info (332115): 6.420 0.000 FF CELL mem|ddr4b|ddr4b|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[1].lane_gen[3].lane_inst~phy_reg1
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 3.869 3.869 latch edge time
|
|
Info (332115): 6.360 2.491 R clock network delay
|
|
Info (332115): 6.458 0.098 clock pessimism removed
|
|
Info (332115): 6.169 -0.289 clock uncertainty
|
|
Info (332115): 6.504 0.335 uTsu mem|ddr4b|ddr4b|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[1].lane_gen[3].lane_inst~phy_reg1
|
|
Info (332115): Data Arrival Time : 6.420
|
|
Info (332115): Data Required Time : 6.504
|
|
Info (332115): Slack : 0.084
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 0.097
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|wys~CORE_CLK_OUT}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 0.097
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_sriov_2.sriov2.sriov_bridge|altpcie_pcie_sriov2_top_inst|altpcie_sriov2_tx_data_bridge_inst|poisoned_req_sent_vf_o
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_sriov_2.sriov2.sriov_bridge|altpcie_pcie_sriov2_top_inst|altpcie_sriov2_cfg_dataflow_inst|gen_vf_regset_pf0.altpcie_sriov2_cfg_vf_regset_pf0_inst|vf_pci_status_reg_mod|altpcie_sriov2_cfg_vf_poisoned_req_sent_error_status_fifo|fifo_occupancy[2]
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|wys~CORE_CLK_OUT
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|wys~CORE_CLK_OUT
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 9.243 9.243 R clock network delay
|
|
Info (332115): 9.243 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_sriov_2.sriov2.sriov_bridge|altpcie_pcie_sriov2_top_inst|altpcie_sriov2_tx_data_bridge_inst|poisoned_req_sent_vf_o
|
|
Info (332115): 9.462 0.219 RR uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_sriov_2.sriov2.sriov_bridge|altpcie_pcie_sriov2_top_inst|altpcie_sriov2_tx_data_bridge_inst|poisoned_req_sent_vf_o|q
|
|
Info (332115): 9.577 0.115 RR CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_sriov_2.sriov2.sriov_bridge|altpcie_pcie_sriov2_top_inst|altpcie_sriov2_tx_data_bridge_inst|poisoned_req_sent_vf_o~la_mlab/laboutb[5]
|
|
Info (332115): 12.861 3.284 RR IC High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_sriov_2.sriov2.sriov_bridge|altpcie_pcie_sriov2_top_inst|altpcie_sriov2_cfg_dataflow_inst|gen_vf_regset_pf0.altpcie_sriov2_cfg_vf_regset_pf0_inst|vf_pci_status_reg_mod|altpcie_sriov2_cfg_vf_poisoned_req_sent_error_status_fifo|fifo_occupancy[3]~0|dataf
|
|
Info (332115): 12.909 0.048 RR CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_sriov_2.sriov2.sriov_bridge|altpcie_pcie_sriov2_top_inst|altpcie_sriov2_cfg_dataflow_inst|gen_vf_regset_pf0.altpcie_sriov2_cfg_vf_regset_pf0_inst|vf_pci_status_reg_mod|altpcie_sriov2_cfg_vf_poisoned_req_sent_error_status_fifo|fifo_occupancy[3]~0|combout
|
|
Info (332115): 12.913 0.004 RR CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_sriov_2.sriov2.sriov_bridge|altpcie_pcie_sriov2_top_inst|altpcie_sriov2_cfg_dataflow_inst|gen_vf_regset_pf0.altpcie_sriov2_cfg_vf_regset_pf0_inst|vf_pci_status_reg_mod|altpcie_sriov2_cfg_vf_poisoned_req_sent_error_status_fifo|fifo_occupancy[3]~0~la_lab/laboutb[18]
|
|
Info (332115): 13.100 0.187 RR IC High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_sriov_2.sriov2.sriov_bridge|altpcie_pcie_sriov2_top_inst|altpcie_sriov2_cfg_dataflow_inst|gen_vf_regset_pf0.altpcie_sriov2_cfg_vf_regset_pf0_inst|vf_pci_status_reg_mod|altpcie_sriov2_cfg_vf_poisoned_req_sent_error_status_fifo|fifo_occupancy[2]|ena
|
|
Info (332115): 13.100 0.000 RR CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_sriov_2.sriov2.sriov_bridge|altpcie_pcie_sriov2_top_inst|altpcie_sriov2_cfg_dataflow_inst|gen_vf_regset_pf0.altpcie_sriov2_cfg_vf_regset_pf0_inst|vf_pci_status_reg_mod|altpcie_sriov2_cfg_vf_poisoned_req_sent_error_status_fifo|fifo_occupancy[2]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 4.000 4.000 latch edge time
|
|
Info (332115): 11.883 7.883 R clock network delay
|
|
Info (332115): 13.144 1.261 clock pessimism removed
|
|
Info (332115): 13.197 0.053 uTsu fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_sriov_2.sriov2.sriov_bridge|altpcie_pcie_sriov2_top_inst|altpcie_sriov2_cfg_dataflow_inst|gen_vf_regset_pf0.altpcie_sriov2_cfg_vf_regset_pf0_inst|vf_pci_status_reg_mod|altpcie_sriov2_cfg_vf_poisoned_req_sent_error_status_fifo|fifo_occupancy[2]
|
|
Info (332115): Data Arrival Time : 13.100
|
|
Info (332115): Data Required Time : 13.197
|
|
Info (332115): Slack : 0.097
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 0.126
|
|
Info (20696): -to_clock [get_clocks {mem|ddr4b|ddr4b_phy_clk_l_0}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 0.126
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : mem|ddr4b_bridge|ddr_avmm_bridge|cmd_burstcount[4]
|
|
Info (332115): To Node : mem|ddr4b|ddr4b|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[1].tile_ctrl_inst~hmc_reg1
|
|
Info (332115): Launch Clock : mem|ddr4a|ddr4a_core_usr_clk
|
|
Info (332115): Latch Clock : mem|ddr4b|ddr4b_phy_clk_l_0
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.117 0.117 launch edge time
|
|
Info (332115): 3.546 3.429 R clock network delay
|
|
Info (332115): 3.546 0.000 mem|ddr4b_bridge|ddr_avmm_bridge|cmd_burstcount[4]
|
|
Info (332115): 3.773 0.227 RR uTco mem|ddr4b_bridge|ddr_avmm_bridge|cmd_burstcount[4]|q
|
|
Info (332115): 3.954 0.181 RR CELL High Speed mem|ddr4b_bridge|ddr_avmm_bridge|cmd_burstcount[4]~la_mlab/laboutb[12]
|
|
Info (332115): 4.403 0.449 RR IC High Speed mem|ddr4b_avmm_chkr|LessThan_0~0|datad
|
|
Info (332115): 4.573 0.170 RF CELL High Speed mem|ddr4b_avmm_chkr|LessThan_0~0|combout
|
|
Info (332115): 4.579 0.006 FF CELL High Speed mem|ddr4b_avmm_chkr|LessThan_0~0~la_mlab/laboutt[17]
|
|
Info (332115): 4.914 0.335 FF IC High Speed mem|ddr4b_avmm_chkr|start_error|datad
|
|
Info (332115): 5.062 0.148 FR CELL High Speed mem|ddr4b_avmm_chkr|start_error|combout
|
|
Info (332115): 5.066 0.004 RR CELL High Speed mem|ddr4b_avmm_chkr|start_error~la_lab/laboutt[0]
|
|
Info (332115): 5.428 0.362 RR IC High Speed mem|ddr4b_emif_read_mux~0|datad
|
|
Info (332115): 5.560 0.132 RR CELL High Speed mem|ddr4b_emif_read_mux~0|combout
|
|
Info (332115): 5.565 0.005 RR CELL High Speed mem|ddr4b_emif_read_mux~0~la_lab/laboutt[7]
|
|
Info (332115): 6.294 0.729 RR IC High Speed mem|ddr4b|ddr4b|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[1].tile_ctrl_inst|core2ctl_avl0[0]
|
|
Info (332115): 6.294 0.000 RR CELL mem|ddr4b|ddr4b|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[1].tile_ctrl_inst~hmc_reg1
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 3.869 3.869 latch edge time
|
|
Info (332115): 6.412 2.543 R clock network delay
|
|
Info (332115): 6.510 0.098 clock pessimism removed
|
|
Info (332115): 6.221 -0.289 clock uncertainty
|
|
Info (332115): 6.420 0.199 uTsu mem|ddr4b|ddr4b|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[1].tile_ctrl_inst~hmc_reg1
|
|
Info (332115): Data Arrival Time : 6.294
|
|
Info (332115): Data Required Time : 6.420
|
|
Info (332115): Slack : 0.126
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 0.186
|
|
Info (20696): -to_clock [get_clocks {mem|ddr4a|ddr4a_core_usr_clk}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 0.186
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : mem|ddr4b|ddr4b|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[0].lane_gen[2].lane_inst~phy_reg1
|
|
Info (332115): To Node : mem|u0|ram_2port_0|altera_syncram_component|auto_generated|altsyncram1|lutrama19~reg0
|
|
Info (332115): Launch Clock : mem|ddr4b|ddr4b_phy_clk_l_2
|
|
Info (332115): Latch Clock : mem|ddr4a|ddr4a_core_usr_clk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.117 0.117 launch edge time
|
|
Info (332115): 3.334 3.217 R clock network delay
|
|
Info (332115): 3.334 0.000 mem|ddr4b|ddr4b|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[0].lane_gen[2].lane_inst~phy_reg1
|
|
Info (332115): 4.206 0.872 FF uTco mem|ddr4b|ddr4b|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[0].lane_gen[2].lane_inst|data_to_core[56]
|
|
Info (332115): 6.110 1.904 FF IC High Speed mem|u0|ram_2port_0|altera_syncram_component|auto_generated|altsyncram1|lutrama19|portadatain[0]
|
|
Info (332115): 6.110 0.000 FF CELL High Speed mem|u0|ram_2port_0|altera_syncram_component|auto_generated|altsyncram1|lutrama19~reg0
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 3.869 3.869 latch edge time
|
|
Info (332115): 6.449 2.580 R clock network delay
|
|
Info (332115): 6.547 0.098 clock pessimism removed
|
|
Info (332115): 6.279 -0.268 clock uncertainty
|
|
Info (332115): 6.296 0.017 uTsu mem|u0|ram_2port_0|altera_syncram_component|auto_generated|altsyncram1|lutrama19~reg0
|
|
Info (332115): Data Arrival Time : 6.110
|
|
Info (332115): Data Required Time : 6.296
|
|
Info (332115): Slack : 0.186
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 0.294
|
|
Info (20696): -to_clock [get_clocks {mem|ddr4b|ddr4b_phy_clk_l_2}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 0.294
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : mem|ddr4b_avmm_chkr|clearing
|
|
Info (332115): To Node : mem|ddr4b|ddr4b|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[0].lane_gen[0].lane_inst~phy_reg1
|
|
Info (332115): Launch Clock : mem|ddr4a|ddr4a_core_usr_clk
|
|
Info (332115): Latch Clock : mem|ddr4b|ddr4b_phy_clk_l_2
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.117 0.117 launch edge time
|
|
Info (332115): 3.531 3.414 R clock network delay
|
|
Info (332115): 3.531 0.000 mem|ddr4b_avmm_chkr|clearing
|
|
Info (332115): 3.747 0.216 RR uTco mem|ddr4b_avmm_chkr|clearing|q
|
|
Info (332115): 3.877 0.130 RR CELL High Speed mem|ddr4b_avmm_chkr|clearing~la_lab/laboutb[17]
|
|
Info (332115): 4.836 0.959 RR IC High Speed mem|ddr4b_avmm_chkr|avm_writedata[0]~36|datad
|
|
Info (332115): 4.974 0.138 RF CELL High Speed mem|ddr4b_avmm_chkr|avm_writedata[0]~36|combout
|
|
Info (332115): 4.978 0.004 FF CELL High Speed mem|ddr4b_avmm_chkr|avm_writedata[0]~36~la_lab/laboutt[0]
|
|
Info (332115): 6.230 1.252 FF IC High Speed mem|ddr4b|ddr4b|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[0].lane_gen[0].lane_inst|data_from_core[28]
|
|
Info (332115): 6.230 0.000 FF CELL mem|ddr4b|ddr4b|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[0].lane_gen[0].lane_inst~phy_reg1
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 3.869 3.869 latch edge time
|
|
Info (332115): 6.358 2.489 R clock network delay
|
|
Info (332115): 6.456 0.098 clock pessimism removed
|
|
Info (332115): 6.167 -0.289 clock uncertainty
|
|
Info (332115): 6.524 0.357 uTsu mem|ddr4b|ddr4b|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[0].lane_gen[0].lane_inst~phy_reg1
|
|
Info (332115): Data Arrival Time : 6.230
|
|
Info (332115): Data Required Time : 6.524
|
|
Info (332115): Slack : 0.294
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 0.506
|
|
Info (20696): -to_clock [get_clocks {u0|dcp_iopll|dcp_iopll|clk1x}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 0.506
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|ReqAddr_q[9]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|TxCfgRdData[22]
|
|
Info (332115): Launch Clock : u0|dcp_iopll|dcp_iopll|clk1x
|
|
Info (332115): Latch Clock : u0|dcp_iopll|dcp_iopll|clk1x
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 9.595 9.595 R clock network delay
|
|
Info (332115): 9.595 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|ReqAddr_q[9]
|
|
Info (332115): 9.855 0.260 RR uTco fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|ReqAddr_q[9]|q
|
|
Info (332115): 10.006 0.151 RR CELL Low Power fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|ReqAddr_q[9]~la_lab/laboutt[6]
|
|
Info (332115): 10.793 0.787 RR IC Low Power fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|i1006~3|datae
|
|
Info (332115): 10.956 0.163 RR CELL Low Power fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|i1006~3|combout
|
|
Info (332115): 10.962 0.006 RR CELL Low Power fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|i1006~3~la_mlab/laboutb[16]
|
|
Info (332115): 11.188 0.226 RR IC Low Power fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|i1006~158|dataa
|
|
Info (332115): 11.483 0.295 RR CELL Low Power fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|i1006~158|combout
|
|
Info (332115): 11.489 0.006 RR CELL Low Power fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|i1006~158~la_mlab/laboutt[18]
|
|
Info (332115): 11.860 0.371 RR IC Low Power fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|i1006~163|datab
|
|
Info (332115): 12.153 0.293 RR CELL Low Power fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|i1006~163|combout
|
|
Info (332115): 12.159 0.006 RR CELL Low Power fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|i1006~163~la_mlab/laboutb[9]
|
|
Info (332115): 12.880 0.721 RR IC Low Power fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|i1006~164|datad
|
|
Info (332115): 13.082 0.202 RR CELL Low Power fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|i1006~164|combout
|
|
Info (332115): 13.088 0.006 RR CELL Low Power fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|i1006~164~la_mlab/laboutb[13]
|
|
Info (332115): 14.150 1.062 RR IC Low Power fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|i1006~165|dataf
|
|
Info (332115): 14.204 0.054 RR CELL Low Power fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|i1006~165|combout
|
|
Info (332115): 14.204 0.000 RR CELL Low Power fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|TxCfgRdData[22]|d
|
|
Info (332115): 14.204 0.000 RR CELL Low Power fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|TxCfgRdData[22]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 5.000 5.000 latch edge time
|
|
Info (332115): 13.277 8.277 R clock network delay
|
|
Info (332115): 14.536 1.259 clock pessimism removed
|
|
Info (332115): 14.386 -0.150 clock uncertainty
|
|
Info (332115): 14.710 0.324 uTsu fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|TxCfgRdData[22]
|
|
Info (332115): Data Arrival Time : 14.204
|
|
Info (332115): Data Required Time : 14.710
|
|
Info (332115): Slack : 0.506
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 0.539
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_bonding_clocks[0]}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 0.539
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|sta_rx_clk2_by4_1
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs~byte_deserializer_pcs_clk_div_by_4_txclk_reg.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|rx_clk (INVERTED)
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_bonding_clocks[0]
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 1.000 1.000 launch edge time
|
|
Info (332115): 5.219 4.219 F clock network delay
|
|
Info (332115): 5.219 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|sta_rx_clk2_by4_1
|
|
Info (332115): 5.219 0.000 FF CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs~byte_deserializer_pcs_clk_div_by_4_txclk_reg.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 2.000 2.000 latch edge time
|
|
Info (332115): 4.384 2.384 R clock network delay
|
|
Info (332115): 5.784 1.400 clock pessimism removed
|
|
Info (332115): 5.758 -0.026 uTsu fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs~byte_deserializer_pcs_clk_div_by_4_txclk_reg.reg
|
|
Info (332115): Data Arrival Time : 5.219
|
|
Info (332115): Data Required Time : 5.758
|
|
Info (332115): Slack : 0.539
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 0.565
|
|
Info (20696): -to_clock [get_clocks {u0|dcp_iopll|dcp_iopll|clk100}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 0.565
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_bitstream_host|alt_pr_bitstream_controller_v2|pr_data_reg[3]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_bitstream_host|alt_pr_bitstream_controller_v2|pr_data_reg2[3]
|
|
Info (332115): Launch Clock : u0|dcp_iopll|dcp_iopll|clk100
|
|
Info (332115): Latch Clock : u0|dcp_iopll|dcp_iopll|clk100 (INVERTED)
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 9.565 9.565 R clock network delay
|
|
Info (332115): 9.565 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_bitstream_host|alt_pr_bitstream_controller_v2|pr_data_reg[3]
|
|
Info (332115): 9.782 0.217 RR uTco fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_bitstream_host|alt_pr_bitstream_controller_v2|pr_data_reg[3]|q
|
|
Info (332115): 9.905 0.123 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_bitstream_host|alt_pr_bitstream_controller_v2|pr_data_reg[3]~la_lab/laboutb[2]
|
|
Info (332115): 13.919 4.014 RR IC Mixed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_bitstream_host|alt_pr_bitstream_controller_v2|pr_data_reg2[3]|d
|
|
Info (332115): 13.919 0.000 RR CELL Low Power fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_bitstream_host|alt_pr_bitstream_controller_v2|pr_data_reg2[3]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 5.000 5.000 latch edge time
|
|
Info (332115): 13.208 8.208 F clock network delay
|
|
Info (332115): 14.379 1.171 clock pessimism removed
|
|
Info (332115): 14.209 -0.170 clock uncertainty
|
|
Info (332115): 14.484 0.275 uTsu fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_bitstream_host|alt_pr_bitstream_controller_v2|pr_data_reg2[3]
|
|
Info (332115): Data Arrival Time : 13.919
|
|
Info (332115): Data Required Time : 14.484
|
|
Info (332115): Slack : 0.565
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 0.603
|
|
Info (20696): -to_clock [get_clocks {mem|ddr4a|ddr4a_phy_clk_l_0}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 0.603
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : mem|ddr4a_bridge|ddr_avmm_bridge|cmd_burstcount[5]
|
|
Info (332115): To Node : mem|ddr4a|ddr4a|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[1].tile_ctrl_inst~hmc_reg1
|
|
Info (332115): Launch Clock : mem|ddr4a|ddr4a_core_usr_clk
|
|
Info (332115): Latch Clock : mem|ddr4a|ddr4a_phy_clk_l_0
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.117 0.117 launch edge time
|
|
Info (332115): 3.663 3.546 R clock network delay
|
|
Info (332115): 3.663 0.000 mem|ddr4a_bridge|ddr_avmm_bridge|cmd_burstcount[5]
|
|
Info (332115): 3.890 0.227 RR uTco mem|ddr4a_bridge|ddr_avmm_bridge|cmd_burstcount[5]|q
|
|
Info (332115): 4.072 0.182 RR CELL High Speed mem|ddr4a_bridge|ddr_avmm_bridge|cmd_burstcount[5]~la_mlab/laboutb[15]
|
|
Info (332115): 4.450 0.378 RR IC High Speed mem|ddr4a_avmm_chkr|LessThan_0~0|datab
|
|
Info (332115): 4.692 0.242 RF CELL High Speed mem|ddr4a_avmm_chkr|LessThan_0~0|combout
|
|
Info (332115): 4.696 0.004 FF CELL High Speed mem|ddr4a_avmm_chkr|LessThan_0~0~la_lab/laboutb[6]
|
|
Info (332115): 4.896 0.200 FF IC High Speed mem|ddr4a_avmm_chkr|start_error|datac
|
|
Info (332115): 5.066 0.170 FR CELL High Speed mem|ddr4a_avmm_chkr|start_error|combout
|
|
Info (332115): 5.071 0.005 RR CELL High Speed mem|ddr4a_avmm_chkr|start_error~la_mlab/laboutt[6]
|
|
Info (332115): 5.243 0.172 RR IC High Speed mem|ddr4a_avmm_chkr|avm_write~1|datae
|
|
Info (332115): 5.384 0.141 RR CELL High Speed mem|ddr4a_avmm_chkr|avm_write~1|combout
|
|
Info (332115): 5.390 0.006 RR CELL High Speed mem|ddr4a_avmm_chkr|avm_write~1~la_mlab/laboutt[9]
|
|
Info (332115): 6.513 1.123 RR IC High Speed mem|ddr4a|ddr4a|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[1].tile_ctrl_inst|core2ctl_avl0[1]
|
|
Info (332115): 6.513 0.000 RR CELL mem|ddr4a|ddr4a|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[1].tile_ctrl_inst~hmc_reg1
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 3.869 3.869 latch edge time
|
|
Info (332115): 6.515 2.646 R clock network delay
|
|
Info (332115): 7.070 0.555 clock pessimism removed
|
|
Info (332115): 6.878 -0.192 clock uncertainty
|
|
Info (332115): 7.116 0.238 uTsu mem|ddr4a|ddr4a|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[1].tile_ctrl_inst~hmc_reg1
|
|
Info (332115): Data Arrival Time : 6.513
|
|
Info (332115): Data Required Time : 7.116
|
|
Info (332115): Slack : 0.603
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 0.636
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|pld_clk}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 0.636
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_sriov_2.sriov2.sriov_bridge|altpcie_pcie_sriov2_top_inst|altpcie_sriov2_tx_data_bridge_inst|TxStData_hip_o[234]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~pld_clk.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|wys~CORE_CLK_OUT
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|pld_clk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 9.189 9.189 R clock network delay
|
|
Info (332115): 9.189 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_sriov_2.sriov2.sriov_bridge|altpcie_pcie_sriov2_top_inst|altpcie_sriov2_tx_data_bridge_inst|TxStData_hip_o[234]
|
|
Info (332115): 9.518 0.329 RR uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_sriov_2.sriov2.sriov_bridge|altpcie_pcie_sriov2_top_inst|altpcie_sriov2_tx_data_bridge_inst|TxStData_hip_o[234]|q
|
|
Info (332115): 9.738 0.220 RR CELL Low Power fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_sriov_2.sriov2.sriov_bridge|altpcie_pcie_sriov2_top_inst|altpcie_sriov2_tx_data_bridge_inst|TxStData_hip_o[234]~la_mlab/laboutb[15]
|
|
Info (332115): 12.626 2.888 RR IC Mixed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|tx_st_data[234]
|
|
Info (332115): 12.626 0.000 RR CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~pld_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 4.000 4.000 latch edge time
|
|
Info (332115): 12.027 8.027 R clock network delay
|
|
Info (332115): 13.288 1.261 clock pessimism removed
|
|
Info (332115): 13.269 -0.019 clock uncertainty
|
|
Info (332115): 13.262 -0.007 uTsu fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~pld_clk.reg
|
|
Info (332115): Data Arrival Time : 12.626
|
|
Info (332115): Data Required Time : 13.262
|
|
Info (332115): Slack : 0.636
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 1.057
|
|
Info (20696): -to_clock [get_clocks {PCIE_REFCLK}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 1.057
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|rom_rtl_0|auto_generated|ram_block1a35~reg0
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|cpu_memory[87][7]
|
|
Info (332115): Launch Clock : PCIE_REFCLK
|
|
Info (332115): Latch Clock : PCIE_REFCLK
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 5.673 5.673 R clock network delay
|
|
Info (332115): 5.673 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|rom_rtl_0|auto_generated|ram_block1a35~reg0
|
|
Info (332115): 7.641 1.968 FF uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|rom_rtl_0|auto_generated|ram_block1a35|portadataout[0]
|
|
Info (332115): 8.418 0.777 FF IC Mixed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|i45392~1|dataf
|
|
Info (332115): 8.474 0.056 FR CELL Low Power fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|i45392~1|combout
|
|
Info (332115): 8.478 0.004 RR CELL Low Power fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|i45392~1~la_lab/laboutb[16]
|
|
Info (332115): 8.909 0.431 RR IC Mixed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|cpu_memory[64][31]~16|dataf
|
|
Info (332115): 8.953 0.044 RR CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|cpu_memory[64][31]~16|combout
|
|
Info (332115): 8.958 0.005 RR CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|cpu_memory[64][31]~16~la_lab/laboutb[9]
|
|
Info (332115): 11.801 2.843 RR IC Mixed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|cpu_memory[87][31]~50|dataf
|
|
Info (332115): 11.854 0.053 RR CELL Low Power fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|cpu_memory[87][31]~50|combout
|
|
Info (332115): 11.860 0.006 RR CELL Low Power fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|cpu_memory[87][31]~50~la_mlab/laboutb[0]
|
|
Info (332115): 14.558 2.698 RR IC Mixed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|cpu_memory[87][7]|ena
|
|
Info (332115): 14.558 0.000 RR CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|cpu_memory[87][7]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 10.000 10.000 latch edge time
|
|
Info (332115): 15.061 5.061 R clock network delay
|
|
Info (332115): 15.602 0.541 clock pessimism removed
|
|
Info (332115): 15.562 -0.040 clock uncertainty
|
|
Info (332115): 15.615 0.053 uTsu fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|cpu_memory[87][7]
|
|
Info (332115): Data Arrival Time : 14.558
|
|
Info (332115): Data Required Time : 15.615
|
|
Info (332115): Slack : 1.057
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 1.217
|
|
Info (20696): -to_clock [get_clocks {mem|ddr4a|ddr4a_core_cal_slave_clk}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 1.217
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : mem|ddr4b|ddr4b|arch|arch_inst|io_aux_inst|io_aux~soft_ram_reg
|
|
Info (332115): To Node : mem|ddr4b|ddr4b|cal_slave_component|ioaux_master_bridge|cmd_writedata[1]
|
|
Info (332115): Launch Clock : mem|ddr4a|ddr4a_core_cal_slave_clk
|
|
Info (332115): Latch Clock : mem|ddr4a|ddr4a_core_cal_slave_clk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 7.272 7.272 R clock network delay
|
|
Info (332115): 7.272 0.000 mem|ddr4b|ddr4b|arch|arch_inst|io_aux_inst|io_aux~soft_ram_reg
|
|
Info (332115): 8.075 0.803 FF uTco mem|ddr4b|ddr4b|arch|arch_inst|io_aux_inst|io_aux|soft_ram_write_data[1]
|
|
Info (332115): 12.234 4.159 FF IC High Speed mem|ddr4b|ddr4b|cal_slave_component|ioaux_master_bridge|cmd_writedata[1]|asdata
|
|
Info (332115): 12.234 0.000 FF CELL High Speed mem|ddr4b|ddr4b|cal_slave_component|ioaux_master_bridge|cmd_writedata[1]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 6.566 6.566 latch edge time
|
|
Info (332115): 12.521 5.955 R clock network delay
|
|
Info (332115): 13.381 0.860 clock pessimism removed
|
|
Info (332115): 13.331 -0.050 clock uncertainty
|
|
Info (332115): 13.451 0.120 uTsu mem|ddr4b|ddr4b|cal_slave_component|ioaux_master_bridge|cmd_writedata[1]
|
|
Info (332115): Data Arrival Time : 12.234
|
|
Info (332115): Data Required Time : 13.451
|
|
Info (332115): Slack : 1.217
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 1.585
|
|
Info (20696): -to_clock [get_clocks {SYS_RefClk}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 1.585
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_cb_host|alt_pr_cb_controller_v2|freeze_reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi.f2a_prmgmt_freeze
|
|
Info (332115): Launch Clock : u0|dcp_iopll|dcp_iopll|clk100
|
|
Info (332115): Latch Clock : SYS_RefClk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 9.509 9.509 R clock network delay
|
|
Info (332115): 9.509 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_cb_host|alt_pr_cb_controller_v2|freeze_reg
|
|
Info (332115): 9.731 0.222 RR uTco fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_cb_host|alt_pr_cb_controller_v2|freeze_reg|q
|
|
Info (332115): 9.890 0.159 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_cb_host|alt_pr_cb_controller_v2|freeze_reg~la_lab/laboutt[8]
|
|
Info (332115): 12.856 2.966 RR IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|i617~0|datae
|
|
Info (332115): 12.985 0.129 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|i617~0|combout
|
|
Info (332115): 12.985 0.000 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi.f2a_prmgmt_freeze|d
|
|
Info (332115): 12.985 0.000 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi.f2a_prmgmt_freeze
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 10.000 10.000 latch edge time
|
|
Info (332115): 14.329 4.329 R clock network delay
|
|
Info (332115): 14.565 0.236 clock pessimism removed
|
|
Info (332115): 14.255 -0.310 clock uncertainty
|
|
Info (332115): 14.570 0.315 uTsu fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi.f2a_prmgmt_freeze
|
|
Info (332115): Data Arrival Time : 12.985
|
|
Info (332115): Data Required Time : 14.570
|
|
Info (332115): Slack : 1.585
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 2.294
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_clk}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 2.294
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_prbs_done_sync|resync_chains[0].sync_r[1]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_snapshot[6]
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_clk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_clk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 7.034 7.034 R clock network delay
|
|
Info (332115): 7.034 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_prbs_done_sync|resync_chains[0].sync_r[1]
|
|
Info (332115): 7.250 0.216 RR uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_prbs_done_sync|resync_chains[0].sync_r[1]|q
|
|
Info (332115): 7.415 0.165 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_prbs_done_sync|resync_chains[0].sync_r[1]~la_lab/laboutb[3]
|
|
Info (332115): 7.987 0.572 RR IC High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_snapshot[1]~0|datac
|
|
Info (332115): 8.137 0.150 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_snapshot[1]~0|combout
|
|
Info (332115): 8.142 0.005 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_snapshot[1]~0~la_lab/laboutt[7]
|
|
Info (332115): 8.591 0.449 RR IC High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_snapshot[6]|ena
|
|
Info (332115): 8.591 0.000 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_snapshot[6]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 3.878 3.878 latch edge time
|
|
Info (332115): 8.930 5.052 R clock network delay
|
|
Info (332115): 10.866 1.936 clock pessimism removed
|
|
Info (332115): 10.836 -0.030 clock uncertainty
|
|
Info (332115): 10.885 0.049 uTsu fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_snapshot[6]
|
|
Info (332115): Data Arrival Time : 8.591
|
|
Info (332115): Data Required Time : 10.885
|
|
Info (332115): Slack : 2.294
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 2.305
|
|
Info (20696): -to_clock [get_clocks {ETH_RefClk}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 2.305
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[6].ct0|dout_r[0]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[6].ct0|dout_r[1]
|
|
Info (332115): Launch Clock : ETH_RefClk
|
|
Info (332115): Latch Clock : ETH_RefClk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 5.493 5.493 R clock network delay
|
|
Info (332115): 5.493 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[6].ct0|dout_r[0]
|
|
Info (332115): 5.742 0.249 RR uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[6].ct0|dout_r[0]|q
|
|
Info (332115): 5.877 0.135 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[6].ct0|dout_r[0]~la_lab/laboutb[13]
|
|
Info (332115): 6.211 0.334 RR IC Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[6].ct0|t1|dout|datab
|
|
Info (332115): 6.518 0.307 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[6].ct0|t1|dout|combout
|
|
Info (332115): 6.518 0.000 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[6].ct0|dout_r[1]|d
|
|
Info (332115): 6.518 0.000 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[6].ct0|dout_r[1]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 3.103 3.103 latch edge time
|
|
Info (332115): 8.033 4.930 R clock network delay
|
|
Info (332115): 8.596 0.563 clock pessimism removed
|
|
Info (332115): 8.556 -0.040 clock uncertainty
|
|
Info (332115): 8.823 0.267 uTsu fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[6].ct0|dout_r[1]
|
|
Info (332115): Data Arrival Time : 6.518
|
|
Info (332115): Data Required Time : 8.823
|
|
Info (332115): Slack : 2.305
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 2.305
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|rx_pma_clk}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 2.305
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_prbs_reset_sync|resync_chains[0].sync_r[2]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_snapshot[6]
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|rx_pma_clk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|rx_pma_clk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 7.027 7.027 R clock network delay
|
|
Info (332115): 7.027 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_prbs_reset_sync|resync_chains[0].sync_r[2]
|
|
Info (332115): 7.243 0.216 RR uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_prbs_reset_sync|resync_chains[0].sync_r[2]|q
|
|
Info (332115): 7.355 0.112 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_prbs_reset_sync|resync_chains[0].sync_r[2]~la_lab/laboutt[14]
|
|
Info (332115): 7.860 0.505 RR IC High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_snapshot[0]~0|dataa
|
|
Info (332115): 8.107 0.247 RF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_snapshot[0]~0|combout
|
|
Info (332115): 8.111 0.004 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_snapshot[0]~0~la_lab/laboutt[8]
|
|
Info (332115): 8.590 0.479 FF IC High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_snapshot[6]|ena
|
|
Info (332115): 8.590 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_snapshot[6]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 3.878 3.878 latch edge time
|
|
Info (332115): 8.925 5.047 R clock network delay
|
|
Info (332115): 10.869 1.944 clock pessimism removed
|
|
Info (332115): 10.839 -0.030 clock uncertainty
|
|
Info (332115): 10.895 0.056 uTsu fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_snapshot[6]
|
|
Info (332115): Data Arrival Time : 8.590
|
|
Info (332115): Data Required Time : 10.895
|
|
Info (332115): Slack : 2.305
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 2.308
|
|
Info (20696): -to_clock [get_clocks {DDR4_RefClk}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 2.308
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|use_counter_lock.counter_lock_gen_master.cpa_count_to_lock[1]
|
|
Info (332115): To Node : mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|use_counter_lock.counter_lock_gen_master.cpa_count_to_lock[16]~LRTM_3
|
|
Info (332115): Launch Clock : DDR4_RefClk
|
|
Info (332115): Latch Clock : DDR4_RefClk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 4.346 4.346 R clock network delay
|
|
Info (332115): 4.346 0.000 mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|use_counter_lock.counter_lock_gen_master.cpa_count_to_lock[1]
|
|
Info (332115): 4.563 0.217 RR uTco mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|use_counter_lock.counter_lock_gen_master.cpa_count_to_lock[1]|q
|
|
Info (332115): 4.679 0.116 RR CELL High Speed mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|use_counter_lock.counter_lock_gen_master.cpa_count_to_lock[1]~la_lab/laboutt[1]
|
|
Info (332115): 4.858 0.179 RR IC High Speed mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|add_0~61|datac
|
|
Info (332115): 5.528 0.670 RR CELL High Speed mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|add_0~21|cin
|
|
Info (332115): 5.557 0.029 RF CELL High Speed mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|add_0~17|cout
|
|
Info (332115): 5.557 0.000 FF CELL High Speed mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|add_0~13|cin
|
|
Info (332115): 5.589 0.032 FR CELL High Speed mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|add_0~9|cout
|
|
Info (332115): 5.589 0.000 RR CELL High Speed mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|add_0~5|cin
|
|
Info (332115): 5.811 0.222 RR CELL High Speed mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|add_0~1|sumout
|
|
Info (332115): 5.815 0.004 RR CELL High Speed mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|add_0~1~la_lab/laboutb[10]
|
|
Info (332115): 5.980 0.165 RR IC High Speed mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|use_counter_lock.counter_lock_gen_master.cpa_count_to_lock[16]~LRTM_3|d
|
|
Info (332115): 5.980 0.000 RR CELL High Speed mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|use_counter_lock.counter_lock_gen_master.cpa_count_to_lock[16]~LRTM_3
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 3.752 3.752 latch edge time
|
|
Info (332115): 7.777 4.025 R clock network delay
|
|
Info (332115): 8.079 0.302 clock pessimism removed
|
|
Info (332115): 8.049 -0.030 clock uncertainty
|
|
Info (332115): 8.288 0.239 uTsu mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|use_counter_lock.counter_lock_gen_master.cpa_count_to_lock[16]~LRTM_3
|
|
Info (332115): Data Arrival Time : 5.980
|
|
Info (332115): Data Required Time : 8.288
|
|
Info (332115): Slack : 2.308
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 2.315
|
|
Info (20696): -to_clock [get_clocks {hssi_pll_r_0_outclk0}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 2.315
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[2].ct0|dout_r[4]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[2].ct0|dout_r[5]
|
|
Info (332115): Launch Clock : hssi_pll_r_0_outclk0
|
|
Info (332115): Latch Clock : hssi_pll_r_0_outclk0
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 4.942 4.942 R clock network delay
|
|
Info (332115): 4.942 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[2].ct0|dout_r[4]
|
|
Info (332115): 5.259 0.317 RR uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[2].ct0|dout_r[4]|q
|
|
Info (332115): 5.443 0.184 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[2].ct0|dout_r[4]~la_lab/laboutt[12]
|
|
Info (332115): 5.964 0.521 RR IC Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[2].ct0|t5|dout|dataf
|
|
Info (332115): 6.021 0.057 RF CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[2].ct0|t5|dout|combout
|
|
Info (332115): 6.021 0.000 FF CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[2].ct0|dout_r[5]|d
|
|
Info (332115): 6.021 0.000 FF CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[2].ct0|dout_r[5]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 3.200 3.200 latch edge time
|
|
Info (332115): 7.644 4.444 R clock network delay
|
|
Info (332115): 8.142 0.498 clock pessimism removed
|
|
Info (332115): 8.032 -0.110 clock uncertainty
|
|
Info (332115): 8.336 0.304 uTsu fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[2].ct0|dout_r[5]
|
|
Info (332115): Data Arrival Time : 6.021
|
|
Info (332115): Data Required Time : 8.336
|
|
Info (332115): Slack : 2.315
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 2.357
|
|
Info (20696): -to_clock [get_clocks {hssi_pll_t_outclk0}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 2.357
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[3].ct0|dout_r[1]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[3].ct0|dout_r[5]
|
|
Info (332115): Launch Clock : hssi_pll_t_outclk0
|
|
Info (332115): Latch Clock : hssi_pll_t_outclk0
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 4.649 4.649 R clock network delay
|
|
Info (332115): 4.649 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[3].ct0|dout_r[1]
|
|
Info (332115): 4.896 0.247 RR uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[3].ct0|dout_r[1]|q
|
|
Info (332115): 5.080 0.184 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[3].ct0|dout_r[1]~la_lab/laboutb[16]
|
|
Info (332115): 5.599 0.519 RR IC Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[3].ct0|t5|dout|dataf
|
|
Info (332115): 5.656 0.057 RF CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[3].ct0|t5|dout|combout
|
|
Info (332115): 5.656 0.000 FF CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[3].ct0|dout_r[5]|d
|
|
Info (332115): 5.656 0.000 FF CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[3].ct0|dout_r[5]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 3.200 3.200 latch edge time
|
|
Info (332115): 7.398 4.198 R clock network delay
|
|
Info (332115): 7.848 0.450 clock pessimism removed
|
|
Info (332115): 7.738 -0.110 clock uncertainty
|
|
Info (332115): 8.013 0.275 uTsu fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[3].ct0|dout_r[5]
|
|
Info (332115): Data Arrival Time : 5.656
|
|
Info (332115): Data Required Time : 8.013
|
|
Info (332115): Slack : 2.357
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 2.439
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|rx_pma_clk}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 2.439
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_prbs_reset_sync|resync_chains[0].sync_r[2]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_snapshot[1]
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|rx_pma_clk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|rx_pma_clk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 6.928 6.928 R clock network delay
|
|
Info (332115): 6.928 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_prbs_reset_sync|resync_chains[0].sync_r[2]
|
|
Info (332115): 7.154 0.226 RR uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_prbs_reset_sync|resync_chains[0].sync_r[2]|q
|
|
Info (332115): 7.336 0.182 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_prbs_reset_sync|resync_chains[0].sync_r[2]~la_mlab/laboutb[12]
|
|
Info (332115): 8.034 0.698 RR IC High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_snapshot[5]~0|datad
|
|
Info (332115): 8.171 0.137 RF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_snapshot[5]~0|combout
|
|
Info (332115): 8.175 0.004 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_snapshot[5]~0~la_lab/laboutb[0]
|
|
Info (332115): 8.341 0.166 FF IC High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_snapshot[1]|ena
|
|
Info (332115): 8.341 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_snapshot[1]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 3.878 3.878 latch edge time
|
|
Info (332115): 8.811 4.933 R clock network delay
|
|
Info (332115): 10.757 1.946 clock pessimism removed
|
|
Info (332115): 10.727 -0.030 clock uncertainty
|
|
Info (332115): 10.780 0.053 uTsu fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_snapshot[1]
|
|
Info (332115): Data Arrival Time : 8.341
|
|
Info (332115): Data Required Time : 10.780
|
|
Info (332115): Slack : 2.439
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 2.532
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|rx_pma_clk}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 2.532
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_prbs_err_sync|resync_chains[0].sync_r[1]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_count[0]
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|rx_pma_clk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|rx_pma_clk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 7.001 7.001 R clock network delay
|
|
Info (332115): 7.001 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_prbs_err_sync|resync_chains[0].sync_r[1]
|
|
Info (332115): 7.219 0.218 RR uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_prbs_err_sync|resync_chains[0].sync_r[1]|q
|
|
Info (332115): 7.330 0.111 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_prbs_err_sync|resync_chains[0].sync_r[1]~la_mlab/laboutt[14]
|
|
Info (332115): 7.722 0.392 RR IC High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|add_2~1|datab
|
|
Info (332115): 8.201 0.479 RF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|add_2~1|sumout
|
|
Info (332115): 8.206 0.005 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|add_2~1~la_lab/laboutb[1]
|
|
Info (332115): 8.424 0.218 FF IC High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|i58~0|datad
|
|
Info (332115): 8.596 0.172 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|i58~0|combout
|
|
Info (332115): 8.596 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_count[0]|d
|
|
Info (332115): 8.596 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_count[0]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 3.878 3.878 latch edge time
|
|
Info (332115): 8.896 5.018 R clock network delay
|
|
Info (332115): 10.880 1.984 clock pessimism removed
|
|
Info (332115): 10.850 -0.030 clock uncertainty
|
|
Info (332115): 11.128 0.278 uTsu fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_count[0]
|
|
Info (332115): Data Arrival Time : 8.596
|
|
Info (332115): Data Required Time : 11.128
|
|
Info (332115): Slack : 2.532
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 2.944
|
|
Info (20696): -to_clock [get_clocks {hssi_pll_r_0_outclk1}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 2.944
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[0].ct0|dout_r[0]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[0].ct0|dout_r[2]
|
|
Info (332115): Launch Clock : hssi_pll_r_0_outclk1
|
|
Info (332115): Latch Clock : hssi_pll_r_0_outclk1
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 4.934 4.934 R clock network delay
|
|
Info (332115): 4.934 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[0].ct0|dout_r[0]
|
|
Info (332115): 5.183 0.249 RR uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[0].ct0|dout_r[0]|q
|
|
Info (332115): 5.374 0.191 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[0].ct0|dout_r[0]~la_lab/laboutb[15]
|
|
Info (332115): 5.685 0.311 RR IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[0].ct0|t2|dout|dataa
|
|
Info (332115): 5.992 0.307 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[0].ct0|t2|dout|combout
|
|
Info (332115): 5.992 0.000 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[0].ct0|dout_r[2]|d
|
|
Info (332115): 5.992 0.000 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[0].ct0|dout_r[2]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 3.800 3.800 latch edge time
|
|
Info (332115): 8.233 4.433 R clock network delay
|
|
Info (332115): 8.734 0.501 clock pessimism removed
|
|
Info (332115): 8.624 -0.110 clock uncertainty
|
|
Info (332115): 8.936 0.312 uTsu fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[0].ct0|dout_r[2]
|
|
Info (332115): Data Arrival Time : 5.992
|
|
Info (332115): Data Required Time : 8.936
|
|
Info (332115): Slack : 2.944
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 2.986
|
|
Info (20696): -to_clock [get_clocks {hssi_pll_t_outclk1}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 2.986
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[1].ct0|dout_r[5]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[1].ct0|dout_r[5]
|
|
Info (332115): Launch Clock : hssi_pll_t_outclk1
|
|
Info (332115): Latch Clock : hssi_pll_t_outclk1
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 4.568 4.568 R clock network delay
|
|
Info (332115): 4.568 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[1].ct0|dout_r[5]
|
|
Info (332115): 4.793 0.225 RR uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[1].ct0|dout_r[5]|q
|
|
Info (332115): 4.953 0.160 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[1].ct0|dout_r[5]~la_mlab/laboutt[16]
|
|
Info (332115): 5.335 0.382 RR IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[1].ct0|t5|dout|datae
|
|
Info (332115): 5.479 0.144 RF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[1].ct0|t5|dout|combout
|
|
Info (332115): 5.479 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[1].ct0|dout_r[5]|d
|
|
Info (332115): 5.479 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[1].ct0|dout_r[5]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 3.800 3.800 latch edge time
|
|
Info (332115): 7.924 4.124 R clock network delay
|
|
Info (332115): 8.367 0.443 clock pessimism removed
|
|
Info (332115): 8.257 -0.110 clock uncertainty
|
|
Info (332115): 8.465 0.208 uTsu fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[1].ct0|dout_r[5]
|
|
Info (332115): Data Arrival Time : 5.479
|
|
Info (332115): Data Required Time : 8.465
|
|
Info (332115): Slack : 2.986
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 3.210
|
|
Info (20696): -to_clock [get_clocks {vl_qph_user_clk_clkpsc_clk1}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 3.210
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[0]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[1]
|
|
Info (332115): Launch Clock : vl_qph_user_clk_clkpsc_clk1
|
|
Info (332115): Latch Clock : vl_qph_user_clk_clkpsc_clk1
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 6.916 6.916 R clock network delay
|
|
Info (332115): 6.916 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[0]
|
|
Info (332115): 7.148 0.232 RR uTco fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[0]|q
|
|
Info (332115): 7.263 0.115 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[0]~la_mlab/laboutb[9]
|
|
Info (332115): 8.211 0.948 RR IC Mixed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[1]~2|dataa
|
|
Info (332115): 8.468 0.257 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[1]~2|combout
|
|
Info (332115): 8.468 0.000 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[1]|d
|
|
Info (332115): 8.468 0.000 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[1]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 4.545 4.545 latch edge time
|
|
Info (332115): 10.266 5.721 R clock network delay
|
|
Info (332115): 11.455 1.189 clock pessimism removed
|
|
Info (332115): 11.425 -0.030 clock uncertainty
|
|
Info (332115): 11.678 0.253 uTsu fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[1]
|
|
Info (332115): Data Arrival Time : 8.468
|
|
Info (332115): Data Required Time : 11.678
|
|
Info (332115): Slack : 3.210
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 3.381
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|avmmclk}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 3.381
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|reconfig_read
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Launch Clock : SYS_RefClk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|avmmclk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 4.678 4.678 R clock network delay
|
|
Info (332115): 4.678 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|reconfig_read
|
|
Info (332115): 4.912 0.234 FF uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|reconfig_read|q
|
|
Info (332115): 5.039 0.127 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|reconfig_read~la_mlab/laboutb[4]
|
|
Info (332115): 6.595 1.556 FF IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|avmm_read[1]~1|dataa
|
|
Info (332115): 6.814 0.219 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|avmm_read[1]~1|combout
|
|
Info (332115): 6.819 0.005 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|avmm_read[1]~1~la_lab/laboutt[7]
|
|
Info (332115): 11.577 4.758 FF IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst|avmmread
|
|
Info (332115): 11.577 0.000 FF CELL fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 10.000 10.000 latch edge time
|
|
Info (332115): 14.542 4.542 R clock network delay
|
|
Info (332115): 14.778 0.236 clock pessimism removed
|
|
Info (332115): 14.748 -0.030 clock uncertainty
|
|
Info (332115): 14.958 0.210 uTsu fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Arrival Time : 11.577
|
|
Info (332115): Data Required Time : 14.958
|
|
Info (332115): Slack : 3.381
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 3.496
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|avmmclk}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 3.496
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|reconfig_write
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Launch Clock : SYS_RefClk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|avmmclk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 4.678 4.678 R clock network delay
|
|
Info (332115): 4.678 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|reconfig_write
|
|
Info (332115): 4.919 0.241 RR uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|reconfig_write|q
|
|
Info (332115): 5.043 0.124 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|reconfig_write~la_mlab/laboutt[10]
|
|
Info (332115): 6.743 1.700 RR IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|avmm_write[2]~2|datac
|
|
Info (332115): 6.901 0.158 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|avmm_write[2]~2|combout
|
|
Info (332115): 6.905 0.004 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|avmm_write[2]~2~la_lab/laboutb[4]
|
|
Info (332115): 11.290 4.385 RR IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst|avmmwrite
|
|
Info (332115): 11.290 0.000 RR CELL fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 10.000 10.000 latch edge time
|
|
Info (332115): 14.543 4.543 R clock network delay
|
|
Info (332115): 14.779 0.236 clock pessimism removed
|
|
Info (332115): 14.749 -0.030 clock uncertainty
|
|
Info (332115): 14.786 0.037 uTsu fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Arrival Time : 11.290
|
|
Info (332115): Data Required Time : 14.786
|
|
Info (332115): Slack : 3.496
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 3.675
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|avmmclk}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 3.675
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|reconfig_read
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Launch Clock : SYS_RefClk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|avmmclk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 4.678 4.678 R clock network delay
|
|
Info (332115): 4.678 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|reconfig_read
|
|
Info (332115): 4.912 0.234 RR uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|reconfig_read|q
|
|
Info (332115): 5.083 0.171 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|reconfig_read~la_mlab/laboutb[4]
|
|
Info (332115): 6.710 1.627 RR IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|avmm_read[0]~0|dataa
|
|
Info (332115): 6.976 0.266 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|avmm_read[0]~0|combout
|
|
Info (332115): 6.980 0.004 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|avmm_read[0]~0~la_lab/laboutt[4]
|
|
Info (332115): 11.293 4.313 RR IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst|avmmread
|
|
Info (332115): 11.293 0.000 RR CELL fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 10.000 10.000 latch edge time
|
|
Info (332115): 14.545 4.545 R clock network delay
|
|
Info (332115): 14.781 0.236 clock pessimism removed
|
|
Info (332115): 14.751 -0.030 clock uncertainty
|
|
Info (332115): 14.968 0.217 uTsu fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Arrival Time : 11.293
|
|
Info (332115): Data Required Time : 14.968
|
|
Info (332115): Slack : 3.675
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 4.499
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|avmmclk}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 4.499
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_address[3]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Launch Clock : PCIE_REFCLK
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|avmmclk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 5.652 5.652 R clock network delay
|
|
Info (332115): 5.652 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_address[3]
|
|
Info (332115): 5.902 0.250 RR uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_address[3]|q
|
|
Info (332115): 6.114 0.212 RR CELL Low Power fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_address[3]~la_lab/laboutt[19]
|
|
Info (332115): 7.301 1.187 RR IC Mixed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i1697|dataf
|
|
Info (332115): 7.346 0.045 RR CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i1697|combout
|
|
Info (332115): 7.350 0.004 RR CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i1697~la_lab/laboutb[0]
|
|
Info (332115): 11.209 3.859 RR IC Mixed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst|avmmaddress[3]
|
|
Info (332115): 11.209 0.000 RR CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 10.000 10.000 latch edge time
|
|
Info (332115): 15.277 5.277 R clock network delay
|
|
Info (332115): 15.761 0.484 clock pessimism removed
|
|
Info (332115): 15.721 -0.040 clock uncertainty
|
|
Info (332115): 15.708 -0.013 uTsu fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Arrival Time : 11.209
|
|
Info (332115): Data Required Time : 15.708
|
|
Info (332115): Slack : 4.499
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 4.502
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|avmmclk}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 4.502
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|reconfig_read
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Launch Clock : SYS_RefClk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|avmmclk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 4.678 4.678 R clock network delay
|
|
Info (332115): 4.678 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|reconfig_read
|
|
Info (332115): 4.912 0.234 RR uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|reconfig_read|q
|
|
Info (332115): 5.083 0.171 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|reconfig_read~la_mlab/laboutb[4]
|
|
Info (332115): 6.606 1.523 RR IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|avmm_read[3]~3|datab
|
|
Info (332115): 6.864 0.258 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|avmm_read[3]~3|combout
|
|
Info (332115): 6.869 0.005 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|avmm_read[3]~3~la_mlab/laboutt[2]
|
|
Info (332115): 10.566 3.697 RR IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst|avmmread
|
|
Info (332115): 10.566 0.000 RR CELL fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 10.000 10.000 latch edge time
|
|
Info (332115): 14.645 4.645 R clock network delay
|
|
Info (332115): 14.881 0.236 clock pessimism removed
|
|
Info (332115): 14.851 -0.030 clock uncertainty
|
|
Info (332115): 15.068 0.217 uTsu fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Arrival Time : 10.566
|
|
Info (332115): Data Required Time : 15.068
|
|
Info (332115): Slack : 4.502
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 4.768
|
|
Info (20696): -to_clock [get_clocks {fspi_sclk}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 4.768
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_altera_avalon_st_packets_to_bytes_inst_for_spichain|the_altera_avalon_st_packets_to_bytes|out_data[6]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MISOctl|rdshiftreg[0]
|
|
Info (332115): Launch Clock : u0|dcp_iopll|dcp_iopll|clk1x
|
|
Info (332115): Latch Clock : fspi_sclk
|
|
Info (332115): Exception : dcp_bbs.sdc:3006: set_multicycle_path -setup -to [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MISOctl|rdshiftreg*}] 2
|
|
Info (332115): Multicycle - Setup Start : 2
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 240.000 240.000 launch edge time
|
|
Info (332115): 249.537 9.537 R clock network delay
|
|
Info (332115): 249.537 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_altera_avalon_st_packets_to_bytes_inst_for_spichain|the_altera_avalon_st_packets_to_bytes|out_data[6]
|
|
Info (332115): 249.753 0.216 RR uTco fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_altera_avalon_st_packets_to_bytes_inst_for_spichain|the_altera_avalon_st_packets_to_bytes|out_data[6]|q
|
|
Info (332115): 249.912 0.159 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_altera_avalon_st_packets_to_bytes_inst_for_spichain|the_altera_avalon_st_packets_to_bytes|out_data[6]~la_lab/laboutb[8]
|
|
Info (332115): 250.197 0.285 RR IC High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_altera_avalon_st_idle_inserter|i15~1|datab
|
|
Info (332115): 250.462 0.265 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_altera_avalon_st_idle_inserter|i15~1|combout
|
|
Info (332115): 250.467 0.005 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_altera_avalon_st_idle_inserter|i15~1~la_lab/laboutb[5]
|
|
Info (332115): 250.658 0.191 RR IC High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MISOctl|i36~7|dataa
|
|
Info (332115): 250.925 0.267 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MISOctl|i36~7|combout
|
|
Info (332115): 250.925 0.000 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MISOctl|rdshiftreg[0]|d
|
|
Info (332115): 250.925 0.000 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MISOctl|rdshiftreg[0]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 250.000 250.000 latch edge time
|
|
Info (332115): 255.722 5.722 R clock network delay
|
|
Info (332115): 255.412 -0.310 clock uncertainty
|
|
Info (332115): 255.693 0.281 uTsu fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MISOctl|rdshiftreg[0]
|
|
Info (332115): Data Arrival Time : 250.925
|
|
Info (332115): Data Required Time : 255.693
|
|
Info (332115): Slack : 4.768
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 4.946
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|avmmclk}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 4.946
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_writedata[4]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Launch Clock : PCIE_REFCLK
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|avmmclk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 5.630 5.630 R clock network delay
|
|
Info (332115): 5.630 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_writedata[4]
|
|
Info (332115): 5.855 0.225 FF uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_writedata[4]|q
|
|
Info (332115): 5.943 0.088 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_writedata[4]~la_lab/laboutt[5]
|
|
Info (332115): 7.029 1.086 FF IC Mixed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i1496~4|datac
|
|
Info (332115): 7.225 0.196 FF CELL Low Power fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i1496~4|combout
|
|
Info (332115): 7.231 0.006 FF CELL Low Power fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i1496~4~la_mlab/laboutt[14]
|
|
Info (332115): 10.724 3.493 FF IC Mixed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst|avmmwritedata[4]
|
|
Info (332115): 10.724 0.000 FF CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 10.000 10.000 latch edge time
|
|
Info (332115): 15.272 5.272 R clock network delay
|
|
Info (332115): 15.756 0.484 clock pessimism removed
|
|
Info (332115): 15.716 -0.040 clock uncertainty
|
|
Info (332115): 15.670 -0.046 uTsu fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Arrival Time : 10.724
|
|
Info (332115): Data Required Time : 15.670
|
|
Info (332115): Slack : 4.946
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 5.231
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|avmmclk}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 5.231
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|g_arb[5].arbiter_inst|grant[0]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Launch Clock : PCIE_REFCLK
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|avmmclk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 5.645 5.645 R clock network delay
|
|
Info (332115): 5.645 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|g_arb[5].arbiter_inst|grant[0]
|
|
Info (332115): 5.907 0.262 FF uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|g_arb[5].arbiter_inst|grant[0]|q
|
|
Info (332115): 6.047 0.140 FF CELL Low Power fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|g_arb[5].arbiter_inst|grant[0]~la_mlab/laboutb[11]
|
|
Info (332115): 6.883 0.836 FF IC Low Power fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i1215|dataf
|
|
Info (332115): 6.931 0.048 FF CELL Low Power fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i1215|combout
|
|
Info (332115): 6.936 0.005 FF CELL Low Power fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i1215~la_lab/laboutt[2]
|
|
Info (332115): 10.397 3.461 FF IC Mixed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst|avmmaddress[1]
|
|
Info (332115): 10.397 0.000 FF CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 10.000 10.000 latch edge time
|
|
Info (332115): 15.230 5.230 R clock network delay
|
|
Info (332115): 15.714 0.484 clock pessimism removed
|
|
Info (332115): 15.674 -0.040 clock uncertainty
|
|
Info (332115): 15.628 -0.046 uTsu fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Arrival Time : 10.397
|
|
Info (332115): Data Required Time : 15.628
|
|
Info (332115): Slack : 5.231
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 5.508
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|avmmclk}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 5.508
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_address[2]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Launch Clock : PCIE_REFCLK
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|avmmclk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 5.652 5.652 R clock network delay
|
|
Info (332115): 5.652 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_address[2]
|
|
Info (332115): 5.902 0.250 FF uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_address[2]|q
|
|
Info (332115): 6.005 0.103 FF CELL Low Power fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_address[2]~la_lab/laboutb[13]
|
|
Info (332115): 7.165 1.160 FF IC Mixed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i984|datac
|
|
Info (332115): 7.320 0.155 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i984|combout
|
|
Info (332115): 7.326 0.006 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i984~la_mlab/laboutt[0]
|
|
Info (332115): 10.248 2.922 FF IC Mixed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst|avmmaddress[2]
|
|
Info (332115): 10.248 0.000 FF CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 10.000 10.000 latch edge time
|
|
Info (332115): 15.248 5.248 R clock network delay
|
|
Info (332115): 15.732 0.484 clock pessimism removed
|
|
Info (332115): 15.692 -0.040 clock uncertainty
|
|
Info (332115): 15.756 0.064 uTsu fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Arrival Time : 10.248
|
|
Info (332115): Data Required Time : 15.756
|
|
Info (332115): Slack : 5.508
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 5.547
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|tx_pma_div_clk}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 5.547
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[5].ct0|dout_r[5]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[5].ct0|dout_r[5]
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|tx_pma_div_clk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|tx_pma_div_clk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 8.701 8.701 R clock network delay
|
|
Info (332115): 8.701 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[5].ct0|dout_r[5]
|
|
Info (332115): 8.917 0.216 RR uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[5].ct0|dout_r[5]|q
|
|
Info (332115): 9.076 0.159 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[5].ct0|dout_r[5]~la_lab/laboutb[8]
|
|
Info (332115): 9.598 0.522 RR IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[5].ct0|t5|dout|datae
|
|
Info (332115): 9.734 0.136 RF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[5].ct0|t5|dout|combout
|
|
Info (332115): 9.734 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[5].ct0|dout_r[5]|d
|
|
Info (332115): 9.734 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[5].ct0|dout_r[5]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 6.399 6.399 latch edge time
|
|
Info (332115): 13.174 6.775 R clock network delay
|
|
Info (332115): 15.100 1.926 clock pessimism removed
|
|
Info (332115): 15.080 -0.020 clock uncertainty
|
|
Info (332115): 15.281 0.201 uTsu fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[5].ct0|dout_r[5]
|
|
Info (332115): Data Arrival Time : 9.734
|
|
Info (332115): Data Required Time : 15.281
|
|
Info (332115): Slack : 5.547
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 5.666
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_div_clk}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 5.666
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[4].ct0|dout_r[5]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[4].sn0|ff_launch[0]
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_div_clk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_div_clk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 10.266 10.266 R clock network delay
|
|
Info (332115): 10.266 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[4].ct0|dout_r[5]
|
|
Info (332115): 10.486 0.220 RR uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[4].ct0|dout_r[5]|q
|
|
Info (332115): 10.645 0.159 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[4].ct0|dout_r[5]~la_lab/laboutt[16]
|
|
Info (332115): 10.939 0.294 RR IC High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[4].sn0|ff_launch[0]|d
|
|
Info (332115): 10.939 0.000 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[4].sn0|ff_launch[0]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 6.399 6.399 latch edge time
|
|
Info (332115): 14.142 7.743 R clock network delay
|
|
Info (332115): 16.610 2.468 clock pessimism removed
|
|
Info (332115): 16.580 -0.030 clock uncertainty
|
|
Info (332115): 16.605 0.025 uTsu fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[4].sn0|ff_launch[0]
|
|
Info (332115): Data Arrival Time : 10.939
|
|
Info (332115): Data Required Time : 16.605
|
|
Info (332115): Slack : 5.666
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 5.834
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|avmmclk}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 5.834
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|channel_count[2]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Launch Clock : PCIE_REFCLK
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|avmmclk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 5.631 5.631 R clock network delay
|
|
Info (332115): 5.631 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|channel_count[2]
|
|
Info (332115): 5.851 0.220 RR uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|channel_count[2]|q
|
|
Info (332115): 5.988 0.137 RR CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|channel_count[2]~la_mlab/laboutb[17]
|
|
Info (332115): 7.434 1.446 RR IC Mixed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i723~1|datac
|
|
Info (332115): 7.609 0.175 RF CELL Low Power fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i723~1|combout
|
|
Info (332115): 7.613 0.004 FF CELL Low Power fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i723~1~la_lab/laboutt[8]
|
|
Info (332115): 10.127 2.514 FF IC Mixed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst|avmmread
|
|
Info (332115): 10.127 0.000 FF CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 10.000 10.000 latch edge time
|
|
Info (332115): 15.307 5.307 R clock network delay
|
|
Info (332115): 15.791 0.484 clock pessimism removed
|
|
Info (332115): 15.751 -0.040 clock uncertainty
|
|
Info (332115): 15.961 0.210 uTsu fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Arrival Time : 10.127
|
|
Info (332115): Data Required Time : 15.961
|
|
Info (332115): Slack : 5.834
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 6.158
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|avmmclk}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 6.158
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|channel_count[2]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Launch Clock : PCIE_REFCLK
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|avmmclk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 5.631 5.631 R clock network delay
|
|
Info (332115): 5.631 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|channel_count[2]
|
|
Info (332115): 5.851 0.220 RR uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|channel_count[2]|q
|
|
Info (332115): 5.988 0.137 RR CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|channel_count[2]~la_mlab/laboutb[17]
|
|
Info (332115): 7.472 1.484 RR IC Mixed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i487~0|datab
|
|
Info (332115): 7.740 0.268 RF CELL Low Power fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i487~0|combout
|
|
Info (332115): 7.746 0.006 FF CELL Low Power fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i487~0~la_mlab/laboutb[3]
|
|
Info (332115): 9.771 2.025 FF IC Mixed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst|avmmread
|
|
Info (332115): 9.771 0.000 FF CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 10.000 10.000 latch edge time
|
|
Info (332115): 15.275 5.275 R clock network delay
|
|
Info (332115): 15.759 0.484 clock pessimism removed
|
|
Info (332115): 15.719 -0.040 clock uncertainty
|
|
Info (332115): 15.929 0.210 uTsu fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Arrival Time : 9.771
|
|
Info (332115): Data Required Time : 15.929
|
|
Info (332115): Slack : 6.158
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 6.426
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|avmmclk}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 6.426
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|g_arb[1].arbiter_inst|grant[0]~DUPLICATE
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Launch Clock : PCIE_REFCLK
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|avmmclk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 5.621 5.621 R clock network delay
|
|
Info (332115): 5.621 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|g_arb[1].arbiter_inst|grant[0]~DUPLICATE
|
|
Info (332115): 5.852 0.231 FF uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|g_arb[1].arbiter_inst|grant[0]~DUPLICATE|q
|
|
Info (332115): 5.973 0.121 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|g_arb[1].arbiter_inst|grant[0]~DUPLICATE~la_mlab/laboutb[16]
|
|
Info (332115): 6.592 0.619 FF IC Mixed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i276|dataa
|
|
Info (332115): 6.815 0.223 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i276|combout
|
|
Info (332115): 6.821 0.006 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i276~la_mlab/laboutb[9]
|
|
Info (332115): 9.478 2.657 FF IC Mixed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst|avmmaddress[2]
|
|
Info (332115): 9.478 0.000 FF CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 10.000 10.000 latch edge time
|
|
Info (332115): 15.376 5.376 R clock network delay
|
|
Info (332115): 15.880 0.504 clock pessimism removed
|
|
Info (332115): 15.840 -0.040 clock uncertainty
|
|
Info (332115): 15.904 0.064 uTsu fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Arrival Time : 9.478
|
|
Info (332115): Data Required Time : 15.904
|
|
Info (332115): Slack : 6.426
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 7.436
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|avmmclk}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 7.436
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_writedata[3]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Launch Clock : PCIE_REFCLK
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|avmmclk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 5.630 5.630 R clock network delay
|
|
Info (332115): 5.630 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_writedata[3]
|
|
Info (332115): 5.919 0.289 RR uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_writedata[3]|q
|
|
Info (332115): 6.035 0.116 RR CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_writedata[3]~la_lab/laboutt[17]
|
|
Info (332115): 7.019 0.984 RR IC Mixed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i80~3|datae
|
|
Info (332115): 7.159 0.140 RR CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i80~3|combout
|
|
Info (332115): 7.164 0.005 RR CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i80~3~la_mlab/laboutb[8]
|
|
Info (332115): 8.516 1.352 RR IC High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst|avmmwritedata[3]
|
|
Info (332115): 8.516 0.000 RR CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 10.000 10.000 latch edge time
|
|
Info (332115): 15.360 5.360 R clock network delay
|
|
Info (332115): 15.864 0.504 clock pessimism removed
|
|
Info (332115): 15.824 -0.040 clock uncertainty
|
|
Info (332115): 15.952 0.128 uTsu fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Arrival Time : 8.516
|
|
Info (332115): Data Required Time : 15.952
|
|
Info (332115): Slack : 7.436
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 7.755
|
|
Info (20696): -to_clock [get_clocks {vl_qph_user_clk_clkpsc_clk0}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 7.755
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[0]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[1]
|
|
Info (332115): Launch Clock : vl_qph_user_clk_clkpsc_clk0
|
|
Info (332115): Latch Clock : vl_qph_user_clk_clkpsc_clk0
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 6.786 6.786 R clock network delay
|
|
Info (332115): 6.786 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[0]
|
|
Info (332115): 7.018 0.232 RR uTco fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[0]|q
|
|
Info (332115): 7.133 0.115 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[0]~la_mlab/laboutb[9]
|
|
Info (332115): 8.081 0.948 RR IC Mixed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[1]~2|dataa
|
|
Info (332115): 8.338 0.257 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[1]~2|combout
|
|
Info (332115): 8.338 0.000 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[1]|d
|
|
Info (332115): 8.338 0.000 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[1]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 9.090 9.090 latch edge time
|
|
Info (332115): 14.715 5.625 R clock network delay
|
|
Info (332115): 15.870 1.155 clock pessimism removed
|
|
Info (332115): 15.840 -0.030 clock uncertainty
|
|
Info (332115): 16.093 0.253 uTsu fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[1]
|
|
Info (332115): Data Arrival Time : 8.338
|
|
Info (332115): Data Required Time : 16.093
|
|
Info (332115): Slack : 7.755
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 8.557
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk0}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 8.557
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_green_bs|uClk_usrDiv2_q1
|
|
Info (332115): To Node : fpga_top|inst_green_bs|uClk_usrDiv2_q2
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk0
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk0
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 6.382 6.382 R clock network delay
|
|
Info (332115): 6.382 0.000 fpga_top|inst_green_bs|uClk_usrDiv2_q1
|
|
Info (332115): 6.646 0.264 RR uTco fpga_top|inst_green_bs|uClk_usrDiv2_q1|q
|
|
Info (332115): 6.646 0.000 RR CELL High Speed fpga_top|inst_green_bs|uClk_usrDiv2_q2~0|datae
|
|
Info (332115): 7.087 0.441 RF CELL High Speed fpga_top|inst_green_bs|uClk_usrDiv2_q2~0|combout
|
|
Info (332115): 7.087 0.000 FF CELL High Speed fpga_top|inst_green_bs|uClk_usrDiv2_q2|d
|
|
Info (332115): 7.087 0.000 FF CELL High Speed fpga_top|inst_green_bs|uClk_usrDiv2_q2
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 9.090 9.090 latch edge time
|
|
Info (332115): 14.364 5.274 R clock network delay
|
|
Info (332115): 15.472 1.108 clock pessimism removed
|
|
Info (332115): 15.442 -0.030 clock uncertainty
|
|
Info (332115): 15.644 0.202 uTsu fpga_top|inst_green_bs|uClk_usrDiv2_q2
|
|
Info (332115): Data Arrival Time : 7.087
|
|
Info (332115): Data Required Time : 15.644
|
|
Info (332115): Slack : 8.557
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 10.498
|
|
Info (20696): -to_clock [get_clocks {pr_clk_enable_dclk_reg2_user_clk}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 10.498
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_cb_host|alt_pr_cb_controller_v2|pr_request_reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_cb_host|alt_pr_cb_controller_v2|alt_pr_cb_interface|m_prblock~cs_css/pr_clk_core.reg
|
|
Info (332115): Launch Clock : u0|dcp_iopll|dcp_iopll|clk100
|
|
Info (332115): Latch Clock : pr_clk_enable_dclk_reg2_user_clk
|
|
Info (332115): Exception : dcp_bbs.sdc:3118: set_multicycle_path -setup -from [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_cb_host|alt_pr_cb_controller_v2|pr_request_reg}] -to [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_cb_host|alt_pr_cb_controller_v2|alt_pr_cb_interface|m_prblock~cs_css/pr_clk_core.reg}] 2
|
|
Info (332115): Multicycle - Setup Start : 2
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 9.509 9.509 R clock network delay
|
|
Info (332115): 9.509 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_cb_host|alt_pr_cb_controller_v2|pr_request_reg
|
|
Info (332115): 9.798 0.289 FF uTco fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_cb_host|alt_pr_cb_controller_v2|pr_request_reg|q
|
|
Info (332115): 9.919 0.121 FF CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_cb_host|alt_pr_cb_controller_v2|pr_request_reg~la_lab/laboutt[0]
|
|
Info (332115): 15.412 5.493 FF IC High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_cb_host|alt_pr_cb_controller_v2|alt_pr_cb_interface|m_prblock|prrequest
|
|
Info (332115): 15.412 0.000 FF CELL fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_cb_host|alt_pr_cb_controller_v2|alt_pr_cb_interface|m_prblock~cs_css/pr_clk_core.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 15.000 15.000 latch edge time
|
|
Info (332115): 24.367 9.367 R clock network delay
|
|
Info (332115): 25.538 1.171 clock pessimism removed
|
|
Info (332115): 25.368 -0.170 clock uncertainty
|
|
Info (332115): 25.910 0.542 uTsu fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_cb_host|alt_pr_cb_controller_v2|alt_pr_cb_interface|m_prblock~cs_css/pr_clk_core.reg
|
|
Info (332115): Data Arrival Time : 15.412
|
|
Info (332115): Data Required Time : 25.910
|
|
Info (332115): Slack : 10.498
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 18.260
|
|
Info (20696): -to_clock [get_clocks {u0|dcp_iopll|dcp_iopll|clk25}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 18.260
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|generic_quad_spi_controller2_0|generic_quad_spi_controller2_0|asmi2_inst_qspi_ctrl|asmi2_cmd_generator_0|state.ST_SEND_ADDR
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|generic_quad_spi_controller2_0|generic_quad_spi_controller2_0|asmi2_inst_qspi_ctrl|asmi2_qspi_interface_0|dataout_reg[0]~RTM_7
|
|
Info (332115): Launch Clock : u0|dcp_iopll|dcp_iopll|clk25
|
|
Info (332115): Latch Clock : u0|dcp_iopll|dcp_iopll|clk25 (INVERTED)
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 9.733 9.733 R clock network delay
|
|
Info (332115): 9.733 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|generic_quad_spi_controller2_0|generic_quad_spi_controller2_0|asmi2_inst_qspi_ctrl|asmi2_cmd_generator_0|state.ST_SEND_ADDR
|
|
Info (332115): 9.959 0.226 RR uTco fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|generic_quad_spi_controller2_0|generic_quad_spi_controller2_0|asmi2_inst_qspi_ctrl|asmi2_cmd_generator_0|state.ST_SEND_ADDR|q
|
|
Info (332115): 10.075 0.116 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|generic_quad_spi_controller2_0|generic_quad_spi_controller2_0|asmi2_inst_qspi_ctrl|asmi2_cmd_generator_0|state.ST_SEND_ADDR~la_lab/laboutb[13]
|
|
Info (332115): 10.650 0.575 RR IC High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|generic_quad_spi_controller2_0|generic_quad_spi_controller2_0|asmi2_inst_qspi_ctrl|asmi2_cmd_generator_0|Select_8~0|datac
|
|
Info (332115): 10.811 0.161 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|generic_quad_spi_controller2_0|generic_quad_spi_controller2_0|asmi2_inst_qspi_ctrl|asmi2_cmd_generator_0|Select_8~0|combout
|
|
Info (332115): 10.815 0.004 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|generic_quad_spi_controller2_0|generic_quad_spi_controller2_0|asmi2_inst_qspi_ctrl|asmi2_cmd_generator_0|Select_8~0~la_lab/laboutt[4]
|
|
Info (332115): 11.033 0.218 RR IC High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|generic_quad_spi_controller2_0|generic_quad_spi_controller2_0|asmi2_inst_qspi_ctrl|asmi2_qspi_interface_0|dataout_reg[1]~0|dataf
|
|
Info (332115): 11.079 0.046 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|generic_quad_spi_controller2_0|generic_quad_spi_controller2_0|asmi2_inst_qspi_ctrl|asmi2_qspi_interface_0|dataout_reg[1]~0|combout
|
|
Info (332115): 11.083 0.004 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|generic_quad_spi_controller2_0|generic_quad_spi_controller2_0|asmi2_inst_qspi_ctrl|asmi2_qspi_interface_0|dataout_reg[1]~0~la_lab/laboutb[18]
|
|
Info (332115): 11.418 0.335 RR IC High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|generic_quad_spi_controller2_0|generic_quad_spi_controller2_0|asmi2_inst_qspi_ctrl|asmi2_qspi_interface_0|dataout_reg[0]~RTM_7|d
|
|
Info (332115): 11.418 0.000 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|generic_quad_spi_controller2_0|generic_quad_spi_controller2_0|asmi2_inst_qspi_ctrl|asmi2_qspi_interface_0|dataout_reg[0]~RTM_7
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 20.000 20.000 latch edge time
|
|
Info (332115): 28.336 8.336 F clock network delay
|
|
Info (332115): 29.651 1.315 clock pessimism removed
|
|
Info (332115): 29.431 -0.220 clock uncertainty
|
|
Info (332115): 29.678 0.247 uTsu fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|generic_quad_spi_controller2_0|generic_quad_spi_controller2_0|asmi2_inst_qspi_ctrl|asmi2_qspi_interface_0|dataout_reg[0]~RTM_7
|
|
Info (332115): Data Arrival Time : 11.418
|
|
Info (332115): Data Required Time : 29.678
|
|
Info (332115): Slack : 18.260
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 19.306
|
|
Info (20696): -to_clock [get_clocks {u0|dcp_iopll|dcp_iopll|clk50}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 19.306
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_green_bs|pClkDiv4_q2
|
|
Info (332115): To Node : fpga_top|inst_green_bs|pClkDiv4_q1
|
|
Info (332115): Launch Clock : u0|dcp_iopll|dcp_iopll|clk50
|
|
Info (332115): Latch Clock : u0|dcp_iopll|dcp_iopll|clk50
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 9.694 9.694 R clock network delay
|
|
Info (332115): 9.694 0.000 fpga_top|inst_green_bs|pClkDiv4_q2
|
|
Info (332115): 9.912 0.218 RR uTco fpga_top|inst_green_bs|pClkDiv4_q2|q
|
|
Info (332115): 10.027 0.115 RR CELL High Speed fpga_top|inst_green_bs|pClkDiv4_q2~la_mlab/laboutb[17]
|
|
Info (332115): 10.321 0.294 RR IC High Speed fpga_top|inst_green_bs|pClkDiv4_q1|asdata
|
|
Info (332115): 10.321 0.000 RR CELL High Speed fpga_top|inst_green_bs|pClkDiv4_q1
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 20.000 20.000 latch edge time
|
|
Info (332115): 28.340 8.340 R clock network delay
|
|
Info (332115): 29.694 1.354 clock pessimism removed
|
|
Info (332115): 29.504 -0.190 clock uncertainty
|
|
Info (332115): 29.627 0.123 uTsu fpga_top|inst_green_bs|pClkDiv4_q1
|
|
Info (332115): Data Arrival Time : 10.321
|
|
Info (332115): Data Required Time : 29.627
|
|
Info (332115): Slack : 19.306
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 19.717
|
|
Info (20696): -to_clock [get_clocks {filtered_sclk_negedge}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 19.717
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MOSIctl|filtered_mosi_out
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MOSIctl|wrshiftreg[0]
|
|
Info (332115): Launch Clock : u0|dcp_iopll|dcp_iopll|clk1x
|
|
Info (332115): Latch Clock : filtered_sclk_negedge
|
|
Info (332115): Exception : dcp_bbs.sdc:3138: set_max_delay -from [get_keepers {*filtered_mosi*}] 30.000
|
|
Info (332115): Max Delay Exception : 30.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 9.531 9.531 R clock network delay
|
|
Info (332115): 9.531 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MOSIctl|filtered_mosi_out
|
|
Info (332115): 9.814 0.283 RR uTco fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MOSIctl|filtered_mosi_out|q
|
|
Info (332115): 9.929 0.115 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MOSIctl|filtered_mosi_out~la_lab/laboutb[5]
|
|
Info (332115): 10.374 0.445 RR IC High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MOSIctl|wrshiftreg[0]|asdata
|
|
Info (332115): 10.374 0.000 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MOSIctl|wrshiftreg[0]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 30.000 30.000 latch edge time
|
|
Info (332115): 30.236 0.236 R clock network delay
|
|
Info (332115): 29.936 -0.300 clock uncertainty
|
|
Info (332115): 30.091 0.155 uTsu fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MOSIctl|wrshiftreg[0]
|
|
Info (332115): Data Arrival Time : 10.374
|
|
Info (332115): Data Required Time : 30.091
|
|
Info (332115): Slack : 19.717
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 40.325
|
|
Info (20696): -to_clock [get_clocks {altera_reserved_tck}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 40.325
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|nios2_gen2_0|nios2_gen2_0|cpu|the_tcm_nios2_gen2_0_altera_nios2_gen2_unit_191_dbuc52a_nios2_oci|the_tcm_nios2_gen2_0_altera_nios2_gen2_unit_191_dbuc52a_debug_slave_wrapper|the_tcm_nios2_gen2_0_altera_nios2_gen2_unit_191_dbuc52a_debug_slave_tck|sr[0]
|
|
Info (332115): To Node : auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|jtagpins|int_tdo_reg~LRTM_5
|
|
Info (332115): Launch Clock : altera_reserved_tck
|
|
Info (332115): Latch Clock : altera_reserved_tck (INVERTED)
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 5.928 5.928 R clock network delay
|
|
Info (332115): 5.928 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|nios2_gen2_0|nios2_gen2_0|cpu|the_tcm_nios2_gen2_0_altera_nios2_gen2_unit_191_dbuc52a_nios2_oci|the_tcm_nios2_gen2_0_altera_nios2_gen2_unit_191_dbuc52a_debug_slave_wrapper|the_tcm_nios2_gen2_0_altera_nios2_gen2_unit_191_dbuc52a_debug_slave_tck|sr[0]
|
|
Info (332115): 6.161 0.233 FF uTco fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|nios2_gen2_0|nios2_gen2_0|cpu|the_tcm_nios2_gen2_0_altera_nios2_gen2_unit_191_dbuc52a_nios2_oci|the_tcm_nios2_gen2_0_altera_nios2_gen2_unit_191_dbuc52a_debug_slave_wrapper|the_tcm_nios2_gen2_0_altera_nios2_gen2_unit_191_dbuc52a_debug_slave_tck|sr[0]|q
|
|
Info (332115): 6.236 0.075 FF CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|nios2_gen2_0|nios2_gen2_0|cpu|the_tcm_nios2_gen2_0_altera_nios2_gen2_unit_191_dbuc52a_nios2_oci|the_tcm_nios2_gen2_0_altera_nios2_gen2_unit_191_dbuc52a_debug_slave_wrapper|the_tcm_nios2_gen2_0_altera_nios2_gen2_unit_191_dbuc52a_debug_slave_tck|sr[0]~la_lab/laboutb[9]
|
|
Info (332115): 6.236 0.000 FF IC auto_fab_0|auto_export_alt_sld_fab_0_alt_sld_fab_0_splitter_send_2[0]|input
|
|
Info (332115): 6.236 0.000 FF CELL auto_fab_0|auto_export_alt_sld_fab_0_alt_sld_fab_0_splitter_send_2[0]
|
|
Info (332115): 13.508 7.272 FF IC High Speed auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|sldfabric|\jtag_hub_gen:real_sld_jtag_hub|i705~4|datab
|
|
Info (332115): 13.726 0.218 FF CELL High Speed auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|sldfabric|\jtag_hub_gen:real_sld_jtag_hub|i705~4|combout
|
|
Info (332115): 13.726 0.000 FF CELL High Speed auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|jtagpins|int_tdo_reg~LRTM_5|d
|
|
Info (332115): 13.726 0.000 FF CELL High Speed auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|jtagpins|int_tdo_reg~LRTM_5
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 50.000 50.000 latch edge time
|
|
Info (332115): 53.272 3.272 F clock network delay
|
|
Info (332115): 53.772 0.500 clock pessimism removed
|
|
Info (332115): 53.742 -0.030 clock uncertainty
|
|
Info (332115): 54.051 0.309 uTsu auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|jtagpins|int_tdo_reg~LRTM_5
|
|
Info (332115): Data Arrival Time : 13.726
|
|
Info (332115): Data Required Time : 54.051
|
|
Info (332115): Slack : 40.325
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.033
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk1}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.033
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[3].core|pipeline|issue|instr_demux|gpu_buffer|shift_reg[1][170]
|
|
Info (332115): To Node : fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[3].core|pipeline|execute|gpu_unit|pipe_reg|value_d[5]
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk1
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk1
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 5.337 5.337 R clock network delay
|
|
Info (332115): 5.337 0.000 fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[3].core|pipeline|issue|instr_demux|gpu_buffer|shift_reg[1][170]
|
|
Info (332115): 5.523 0.186 FF uTco fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[3].core|pipeline|issue|instr_demux|gpu_buffer|shift_reg[1][170]|q
|
|
Info (332115): 5.836 0.313 FF CELL High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[3].core|pipeline|execute|gpu_unit|pipe_reg|value_d[5]|d
|
|
Info (332115): 5.836 0.000 FF CELL High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[3].core|pipeline|execute|gpu_unit|pipe_reg|value_d[5]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 6.455 6.455 R clock network delay
|
|
Info (332115): 5.337 -1.118 clock pessimism removed
|
|
Info (332115): 5.337 0.000 clock uncertainty
|
|
Info (332115): 5.803 0.466 uTh fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[3].core|pipeline|execute|gpu_unit|pipe_reg|value_d[5]
|
|
Info (332115): Data Arrival Time : 5.836
|
|
Info (332115): Data Required Time : 5.803
|
|
Info (332115): Slack : 0.033
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.044
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|wys~CORE_CLK_OUT}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.044
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_sriov_2.sriov2.sriov_bridge|altpcie_pcie_sriov2_top_inst|altpcie_sriov2_cfg_dataflow_inst|gen_vf_regset_pf0.altpcie_sriov2_cfg_vf_regset_pf0_inst|vf_pci_status_reg_mod|altpcie_sriov2_cfg_vf_bar_check_error_status_fifo|read_ptr[0]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_sriov_2.sriov2.sriov_bridge|altpcie_pcie_sriov2_top_inst|altpcie_sriov2_cfg_dataflow_inst|gen_vf_regset_pf0.altpcie_sriov2_cfg_vf_regset_pf0_inst|vf_pci_status_reg_mod|altpcie_sriov2_cfg_vf_bar_check_error_status_fifo|reg_array_rtl_0|auto_generated|rdaddr_reg[0]
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|wys~CORE_CLK_OUT
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|wys~CORE_CLK_OUT
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 7.855 7.855 R clock network delay
|
|
Info (332115): 7.855 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_sriov_2.sriov2.sriov_bridge|altpcie_pcie_sriov2_top_inst|altpcie_sriov2_cfg_dataflow_inst|gen_vf_regset_pf0.altpcie_sriov2_cfg_vf_regset_pf0_inst|vf_pci_status_reg_mod|altpcie_sriov2_cfg_vf_bar_check_error_status_fifo|read_ptr[0]
|
|
Info (332115): 8.054 0.199 FF uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_sriov_2.sriov2.sriov_bridge|altpcie_pcie_sriov2_top_inst|altpcie_sriov2_cfg_dataflow_inst|gen_vf_regset_pf0.altpcie_sriov2_cfg_vf_regset_pf0_inst|vf_pci_status_reg_mod|altpcie_sriov2_cfg_vf_bar_check_error_status_fifo|read_ptr[0]|q
|
|
Info (332115): 8.054 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_sriov_2.sriov2.sriov_bridge|altpcie_pcie_sriov2_top_inst|altpcie_sriov2_cfg_dataflow_inst|gen_vf_regset_pf0.altpcie_sriov2_cfg_vf_regset_pf0_inst|vf_pci_status_reg_mod|altpcie_sriov2_cfg_vf_bar_check_error_status_fifo|i26~0|datad
|
|
Info (332115): 8.363 0.309 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_sriov_2.sriov2.sriov_bridge|altpcie_pcie_sriov2_top_inst|altpcie_sriov2_cfg_dataflow_inst|gen_vf_regset_pf0.altpcie_sriov2_cfg_vf_regset_pf0_inst|vf_pci_status_reg_mod|altpcie_sriov2_cfg_vf_bar_check_error_status_fifo|i26~0|combout
|
|
Info (332115): 8.363 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_sriov_2.sriov2.sriov_bridge|altpcie_pcie_sriov2_top_inst|altpcie_sriov2_cfg_dataflow_inst|gen_vf_regset_pf0.altpcie_sriov2_cfg_vf_regset_pf0_inst|vf_pci_status_reg_mod|altpcie_sriov2_cfg_vf_bar_check_error_status_fifo|reg_array_rtl_0|auto_generated|rdaddr_reg[0]|d
|
|
Info (332115): 8.363 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_sriov_2.sriov2.sriov_bridge|altpcie_pcie_sriov2_top_inst|altpcie_sriov2_cfg_dataflow_inst|gen_vf_regset_pf0.altpcie_sriov2_cfg_vf_regset_pf0_inst|vf_pci_status_reg_mod|altpcie_sriov2_cfg_vf_bar_check_error_status_fifo|reg_array_rtl_0|auto_generated|rdaddr_reg[0]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 9.269 9.269 R clock network delay
|
|
Info (332115): 7.855 -1.414 clock pessimism removed
|
|
Info (332115): 8.319 0.464 uTh fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_sriov_2.sriov2.sriov_bridge|altpcie_pcie_sriov2_top_inst|altpcie_sriov2_cfg_dataflow_inst|gen_vf_regset_pf0.altpcie_sriov2_cfg_vf_regset_pf0_inst|vf_pci_status_reg_mod|altpcie_sriov2_cfg_vf_bar_check_error_status_fifo|reg_array_rtl_0|auto_generated|rdaddr_reg[0]
|
|
Info (332115): Data Arrival Time : 8.363
|
|
Info (332115): Data Required Time : 8.319
|
|
Info (332115): Slack : 0.044
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.047
|
|
Info (20696): -to_clock [get_clocks {u0|dcp_iopll|dcp_iopll|clk1x}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.047
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_perf_mon_fab|inst_ss_fab_ctr|preamble_sent
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_perf_mon_fab|inst_ss_fab_ctr|preamble_sent
|
|
Info (332115): Launch Clock : u0|dcp_iopll|dcp_iopll|clk1x
|
|
Info (332115): Latch Clock : u0|dcp_iopll|dcp_iopll|clk1x
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 8.212 8.212 R clock network delay
|
|
Info (332115): 8.212 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_perf_mon_fab|inst_ss_fab_ctr|preamble_sent
|
|
Info (332115): 8.412 0.200 FF uTco fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_perf_mon_fab|inst_ss_fab_ctr|preamble_sent|q
|
|
Info (332115): 8.412 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_perf_mon_fab|inst_ss_fab_ctr|i13~0|datad
|
|
Info (332115): 8.719 0.307 FF CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_perf_mon_fab|inst_ss_fab_ctr|i13~0|combout
|
|
Info (332115): 8.719 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_perf_mon_fab|inst_ss_fab_ctr|preamble_sent|d
|
|
Info (332115): 8.719 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_perf_mon_fab|inst_ss_fab_ctr|preamble_sent
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 9.522 9.522 R clock network delay
|
|
Info (332115): 8.212 -1.310 clock pessimism removed
|
|
Info (332115): 8.212 0.000 clock uncertainty
|
|
Info (332115): 8.672 0.460 uTh fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_perf_mon_fab|inst_ss_fab_ctr|preamble_sent
|
|
Info (332115): Data Arrival Time : 8.719
|
|
Info (332115): Data Required Time : 8.672
|
|
Info (332115): Slack : 0.047
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.048
|
|
Info (20696): -to_clock [get_clocks {SYS_RefClk}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.048
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|memfabric|transacto|p2m|state.GET_ADDR1
|
|
Info (332115): To Node : auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|memfabric|transacto|p2m|state.GET_ADDR1
|
|
Info (332115): Launch Clock : SYS_RefClk
|
|
Info (332115): Latch Clock : SYS_RefClk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 4.267 4.267 R clock network delay
|
|
Info (332115): 4.267 0.000 auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|memfabric|transacto|p2m|state.GET_ADDR1
|
|
Info (332115): 4.465 0.198 FF uTco auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|memfabric|transacto|p2m|state.GET_ADDR1|q
|
|
Info (332115): 4.465 0.000 FF CELL High Speed auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|memfabric|transacto|p2m|i774~1|datad
|
|
Info (332115): 4.774 0.309 FF CELL High Speed auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|memfabric|transacto|p2m|i774~1|combout
|
|
Info (332115): 4.774 0.000 FF CELL High Speed auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|memfabric|transacto|p2m|state.GET_ADDR1|d
|
|
Info (332115): 4.774 0.000 FF CELL High Speed auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|memfabric|transacto|p2m|state.GET_ADDR1
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 4.648 4.648 R clock network delay
|
|
Info (332115): 4.267 -0.381 clock pessimism removed
|
|
Info (332115): 4.267 0.000 clock uncertainty
|
|
Info (332115): 4.726 0.459 uTh auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|memfabric|transacto|p2m|state.GET_ADDR1
|
|
Info (332115): Data Arrival Time : 4.774
|
|
Info (332115): Data Required Time : 4.726
|
|
Info (332115): Slack : 0.048
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.051
|
|
Info (20696): -to_clock [get_clocks {u0|dcp_iopll|dcp_iopll|clk25}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.051
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|generic_quad_spi_controller2_0_avl_mem_agent_rdata_fifo|mem[1][15]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|generic_quad_spi_controller2_0_avl_mem_agent_rdata_fifo|mem[1][15]
|
|
Info (332115): Launch Clock : u0|dcp_iopll|dcp_iopll|clk25
|
|
Info (332115): Latch Clock : u0|dcp_iopll|dcp_iopll|clk25
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 8.356 8.356 R clock network delay
|
|
Info (332115): 8.356 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|generic_quad_spi_controller2_0_avl_mem_agent_rdata_fifo|mem[1][15]
|
|
Info (332115): 8.556 0.200 FF uTco fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|generic_quad_spi_controller2_0_avl_mem_agent_rdata_fifo|mem[1][15]|q
|
|
Info (332115): 8.556 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|generic_quad_spi_controller2_0_avl_mem_agent_rdata_fifo|i122~15|datad
|
|
Info (332115): 8.870 0.314 FF CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|generic_quad_spi_controller2_0_avl_mem_agent_rdata_fifo|i122~15|combout
|
|
Info (332115): 8.870 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|generic_quad_spi_controller2_0_avl_mem_agent_rdata_fifo|mem[1][15]|d
|
|
Info (332115): 8.870 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|generic_quad_spi_controller2_0_avl_mem_agent_rdata_fifo|mem[1][15]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 9.726 9.726 R clock network delay
|
|
Info (332115): 8.356 -1.370 clock pessimism removed
|
|
Info (332115): 8.356 0.000 clock uncertainty
|
|
Info (332115): 8.819 0.463 uTh fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|generic_quad_spi_controller2_0_avl_mem_agent_rdata_fifo|mem[1][15]
|
|
Info (332115): Data Arrival Time : 8.870
|
|
Info (332115): Data Required Time : 8.819
|
|
Info (332115): Slack : 0.051
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.052
|
|
Info (20696): -to_clock [get_clocks {altera_reserved_tck}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.052
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|jtag_uart_0|jtag_uart_0|tcm_jtag_uart_0_altera_avalon_jtag_uart_191_vk7uuay_alt_jtag_atlantic|count[4]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|jtag_uart_0|jtag_uart_0|tcm_jtag_uart_0_altera_avalon_jtag_uart_191_vk7uuay_alt_jtag_atlantic|count[5]
|
|
Info (332115): Launch Clock : altera_reserved_tck
|
|
Info (332115): Latch Clock : altera_reserved_tck
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 3.014 3.014 R clock network delay
|
|
Info (332115): 3.014 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|jtag_uart_0|jtag_uart_0|tcm_jtag_uart_0_altera_avalon_jtag_uart_191_vk7uuay_alt_jtag_atlantic|count[4]
|
|
Info (332115): 3.214 0.200 FF uTco fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|jtag_uart_0|jtag_uart_0|tcm_jtag_uart_0_altera_avalon_jtag_uart_191_vk7uuay_alt_jtag_atlantic|count[4]|q
|
|
Info (332115): 3.532 0.318 FF CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|jtag_uart_0|jtag_uart_0|tcm_jtag_uart_0_altera_avalon_jtag_uart_191_vk7uuay_alt_jtag_atlantic|count[5]|d
|
|
Info (332115): 3.532 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|jtag_uart_0|jtag_uart_0|tcm_jtag_uart_0_altera_avalon_jtag_uart_191_vk7uuay_alt_jtag_atlantic|count[5]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 3.764 3.764 R clock network delay
|
|
Info (332115): 3.021 -0.743 clock pessimism removed
|
|
Info (332115): 3.021 0.000 clock uncertainty
|
|
Info (332115): 3.480 0.459 uTh fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|jtag_uart_0|jtag_uart_0|tcm_jtag_uart_0_altera_avalon_jtag_uart_191_vk7uuay_alt_jtag_atlantic|count[5]
|
|
Info (332115): Data Arrival Time : 3.532
|
|
Info (332115): Data Required Time : 3.480
|
|
Info (332115): Slack : 0.052
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.053
|
|
Info (20696): -to_clock [get_clocks {mem|ddr4a|ddr4a_core_usr_clk}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.053
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : mem|ddr4b_tcm_readissued
|
|
Info (332115): To Node : mem|ddr4b_tcm_readissued
|
|
Info (332115): Launch Clock : mem|ddr4a|ddr4a_core_usr_clk
|
|
Info (332115): Latch Clock : mem|ddr4a|ddr4a_core_usr_clk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.117 0.117 launch edge time
|
|
Info (332115): 2.689 2.572 R clock network delay
|
|
Info (332115): 2.689 0.000 mem|ddr4b_tcm_readissued
|
|
Info (332115): 2.870 0.181 FF uTco mem|ddr4b_tcm_readissued|q
|
|
Info (332115): 2.870 0.000 FF CELL High Speed mem|i145~0|datad
|
|
Info (332115): 3.177 0.307 FF CELL High Speed mem|i145~0|combout
|
|
Info (332115): 3.177 0.000 FF CELL High Speed mem|ddr4b_tcm_readissued|d
|
|
Info (332115): 3.177 0.000 FF CELL High Speed mem|ddr4b_tcm_readissued
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.117 0.117 latch edge time
|
|
Info (332115): 3.546 3.429 R clock network delay
|
|
Info (332115): 2.689 -0.857 clock pessimism removed
|
|
Info (332115): 2.689 0.000 clock uncertainty
|
|
Info (332115): 3.124 0.435 uTh mem|ddr4b_tcm_readissued
|
|
Info (332115): Data Arrival Time : 3.177
|
|
Info (332115): Data Required Time : 3.124
|
|
Info (332115): Slack : 0.053
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.054
|
|
Info (20696): -to_clock [get_clocks {PCIE_REFCLK}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.054
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|timer_threshold[6]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|timer_threshold[6]
|
|
Info (332115): Launch Clock : PCIE_REFCLK
|
|
Info (332115): Latch Clock : PCIE_REFCLK
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 5.069 5.069 R clock network delay
|
|
Info (332115): 5.069 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|timer_threshold[6]
|
|
Info (332115): 5.253 0.184 FF uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|timer_threshold[6]|q
|
|
Info (332115): 5.253 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|Select_41~0|datad
|
|
Info (332115): 5.562 0.309 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|Select_41~0|combout
|
|
Info (332115): 5.562 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|timer_threshold[6]|d
|
|
Info (332115): 5.562 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|timer_threshold[6]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 5.631 5.631 R clock network delay
|
|
Info (332115): 5.070 -0.561 clock pessimism removed
|
|
Info (332115): 5.070 0.000 clock uncertainty
|
|
Info (332115): 5.508 0.438 uTh fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|timer_threshold[6]
|
|
Info (332115): Data Arrival Time : 5.562
|
|
Info (332115): Data Required Time : 5.508
|
|
Info (332115): Slack : 0.054
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.055
|
|
Info (20696): -to_clock [get_clocks {u0|dcp_iopll|dcp_iopll|clk100}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.055
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|gen_ccip_ports[0].inst_remote_green_stp|inst_stp_ep|inst_SLD_HUB_cont_sys|sld_hub_controller_system_without_sldep_0|sld_hub_controller_system_without_sldep_0|hub_controller|core|resp_data[0]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|gen_ccip_ports[0].inst_remote_green_stp|inst_stp_ep|inst_SLD_HUB_cont_sys|sld_hub_controller_system_without_sldep_0|sld_hub_controller_system_without_sldep_0|hub_controller|core|resp_data[0]
|
|
Info (332115): Launch Clock : u0|dcp_iopll|dcp_iopll|clk100
|
|
Info (332115): Latch Clock : u0|dcp_iopll|dcp_iopll|clk100
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 8.256 8.256 R clock network delay
|
|
Info (332115): 8.256 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|gen_ccip_ports[0].inst_remote_green_stp|inst_stp_ep|inst_SLD_HUB_cont_sys|sld_hub_controller_system_without_sldep_0|sld_hub_controller_system_without_sldep_0|hub_controller|core|resp_data[0]
|
|
Info (332115): 8.435 0.179 FF uTco fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|gen_ccip_ports[0].inst_remote_green_stp|inst_stp_ep|inst_SLD_HUB_cont_sys|sld_hub_controller_system_without_sldep_0|sld_hub_controller_system_without_sldep_0|hub_controller|core|resp_data[0]|q
|
|
Info (332115): 8.435 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|gen_ccip_ports[0].inst_remote_green_stp|inst_stp_ep|inst_SLD_HUB_cont_sys|sld_hub_controller_system_without_sldep_0|sld_hub_controller_system_without_sldep_0|hub_controller|core|resp_data[0]~8|datad
|
|
Info (332115): 8.744 0.309 FF CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|gen_ccip_ports[0].inst_remote_green_stp|inst_stp_ep|inst_SLD_HUB_cont_sys|sld_hub_controller_system_without_sldep_0|sld_hub_controller_system_without_sldep_0|hub_controller|core|resp_data[0]~8|combout
|
|
Info (332115): 8.744 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|gen_ccip_ports[0].inst_remote_green_stp|inst_stp_ep|inst_SLD_HUB_cont_sys|sld_hub_controller_system_without_sldep_0|sld_hub_controller_system_without_sldep_0|hub_controller|core|resp_data[0]|d
|
|
Info (332115): 8.744 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|gen_ccip_ports[0].inst_remote_green_stp|inst_stp_ep|inst_SLD_HUB_cont_sys|sld_hub_controller_system_without_sldep_0|sld_hub_controller_system_without_sldep_0|hub_controller|core|resp_data[0]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 9.584 9.584 R clock network delay
|
|
Info (332115): 8.256 -1.328 clock pessimism removed
|
|
Info (332115): 8.256 0.000 clock uncertainty
|
|
Info (332115): 8.689 0.433 uTh fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|gen_ccip_ports[0].inst_remote_green_stp|inst_stp_ep|inst_SLD_HUB_cont_sys|sld_hub_controller_system_without_sldep_0|sld_hub_controller_system_without_sldep_0|hub_controller|core|resp_data[0]
|
|
Info (332115): Data Arrival Time : 8.744
|
|
Info (332115): Data Required Time : 8.689
|
|
Info (332115): Slack : 0.055
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.057
|
|
Info (20696): -to_clock [get_clocks {DDR4_RefClk}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.057
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|use_counter_lock.counter_lock_gen_master.pll_ref_clk_reset_n_sync_rr
|
|
Info (332115): To Node : mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|use_counter_lock.counter_lock_gen_master.pll_ref_clk_reset_n_sync_rrr
|
|
Info (332115): Launch Clock : DDR4_RefClk
|
|
Info (332115): Latch Clock : DDR4_RefClk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 4.025 4.025 R clock network delay
|
|
Info (332115): 4.025 0.000 mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|use_counter_lock.counter_lock_gen_master.pll_ref_clk_reset_n_sync_rr
|
|
Info (332115): 4.207 0.182 FF uTco mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|use_counter_lock.counter_lock_gen_master.pll_ref_clk_reset_n_sync_rr|q
|
|
Info (332115): 4.523 0.316 FF CELL High Speed mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|use_counter_lock.counter_lock_gen_master.pll_ref_clk_reset_n_sync_rrr|d
|
|
Info (332115): 4.523 0.000 FF CELL High Speed mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|use_counter_lock.counter_lock_gen_master.pll_ref_clk_reset_n_sync_rrr
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 4.350 4.350 R clock network delay
|
|
Info (332115): 4.026 -0.324 clock pessimism removed
|
|
Info (332115): 4.026 0.000 clock uncertainty
|
|
Info (332115): 4.466 0.440 uTh mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|use_counter_lock.counter_lock_gen_master.pll_ref_clk_reset_n_sync_rrr
|
|
Info (332115): Data Arrival Time : 4.523
|
|
Info (332115): Data Required Time : 4.466
|
|
Info (332115): Slack : 0.057
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.059
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|rx_pma_clk}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.059
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_prbs_err_sync|resync_chains[0].sync_r[0]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_prbs_err_sync|resync_chains[0].sync_r[1]
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|rx_pma_clk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|rx_pma_clk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 4.932 4.932 R clock network delay
|
|
Info (332115): 4.932 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_prbs_err_sync|resync_chains[0].sync_r[0]
|
|
Info (332115): 5.111 0.179 FF uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_prbs_err_sync|resync_chains[0].sync_r[0]|q
|
|
Info (332115): 5.427 0.316 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_prbs_err_sync|resync_chains[0].sync_r[1]|d
|
|
Info (332115): 5.427 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_prbs_err_sync|resync_chains[0].sync_r[1]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 6.926 6.926 R clock network delay
|
|
Info (332115): 4.932 -1.994 clock pessimism removed
|
|
Info (332115): 4.932 0.000 clock uncertainty
|
|
Info (332115): 5.368 0.436 uTh fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_prbs_err_sync|resync_chains[0].sync_r[1]
|
|
Info (332115): Data Arrival Time : 5.427
|
|
Info (332115): Data Required Time : 5.368
|
|
Info (332115): Slack : 0.059
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.059
|
|
Info (20696): -to_clock [get_clocks {mem|ddr4a|ddr4a_core_cal_slave_clk}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.059
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : mem|ddr4b|ddr4b|arch|arch_inst|non_hps.core_clks_rsts_inst|per_if_cal_slave_reset_sync[8]
|
|
Info (332115): To Node : mem|ddr4b|ddr4b|arch|arch_inst|non_hps.core_clks_rsts_inst|per_if_cal_slave_reset_sync[9]
|
|
Info (332115): Launch Clock : mem|ddr4a|ddr4a_core_cal_slave_clk
|
|
Info (332115): Latch Clock : mem|ddr4a|ddr4a_core_cal_slave_clk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 5.951 5.951 R clock network delay
|
|
Info (332115): 5.951 0.000 mem|ddr4b|ddr4b|arch|arch_inst|non_hps.core_clks_rsts_inst|per_if_cal_slave_reset_sync[8]
|
|
Info (332115): 6.131 0.180 FF uTco mem|ddr4b|ddr4b|arch|arch_inst|non_hps.core_clks_rsts_inst|per_if_cal_slave_reset_sync[8]|q
|
|
Info (332115): 6.448 0.317 FF CELL High Speed mem|ddr4b|ddr4b|arch|arch_inst|non_hps.core_clks_rsts_inst|per_if_cal_slave_reset_sync[9]|d
|
|
Info (332115): 6.448 0.000 FF CELL High Speed mem|ddr4b|ddr4b|arch|arch_inst|non_hps.core_clks_rsts_inst|per_if_cal_slave_reset_sync[9]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 6.972 6.972 R clock network delay
|
|
Info (332115): 5.951 -1.021 clock pessimism removed
|
|
Info (332115): 5.951 0.000 clock uncertainty
|
|
Info (332115): 6.389 0.438 uTh mem|ddr4b|ddr4b|arch|arch_inst|non_hps.core_clks_rsts_inst|per_if_cal_slave_reset_sync[9]
|
|
Info (332115): Data Arrival Time : 6.448
|
|
Info (332115): Data Required Time : 6.389
|
|
Info (332115): Slack : 0.059
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.060
|
|
Info (20696): -to_clock [get_clocks {filtered_sclk_negedge}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.060
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MOSIctl|wrshiftreg[5]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MOSIctl|wrshiftreg[6]
|
|
Info (332115): Launch Clock : filtered_sclk_negedge
|
|
Info (332115): Latch Clock : filtered_sclk_negedge
|
|
Info (332115): Exception : dcp_bbs.sdc:3041: set_multicycle_path -hold -to [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MOSIctl|wrshiftreg[6]}] 1
|
|
Info (332115): Multicycle - Setup Start : 2
|
|
Info (332115): Multicycle - Hold Start : 1
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 0.236 0.236 R clock network delay
|
|
Info (332115): 0.236 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MOSIctl|wrshiftreg[5]
|
|
Info (332115): 0.435 0.199 FF uTco fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MOSIctl|wrshiftreg[5]|q
|
|
Info (332115): 0.746 0.311 FF CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MOSIctl|wrshiftreg[6]|d
|
|
Info (332115): 0.746 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MOSIctl|wrshiftreg[6]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 0.282 0.282 R clock network delay
|
|
Info (332115): 0.242 -0.040 clock pessimism removed
|
|
Info (332115): 0.686 0.444 uTh fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MOSIctl|wrshiftreg[6]
|
|
Info (332115): Data Arrival Time : 0.746
|
|
Info (332115): Data Required Time : 0.686
|
|
Info (332115): Slack : 0.060
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.064
|
|
Info (20696): -to_clock [get_clocks {hssi_pll_t_outclk1}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.064
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[1].ct0|dout_r[2]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[1].ct0|dout_r[2]
|
|
Info (332115): Launch Clock : hssi_pll_t_outclk1
|
|
Info (332115): Latch Clock : hssi_pll_t_outclk1
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 4.124 4.124 R clock network delay
|
|
Info (332115): 4.124 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[1].ct0|dout_r[2]
|
|
Info (332115): 4.309 0.185 FF uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[1].ct0|dout_r[2]|q
|
|
Info (332115): 4.309 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[1].ct0|t2|dout|datae
|
|
Info (332115): 4.632 0.323 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[1].ct0|t2|dout|combout
|
|
Info (332115): 4.632 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[1].ct0|dout_r[2]|d
|
|
Info (332115): 4.632 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[1].ct0|dout_r[2]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 4.568 4.568 R clock network delay
|
|
Info (332115): 4.125 -0.443 clock pessimism removed
|
|
Info (332115): 4.125 0.000 clock uncertainty
|
|
Info (332115): 4.568 0.443 uTh fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[1].ct0|dout_r[2]
|
|
Info (332115): Data Arrival Time : 4.632
|
|
Info (332115): Data Required Time : 4.568
|
|
Info (332115): Slack : 0.064
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.068
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_clk}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.068
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[7].ct0|dout_r[3]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[7].ct0|dout_r[3]
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_clk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_clk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 5.038 5.038 R clock network delay
|
|
Info (332115): 5.038 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[7].ct0|dout_r[3]
|
|
Info (332115): 5.220 0.182 FF uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[7].ct0|dout_r[3]|q
|
|
Info (332115): 5.220 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[7].ct0|t3|dout|datae
|
|
Info (332115): 5.546 0.326 FR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[7].ct0|t3|dout|combout
|
|
Info (332115): 5.546 0.000 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[7].ct0|dout_r[3]|d
|
|
Info (332115): 5.546 0.000 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[7].ct0|dout_r[3]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 7.020 7.020 R clock network delay
|
|
Info (332115): 5.038 -1.982 clock pessimism removed
|
|
Info (332115): 5.038 0.000 clock uncertainty
|
|
Info (332115): 5.478 0.440 uTh fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[7].ct0|dout_r[3]
|
|
Info (332115): Data Arrival Time : 5.546
|
|
Info (332115): Data Required Time : 5.478
|
|
Info (332115): Slack : 0.068
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.069
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_div_clk}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.069
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[4].ct0|dout_r[3]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[4].ct0|dout_r[3]
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_div_clk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_div_clk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 7.743 7.743 R clock network delay
|
|
Info (332115): 7.743 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[4].ct0|dout_r[3]
|
|
Info (332115): 7.923 0.180 FF uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[4].ct0|dout_r[3]|q
|
|
Info (332115): 7.923 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[4].ct0|t3|dout|datae
|
|
Info (332115): 8.249 0.326 FR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[4].ct0|t3|dout|combout
|
|
Info (332115): 8.249 0.000 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[4].ct0|dout_r[3]|d
|
|
Info (332115): 8.249 0.000 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[4].ct0|dout_r[3]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 10.266 10.266 R clock network delay
|
|
Info (332115): 7.743 -2.523 clock pessimism removed
|
|
Info (332115): 7.743 0.000 clock uncertainty
|
|
Info (332115): 8.180 0.437 uTh fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[4].ct0|dout_r[3]
|
|
Info (332115): Data Arrival Time : 8.249
|
|
Info (332115): Data Required Time : 8.180
|
|
Info (332115): Slack : 0.069
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.077
|
|
Info (20696): -to_clock [get_clocks {hssi_pll_r_0_outclk0}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.077
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[2].ct0|dout_r[1]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[2].ct0|dout_r[1]
|
|
Info (332115): Launch Clock : hssi_pll_r_0_outclk0
|
|
Info (332115): Latch Clock : hssi_pll_r_0_outclk0
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 4.444 4.444 R clock network delay
|
|
Info (332115): 4.444 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[2].ct0|dout_r[1]
|
|
Info (332115): 4.653 0.209 FF uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[2].ct0|dout_r[1]|q
|
|
Info (332115): 4.653 0.000 FF CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[2].ct0|t1|dout|datad
|
|
Info (332115): 5.007 0.354 FF CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[2].ct0|t1|dout|combout
|
|
Info (332115): 5.007 0.000 FF CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[2].ct0|dout_r[1]|d
|
|
Info (332115): 5.007 0.000 FF CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[2].ct0|dout_r[1]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 4.942 4.942 R clock network delay
|
|
Info (332115): 4.444 -0.498 clock pessimism removed
|
|
Info (332115): 4.444 0.000 clock uncertainty
|
|
Info (332115): 4.930 0.486 uTh fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[2].ct0|dout_r[1]
|
|
Info (332115): Data Arrival Time : 5.007
|
|
Info (332115): Data Required Time : 4.930
|
|
Info (332115): Slack : 0.077
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.078
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|tx_pma_div_clk}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.078
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[5].ct0|dout_r[1]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[5].ct0|dout_r[1]
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|tx_pma_div_clk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|tx_pma_div_clk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 6.775 6.775 R clock network delay
|
|
Info (332115): 6.775 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[5].ct0|dout_r[1]
|
|
Info (332115): 6.952 0.177 FF uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[5].ct0|dout_r[1]|q
|
|
Info (332115): 6.952 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[5].ct0|t1|dout|datae
|
|
Info (332115): 7.278 0.326 FR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[5].ct0|t1|dout|combout
|
|
Info (332115): 7.278 0.000 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[5].ct0|dout_r[1]|d
|
|
Info (332115): 7.278 0.000 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[5].ct0|dout_r[1]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 8.701 8.701 R clock network delay
|
|
Info (332115): 6.775 -1.926 clock pessimism removed
|
|
Info (332115): 6.775 0.000 clock uncertainty
|
|
Info (332115): 7.200 0.425 uTh fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[5].ct0|dout_r[1]
|
|
Info (332115): Data Arrival Time : 7.278
|
|
Info (332115): Data Required Time : 7.200
|
|
Info (332115): Slack : 0.078
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.087
|
|
Info (20696): -to_clock [get_clocks {hssi_pll_r_0_outclk1}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.087
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[0].ct0|dout_r[1]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[0].ct0|dout_r[1]
|
|
Info (332115): Launch Clock : hssi_pll_r_0_outclk1
|
|
Info (332115): Latch Clock : hssi_pll_r_0_outclk1
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 4.433 4.433 R clock network delay
|
|
Info (332115): 4.433 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[0].ct0|dout_r[1]
|
|
Info (332115): 4.637 0.204 FF uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[0].ct0|dout_r[1]|q
|
|
Info (332115): 4.637 0.000 FF CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[0].ct0|t1|dout|datad
|
|
Info (332115): 4.991 0.354 FF CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[0].ct0|t1|dout|combout
|
|
Info (332115): 4.991 0.000 FF CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[0].ct0|dout_r[1]|d
|
|
Info (332115): 4.991 0.000 FF CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[0].ct0|dout_r[1]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 4.934 4.934 R clock network delay
|
|
Info (332115): 4.433 -0.501 clock pessimism removed
|
|
Info (332115): 4.433 0.000 clock uncertainty
|
|
Info (332115): 4.904 0.471 uTh fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[0].ct0|dout_r[1]
|
|
Info (332115): Data Arrival Time : 4.991
|
|
Info (332115): Data Required Time : 4.904
|
|
Info (332115): Slack : 0.087
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.090
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|rx_pma_clk}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.090
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_consecutive_error[0]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_consecutive_error[0]
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|rx_pma_clk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|rx_pma_clk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 5.047 5.047 R clock network delay
|
|
Info (332115): 5.047 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_consecutive_error[0]
|
|
Info (332115): 5.223 0.176 FF uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_consecutive_error[0]|q
|
|
Info (332115): 5.223 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|i41~1|datae
|
|
Info (332115): 5.556 0.333 FR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|i41~1|combout
|
|
Info (332115): 5.556 0.000 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_consecutive_error[0]|d
|
|
Info (332115): 5.556 0.000 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_consecutive_error[0]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 7.036 7.036 R clock network delay
|
|
Info (332115): 5.046 -1.990 clock pessimism removed
|
|
Info (332115): 5.046 0.000 clock uncertainty
|
|
Info (332115): 5.466 0.420 uTh fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_consecutive_error[0]
|
|
Info (332115): Data Arrival Time : 5.556
|
|
Info (332115): Data Required Time : 5.466
|
|
Info (332115): Slack : 0.090
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.095
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk0}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.095
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_green_bs|uClk_usrDiv2_q1
|
|
Info (332115): To Node : fpga_top|inst_green_bs|uClk_usrDiv2_q2
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk0
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk0
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 5.274 5.274 R clock network delay
|
|
Info (332115): 5.274 0.000 fpga_top|inst_green_bs|uClk_usrDiv2_q1
|
|
Info (332115): 5.458 0.184 FF uTco fpga_top|inst_green_bs|uClk_usrDiv2_q1|q
|
|
Info (332115): 5.458 0.000 FF CELL High Speed fpga_top|inst_green_bs|uClk_usrDiv2_q2~0|datae
|
|
Info (332115): 5.807 0.349 FR CELL High Speed fpga_top|inst_green_bs|uClk_usrDiv2_q2~0|combout
|
|
Info (332115): 5.807 0.000 RR CELL High Speed fpga_top|inst_green_bs|uClk_usrDiv2_q2|d
|
|
Info (332115): 5.807 0.000 RR CELL High Speed fpga_top|inst_green_bs|uClk_usrDiv2_q2
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 6.382 6.382 R clock network delay
|
|
Info (332115): 5.274 -1.108 clock pessimism removed
|
|
Info (332115): 5.274 0.000 clock uncertainty
|
|
Info (332115): 5.712 0.438 uTh fpga_top|inst_green_bs|uClk_usrDiv2_q2
|
|
Info (332115): Data Arrival Time : 5.807
|
|
Info (332115): Data Required Time : 5.712
|
|
Info (332115): Slack : 0.095
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.097
|
|
Info (20696): -to_clock [get_clocks {ETH_RefClk}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.097
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[6].ct0|dout_r[4]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[6].ct0|dout_r[4]
|
|
Info (332115): Launch Clock : ETH_RefClk
|
|
Info (332115): Latch Clock : ETH_RefClk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 4.930 4.930 R clock network delay
|
|
Info (332115): 4.930 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[6].ct0|dout_r[4]
|
|
Info (332115): 5.133 0.203 FF uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[6].ct0|dout_r[4]|q
|
|
Info (332115): 5.133 0.000 FF CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[6].ct0|t4|dout|datae
|
|
Info (332115): 5.499 0.366 FR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[6].ct0|t4|dout|combout
|
|
Info (332115): 5.499 0.000 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[6].ct0|dout_r[4]|d
|
|
Info (332115): 5.499 0.000 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[6].ct0|dout_r[4]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 5.493 5.493 R clock network delay
|
|
Info (332115): 4.930 -0.563 clock pessimism removed
|
|
Info (332115): 4.930 0.000 clock uncertainty
|
|
Info (332115): 5.402 0.472 uTh fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[6].ct0|dout_r[4]
|
|
Info (332115): Data Arrival Time : 5.499
|
|
Info (332115): Data Required Time : 5.402
|
|
Info (332115): Slack : 0.097
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.097
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|rx_pma_clk}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.097
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_prbs_err_sync|resync_chains[0].sync_r[0]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_prbs_err_sync|resync_chains[0].sync_r[1]
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|rx_pma_clk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|rx_pma_clk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 5.018 5.018 R clock network delay
|
|
Info (332115): 5.018 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_prbs_err_sync|resync_chains[0].sync_r[0]
|
|
Info (332115): 5.205 0.187 FF uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_prbs_err_sync|resync_chains[0].sync_r[0]|q
|
|
Info (332115): 5.541 0.336 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_prbs_err_sync|resync_chains[0].sync_r[1]|d
|
|
Info (332115): 5.541 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_prbs_err_sync|resync_chains[0].sync_r[1]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 7.001 7.001 R clock network delay
|
|
Info (332115): 5.017 -1.984 clock pessimism removed
|
|
Info (332115): 5.017 0.000 clock uncertainty
|
|
Info (332115): 5.444 0.427 uTh fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_prbs_err_sync|resync_chains[0].sync_r[1]
|
|
Info (332115): Data Arrival Time : 5.541
|
|
Info (332115): Data Required Time : 5.444
|
|
Info (332115): Slack : 0.097
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.097
|
|
Info (20696): -to_clock [get_clocks {hssi_pll_t_outclk0}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.097
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[3].ct0|dout_r[2]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[3].ct0|dout_r[2]
|
|
Info (332115): Launch Clock : hssi_pll_t_outclk0
|
|
Info (332115): Latch Clock : hssi_pll_t_outclk0
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 4.198 4.198 R clock network delay
|
|
Info (332115): 4.198 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[3].ct0|dout_r[2]
|
|
Info (332115): 4.402 0.204 FF uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[3].ct0|dout_r[2]|q
|
|
Info (332115): 4.402 0.000 FF CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[3].ct0|t2|dout|datae
|
|
Info (332115): 4.768 0.366 FR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[3].ct0|t2|dout|combout
|
|
Info (332115): 4.768 0.000 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[3].ct0|dout_r[2]|d
|
|
Info (332115): 4.768 0.000 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[3].ct0|dout_r[2]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 4.649 4.649 R clock network delay
|
|
Info (332115): 4.199 -0.450 clock pessimism removed
|
|
Info (332115): 4.199 0.000 clock uncertainty
|
|
Info (332115): 4.671 0.472 uTh fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[3].ct0|dout_r[2]
|
|
Info (332115): Data Arrival Time : 4.768
|
|
Info (332115): Data Required Time : 4.671
|
|
Info (332115): Slack : 0.097
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.114
|
|
Info (20696): -to_clock [get_clocks {u0|dcp_iopll|dcp_iopll|clk50}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.114
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_green_bs|pClkDiv4_q1
|
|
Info (332115): To Node : fpga_top|inst_green_bs|pClkDiv4_q2
|
|
Info (332115): Launch Clock : u0|dcp_iopll|dcp_iopll|clk50
|
|
Info (332115): Latch Clock : u0|dcp_iopll|dcp_iopll|clk50
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 8.340 8.340 R clock network delay
|
|
Info (332115): 8.340 0.000 fpga_top|inst_green_bs|pClkDiv4_q1
|
|
Info (332115): 8.531 0.191 FF uTco fpga_top|inst_green_bs|pClkDiv4_q1|q
|
|
Info (332115): 8.531 0.000 FF CELL High Speed fpga_top|inst_green_bs|pClkDiv4_q2~0|datae
|
|
Info (332115): 8.883 0.352 FR CELL High Speed fpga_top|inst_green_bs|pClkDiv4_q2~0|combout
|
|
Info (332115): 8.883 0.000 RR CELL High Speed fpga_top|inst_green_bs|pClkDiv4_q2|d
|
|
Info (332115): 8.883 0.000 RR CELL High Speed fpga_top|inst_green_bs|pClkDiv4_q2
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 9.694 9.694 R clock network delay
|
|
Info (332115): 8.340 -1.354 clock pessimism removed
|
|
Info (332115): 8.340 0.000 clock uncertainty
|
|
Info (332115): 8.769 0.429 uTh fpga_top|inst_green_bs|pClkDiv4_q2
|
|
Info (332115): Data Arrival Time : 8.883
|
|
Info (332115): Data Required Time : 8.769
|
|
Info (332115): Slack : 0.114
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.141
|
|
Info (20696): -to_clock [get_clocks {fspi_sclk}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.141
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MISOctl|sync_miso_ack|dreg[0]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MISOctl|loadstsinkdata
|
|
Info (332115): Launch Clock : fspi_sclk
|
|
Info (332115): Latch Clock : fspi_sclk
|
|
Info (332115): Exception : dcp_bbs.sdc:3032: set_multicycle_path -hold -to [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MISOctl|loadstsinkdata}] 1
|
|
Info (332115): Multicycle - Setup Start : 2
|
|
Info (332115): Multicycle - Hold Start : 1
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 5.724 5.724 R clock network delay
|
|
Info (332115): 5.724 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MISOctl|sync_miso_ack|dreg[0]
|
|
Info (332115): 5.903 0.179 FF uTco fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MISOctl|sync_miso_ack|dreg[0]|q
|
|
Info (332115): 5.964 0.061 FF CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MISOctl|sync_miso_ack|dreg[0]~la_mlab/laboutt[10]
|
|
Info (332115): 6.185 0.221 FF IC High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MISOctl|i20~0|datad
|
|
Info (332115): 6.295 0.110 FR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MISOctl|i20~0|combout
|
|
Info (332115): 6.295 0.000 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MISOctl|loadstsinkdata|d
|
|
Info (332115): 6.295 0.000 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MISOctl|loadstsinkdata
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 6.641 6.641 R clock network delay
|
|
Info (332115): 5.724 -0.917 clock pessimism removed
|
|
Info (332115): 5.724 0.000 clock uncertainty
|
|
Info (332115): 6.154 0.430 uTh fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MISOctl|loadstsinkdata
|
|
Info (332115): Data Arrival Time : 6.295
|
|
Info (332115): Data Required Time : 6.154
|
|
Info (332115): Slack : 0.141
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.220
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_bonding_clocks[0]}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.220
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|sta_rx_clk2_by4_1
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs~byte_deserializer_pcs_clk_div_by_4_txclk_reg.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|rx_clk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_bonding_clocks[0]
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 2.747 2.747 R clock network delay
|
|
Info (332115): 2.747 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|sta_rx_clk2_by4_1
|
|
Info (332115): 2.747 0.000 RR CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs~byte_deserializer_pcs_clk_div_by_4_txclk_reg.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 3.784 3.784 R clock network delay
|
|
Info (332115): 2.384 -1.400 clock pessimism removed
|
|
Info (332115): 2.527 0.143 uTh fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs~byte_deserializer_pcs_clk_div_by_4_txclk_reg.reg
|
|
Info (332115): Data Arrival Time : 2.747
|
|
Info (332115): Data Required Time : 2.527
|
|
Info (332115): Slack : 0.220
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.241
|
|
Info (20696): -to_clock [get_clocks {mem|ddr4a|ddr4a_phy_clk_l_2}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.241
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : mem|ddr4a_bridge|ddr_avmm_bridge|cmd_writedata[414]
|
|
Info (332115): To Node : mem|ddr4a|ddr4a|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[0].lane_gen[3].lane_inst~phy_reg1
|
|
Info (332115): Launch Clock : mem|ddr4a|ddr4a_core_usr_clk
|
|
Info (332115): Latch Clock : mem|ddr4a|ddr4a_phy_clk_l_2
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.117 0.117 launch edge time
|
|
Info (332115): 2.789 2.672 R clock network delay
|
|
Info (332115): 2.789 0.000 mem|ddr4a_bridge|ddr_avmm_bridge|cmd_writedata[414]
|
|
Info (332115): 2.967 0.178 FF uTco mem|ddr4a_bridge|ddr_avmm_bridge|cmd_writedata[414]|q
|
|
Info (332115): 3.059 0.092 FF CELL High Speed mem|ddr4a_bridge|ddr_avmm_bridge|cmd_writedata[414]~la_lab/laboutt[8]
|
|
Info (332115): 3.469 0.410 FF IC High Speed mem|ddr4a_avmm_chkr|avm_writedata[414]~246|datac
|
|
Info (332115): 3.575 0.106 FF CELL High Speed mem|ddr4a_avmm_chkr|avm_writedata[414]~246|combout
|
|
Info (332115): 3.576 0.001 FF CELL High Speed mem|ddr4a_avmm_chkr|avm_writedata[414]~246~la_lab/laboutb[19]
|
|
Info (332115): 4.330 0.754 FF IC High Speed mem|ddr4a|ddr4a|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[0].lane_gen[3].lane_inst|data_from_core[22]
|
|
Info (332115): 4.330 0.000 FF CELL mem|ddr4a|ddr4a|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[0].lane_gen[3].lane_inst~phy_reg1
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.117 0.117 latch edge time
|
|
Info (332115): 3.456 3.339 R clock network delay
|
|
Info (332115): 3.283 -0.173 clock pessimism removed
|
|
Info (332115): 3.603 0.320 clock uncertainty
|
|
Info (332115): 4.089 0.486 uTh mem|ddr4a|ddr4a|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[0].lane_gen[3].lane_inst~phy_reg1
|
|
Info (332115): Data Arrival Time : 4.330
|
|
Info (332115): Data Required Time : 4.089
|
|
Info (332115): Slack : 0.241
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.264
|
|
Info (20696): -to_clock [get_clocks {mem|ddr4a|ddr4a_phy_clk_l_1}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.264
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : mem|ddr4a_bridge|ddr_avmm_bridge|cmd_writedata[121]
|
|
Info (332115): To Node : mem|ddr4a|ddr4a|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[2].lane_gen[2].lane_inst~phy_reg1
|
|
Info (332115): Launch Clock : mem|ddr4a|ddr4a_core_usr_clk
|
|
Info (332115): Latch Clock : mem|ddr4a|ddr4a_phy_clk_l_1
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.117 0.117 launch edge time
|
|
Info (332115): 2.784 2.667 R clock network delay
|
|
Info (332115): 2.784 0.000 mem|ddr4a_bridge|ddr_avmm_bridge|cmd_writedata[121]
|
|
Info (332115): 2.964 0.180 FF uTco mem|ddr4a_bridge|ddr_avmm_bridge|cmd_writedata[121]|q
|
|
Info (332115): 3.057 0.093 FF CELL High Speed mem|ddr4a_bridge|ddr_avmm_bridge|cmd_writedata[121]~la_lab/laboutt[11]
|
|
Info (332115): 3.484 0.427 FF IC High Speed mem|ddr4a_avmm_chkr|avm_writedata[121]~457|datac
|
|
Info (332115): 3.590 0.106 FF CELL High Speed mem|ddr4a_avmm_chkr|avm_writedata[121]~457|combout
|
|
Info (332115): 3.591 0.001 FF CELL High Speed mem|ddr4a_avmm_chkr|avm_writedata[121]~457~la_lab/laboutb[3]
|
|
Info (332115): 4.378 0.787 FF IC High Speed mem|ddr4a|ddr4a|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[2].lane_gen[2].lane_inst|data_from_core[81]
|
|
Info (332115): 4.378 0.000 FF CELL mem|ddr4a|ddr4a|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[2].lane_gen[2].lane_inst~phy_reg1
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.117 0.117 latch edge time
|
|
Info (332115): 3.469 3.352 R clock network delay
|
|
Info (332115): 3.296 -0.173 clock pessimism removed
|
|
Info (332115): 3.616 0.320 clock uncertainty
|
|
Info (332115): 4.114 0.498 uTh mem|ddr4a|ddr4a|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[2].lane_gen[2].lane_inst~phy_reg1
|
|
Info (332115): Data Arrival Time : 4.378
|
|
Info (332115): Data Required Time : 4.114
|
|
Info (332115): Slack : 0.264
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.296
|
|
Info (20696): -to_clock [get_clocks {mem|ddr4a|ddr4a_phy_clk_l_0}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.296
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : mem|ddr4a_bridge|ddr_avmm_bridge|cmd_address[14]
|
|
Info (332115): To Node : mem|ddr4a|ddr4a|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[1].tile_ctrl_inst~hmc_reg1
|
|
Info (332115): Launch Clock : mem|ddr4a|ddr4a_core_usr_clk
|
|
Info (332115): Latch Clock : mem|ddr4a|ddr4a_phy_clk_l_0
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.117 0.117 launch edge time
|
|
Info (332115): 2.795 2.678 R clock network delay
|
|
Info (332115): 2.795 0.000 mem|ddr4a_bridge|ddr_avmm_bridge|cmd_address[14]
|
|
Info (332115): 2.972 0.177 FF uTco mem|ddr4a_bridge|ddr_avmm_bridge|cmd_address[14]|q
|
|
Info (332115): 3.029 0.057 FF CELL High Speed mem|ddr4a_bridge|ddr_avmm_bridge|cmd_address[14]~la_lab/laboutt[1]
|
|
Info (332115): 3.144 0.115 FF IC High Speed mem|ddr4a_avmm_chkr|avm_address[14]~14|datac
|
|
Info (332115): 3.249 0.105 FF CELL High Speed mem|ddr4a_avmm_chkr|avm_address[14]~14|combout
|
|
Info (332115): 3.250 0.001 FF CELL High Speed mem|ddr4a_avmm_chkr|avm_address[14]~14~la_lab/laboutt[3]
|
|
Info (332115): 3.995 0.745 FF IC High Speed mem|ddr4a|ddr4a|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[1].tile_ctrl_inst|core2ctl_avl0[16]
|
|
Info (332115): 3.995 0.000 FF CELL mem|ddr4a|ddr4a|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[1].tile_ctrl_inst~hmc_reg1
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.117 0.117 latch edge time
|
|
Info (332115): 3.492 3.375 R clock network delay
|
|
Info (332115): 2.937 -0.555 clock pessimism removed
|
|
Info (332115): 3.160 0.223 clock uncertainty
|
|
Info (332115): 3.699 0.539 uTh mem|ddr4a|ddr4a|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[1].tile_ctrl_inst~hmc_reg1
|
|
Info (332115): Data Arrival Time : 3.995
|
|
Info (332115): Data Required Time : 3.699
|
|
Info (332115): Slack : 0.296
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.304
|
|
Info (20696): -to_clock [get_clocks {mem|ddr4b|ddr4b_phy_clk_l_0}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.304
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : mem|ddr4b_bridge|ddr_avmm_bridge|cmd_address[23]
|
|
Info (332115): To Node : mem|ddr4b|ddr4b|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[1].tile_ctrl_inst~hmc_reg1
|
|
Info (332115): Launch Clock : mem|ddr4a|ddr4a_core_usr_clk
|
|
Info (332115): Latch Clock : mem|ddr4b|ddr4b_phy_clk_l_0
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.117 0.117 launch edge time
|
|
Info (332115): 2.696 2.579 R clock network delay
|
|
Info (332115): 2.696 0.000 mem|ddr4b_bridge|ddr_avmm_bridge|cmd_address[23]
|
|
Info (332115): 2.875 0.179 FF uTco mem|ddr4b_bridge|ddr_avmm_bridge|cmd_address[23]|q
|
|
Info (332115): 2.932 0.057 FF CELL High Speed mem|ddr4b_bridge|ddr_avmm_bridge|cmd_address[23]~la_mlab/laboutb[13]
|
|
Info (332115): 3.400 0.468 FF IC High Speed mem|ddr4b_emif_address_mux[23]~23|datab
|
|
Info (332115): 3.558 0.158 FF CELL High Speed mem|ddr4b_emif_address_mux[23]~23|combout
|
|
Info (332115): 3.561 0.003 FF CELL High Speed mem|ddr4b_emif_address_mux[23]~23~la_mlab/laboutt[12]
|
|
Info (332115): 4.437 0.876 FF IC High Speed mem|ddr4b|ddr4b|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[1].tile_ctrl_inst|core2ctl_avl0[25]
|
|
Info (332115): 4.437 0.000 FF CELL mem|ddr4b|ddr4b|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[1].tile_ctrl_inst~hmc_reg1
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.117 0.117 latch edge time
|
|
Info (332115): 3.370 3.253 R clock network delay
|
|
Info (332115): 3.272 -0.098 clock pessimism removed
|
|
Info (332115): 3.592 0.320 clock uncertainty
|
|
Info (332115): 4.133 0.541 uTh mem|ddr4b|ddr4b|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[1].tile_ctrl_inst~hmc_reg1
|
|
Info (332115): Data Arrival Time : 4.437
|
|
Info (332115): Data Required Time : 4.133
|
|
Info (332115): Slack : 0.304
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.304
|
|
Info (20696): -to_clock [get_clocks {mem|ddr4b|ddr4b_phy_clk_l_1}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.304
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : mem|ddr4b_bridge|ddr_avmm_bridge|cmd_writedata[238]
|
|
Info (332115): To Node : mem|ddr4b|ddr4b|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[2].lane_gen[0].lane_inst~phy_reg1
|
|
Info (332115): Launch Clock : mem|ddr4a|ddr4a_core_usr_clk
|
|
Info (332115): Latch Clock : mem|ddr4b|ddr4b_phy_clk_l_1
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.117 0.117 launch edge time
|
|
Info (332115): 2.743 2.626 R clock network delay
|
|
Info (332115): 2.743 0.000 mem|ddr4b_bridge|ddr_avmm_bridge|cmd_writedata[238]
|
|
Info (332115): 2.920 0.177 FF uTco mem|ddr4b_bridge|ddr_avmm_bridge|cmd_writedata[238]|q
|
|
Info (332115): 3.013 0.093 FF CELL High Speed mem|ddr4b_bridge|ddr_avmm_bridge|cmd_writedata[238]~la_lab/laboutb[11]
|
|
Info (332115): 3.581 0.568 FF IC High Speed mem|ddr4b_avmm_chkr|avm_writedata[0]~371|datab
|
|
Info (332115): 3.742 0.161 FF CELL High Speed mem|ddr4b_avmm_chkr|avm_writedata[0]~371|combout
|
|
Info (332115): 3.744 0.002 FF CELL High Speed mem|ddr4b_avmm_chkr|avm_writedata[0]~371~la_lab/laboutb[1]
|
|
Info (332115): 4.374 0.630 FF IC High Speed mem|ddr4b|ddr4b|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[2].lane_gen[0].lane_inst|data_from_core[51]
|
|
Info (332115): 4.374 0.000 FF CELL mem|ddr4b|ddr4b|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[2].lane_gen[0].lane_inst~phy_reg1
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.117 0.117 latch edge time
|
|
Info (332115): 3.344 3.227 R clock network delay
|
|
Info (332115): 3.246 -0.098 clock pessimism removed
|
|
Info (332115): 3.566 0.320 clock uncertainty
|
|
Info (332115): 4.070 0.504 uTh mem|ddr4b|ddr4b|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[2].lane_gen[0].lane_inst~phy_reg1
|
|
Info (332115): Data Arrival Time : 4.374
|
|
Info (332115): Data Required Time : 4.070
|
|
Info (332115): Slack : 0.304
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.318
|
|
Info (20696): -to_clock [get_clocks {mem|ddr4b|ddr4b_phy_clk_l_2}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.318
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : mem|ddr4b_bridge|ddr_avmm_bridge|cmd_writedata[141]
|
|
Info (332115): To Node : mem|ddr4b|ddr4b|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[0].lane_gen[1].lane_inst~phy_reg1
|
|
Info (332115): Launch Clock : mem|ddr4a|ddr4a_core_usr_clk
|
|
Info (332115): Latch Clock : mem|ddr4b|ddr4b_phy_clk_l_2
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.117 0.117 launch edge time
|
|
Info (332115): 2.722 2.605 R clock network delay
|
|
Info (332115): 2.722 0.000 mem|ddr4b_bridge|ddr_avmm_bridge|cmd_writedata[141]
|
|
Info (332115): 2.903 0.181 FF uTco mem|ddr4b_bridge|ddr_avmm_bridge|cmd_writedata[141]|q
|
|
Info (332115): 2.960 0.057 FF CELL High Speed mem|ddr4b_bridge|ddr_avmm_bridge|cmd_writedata[141]~la_mlab/laboutb[1]
|
|
Info (332115): 3.488 0.528 FF IC High Speed mem|ddr4b_avmm_chkr|avm_writedata[0]~106|datab
|
|
Info (332115): 3.646 0.158 FF CELL High Speed mem|ddr4b_avmm_chkr|avm_writedata[0]~106|combout
|
|
Info (332115): 3.649 0.003 FF CELL High Speed mem|ddr4b_avmm_chkr|avm_writedata[0]~106~la_mlab/laboutb[8]
|
|
Info (332115): 4.330 0.681 FF IC High Speed mem|ddr4b|ddr4b|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[0].lane_gen[1].lane_inst|data_from_core[2]
|
|
Info (332115): 4.330 0.000 FF CELL mem|ddr4b|ddr4b|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[0].lane_gen[1].lane_inst~phy_reg1
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.117 0.117 latch edge time
|
|
Info (332115): 3.329 3.212 R clock network delay
|
|
Info (332115): 3.231 -0.098 clock pessimism removed
|
|
Info (332115): 3.551 0.320 clock uncertainty
|
|
Info (332115): 4.012 0.461 uTh mem|ddr4b|ddr4b|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[0].lane_gen[1].lane_inst~phy_reg1
|
|
Info (332115): Data Arrival Time : 4.330
|
|
Info (332115): Data Required Time : 4.012
|
|
Info (332115): Slack : 0.318
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.446
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|pld_clk}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.446
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_sriov_2.sriov2.sriov_bridge|altpcie_pcie_sriov2_top_inst|altpcie_sriov2_tx_data_bridge_inst|TxStData_hip_o[19]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~pld_clk.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|wys~CORE_CLK_OUT
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|pld_clk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 7.805 7.805 R clock network delay
|
|
Info (332115): 7.805 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_sriov_2.sriov2.sriov_bridge|altpcie_pcie_sriov2_top_inst|altpcie_sriov2_tx_data_bridge_inst|TxStData_hip_o[19]
|
|
Info (332115): 7.984 0.179 FF uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_sriov_2.sriov2.sriov_bridge|altpcie_pcie_sriov2_top_inst|altpcie_sriov2_tx_data_bridge_inst|TxStData_hip_o[19]|q
|
|
Info (332115): 8.041 0.057 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_sriov_2.sriov2.sriov_bridge|altpcie_pcie_sriov2_top_inst|altpcie_sriov2_tx_data_bridge_inst|TxStData_hip_o[19]~la_mlab/laboutt[9]
|
|
Info (332115): 9.008 0.967 FF IC High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|tx_st_data[19]
|
|
Info (332115): 9.008 0.000 FF CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~pld_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 9.547 9.547 R clock network delay
|
|
Info (332115): 8.286 -1.261 clock pessimism removed
|
|
Info (332115): 8.353 0.067 clock uncertainty
|
|
Info (332115): 8.562 0.209 uTh fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~pld_clk.reg
|
|
Info (332115): Data Arrival Time : 9.008
|
|
Info (332115): Data Required Time : 8.562
|
|
Info (332115): Slack : 0.446
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.639
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|avmmclk}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.639
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|channel_count[2]~RTMDUPLICATE
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Launch Clock : PCIE_REFCLK
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|avmmclk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 5.055 5.055 R clock network delay
|
|
Info (332115): 5.055 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|channel_count[2]~RTMDUPLICATE
|
|
Info (332115): 5.234 0.179 FF uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|channel_count[2]~RTMDUPLICATE|q
|
|
Info (332115): 5.291 0.057 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|channel_count[2]~RTMDUPLICATE~la_mlab/laboutt[2]
|
|
Info (332115): 5.452 0.161 FF IC High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i8~0|datab
|
|
Info (332115): 5.627 0.175 FR CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i8~0|combout
|
|
Info (332115): 5.629 0.002 RR CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i8~0~la_mlab/laboutb[15]
|
|
Info (332115): 6.493 0.864 RR IC Mixed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst|avmmwrite
|
|
Info (332115): 6.493 0.000 RR CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 6.058 6.058 R clock network delay
|
|
Info (332115): 5.554 -0.504 clock pessimism removed
|
|
Info (332115): 5.594 0.040 clock uncertainty
|
|
Info (332115): 5.854 0.260 uTh fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Arrival Time : 6.493
|
|
Info (332115): Data Required Time : 5.854
|
|
Info (332115): Slack : 0.639
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.680
|
|
Info (20696): -to_clock [get_clocks {vl_qph_user_clk_clkpsc_clk0}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.680
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[3]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[3]
|
|
Info (332115): Launch Clock : vl_qph_user_clk_clkpsc_clk0
|
|
Info (332115): Latch Clock : vl_qph_user_clk_clkpsc_clk0
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 5.625 5.625 R clock network delay
|
|
Info (332115): 5.625 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[3]
|
|
Info (332115): 5.817 0.192 FF uTco fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[3]|q
|
|
Info (332115): 5.874 0.057 FF CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[3]~la_mlab/laboutb[6]
|
|
Info (332115): 6.617 0.743 FF IC High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[3]~0|datac
|
|
Info (332115): 6.745 0.128 FR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[3]~0|combout
|
|
Info (332115): 6.745 0.000 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[3]|d
|
|
Info (332115): 6.745 0.000 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[3]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 6.786 6.786 R clock network delay
|
|
Info (332115): 5.624 -1.162 clock pessimism removed
|
|
Info (332115): 5.624 0.000 clock uncertainty
|
|
Info (332115): 6.065 0.441 uTh fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[3]
|
|
Info (332115): Data Arrival Time : 6.745
|
|
Info (332115): Data Required Time : 6.065
|
|
Info (332115): Slack : 0.680
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.680
|
|
Info (20696): -to_clock [get_clocks {vl_qph_user_clk_clkpsc_clk1}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.680
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[3]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[3]
|
|
Info (332115): Launch Clock : vl_qph_user_clk_clkpsc_clk1
|
|
Info (332115): Latch Clock : vl_qph_user_clk_clkpsc_clk1
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 5.721 5.721 R clock network delay
|
|
Info (332115): 5.721 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[3]
|
|
Info (332115): 5.913 0.192 FF uTco fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[3]|q
|
|
Info (332115): 5.970 0.057 FF CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[3]~la_mlab/laboutb[6]
|
|
Info (332115): 6.713 0.743 FF IC High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[3]~0|datac
|
|
Info (332115): 6.841 0.128 FR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[3]~0|combout
|
|
Info (332115): 6.841 0.000 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[3]|d
|
|
Info (332115): 6.841 0.000 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[3]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 6.916 6.916 R clock network delay
|
|
Info (332115): 5.720 -1.196 clock pessimism removed
|
|
Info (332115): 5.720 0.000 clock uncertainty
|
|
Info (332115): 6.161 0.441 uTh fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[3]
|
|
Info (332115): Data Arrival Time : 6.841
|
|
Info (332115): Data Required Time : 6.161
|
|
Info (332115): Slack : 0.680
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.742
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|avmmclk}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.742
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|reconfig_address[8]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Launch Clock : SYS_RefClk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|avmmclk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 4.270 4.270 R clock network delay
|
|
Info (332115): 4.270 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|reconfig_address[8]
|
|
Info (332115): 4.457 0.187 FF uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|reconfig_address[8]|q
|
|
Info (332115): 4.554 0.097 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|reconfig_address[8]~la_mlab/laboutt[19]
|
|
Info (332115): 5.969 1.415 FF IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst|avmmaddress[8]
|
|
Info (332115): 5.969 0.000 FF CELL fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 5.039 5.039 R clock network delay
|
|
Info (332115): 4.803 -0.236 clock pessimism removed
|
|
Info (332115): 4.833 0.030 clock uncertainty
|
|
Info (332115): 5.227 0.394 uTh fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Arrival Time : 5.969
|
|
Info (332115): Data Required Time : 5.227
|
|
Info (332115): Slack : 0.742
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.826
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|avmmclk}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.826
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|g_arb[1].arbiter_inst|grant[0]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Launch Clock : PCIE_REFCLK
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|avmmclk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 5.060 5.060 R clock network delay
|
|
Info (332115): 5.060 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|g_arb[1].arbiter_inst|grant[0]
|
|
Info (332115): 5.240 0.180 FF uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|g_arb[1].arbiter_inst|grant[0]|q
|
|
Info (332115): 5.297 0.057 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|g_arb[1].arbiter_inst|grant[0]~la_mlab/laboutb[17]
|
|
Info (332115): 5.636 0.339 FF IC Mixed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i316~3|datab
|
|
Info (332115): 5.796 0.160 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i316~3|combout
|
|
Info (332115): 5.799 0.003 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i316~3~la_mlab/laboutb[17]
|
|
Info (332115): 6.886 1.087 FF IC High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst|avmmwritedata[3]
|
|
Info (332115): 6.886 0.000 FF CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 6.075 6.075 R clock network delay
|
|
Info (332115): 5.571 -0.504 clock pessimism removed
|
|
Info (332115): 5.611 0.040 clock uncertainty
|
|
Info (332115): 6.060 0.449 uTh fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Arrival Time : 6.886
|
|
Info (332115): Data Required Time : 6.060
|
|
Info (332115): Slack : 0.826
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.871
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|avmmclk}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.871
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|reconfig_address[8]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Launch Clock : SYS_RefClk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|avmmclk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 4.270 4.270 R clock network delay
|
|
Info (332115): 4.270 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|reconfig_address[8]
|
|
Info (332115): 4.457 0.187 FF uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|reconfig_address[8]|q
|
|
Info (332115): 4.554 0.097 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|reconfig_address[8]~la_mlab/laboutt[19]
|
|
Info (332115): 6.097 1.543 FF IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst|avmmaddress[8]
|
|
Info (332115): 6.097 0.000 FF CELL fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 5.038 5.038 R clock network delay
|
|
Info (332115): 4.802 -0.236 clock pessimism removed
|
|
Info (332115): 4.832 0.030 clock uncertainty
|
|
Info (332115): 5.226 0.394 uTh fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Arrival Time : 6.097
|
|
Info (332115): Data Required Time : 5.226
|
|
Info (332115): Slack : 0.871
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.980
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|avmmclk}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.980
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_address[4]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Launch Clock : PCIE_REFCLK
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|avmmclk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 5.089 5.089 R clock network delay
|
|
Info (332115): 5.089 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_address[4]
|
|
Info (332115): 5.294 0.205 FF uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_address[4]|q
|
|
Info (332115): 5.362 0.068 FF CELL Low Power fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_address[4]~la_lab/laboutb[1]
|
|
Info (332115): 5.930 0.568 FF IC Mixed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i522|dataf
|
|
Info (332115): 5.963 0.033 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i522|combout
|
|
Info (332115): 5.965 0.002 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i522~la_lab/laboutt[16]
|
|
Info (332115): 6.885 0.920 FF IC High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst|avmmaddress[4]
|
|
Info (332115): 6.885 0.000 FF CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 5.968 5.968 R clock network delay
|
|
Info (332115): 5.484 -0.484 clock pessimism removed
|
|
Info (332115): 5.524 0.040 clock uncertainty
|
|
Info (332115): 5.905 0.381 uTh fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Arrival Time : 6.885
|
|
Info (332115): Data Required Time : 5.905
|
|
Info (332115): Slack : 0.980
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.995
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|avmmclk}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.995
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|g_arb[3].arbiter_inst|grant[0]~DUPLICATE
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Launch Clock : PCIE_REFCLK
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|avmmclk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 5.060 5.060 R clock network delay
|
|
Info (332115): 5.060 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|g_arb[3].arbiter_inst|grant[0]~DUPLICATE
|
|
Info (332115): 5.241 0.181 FF uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|g_arb[3].arbiter_inst|grant[0]~DUPLICATE|q
|
|
Info (332115): 5.298 0.057 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|g_arb[3].arbiter_inst|grant[0]~DUPLICATE~la_mlab/laboutb[6]
|
|
Info (332115): 5.750 0.452 FF IC Mixed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i768|datac
|
|
Info (332115): 5.880 0.130 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i768|combout
|
|
Info (332115): 5.882 0.002 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i768~la_mlab/laboutt[14]
|
|
Info (332115): 6.981 1.099 FF IC High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst|avmmaddress[6]
|
|
Info (332115): 6.981 0.000 FF CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 6.003 6.003 R clock network delay
|
|
Info (332115): 5.519 -0.484 clock pessimism removed
|
|
Info (332115): 5.559 0.040 clock uncertainty
|
|
Info (332115): 5.986 0.427 uTh fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Arrival Time : 6.981
|
|
Info (332115): Data Required Time : 5.986
|
|
Info (332115): Slack : 0.995
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 1.061
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|avmmclk}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 1.061
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|reconfig_address[8]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Launch Clock : SYS_RefClk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|avmmclk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 4.270 4.270 R clock network delay
|
|
Info (332115): 4.270 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|reconfig_address[8]
|
|
Info (332115): 4.457 0.187 FF uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|reconfig_address[8]|q
|
|
Info (332115): 4.554 0.097 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|reconfig_address[8]~la_mlab/laboutt[19]
|
|
Info (332115): 6.289 1.735 FF IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst|avmmaddress[8]
|
|
Info (332115): 6.289 0.000 FF CELL fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 5.040 5.040 R clock network delay
|
|
Info (332115): 4.804 -0.236 clock pessimism removed
|
|
Info (332115): 4.834 0.030 clock uncertainty
|
|
Info (332115): 5.228 0.394 uTh fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Arrival Time : 6.289
|
|
Info (332115): Data Required Time : 5.228
|
|
Info (332115): Slack : 1.061
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 1.174
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|avmmclk}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 1.174
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_writedata[3]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Launch Clock : PCIE_REFCLK
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|avmmclk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 5.068 5.068 R clock network delay
|
|
Info (332115): 5.068 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_writedata[3]
|
|
Info (332115): 5.250 0.182 FF uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_writedata[3]|q
|
|
Info (332115): 5.307 0.057 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_writedata[3]~la_lab/laboutt[17]
|
|
Info (332115): 6.042 0.735 FF IC Mixed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i1024~3|dataf
|
|
Info (332115): 6.073 0.031 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i1024~3|combout
|
|
Info (332115): 6.075 0.002 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i1024~3~la_mlab/laboutb[19]
|
|
Info (332115): 7.118 1.043 FF IC High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst|avmmwritedata[3]
|
|
Info (332115): 7.118 0.000 FF CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 5.939 5.939 R clock network delay
|
|
Info (332115): 5.455 -0.484 clock pessimism removed
|
|
Info (332115): 5.495 0.040 clock uncertainty
|
|
Info (332115): 5.944 0.449 uTh fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Arrival Time : 7.118
|
|
Info (332115): Data Required Time : 5.944
|
|
Info (332115): Slack : 1.174
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 1.257
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|avmmclk}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 1.257
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|channel_count[2]~RTM_1
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Launch Clock : PCIE_REFCLK
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|avmmclk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 5.057 5.057 R clock network delay
|
|
Info (332115): 5.057 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|channel_count[2]~RTM_1
|
|
Info (332115): 5.233 0.176 FF uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|channel_count[2]~RTM_1|q
|
|
Info (332115): 5.290 0.057 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|channel_count[2]~RTM_1~la_lab/laboutb[14]
|
|
Info (332115): 5.817 0.527 FF IC Mixed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i1188~0|dataf
|
|
Info (332115): 5.847 0.030 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i1188~0|combout
|
|
Info (332115): 5.849 0.002 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i1188~0~la_mlab/laboutt[14]
|
|
Info (332115): 7.000 1.151 FF IC Mixed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst|avmmwrite
|
|
Info (332115): 7.000 0.000 FF CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 5.919 5.919 R clock network delay
|
|
Info (332115): 5.435 -0.484 clock pessimism removed
|
|
Info (332115): 5.475 0.040 clock uncertainty
|
|
Info (332115): 5.743 0.268 uTh fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Arrival Time : 7.000
|
|
Info (332115): Data Required Time : 5.743
|
|
Info (332115): Slack : 1.257
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 1.437
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|avmmclk}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 1.437
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_writedata[3]~DUPLICATE
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Launch Clock : PCIE_REFCLK
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|avmmclk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 5.068 5.068 R clock network delay
|
|
Info (332115): 5.068 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_writedata[3]~DUPLICATE
|
|
Info (332115): 5.248 0.180 FF uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_writedata[3]~DUPLICATE|q
|
|
Info (332115): 5.340 0.092 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_writedata[3]~DUPLICATE~la_lab/laboutt[16]
|
|
Info (332115): 5.578 0.238 FF IC High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i1732~3|datac
|
|
Info (332115): 5.685 0.107 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i1732~3|combout
|
|
Info (332115): 5.686 0.001 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i1732~3~la_lab/laboutt[2]
|
|
Info (332115): 7.411 1.725 FF IC Mixed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst|avmmwritedata[3]
|
|
Info (332115): 7.411 0.000 FF CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 5.969 5.969 R clock network delay
|
|
Info (332115): 5.485 -0.484 clock pessimism removed
|
|
Info (332115): 5.525 0.040 clock uncertainty
|
|
Info (332115): 5.974 0.449 uTh fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Arrival Time : 7.411
|
|
Info (332115): Data Required Time : 5.974
|
|
Info (332115): Slack : 1.437
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 1.552
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|avmmclk}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 1.552
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|reconfig_writedata[6]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Launch Clock : SYS_RefClk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|avmmclk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 4.270 4.270 R clock network delay
|
|
Info (332115): 4.270 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|reconfig_writedata[6]
|
|
Info (332115): 4.451 0.181 FF uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|reconfig_writedata[6]|q
|
|
Info (332115): 4.511 0.060 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|reconfig_writedata[6]~la_mlab/laboutb[9]
|
|
Info (332115): 6.927 2.416 FF IC High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst|avmmwritedata[6]
|
|
Info (332115): 6.927 0.000 FF CELL fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 5.169 5.169 R clock network delay
|
|
Info (332115): 4.933 -0.236 clock pessimism removed
|
|
Info (332115): 4.963 0.030 clock uncertainty
|
|
Info (332115): 5.375 0.412 uTh fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Arrival Time : 6.927
|
|
Info (332115): Data Required Time : 5.375
|
|
Info (332115): Slack : 1.552
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 1.795
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|avmmclk}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 1.795
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_writedata[1]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Launch Clock : PCIE_REFCLK
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|avmmclk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 5.068 5.068 R clock network delay
|
|
Info (332115): 5.068 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_writedata[1]
|
|
Info (332115): 5.250 0.182 FF uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_writedata[1]|q
|
|
Info (332115): 5.346 0.096 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_writedata[1]~la_lab/laboutb[8]
|
|
Info (332115): 5.636 0.290 FF IC High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i1496~1|datae
|
|
Info (332115): 5.746 0.110 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i1496~1|combout
|
|
Info (332115): 5.747 0.001 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i1496~1~la_lab/laboutt[18]
|
|
Info (332115): 7.731 1.984 FF IC Mixed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst|avmmwritedata[1]
|
|
Info (332115): 7.731 0.000 FF CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 5.965 5.965 R clock network delay
|
|
Info (332115): 5.481 -0.484 clock pessimism removed
|
|
Info (332115): 5.521 0.040 clock uncertainty
|
|
Info (332115): 5.936 0.415 uTh fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Arrival Time : 7.731
|
|
Info (332115): Data Required Time : 5.936
|
|
Info (332115): Slack : 1.795
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 6.829
|
|
Info (20696): -to_clock [get_clocks {pr_clk_enable_dclk_reg2_user_clk}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 6.829
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_cb_host|alt_pr_cb_controller_v2|pr_request_reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_cb_host|alt_pr_cb_controller_v2|alt_pr_cb_interface|m_prblock~cs_css/pr_clk_core.reg
|
|
Info (332115): Launch Clock : u0|dcp_iopll|dcp_iopll|clk100
|
|
Info (332115): Latch Clock : pr_clk_enable_dclk_reg2_user_clk
|
|
Info (332115): Exception : dcp_bbs.sdc:3119: set_multicycle_path -hold -from [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_cb_host|alt_pr_cb_controller_v2|pr_request_reg}] -to [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_cb_host|alt_pr_cb_controller_v2|alt_pr_cb_interface|m_prblock~cs_css/pr_clk_core.reg}] 1
|
|
Info (332115): Multicycle - Setup Start : 2
|
|
Info (332115): Multicycle - Hold Start : 1
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 10.000 10.000 launch edge time
|
|
Info (332115): 18.187 8.187 R clock network delay
|
|
Info (332115): 18.187 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_cb_host|alt_pr_cb_controller_v2|pr_request_reg
|
|
Info (332115): 18.370 0.183 RR uTco fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_cb_host|alt_pr_cb_controller_v2|pr_request_reg|q
|
|
Info (332115): 18.492 0.122 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_cb_host|alt_pr_cb_controller_v2|pr_request_reg~la_lab/laboutt[0]
|
|
Info (332115): 22.731 4.239 RR IC High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_cb_host|alt_pr_cb_controller_v2|alt_pr_cb_interface|m_prblock|prrequest
|
|
Info (332115): 22.731 0.000 RR CELL fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_cb_host|alt_pr_cb_controller_v2|alt_pr_cb_interface|m_prblock~cs_css/pr_clk_core.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 5.000 5.000 latch edge time
|
|
Info (332115): 16.046 11.046 R clock network delay
|
|
Info (332115): 14.875 -1.171 clock pessimism removed
|
|
Info (332115): 15.045 0.170 clock uncertainty
|
|
Info (332115): 15.902 0.857 uTh fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_cb_host|alt_pr_cb_controller_v2|alt_pr_cb_interface|m_prblock~cs_css/pr_clk_core.reg
|
|
Info (332115): Data Arrival Time : 22.731
|
|
Info (332115): Data Required Time : 15.902
|
|
Info (332115): Slack : 6.829
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 0.254
|
|
Info (20696): -to_clock [get_clocks {mem|ddr4a|ddr4a_core_usr_clk}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 0.254
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_green_bs|ddr4a_reset_sync|resync_chains[0].synchronizer_nocut|dreg[0]
|
|
Info (332115): To Node : fpga_top|inst_green_bs|ddr4a_avmm_bridge|ddr_avmm_bridge|rsp_readdata[69]
|
|
Info (332115): Launch Clock : mem|ddr4a|ddr4a_core_usr_clk
|
|
Info (332115): Latch Clock : mem|ddr4a|ddr4a_core_usr_clk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.117 0.117 launch edge time
|
|
Info (332115): 3.602 3.485 R clock network delay
|
|
Info (332115): 3.602 0.000 fpga_top|inst_green_bs|ddr4a_reset_sync|resync_chains[0].synchronizer_nocut|dreg[0]
|
|
Info (332115): 3.887 0.285 RR uTco fpga_top|inst_green_bs|ddr4a_reset_sync|resync_chains[0].synchronizer_nocut|dreg[0]|q
|
|
Info (332115): 4.019 0.132 RR CELL High Speed fpga_top|inst_green_bs|ddr4a_reset_sync|resync_chains[0].synchronizer_nocut|dreg[0]~la_lab/laboutb[6]
|
|
Info (332115): 6.837 2.818 RR IC High Speed fpga_top|inst_green_bs|ddr4a_avmm_bridge|ddr_avmm_bridge|rsp_readdata[69]|clrn
|
|
Info (332115): 6.837 0.000 RR CELL High Speed fpga_top|inst_green_bs|ddr4a_avmm_bridge|ddr_avmm_bridge|rsp_readdata[69]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 3.869 3.869 latch edge time
|
|
Info (332115): 6.539 2.670 R clock network delay
|
|
Info (332115): 7.247 0.708 clock pessimism removed
|
|
Info (332115): 7.217 -0.030 clock uncertainty
|
|
Info (332115): 7.091 -0.126 uTsu fpga_top|inst_green_bs|ddr4a_avmm_bridge|ddr_avmm_bridge|rsp_readdata[69]
|
|
Info (332115): Data Arrival Time : 6.837
|
|
Info (332115): Data Required Time : 7.091
|
|
Info (332115): Slack : 0.254
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 0.554
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|wys~CORE_CLK_OUT}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 0.554
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_sriov_2.sriov2.sriov_bridge|rs_hip|npor_sync_pld_clk
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_sriov_2.sriov2.sriov_bridge|rs_hip|recovery_cnt[0]
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|wys~CORE_CLK_OUT
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|wys~CORE_CLK_OUT
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 9.284 9.284 R clock network delay
|
|
Info (332115): 9.284 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_sriov_2.sriov2.sriov_bridge|rs_hip|npor_sync_pld_clk
|
|
Info (332115): 9.538 0.254 RR uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_sriov_2.sriov2.sriov_bridge|rs_hip|npor_sync_pld_clk|q
|
|
Info (332115): 9.742 0.204 RR CELL Low Power fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_sriov_2.sriov2.sriov_bridge|rs_hip|npor_sync_pld_clk~la_lab/laboutb[8]
|
|
Info (332115): 12.454 2.712 RR IC Mixed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_sriov_2.sriov2.sriov_bridge|rs_hip|recovery_cnt[0]|clrn
|
|
Info (332115): 12.454 0.000 RR CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_sriov_2.sriov2.sriov_bridge|rs_hip|recovery_cnt[0]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 4.000 4.000 latch edge time
|
|
Info (332115): 11.877 7.877 R clock network delay
|
|
Info (332115): 13.138 1.261 clock pessimism removed
|
|
Info (332115): 13.008 -0.130 uTsu fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_sriov_2.sriov2.sriov_bridge|rs_hip|recovery_cnt[0]
|
|
Info (332115): Data Arrival Time : 12.454
|
|
Info (332115): Data Required Time : 13.008
|
|
Info (332115): Slack : 0.554
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 0.855
|
|
Info (20696): -to_clock [get_clocks {u0|dcp_iopll|dcp_iopll|clk1x}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 0.855
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|c32ui_SystemReset_n
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|tcm_to_bmc_mm_bridge_s0_agent_rdata_fifo|infer_mem_rtl_0|auto_generated|ram_block1a7~reg0
|
|
Info (332115): Launch Clock : u0|dcp_iopll|dcp_iopll|clk1x
|
|
Info (332115): Latch Clock : u0|dcp_iopll|dcp_iopll|clk1x
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 9.550 9.550 R clock network delay
|
|
Info (332115): 9.550 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|c32ui_SystemReset_n
|
|
Info (332115): 9.766 0.216 RR uTco fpga_top|inst_fiu_top|inst_ccip_fabric_top|c32ui_SystemReset_n|q
|
|
Info (332115): 9.879 0.113 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|c32ui_SystemReset_n~la_lab/laboutb[18]
|
|
Info (332115): 11.601 1.722 RR IC Mixed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|tcm_master_reset~0|dataf
|
|
Info (332115): 11.658 0.057 RF CELL Low Power fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|tcm_master_reset~0|combout
|
|
Info (332115): 11.664 0.006 FF CELL Low Power fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|tcm_master_reset~0~la_mlab/laboutb[10]
|
|
Info (332115): 12.988 1.324 FF IC Mixed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|tcm_to_bmc_mm_bridge_s0_agent_rdata_fifo|infer_mem_rtl_0|auto_generated|ram_block1a7|clr0
|
|
Info (332115): 12.988 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|tcm_to_bmc_mm_bridge_s0_agent_rdata_fifo|infer_mem_rtl_0|auto_generated|ram_block1a7~reg0
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 5.000 5.000 latch edge time
|
|
Info (332115): 13.231 8.231 R clock network delay
|
|
Info (332115): 14.470 1.239 clock pessimism removed
|
|
Info (332115): 14.320 -0.150 clock uncertainty
|
|
Info (332115): 13.843 -0.477 uTsu fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|tcm_to_bmc_mm_bridge_s0_agent_rdata_fifo|infer_mem_rtl_0|auto_generated|ram_block1a7~reg0
|
|
Info (332115): Data Arrival Time : 12.988
|
|
Info (332115): Data Required Time : 13.843
|
|
Info (332115): Slack : 0.855
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 1.183
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk1}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 1.183
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[3].core|pipeline|execute|fpu_unit|fpu_fpga|fp_div|[3].reset_relay|reset_r[0]
|
|
Info (332115): To Node : fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[3].core|pipeline|execute|fpu_unit|fpu_fpga|fp_div|[3].fdiv|memoryC2_uid118_invTables_lutmem_dmem|auto_generated|altsyncram1|ram_block2a11~reg0
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk1
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk1
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 6.407 6.407 R clock network delay
|
|
Info (332115): 6.407 0.000 fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[3].core|pipeline|execute|fpu_unit|fpu_fpga|fp_div|[3].reset_relay|reset_r[0]
|
|
Info (332115): 6.631 0.224 FF uTco fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[3].core|pipeline|execute|fpu_unit|fpu_fpga|fp_div|[3].reset_relay|reset_r[0]|q
|
|
Info (332115): 6.769 0.138 FF CELL High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[3].core|pipeline|execute|fpu_unit|fpu_fpga|fp_div|[3].reset_relay|reset_r[0]~la_mlab/laboutb[15]
|
|
Info (332115): 9.030 2.261 FF IC High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[3].core|pipeline|execute|fpu_unit|fpu_fpga|fp_div|[3].fdiv|memoryC2_uid118_invTables_lutmem_dmem|auto_generated|altsyncram1|ram_block2a11|clr0
|
|
Info (332115): 9.030 0.000 FF CELL High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[3].core|pipeline|execute|fpu_unit|fpu_fpga|fp_div|[3].fdiv|memoryC2_uid118_invTables_lutmem_dmem|auto_generated|altsyncram1|ram_block2a11~reg0
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 4.545 4.545 latch edge time
|
|
Info (332115): 9.749 5.204 R clock network delay
|
|
Info (332115): 10.710 0.961 clock pessimism removed
|
|
Info (332115): 10.680 -0.030 clock uncertainty
|
|
Info (332115): 10.213 -0.467 uTsu fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[3].core|pipeline|execute|fpu_unit|fpu_fpga|fp_div|[3].fdiv|memoryC2_uid118_invTables_lutmem_dmem|auto_generated|altsyncram1|ram_block2a11~reg0
|
|
Info (332115): Data Arrival Time : 9.030
|
|
Info (332115): Data Required Time : 10.213
|
|
Info (332115): Slack : 1.183
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 1.215
|
|
Info (20696): -to_clock [get_clocks {u0|dcp_iopll|dcp_iopll|clk100}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 1.215
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|c32ui_SystemReset_n
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|ddr_backchannel|mm_clock_crossing_bridge_0|cmd_fifo|mem_rtl_0|auto_generated|ram_block1a26~reg1
|
|
Info (332115): Launch Clock : u0|dcp_iopll|dcp_iopll|clk1x
|
|
Info (332115): Latch Clock : u0|dcp_iopll|dcp_iopll|clk100
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 5.000 5.000 launch edge time
|
|
Info (332115): 14.550 9.550 R clock network delay
|
|
Info (332115): 14.550 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|c32ui_SystemReset_n
|
|
Info (332115): 14.766 0.216 RR uTco fpga_top|inst_fiu_top|inst_ccip_fabric_top|c32ui_SystemReset_n|q
|
|
Info (332115): 14.879 0.113 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|c32ui_SystemReset_n~la_lab/laboutb[18]
|
|
Info (332115): 16.601 1.722 RR IC Mixed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|tcm_master_reset~0|dataf
|
|
Info (332115): 16.658 0.057 RF CELL Low Power fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|tcm_master_reset~0|combout
|
|
Info (332115): 16.664 0.006 FF CELL Low Power fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|tcm_master_reset~0~la_mlab/laboutb[10]
|
|
Info (332115): 17.288 0.624 FF IC Mixed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|ddr_backchannel|mm_clock_crossing_bridge_0|cmd_fifo|mem_rtl_0|auto_generated|ram_block1a26|clr0
|
|
Info (332115): 17.288 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|ddr_backchannel|mm_clock_crossing_bridge_0|cmd_fifo|mem_rtl_0|auto_generated|ram_block1a26~reg1
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 10.000 10.000 latch edge time
|
|
Info (332115): 18.282 8.282 R clock network delay
|
|
Info (332115): 19.148 0.866 clock pessimism removed
|
|
Info (332115): 18.988 -0.160 clock uncertainty
|
|
Info (332115): 18.503 -0.485 uTsu fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|ddr_backchannel|mm_clock_crossing_bridge_0|cmd_fifo|mem_rtl_0|auto_generated|ram_block1a26~reg1
|
|
Info (332115): Data Arrival Time : 17.288
|
|
Info (332115): Data Required Time : 18.503
|
|
Info (332115): Slack : 1.215
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 1.954
|
|
Info (20696): -to_clock [get_clocks {SYS_RefClk}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 1.954
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_cb_host|alt_pr_cb_controller_v2|freeze_reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|pr_freeze_rsync
|
|
Info (332115): Launch Clock : u0|dcp_iopll|dcp_iopll|clk100
|
|
Info (332115): Latch Clock : SYS_RefClk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 9.509 9.509 R clock network delay
|
|
Info (332115): 9.509 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_cb_host|alt_pr_cb_controller_v2|freeze_reg
|
|
Info (332115): 9.731 0.222 FF uTco fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_cb_host|alt_pr_cb_controller_v2|freeze_reg|q
|
|
Info (332115): 9.852 0.121 FF CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_cb_host|alt_pr_cb_controller_v2|freeze_reg~la_lab/laboutt[8]
|
|
Info (332115): 12.117 2.265 FF IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|pr_freeze_rsync|clrn
|
|
Info (332115): 12.117 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|pr_freeze_rsync
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 10.000 10.000 latch edge time
|
|
Info (332115): 14.273 4.273 R clock network delay
|
|
Info (332115): 14.509 0.236 clock pessimism removed
|
|
Info (332115): 14.199 -0.310 clock uncertainty
|
|
Info (332115): 14.071 -0.128 uTsu fpga_top|inst_fiu_top|inst_hssi_ctrl|pr_freeze_rsync
|
|
Info (332115): Data Arrival Time : 12.117
|
|
Info (332115): Data Required Time : 14.071
|
|
Info (332115): Slack : 1.954
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 2.123
|
|
Info (20696): -to_clock [get_clocks {mem|ddr4a|ddr4a_core_cal_slave_clk}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 2.123
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : mem|ddr4b|ddr4b|arch|arch_inst|non_hps.core_clks_rsts_inst|per_if_cal_slave_reset_sync[9]
|
|
Info (332115): To Node : mem|ddr4b|ddr4b|arch|arch_inst|io_aux_inst|io_aux~soft_ram_reg
|
|
Info (332115): Launch Clock : mem|ddr4a|ddr4a_core_cal_slave_clk
|
|
Info (332115): Latch Clock : mem|ddr4a|ddr4a_core_cal_slave_clk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 6.972 6.972 R clock network delay
|
|
Info (332115): 6.972 0.000 mem|ddr4b|ddr4b|arch|arch_inst|non_hps.core_clks_rsts_inst|per_if_cal_slave_reset_sync[9]
|
|
Info (332115): 7.199 0.227 RR uTco mem|ddr4b|ddr4b|arch|arch_inst|non_hps.core_clks_rsts_inst|per_if_cal_slave_reset_sync[9]|q
|
|
Info (332115): 7.359 0.160 RR CELL High Speed mem|ddr4b|ddr4b|arch|arch_inst|non_hps.core_clks_rsts_inst|per_if_cal_slave_reset_sync[9]~la_mlab/laboutb[8]
|
|
Info (332115): 11.332 3.973 RR IC Mixed mem|ddr4b|ddr4b|arch|arch_inst|io_aux_inst|io_aux|soft_ram_reset_n
|
|
Info (332115): 11.332 0.000 RR CELL mem|ddr4b|ddr4b|arch|arch_inst|io_aux_inst|io_aux~soft_ram_reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 6.566 6.566 latch edge time
|
|
Info (332115): 12.710 6.144 R clock network delay
|
|
Info (332115): 13.570 0.860 clock pessimism removed
|
|
Info (332115): 13.520 -0.050 clock uncertainty
|
|
Info (332115): 13.455 -0.065 uTsu mem|ddr4b|ddr4b|arch|arch_inst|io_aux_inst|io_aux~soft_ram_reg
|
|
Info (332115): Data Arrival Time : 11.332
|
|
Info (332115): Data Required Time : 13.455
|
|
Info (332115): Slack : 2.123
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 2.130
|
|
Info (20696): -to_clock [get_clocks {filtered_sclk_negedge}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 2.130
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|SPISlaveToAvalonMasterBridge_reset_clk_domain_synch|data_out
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MOSIctl|stsourcedata[4]
|
|
Info (332115): Launch Clock : u0|dcp_iopll|dcp_iopll|clk1x
|
|
Info (332115): Latch Clock : filtered_sclk_negedge
|
|
Info (332115): Exception : dcp_bbs.sdc:3060: set_multicycle_path -setup -from [get_keepers {*SPISlaveToAvalonMasterBridge_reset_clk_domain_synch|data_out}] -to [get_keepers {*SPIPhy_MOSIctl|stsourcedata*}] 3
|
|
Info (332115): Multicycle - Setup Start : 3
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 235.000 235.000 launch edge time
|
|
Info (332115): 244.546 9.546 R clock network delay
|
|
Info (332115): 244.546 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|SPISlaveToAvalonMasterBridge_reset_clk_domain_synch|data_out
|
|
Info (332115): 244.790 0.244 RR uTco fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|SPISlaveToAvalonMasterBridge_reset_clk_domain_synch|data_out|q
|
|
Info (332115): 244.927 0.137 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|SPISlaveToAvalonMasterBridge_reset_clk_domain_synch|data_out~la_mlab/laboutt[1]
|
|
Info (332115): 247.671 2.744 RR IC Mixed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MOSIctl|stsourcedata[4]|clrn
|
|
Info (332115): 247.671 0.000 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MOSIctl|stsourcedata[4]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 250.000 250.000 latch edge time
|
|
Info (332115): 250.236 0.236 R clock network delay
|
|
Info (332115): 249.936 -0.300 clock uncertainty
|
|
Info (332115): 249.801 -0.135 uTsu fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MOSIctl|stsourcedata[4]
|
|
Info (332115): Data Arrival Time : 247.671
|
|
Info (332115): Data Required Time : 249.801
|
|
Info (332115): Slack : 2.130
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 2.565
|
|
Info (20696): -to_clock [get_clocks {u0|dcp_iopll|dcp_iopll|clk25}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 2.565
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|c32ui_SystemReset_n
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|tcm_flash_reset_sync_reg[3]
|
|
Info (332115): Launch Clock : u0|dcp_iopll|dcp_iopll|clk1x
|
|
Info (332115): Latch Clock : u0|dcp_iopll|dcp_iopll|clk25
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 35.000 35.000 launch edge time
|
|
Info (332115): 44.550 9.550 R clock network delay
|
|
Info (332115): 44.550 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|c32ui_SystemReset_n
|
|
Info (332115): 44.766 0.216 RR uTco fpga_top|inst_fiu_top|inst_ccip_fabric_top|c32ui_SystemReset_n|q
|
|
Info (332115): 44.879 0.113 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|c32ui_SystemReset_n~la_lab/laboutb[18]
|
|
Info (332115): 46.329 1.450 RR IC Mixed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|tcm_flash_reset_sync_reg[3]|clrn
|
|
Info (332115): 46.329 0.000 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|tcm_flash_reset_sync_reg[3]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 40.000 40.000 latch edge time
|
|
Info (332115): 48.338 8.338 R clock network delay
|
|
Info (332115): 49.204 0.866 clock pessimism removed
|
|
Info (332115): 49.024 -0.180 clock uncertainty
|
|
Info (332115): 48.894 -0.130 uTsu fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|tcm_flash_reset_sync_reg[3]
|
|
Info (332115): Data Arrival Time : 46.329
|
|
Info (332115): Data Required Time : 48.894
|
|
Info (332115): Slack : 2.565
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 2.859
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|rx_pma_clk}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 2.859
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_reset_sync|resync_chains[0].sync_r[2]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_consecutive_error[2]
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|rx_pma_clk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|rx_pma_clk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 7.035 7.035 R clock network delay
|
|
Info (332115): 7.035 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_reset_sync|resync_chains[0].sync_r[2]
|
|
Info (332115): 7.254 0.219 RR uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_reset_sync|resync_chains[0].sync_r[2]|q
|
|
Info (332115): 7.390 0.136 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_reset_sync|resync_chains[0].sync_r[2]~la_mlab/laboutb[5]
|
|
Info (332115): 7.850 0.460 RR IC High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_consecutive_error[2]|clrn
|
|
Info (332115): 7.850 0.000 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_consecutive_error[2]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 3.878 3.878 latch edge time
|
|
Info (332115): 8.925 5.047 R clock network delay
|
|
Info (332115): 10.869 1.944 clock pessimism removed
|
|
Info (332115): 10.839 -0.030 clock uncertainty
|
|
Info (332115): 10.709 -0.130 uTsu fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_consecutive_error[2]
|
|
Info (332115): Data Arrival Time : 7.850
|
|
Info (332115): Data Required Time : 10.709
|
|
Info (332115): Slack : 2.859
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 2.863
|
|
Info (20696): -to_clock [get_clocks {DDR4_RefClk}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 2.863
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|use_counter_lock.counter_lock_gen_master.pll_ref_clk_reset_n_sync_rrr
|
|
Info (332115): To Node : mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|use_counter_lock.counter_lock_gen_master.cpa_count_to_lock[7]
|
|
Info (332115): Launch Clock : DDR4_RefClk
|
|
Info (332115): Latch Clock : DDR4_RefClk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 4.350 4.350 R clock network delay
|
|
Info (332115): 4.350 0.000 mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|use_counter_lock.counter_lock_gen_master.pll_ref_clk_reset_n_sync_rrr
|
|
Info (332115): 4.579 0.229 RR uTco mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|use_counter_lock.counter_lock_gen_master.pll_ref_clk_reset_n_sync_rrr|q
|
|
Info (332115): 4.739 0.160 RR CELL High Speed mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|use_counter_lock.counter_lock_gen_master.pll_ref_clk_reset_n_sync_rrr~la_mlab/laboutb[4]
|
|
Info (332115): 5.025 0.286 RR IC High Speed mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|use_counter_lock.counter_lock_gen_master.cpa_count_to_lock[7]|clrn
|
|
Info (332115): 5.025 0.000 RR CELL High Speed mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|use_counter_lock.counter_lock_gen_master.cpa_count_to_lock[7]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 3.752 3.752 latch edge time
|
|
Info (332115): 7.774 4.022 R clock network delay
|
|
Info (332115): 8.076 0.302 clock pessimism removed
|
|
Info (332115): 8.046 -0.030 clock uncertainty
|
|
Info (332115): 7.888 -0.158 uTsu mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|use_counter_lock.counter_lock_gen_master.cpa_count_to_lock[7]
|
|
Info (332115): Data Arrival Time : 5.025
|
|
Info (332115): Data Required Time : 7.888
|
|
Info (332115): Slack : 2.863
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 2.940
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_clk}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 2.940
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_reset_sync|resync_chains[0].sync_r[2]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_consecutive_error[0]
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_clk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_clk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 7.035 7.035 R clock network delay
|
|
Info (332115): 7.035 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_reset_sync|resync_chains[0].sync_r[2]
|
|
Info (332115): 7.254 0.219 RR uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_reset_sync|resync_chains[0].sync_r[2]|q
|
|
Info (332115): 7.367 0.113 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_reset_sync|resync_chains[0].sync_r[2]~la_lab/laboutb[18]
|
|
Info (332115): 7.765 0.398 RR IC High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_consecutive_error[0]|clrn
|
|
Info (332115): 7.765 0.000 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_consecutive_error[0]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 3.878 3.878 latch edge time
|
|
Info (332115): 8.929 5.051 R clock network delay
|
|
Info (332115): 10.865 1.936 clock pessimism removed
|
|
Info (332115): 10.835 -0.030 clock uncertainty
|
|
Info (332115): 10.705 -0.130 uTsu fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_consecutive_error[0]
|
|
Info (332115): Data Arrival Time : 7.765
|
|
Info (332115): Data Required Time : 10.705
|
|
Info (332115): Slack : 2.940
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 2.948
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|rx_pma_clk}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 2.948
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_reset_sync|resync_chains[0].sync_r[2]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_bit_count[6]
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|rx_pma_clk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|rx_pma_clk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 6.928 6.928 R clock network delay
|
|
Info (332115): 6.928 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_reset_sync|resync_chains[0].sync_r[2]
|
|
Info (332115): 7.146 0.218 RR uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_reset_sync|resync_chains[0].sync_r[2]|q
|
|
Info (332115): 7.258 0.112 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_reset_sync|resync_chains[0].sync_r[2]~la_mlab/laboutb[2]
|
|
Info (332115): 7.650 0.392 RR IC High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_bit_count[6]|clrn
|
|
Info (332115): 7.650 0.000 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_bit_count[6]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 3.878 3.878 latch edge time
|
|
Info (332115): 8.811 4.933 R clock network delay
|
|
Info (332115): 10.757 1.946 clock pessimism removed
|
|
Info (332115): 10.727 -0.030 clock uncertainty
|
|
Info (332115): 10.598 -0.129 uTsu fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_bit_count[6]
|
|
Info (332115): Data Arrival Time : 7.650
|
|
Info (332115): Data Required Time : 10.598
|
|
Info (332115): Slack : 2.948
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 3.036
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|rx_pma_clk}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 3.036
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_reset_sync|resync_chains[0].sync_r[2]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_count[2]
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|rx_pma_clk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|rx_pma_clk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 6.998 6.998 R clock network delay
|
|
Info (332115): 6.998 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_reset_sync|resync_chains[0].sync_r[2]
|
|
Info (332115): 7.218 0.220 RR uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_reset_sync|resync_chains[0].sync_r[2]|q
|
|
Info (332115): 7.331 0.113 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_reset_sync|resync_chains[0].sync_r[2]~la_lab/laboutb[18]
|
|
Info (332115): 7.668 0.337 RR IC High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_count[2]|clrn
|
|
Info (332115): 7.668 0.000 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_count[2]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 3.878 3.878 latch edge time
|
|
Info (332115): 8.895 5.017 R clock network delay
|
|
Info (332115): 10.857 1.962 clock pessimism removed
|
|
Info (332115): 10.827 -0.030 clock uncertainty
|
|
Info (332115): 10.704 -0.123 uTsu fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_count[2]
|
|
Info (332115): Data Arrival Time : 7.668
|
|
Info (332115): Data Required Time : 10.704
|
|
Info (332115): Slack : 3.036
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 4.660
|
|
Info (20696): -to_clock [get_clocks {fspi_sclk}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 4.660
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|SPISlaveToAvalonMasterBridge_reset_clk_domain_synch|data_out
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MISOctl|rdshiftreg[5]
|
|
Info (332115): Launch Clock : u0|dcp_iopll|dcp_iopll|clk1x
|
|
Info (332115): Latch Clock : fspi_sclk
|
|
Info (332115): Exception : dcp_bbs.sdc:3056: set_multicycle_path -setup -from [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|SPISlaveToAvalonMasterBridge_reset_clk_domain_synch|data_out}] -to [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MISOctl|*}] 2
|
|
Info (332115): Multicycle - Setup Start : 2
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 240.000 240.000 launch edge time
|
|
Info (332115): 249.546 9.546 R clock network delay
|
|
Info (332115): 249.546 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|SPISlaveToAvalonMasterBridge_reset_clk_domain_synch|data_out
|
|
Info (332115): 249.790 0.244 RR uTco fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|SPISlaveToAvalonMasterBridge_reset_clk_domain_synch|data_out|q
|
|
Info (332115): 249.927 0.137 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|SPISlaveToAvalonMasterBridge_reset_clk_domain_synch|data_out~la_mlab/laboutt[1]
|
|
Info (332115): 250.369 0.442 RR IC High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MOSIctl|i5|dataf
|
|
Info (332115): 250.418 0.049 RF CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MOSIctl|i5|combout
|
|
Info (332115): 250.424 0.006 FF CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MOSIctl|i5~la_mlab/laboutt[18]
|
|
Info (332115): 250.583 0.159 FF IC High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MISOctl|rdshiftreg[5]|clrn
|
|
Info (332115): 250.583 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MISOctl|rdshiftreg[5]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 250.000 250.000 latch edge time
|
|
Info (332115): 255.722 5.722 R clock network delay
|
|
Info (332115): 255.412 -0.310 clock uncertainty
|
|
Info (332115): 255.243 -0.169 uTsu fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MISOctl|rdshiftreg[5]
|
|
Info (332115): Data Arrival Time : 250.583
|
|
Info (332115): Data Required Time : 255.243
|
|
Info (332115): Slack : 4.660
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 4.939
|
|
Info (20696): -to_clock [get_clocks {PCIE_REFCLK}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 4.939
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|reset_pulse_inst|resync_chains[0].sync_r[2]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|cpu_memory[71][31]
|
|
Info (332115): Launch Clock : PCIE_REFCLK
|
|
Info (332115): Latch Clock : PCIE_REFCLK
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 5.649 5.649 R clock network delay
|
|
Info (332115): 5.649 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|reset_pulse_inst|resync_chains[0].sync_r[2]
|
|
Info (332115): 5.903 0.254 RR uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|reset_pulse_inst|resync_chains[0].sync_r[2]|q
|
|
Info (332115): 6.038 0.135 RR CELL Low Power fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|reset_pulse_inst|resync_chains[0].sync_r[2]~la_mlab/laboutb[13]
|
|
Info (332115): 10.381 4.343 RR IC Mixed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|cpu_memory[71][31]|clrn
|
|
Info (332115): 10.381 0.000 RR CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|cpu_memory[71][31]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 10.000 10.000 latch edge time
|
|
Info (332115): 15.114 5.114 R clock network delay
|
|
Info (332115): 15.520 0.406 clock pessimism removed
|
|
Info (332115): 15.480 -0.040 clock uncertainty
|
|
Info (332115): 15.320 -0.160 uTsu fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|cpu_memory[71][31]
|
|
Info (332115): Data Arrival Time : 10.381
|
|
Info (332115): Data Required Time : 15.320
|
|
Info (332115): Slack : 4.939
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 14.727
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|rx_fref}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 14.727
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|rx_fref
|
|
Info (332115): Exception : dcp_bbs.sdc:3148: set_max_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pma_rxpma_rstb}] 20.000
|
|
Info (332115): Max Delay Exception : 20.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 3.752 3.752 R clock network delay
|
|
Info (332115): 3.752 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): 6.473 2.721 RR uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|rx_pma_rstb7
|
|
Info (332115): 6.473 0.000 RR IC fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_pma_rxpma_rstb
|
|
Info (332115): 6.473 0.000 RR CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 20.000 20.000 latch edge time
|
|
Info (332115): 21.793 1.793 R clock network delay
|
|
Info (332115): 21.673 -0.120 clock uncertainty
|
|
Info (332115): 21.200 -0.473 uTsu fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Data Arrival Time : 6.473
|
|
Info (332115): Data Required Time : 21.200
|
|
Info (332115): Slack : 14.727
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 15.188
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|rx_fref}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 15.188
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|rx_fref
|
|
Info (332115): Exception : dcp_bbs.sdc:3148: set_max_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pma_rxpma_rstb}] 20.000
|
|
Info (332115): Max Delay Exception : 20.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 3.752 3.752 R clock network delay
|
|
Info (332115): 3.752 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): 6.012 2.260 RR uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|rx_pma_rstb6
|
|
Info (332115): 6.012 0.000 RR IC fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_pma_rxpma_rstb
|
|
Info (332115): 6.012 0.000 RR CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 20.000 20.000 latch edge time
|
|
Info (332115): 21.793 1.793 R clock network delay
|
|
Info (332115): 21.673 -0.120 clock uncertainty
|
|
Info (332115): 21.200 -0.473 uTsu fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Data Arrival Time : 6.012
|
|
Info (332115): Data Required Time : 21.200
|
|
Info (332115): Slack : 15.188
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 15.297
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|rx_fref}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 15.297
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|rx_fref
|
|
Info (332115): Exception : dcp_bbs.sdc:3148: set_max_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pma_rxpma_rstb}] 20.000
|
|
Info (332115): Max Delay Exception : 20.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 3.752 3.752 R clock network delay
|
|
Info (332115): 3.752 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): 5.903 2.151 RR uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|rx_pma_rstb5
|
|
Info (332115): 5.903 0.000 RR IC fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_pma_rxpma_rstb
|
|
Info (332115): 5.903 0.000 RR CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 20.000 20.000 latch edge time
|
|
Info (332115): 21.793 1.793 R clock network delay
|
|
Info (332115): 21.673 -0.120 clock uncertainty
|
|
Info (332115): 21.200 -0.473 uTsu fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Data Arrival Time : 5.903
|
|
Info (332115): Data Required Time : 21.200
|
|
Info (332115): Slack : 15.297
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 15.322
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|rx_fref}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 15.322
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|rx_fref
|
|
Info (332115): Exception : dcp_bbs.sdc:3148: set_max_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pma_rxpma_rstb}] 20.000
|
|
Info (332115): Max Delay Exception : 20.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 3.752 3.752 R clock network delay
|
|
Info (332115): 3.752 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): 5.765 2.013 RR uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|rx_pma_rstb1
|
|
Info (332115): 5.765 0.000 RR IC fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_pma_rxpma_rstb
|
|
Info (332115): 5.765 0.000 RR CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 20.000 20.000 latch edge time
|
|
Info (332115): 21.680 1.680 R clock network delay
|
|
Info (332115): 21.560 -0.120 clock uncertainty
|
|
Info (332115): 21.087 -0.473 uTsu fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Data Arrival Time : 5.765
|
|
Info (332115): Data Required Time : 21.087
|
|
Info (332115): Slack : 15.322
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 15.355
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|rx_fref}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 15.355
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|rx_fref
|
|
Info (332115): Exception : dcp_bbs.sdc:3148: set_max_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pma_rxpma_rstb}] 20.000
|
|
Info (332115): Max Delay Exception : 20.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 3.752 3.752 R clock network delay
|
|
Info (332115): 3.752 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): 5.785 2.033 RR uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|rx_pma_rstb4
|
|
Info (332115): 5.786 0.001 RR IC fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_pma_rxpma_rstb
|
|
Info (332115): 5.786 0.000 RR CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 20.000 20.000 latch edge time
|
|
Info (332115): 21.734 1.734 R clock network delay
|
|
Info (332115): 21.614 -0.120 clock uncertainty
|
|
Info (332115): 21.141 -0.473 uTsu fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Data Arrival Time : 5.786
|
|
Info (332115): Data Required Time : 21.141
|
|
Info (332115): Slack : 15.355
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 15.588
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|rx_fref}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 15.588
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|rx_fref
|
|
Info (332115): Exception : dcp_bbs.sdc:3148: set_max_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pma_rxpma_rstb}] 20.000
|
|
Info (332115): Max Delay Exception : 20.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 3.752 3.752 R clock network delay
|
|
Info (332115): 3.752 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): 5.553 1.801 RR uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|rx_pma_rstb2
|
|
Info (332115): 5.553 0.000 RR IC fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_pma_rxpma_rstb
|
|
Info (332115): 5.553 0.000 RR CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 20.000 20.000 latch edge time
|
|
Info (332115): 21.734 1.734 R clock network delay
|
|
Info (332115): 21.614 -0.120 clock uncertainty
|
|
Info (332115): 21.141 -0.473 uTsu fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Data Arrival Time : 5.553
|
|
Info (332115): Data Required Time : 21.141
|
|
Info (332115): Slack : 15.588
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 15.607
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|rx_fref}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 15.607
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|rx_fref
|
|
Info (332115): Exception : dcp_bbs.sdc:3148: set_max_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pma_rxpma_rstb}] 20.000
|
|
Info (332115): Max Delay Exception : 20.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 3.752 3.752 R clock network delay
|
|
Info (332115): 3.752 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): 5.534 1.782 RR uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|rx_pma_rstb3
|
|
Info (332115): 5.534 0.000 RR IC fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_pma_rxpma_rstb
|
|
Info (332115): 5.534 0.000 RR CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 20.000 20.000 latch edge time
|
|
Info (332115): 21.734 1.734 R clock network delay
|
|
Info (332115): 21.614 -0.120 clock uncertainty
|
|
Info (332115): 21.141 -0.473 uTsu fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Data Arrival Time : 5.534
|
|
Info (332115): Data Required Time : 21.141
|
|
Info (332115): Slack : 15.607
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 16.480
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|rx_pma_clk}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 16.480
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|rx_pma_clk
|
|
Info (332115): Exception : dcp_bbs.sdc:3148: set_max_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pma_rxpma_rstb}] 20.000
|
|
Info (332115): Max Delay Exception : 20.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 3.752 3.752 R clock network delay
|
|
Info (332115): 3.752 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): 6.476 2.724 FF uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|rx_pma_rstb7
|
|
Info (332115): 6.476 0.000 FF IC fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_pma_rxpma_rstb
|
|
Info (332115): 6.476 0.000 FF CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 20.000 20.000 latch edge time
|
|
Info (332115): 23.076 3.076 R clock network delay
|
|
Info (332115): 22.956 -0.120 clock uncertainty
|
|
Info (332115): 22.956 0.000 uTsu fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Data Arrival Time : 6.476
|
|
Info (332115): Data Required Time : 22.956
|
|
Info (332115): Slack : 16.480
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 16.805
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 16.805
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332115): Exception : dcp_bbs.sdc:3148: set_max_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pma_rxpma_rstb}] 20.000
|
|
Info (332115): Max Delay Exception : 20.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 3.752 3.752 R clock network delay
|
|
Info (332115): 3.752 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): 6.085 2.333 RR uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|rx_pma_rstb0
|
|
Info (332115): 6.086 0.001 RR IC fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_pma_rxpma_rstb
|
|
Info (332115): 6.086 0.000 RR CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 20.000 20.000 latch edge time
|
|
Info (332115): 21.680 1.680 R clock network delay
|
|
Info (332115): 23.394 1.714 clock pessimism removed
|
|
Info (332115): 23.364 -0.030 clock uncertainty
|
|
Info (332115): 22.891 -0.473 uTsu fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Data Arrival Time : 6.086
|
|
Info (332115): Data Required Time : 22.891
|
|
Info (332115): Slack : 16.805
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 16.944
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|rx_pma_clk}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 16.944
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|rx_pma_clk
|
|
Info (332115): Exception : dcp_bbs.sdc:3148: set_max_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pma_rxpma_rstb}] 20.000
|
|
Info (332115): Max Delay Exception : 20.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 3.752 3.752 R clock network delay
|
|
Info (332115): 3.752 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): 6.012 2.260 RR uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|rx_pma_rstb6
|
|
Info (332115): 6.012 0.000 RR IC fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_pma_rxpma_rstb
|
|
Info (332115): 6.012 0.000 RR CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 20.000 20.000 latch edge time
|
|
Info (332115): 23.076 3.076 R clock network delay
|
|
Info (332115): 22.956 -0.120 clock uncertainty
|
|
Info (332115): 22.956 0.000 uTsu fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Data Arrival Time : 6.012
|
|
Info (332115): Data Required Time : 22.956
|
|
Info (332115): Slack : 16.944
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 17.053
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|rx_pma_clk}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 17.053
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|rx_pma_clk
|
|
Info (332115): Exception : dcp_bbs.sdc:3148: set_max_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pma_rxpma_rstb}] 20.000
|
|
Info (332115): Max Delay Exception : 20.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 3.752 3.752 R clock network delay
|
|
Info (332115): 3.752 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): 5.903 2.151 RR uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|rx_pma_rstb5
|
|
Info (332115): 5.903 0.000 RR IC fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_pma_rxpma_rstb
|
|
Info (332115): 5.903 0.000 RR CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 20.000 20.000 latch edge time
|
|
Info (332115): 23.076 3.076 R clock network delay
|
|
Info (332115): 22.956 -0.120 clock uncertainty
|
|
Info (332115): 22.956 0.000 uTsu fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Data Arrival Time : 5.903
|
|
Info (332115): Data Required Time : 22.956
|
|
Info (332115): Slack : 17.053
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 17.078
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|rx_pma_clk}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 17.078
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|rx_pma_clk
|
|
Info (332115): Exception : dcp_bbs.sdc:3148: set_max_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pma_rxpma_rstb}] 20.000
|
|
Info (332115): Max Delay Exception : 20.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 3.752 3.752 R clock network delay
|
|
Info (332115): 3.752 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): 5.765 2.013 RR uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|rx_pma_rstb1
|
|
Info (332115): 5.765 0.000 RR IC fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_pma_rxpma_rstb
|
|
Info (332115): 5.765 0.000 RR CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 20.000 20.000 latch edge time
|
|
Info (332115): 22.963 2.963 R clock network delay
|
|
Info (332115): 22.843 -0.120 clock uncertainty
|
|
Info (332115): 22.843 0.000 uTsu fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Data Arrival Time : 5.765
|
|
Info (332115): Data Required Time : 22.843
|
|
Info (332115): Slack : 17.078
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 17.082
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_pma_clk}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 17.082
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_pma_clk
|
|
Info (332115): Exception : dcp_bbs.sdc:3148: set_max_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pma_rxpma_rstb}] 20.000
|
|
Info (332115): Max Delay Exception : 20.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 3.752 3.752 R clock network delay
|
|
Info (332115): 3.752 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): 6.085 2.333 RR uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|rx_pma_rstb0
|
|
Info (332115): 6.086 0.001 RR IC fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_pma_rxpma_rstb
|
|
Info (332115): 6.086 0.000 RR CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 20.000 20.000 latch edge time
|
|
Info (332115): 22.963 2.963 R clock network delay
|
|
Info (332115): 23.188 0.225 clock pessimism removed
|
|
Info (332115): 23.168 -0.020 clock uncertainty
|
|
Info (332115): 23.168 0.000 uTsu fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Data Arrival Time : 6.086
|
|
Info (332115): Data Required Time : 23.168
|
|
Info (332115): Slack : 17.082
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 17.111
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|rx_pma_clk}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 17.111
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|rx_pma_clk
|
|
Info (332115): Exception : dcp_bbs.sdc:3148: set_max_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pma_rxpma_rstb}] 20.000
|
|
Info (332115): Max Delay Exception : 20.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 3.752 3.752 R clock network delay
|
|
Info (332115): 3.752 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): 5.785 2.033 RR uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|rx_pma_rstb4
|
|
Info (332115): 5.786 0.001 RR IC fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_pma_rxpma_rstb
|
|
Info (332115): 5.786 0.000 RR CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 20.000 20.000 latch edge time
|
|
Info (332115): 23.017 3.017 R clock network delay
|
|
Info (332115): 22.897 -0.120 clock uncertainty
|
|
Info (332115): 22.897 0.000 uTsu fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Data Arrival Time : 5.786
|
|
Info (332115): Data Required Time : 22.897
|
|
Info (332115): Slack : 17.111
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 17.344
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|rx_pma_clk}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 17.344
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|rx_pma_clk
|
|
Info (332115): Exception : dcp_bbs.sdc:3148: set_max_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pma_rxpma_rstb}] 20.000
|
|
Info (332115): Max Delay Exception : 20.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 3.752 3.752 R clock network delay
|
|
Info (332115): 3.752 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): 5.553 1.801 RR uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|rx_pma_rstb2
|
|
Info (332115): 5.553 0.000 RR IC fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_pma_rxpma_rstb
|
|
Info (332115): 5.553 0.000 RR CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 20.000 20.000 latch edge time
|
|
Info (332115): 23.017 3.017 R clock network delay
|
|
Info (332115): 22.897 -0.120 clock uncertainty
|
|
Info (332115): 22.897 0.000 uTsu fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Data Arrival Time : 5.553
|
|
Info (332115): Data Required Time : 22.897
|
|
Info (332115): Slack : 17.344
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 17.363
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|rx_pma_clk}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 17.363
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|rx_pma_clk
|
|
Info (332115): Exception : dcp_bbs.sdc:3148: set_max_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pma_rxpma_rstb}] 20.000
|
|
Info (332115): Max Delay Exception : 20.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 3.752 3.752 R clock network delay
|
|
Info (332115): 3.752 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): 5.534 1.782 RR uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|rx_pma_rstb3
|
|
Info (332115): 5.534 0.000 RR IC fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_pma_rxpma_rstb
|
|
Info (332115): 5.534 0.000 RR CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 20.000 20.000 latch edge time
|
|
Info (332115): 23.017 3.017 R clock network delay
|
|
Info (332115): 22.897 -0.120 clock uncertainty
|
|
Info (332115): 22.897 0.000 uTsu fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Data Arrival Time : 5.534
|
|
Info (332115): Data Required Time : 22.897
|
|
Info (332115): Slack : 17.363
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 39.729
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|tx_pma_clk}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 39.729
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi_txdig_ena
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_tx_pld_pcs_interface.inst_twentynm_hssi_tx_pld_pcs_interface~pld_pmaif_tx_pld_rst_n_reg.reg
|
|
Info (332115): Launch Clock : SYS_RefClk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|tx_pma_clk
|
|
Info (332115): Exception : dcp_bbs.sdc:3144: set_max_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pmaif_tx_pld_rst_n}] 50.000
|
|
Info (332115): Max Delay Exception : 50.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 4.719 4.719 R clock network delay
|
|
Info (332115): 4.719 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi_txdig_ena
|
|
Info (332115): 5.004 0.285 RR uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi_txdig_ena|q
|
|
Info (332115): 5.119 0.115 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi_txdig_ena~la_mlab/laboutb[17]
|
|
Info (332115): 8.082 2.963 RR IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0|datac
|
|
Info (332115): 8.285 0.203 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0|combout
|
|
Info (332115): 8.291 0.006 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0~la_mlab/laboutb[18]
|
|
Info (332115): 12.156 3.865 RR IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_tx_pld_pcs_interface.inst_twentynm_hssi_tx_pld_pcs_interface|pld_pmaif_tx_pld_rst_n
|
|
Info (332115): 12.156 0.000 RR CELL fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_tx_pld_pcs_interface.inst_twentynm_hssi_tx_pld_pcs_interface~pld_pmaif_tx_pld_rst_n_reg.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 50.000 50.000 latch edge time
|
|
Info (332115): 52.257 2.257 R clock network delay
|
|
Info (332115): 52.187 -0.070 clock uncertainty
|
|
Info (332115): 51.885 -0.302 uTsu fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_tx_pld_pcs_interface.inst_twentynm_hssi_tx_pld_pcs_interface~pld_pmaif_tx_pld_rst_n_reg.reg
|
|
Info (332115): Data Arrival Time : 12.156
|
|
Info (332115): Data Required Time : 51.885
|
|
Info (332115): Slack : 39.729
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 39.994
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|tx_pma_clk}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 39.994
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi_txdig_ena
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_tx_pld_pcs_interface.inst_twentynm_hssi_tx_pld_pcs_interface~pld_pmaif_tx_pld_rst_n_reg.reg
|
|
Info (332115): Launch Clock : SYS_RefClk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|tx_pma_clk
|
|
Info (332115): Exception : dcp_bbs.sdc:3144: set_max_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pmaif_tx_pld_rst_n}] 50.000
|
|
Info (332115): Max Delay Exception : 50.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 4.719 4.719 R clock network delay
|
|
Info (332115): 4.719 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi_txdig_ena
|
|
Info (332115): 5.004 0.285 RR uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi_txdig_ena|q
|
|
Info (332115): 5.119 0.115 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi_txdig_ena~la_mlab/laboutb[17]
|
|
Info (332115): 7.827 2.708 RR IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0|datac
|
|
Info (332115): 8.011 0.184 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0|combout
|
|
Info (332115): 8.015 0.004 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0~la_lab/laboutt[8]
|
|
Info (332115): 11.891 3.876 RR IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_tx_pld_pcs_interface.inst_twentynm_hssi_tx_pld_pcs_interface|pld_pmaif_tx_pld_rst_n
|
|
Info (332115): 11.891 0.000 RR CELL fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_tx_pld_pcs_interface.inst_twentynm_hssi_tx_pld_pcs_interface~pld_pmaif_tx_pld_rst_n_reg.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 50.000 50.000 latch edge time
|
|
Info (332115): 52.257 2.257 R clock network delay
|
|
Info (332115): 52.187 -0.070 clock uncertainty
|
|
Info (332115): 51.885 -0.302 uTsu fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_tx_pld_pcs_interface.inst_twentynm_hssi_tx_pld_pcs_interface~pld_pmaif_tx_pld_rst_n_reg.reg
|
|
Info (332115): Data Arrival Time : 11.891
|
|
Info (332115): Data Required Time : 51.885
|
|
Info (332115): Slack : 39.994
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 40.022
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|tx_pma_clk}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 40.022
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi_txdig_ena
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs~pld_8g_g3_tx_pld_rst_n_reg.reg
|
|
Info (332115): Launch Clock : SYS_RefClk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|tx_pma_clk
|
|
Info (332115): Exception : dcp_bbs.sdc:3145: set_max_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_8g_g3_tx_pld_rst_n}] 50.000
|
|
Info (332115): Max Delay Exception : 50.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 4.719 4.719 R clock network delay
|
|
Info (332115): 4.719 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi_txdig_ena
|
|
Info (332115): 5.004 0.285 RR uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi_txdig_ena|q
|
|
Info (332115): 5.119 0.115 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi_txdig_ena~la_mlab/laboutb[17]
|
|
Info (332115): 7.936 2.817 RR IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0|datac
|
|
Info (332115): 8.142 0.206 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0|combout
|
|
Info (332115): 8.148 0.006 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0~la_mlab/laboutb[18]
|
|
Info (332115): 12.051 3.903 RR IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_tx_pld_pcs_interface.inst_twentynm_hssi_tx_pld_pcs_interface|pld_8g_g3_tx_pld_rst_n
|
|
Info (332115): 12.051 0.000 RR CELL fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs~pld_8g_g3_tx_pld_rst_n_reg.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 50.000 50.000 latch edge time
|
|
Info (332115): 52.288 2.288 R clock network delay
|
|
Info (332115): 52.218 -0.070 clock uncertainty
|
|
Info (332115): 52.073 -0.145 uTsu fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs~pld_8g_g3_tx_pld_rst_n_reg.reg
|
|
Info (332115): Data Arrival Time : 12.051
|
|
Info (332115): Data Required Time : 52.073
|
|
Info (332115): Slack : 40.022
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 40.582
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|tx_pma_clk}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 40.582
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi_txdig_ena
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs~pld_8g_g3_tx_pld_rst_n_reg.reg
|
|
Info (332115): Launch Clock : SYS_RefClk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|tx_pma_clk
|
|
Info (332115): Exception : dcp_bbs.sdc:3145: set_max_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_8g_g3_tx_pld_rst_n}] 50.000
|
|
Info (332115): Max Delay Exception : 50.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 4.719 4.719 R clock network delay
|
|
Info (332115): 4.719 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi_txdig_ena
|
|
Info (332115): 5.004 0.285 RR uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi_txdig_ena|q
|
|
Info (332115): 5.119 0.115 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi_txdig_ena~la_mlab/laboutb[17]
|
|
Info (332115): 7.795 2.676 RR IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0|dataa
|
|
Info (332115): 8.103 0.308 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0|combout
|
|
Info (332115): 8.107 0.004 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0~la_lab/laboutb[16]
|
|
Info (332115): 11.491 3.384 RR IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_tx_pld_pcs_interface.inst_twentynm_hssi_tx_pld_pcs_interface|pld_8g_g3_tx_pld_rst_n
|
|
Info (332115): 11.491 0.000 RR CELL fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs~pld_8g_g3_tx_pld_rst_n_reg.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 50.000 50.000 latch edge time
|
|
Info (332115): 52.288 2.288 R clock network delay
|
|
Info (332115): 52.218 -0.070 clock uncertainty
|
|
Info (332115): 52.073 -0.145 uTsu fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs~pld_8g_g3_tx_pld_rst_n_reg.reg
|
|
Info (332115): Data Arrival Time : 11.491
|
|
Info (332115): Data Required Time : 52.073
|
|
Info (332115): Slack : 40.582
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 41.854
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|tx_coreclkin}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 41.854
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi_txdig_ena
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_10g_tx_pcs.inst_twentynm_hssi_10g_tx_pcs~pld_10g_krfec_tx_pld_rst_n_fifo.reg
|
|
Info (332115): Launch Clock : SYS_RefClk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|tx_coreclkin
|
|
Info (332115): Exception : dcp_bbs.sdc:3146: set_max_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_10g_krfec_tx_pld_rst_n}] 50.000
|
|
Info (332115): Max Delay Exception : 50.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 4.719 4.719 R clock network delay
|
|
Info (332115): 4.719 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi_txdig_ena
|
|
Info (332115): 5.004 0.285 RR uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi_txdig_ena|q
|
|
Info (332115): 5.119 0.115 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi_txdig_ena~la_mlab/laboutb[17]
|
|
Info (332115): 8.082 2.963 RR IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0|datac
|
|
Info (332115): 8.285 0.203 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0|combout
|
|
Info (332115): 8.291 0.006 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0~la_mlab/laboutb[18]
|
|
Info (332115): 12.239 3.948 RR IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_tx_pld_pcs_interface.inst_twentynm_hssi_tx_pld_pcs_interface|pld_10g_krfec_tx_pld_rst_n
|
|
Info (332115): 12.239 0.000 RR CELL fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_10g_tx_pcs.inst_twentynm_hssi_10g_tx_pcs~pld_10g_krfec_tx_pld_rst_n_fifo.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 50.000 50.000 latch edge time
|
|
Info (332115): 54.324 4.324 R clock network delay
|
|
Info (332115): 54.284 -0.040 clock uncertainty
|
|
Info (332115): 54.093 -0.191 uTsu fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_10g_tx_pcs.inst_twentynm_hssi_10g_tx_pcs~pld_10g_krfec_tx_pld_rst_n_fifo.reg
|
|
Info (332115): Data Arrival Time : 12.239
|
|
Info (332115): Data Required Time : 54.093
|
|
Info (332115): Slack : 41.854
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 42.349
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|tx_coreclkin}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 42.349
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi_txdig_ena
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_10g_tx_pcs.inst_twentynm_hssi_10g_tx_pcs~pld_10g_krfec_tx_pld_rst_n_fifo.reg
|
|
Info (332115): Launch Clock : SYS_RefClk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|tx_coreclkin
|
|
Info (332115): Exception : dcp_bbs.sdc:3146: set_max_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_10g_krfec_tx_pld_rst_n}] 50.000
|
|
Info (332115): Max Delay Exception : 50.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 4.719 4.719 R clock network delay
|
|
Info (332115): 4.719 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi_txdig_ena
|
|
Info (332115): 5.004 0.285 RR uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi_txdig_ena|q
|
|
Info (332115): 5.119 0.115 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi_txdig_ena~la_mlab/laboutb[17]
|
|
Info (332115): 7.936 2.817 RR IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0|datac
|
|
Info (332115): 8.142 0.206 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0|combout
|
|
Info (332115): 8.148 0.006 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0~la_mlab/laboutb[18]
|
|
Info (332115): 11.857 3.709 RR IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_tx_pld_pcs_interface.inst_twentynm_hssi_tx_pld_pcs_interface|pld_10g_krfec_tx_pld_rst_n
|
|
Info (332115): 11.857 0.000 RR CELL fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_10g_tx_pcs.inst_twentynm_hssi_10g_tx_pcs~pld_10g_krfec_tx_pld_rst_n_fifo.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 50.000 50.000 latch edge time
|
|
Info (332115): 54.437 4.437 R clock network delay
|
|
Info (332115): 54.397 -0.040 clock uncertainty
|
|
Info (332115): 54.206 -0.191 uTsu fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_10g_tx_pcs.inst_twentynm_hssi_10g_tx_pcs~pld_10g_krfec_tx_pld_rst_n_fifo.reg
|
|
Info (332115): Data Arrival Time : 11.857
|
|
Info (332115): Data Required Time : 54.206
|
|
Info (332115): Slack : 42.349
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 42.379
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|tx_coreclkin}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 42.379
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi_txdig_ena
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_10g_tx_pcs.inst_twentynm_hssi_10g_tx_pcs~pld_10g_krfec_tx_pld_rst_n_fifo.reg
|
|
Info (332115): Launch Clock : SYS_RefClk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|tx_coreclkin
|
|
Info (332115): Exception : dcp_bbs.sdc:3146: set_max_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_10g_krfec_tx_pld_rst_n}] 50.000
|
|
Info (332115): Max Delay Exception : 50.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 4.719 4.719 R clock network delay
|
|
Info (332115): 4.719 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi_txdig_ena
|
|
Info (332115): 5.004 0.285 RR uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi_txdig_ena|q
|
|
Info (332115): 5.119 0.115 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi_txdig_ena~la_mlab/laboutb[17]
|
|
Info (332115): 7.827 2.708 RR IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0|datac
|
|
Info (332115): 8.011 0.184 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0|combout
|
|
Info (332115): 8.015 0.004 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0~la_lab/laboutt[8]
|
|
Info (332115): 11.725 3.710 RR IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_tx_pld_pcs_interface.inst_twentynm_hssi_tx_pld_pcs_interface|pld_10g_krfec_tx_pld_rst_n
|
|
Info (332115): 11.725 0.000 RR CELL fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_10g_tx_pcs.inst_twentynm_hssi_10g_tx_pcs~pld_10g_krfec_tx_pld_rst_n_fifo.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 50.000 50.000 latch edge time
|
|
Info (332115): 54.335 4.335 R clock network delay
|
|
Info (332115): 54.295 -0.040 clock uncertainty
|
|
Info (332115): 54.104 -0.191 uTsu fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_10g_tx_pcs.inst_twentynm_hssi_10g_tx_pcs~pld_10g_krfec_tx_pld_rst_n_fifo.reg
|
|
Info (332115): Data Arrival Time : 11.725
|
|
Info (332115): Data Required Time : 54.104
|
|
Info (332115): Slack : 42.379
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 42.614
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|tx_coreclkin}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 42.614
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi_txdig_ena
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_10g_tx_pcs.inst_twentynm_hssi_10g_tx_pcs~pld_10g_krfec_tx_pld_rst_n_fifo.reg
|
|
Info (332115): Launch Clock : SYS_RefClk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|tx_coreclkin
|
|
Info (332115): Exception : dcp_bbs.sdc:3146: set_max_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_10g_krfec_tx_pld_rst_n}] 50.000
|
|
Info (332115): Max Delay Exception : 50.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 4.719 4.719 R clock network delay
|
|
Info (332115): 4.719 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi_txdig_ena
|
|
Info (332115): 5.004 0.285 RR uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi_txdig_ena|q
|
|
Info (332115): 5.119 0.115 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi_txdig_ena~la_mlab/laboutb[17]
|
|
Info (332115): 7.795 2.676 RR IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0|dataa
|
|
Info (332115): 8.103 0.308 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0|combout
|
|
Info (332115): 8.107 0.004 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0~la_lab/laboutb[16]
|
|
Info (332115): 11.491 3.384 RR IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_tx_pld_pcs_interface.inst_twentynm_hssi_tx_pld_pcs_interface|pld_10g_krfec_tx_pld_rst_n
|
|
Info (332115): 11.491 0.000 RR CELL fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_10g_tx_pcs.inst_twentynm_hssi_10g_tx_pcs~pld_10g_krfec_tx_pld_rst_n_fifo.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 50.000 50.000 latch edge time
|
|
Info (332115): 54.336 4.336 R clock network delay
|
|
Info (332115): 54.296 -0.040 clock uncertainty
|
|
Info (332115): 54.105 -0.191 uTsu fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_10g_tx_pcs.inst_twentynm_hssi_10g_tx_pcs~pld_10g_krfec_tx_pld_rst_n_fifo.reg
|
|
Info (332115): Data Arrival Time : 11.491
|
|
Info (332115): Data Required Time : 54.105
|
|
Info (332115): Slack : 42.614
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 97.252
|
|
Info (20696): -to_clock [get_clocks {altera_reserved_tck}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 97.252
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|host_link_jtag|jtag|normal.jtag_dc_streaming|synchronizer|dreg[1]
|
|
Info (332115): To Node : auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|host_link_jtag|jtag|normal.jtag_dc_streaming|jtag_streaming|idle_inserter|received_esc
|
|
Info (332115): Launch Clock : altera_reserved_tck
|
|
Info (332115): Latch Clock : altera_reserved_tck
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 4.297 4.297 R clock network delay
|
|
Info (332115): 4.297 0.000 auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|host_link_jtag|jtag|normal.jtag_dc_streaming|synchronizer|dreg[1]
|
|
Info (332115): 4.528 0.231 RR uTco auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|host_link_jtag|jtag|normal.jtag_dc_streaming|synchronizer|dreg[1]|q
|
|
Info (332115): 4.705 0.177 RR CELL High Speed auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|host_link_jtag|jtag|normal.jtag_dc_streaming|synchronizer|dreg[1]~la_lab/laboutt[0]
|
|
Info (332115): 6.101 1.396 RR IC High Speed auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|host_link_jtag|jtag|normal.jtag_dc_streaming|jtag_streaming|idle_inserter|received_esc|clrn
|
|
Info (332115): 6.101 0.000 RR CELL High Speed auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|host_link_jtag|jtag|normal.jtag_dc_streaming|jtag_streaming|idle_inserter|received_esc
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 100.000 100.000 latch edge time
|
|
Info (332115): 103.261 3.261 R clock network delay
|
|
Info (332115): 103.519 0.258 clock pessimism removed
|
|
Info (332115): 103.489 -0.030 clock uncertainty
|
|
Info (332115): 103.353 -0.136 uTsu auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|host_link_jtag|jtag|normal.jtag_dc_streaming|jtag_streaming|idle_inserter|received_esc
|
|
Info (332115): Data Arrival Time : 6.101
|
|
Info (332115): Data Required Time : 103.353
|
|
Info (332115): Slack : 97.252
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 0.201
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk1}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 0.201
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[3].core|pipeline|execute|fpu_unit|fpu_fpga|fp_sqrt|[2].reset_relay|reset_r[0]
|
|
Info (332115): To Node : fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[3].core|pipeline|execute|fpu_unit|fpu_fpga|fp_sqrt|[2].fsqrt|mult_1~DATAOUTA0~reg0
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk1
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk1
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 5.295 5.295 R clock network delay
|
|
Info (332115): 5.295 0.000 fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[3].core|pipeline|execute|fpu_unit|fpu_fpga|fp_sqrt|[2].reset_relay|reset_r[0]
|
|
Info (332115): 5.474 0.179 FF uTco fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[3].core|pipeline|execute|fpu_unit|fpu_fpga|fp_sqrt|[2].reset_relay|reset_r[0]|q
|
|
Info (332115): 5.534 0.060 FF CELL High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[3].core|pipeline|execute|fpu_unit|fpu_fpga|fp_sqrt|[2].reset_relay|reset_r[0]~la_mlab/laboutt[9]
|
|
Info (332115): 5.691 0.157 FF IC High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[3].core|pipeline|execute|fpu_unit|fpu_fpga|fp_sqrt|[2].fsqrt|mult_1~DATAOUTA0|aclr[1]
|
|
Info (332115): 5.691 0.000 FF CELL High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[3].core|pipeline|execute|fpu_unit|fpu_fpga|fp_sqrt|[2].fsqrt|mult_1~DATAOUTA0~reg0
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 6.416 6.416 R clock network delay
|
|
Info (332115): 5.322 -1.094 clock pessimism removed
|
|
Info (332115): 5.322 0.000 clock uncertainty
|
|
Info (332115): 5.490 0.168 uTh fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[3].core|pipeline|execute|fpu_unit|fpu_fpga|fp_sqrt|[2].fsqrt|mult_1~DATAOUTA0~reg0
|
|
Info (332115): Data Arrival Time : 5.691
|
|
Info (332115): Data Required Time : 5.490
|
|
Info (332115): Slack : 0.201
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 0.315
|
|
Info (20696): -to_clock [get_clocks {u0|dcp_iopll|dcp_iopll|clk1x}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 0.315
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|rdaclr|dffe7a[0]
|
|
Info (332115): To Node : fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|fifo_ram|ram_block7a591~reg1
|
|
Info (332115): Launch Clock : u0|dcp_iopll|dcp_iopll|clk1x
|
|
Info (332115): Latch Clock : u0|dcp_iopll|dcp_iopll|clk1x
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 8.187 8.187 R clock network delay
|
|
Info (332115): 8.187 0.000 fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|rdaclr|dffe7a[0]
|
|
Info (332115): 8.372 0.185 RR uTco fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|rdaclr|dffe7a[0]|q
|
|
Info (332115): 8.464 0.092 RR CELL High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|rdaclr|dffe7a[0]~la_lab/laboutt[5]
|
|
Info (332115): 8.651 0.187 RR IC High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|fifo_ram|ram_block7a591|clr1
|
|
Info (332115): 8.651 0.000 RR CELL High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|fifo_ram|ram_block7a591~reg1
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 9.476 9.476 R clock network delay
|
|
Info (332115): 8.188 -1.288 clock pessimism removed
|
|
Info (332115): 8.188 0.000 clock uncertainty
|
|
Info (332115): 8.336 0.148 uTh fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|fifo_ram|ram_block7a591~reg1
|
|
Info (332115): Data Arrival Time : 8.651
|
|
Info (332115): Data Required Time : 8.336
|
|
Info (332115): Slack : 0.315
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 0.322
|
|
Info (20696): -to_clock [get_clocks {SYS_RefClk}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 0.322
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].avmm_reset_sync_inst|resync_chains[0].sync_r[1]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_read_r[0]
|
|
Info (332115): Launch Clock : SYS_RefClk
|
|
Info (332115): Latch Clock : SYS_RefClk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 4.311 4.311 R clock network delay
|
|
Info (332115): 4.311 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].avmm_reset_sync_inst|resync_chains[0].sync_r[1]
|
|
Info (332115): 4.487 0.176 RR uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].avmm_reset_sync_inst|resync_chains[0].sync_r[1]|q
|
|
Info (332115): 4.576 0.089 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].avmm_reset_sync_inst|resync_chains[0].sync_r[1]~la_lab/laboutb[14]
|
|
Info (332115): 4.732 0.156 RR IC High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_read_r[0]|clrn
|
|
Info (332115): 4.732 0.000 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_read_r[0]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 4.696 4.696 R clock network delay
|
|
Info (332115): 4.333 -0.363 clock pessimism removed
|
|
Info (332115): 4.333 0.000 clock uncertainty
|
|
Info (332115): 4.410 0.077 uTh fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_read_r[0]
|
|
Info (332115): Data Arrival Time : 4.732
|
|
Info (332115): Data Required Time : 4.410
|
|
Info (332115): Slack : 0.322
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 0.343
|
|
Info (20696): -to_clock [get_clocks {mem|ddr4a|ddr4a_core_usr_clk}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 0.343
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|reset_sync_pri_sdc_anchor
|
|
Info (332115): To Node : mem|ddr4a|ddr4a|arch|arch_inst|seq_if_inst|afi_cal_fail_sync_inst|dreg[0]
|
|
Info (332115): Launch Clock : mem|ddr4a|ddr4a_core_usr_clk
|
|
Info (332115): Latch Clock : mem|ddr4a|ddr4a_core_usr_clk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.117 0.117 launch edge time
|
|
Info (332115): 2.798 2.681 R clock network delay
|
|
Info (332115): 2.798 0.000 mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|reset_sync_pri_sdc_anchor
|
|
Info (332115): 2.977 0.179 RR uTco mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|reset_sync_pri_sdc_anchor|q
|
|
Info (332115): 3.069 0.092 RR CELL High Speed mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|reset_sync_pri_sdc_anchor~la_mlab/laboutb[13]
|
|
Info (332115): 3.245 0.176 RR IC High Speed mem|ddr4a|ddr4a|arch|arch_inst|seq_if_inst|afi_cal_fail_sync_inst|dreg[0]|clrn
|
|
Info (332115): 3.245 0.000 RR CELL High Speed mem|ddr4a|ddr4a|arch|arch_inst|seq_if_inst|afi_cal_fail_sync_inst|dreg[0]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.117 0.117 latch edge time
|
|
Info (332115): 3.658 3.541 R clock network delay
|
|
Info (332115): 2.816 -0.842 clock pessimism removed
|
|
Info (332115): 2.816 0.000 clock uncertainty
|
|
Info (332115): 2.902 0.086 uTh mem|ddr4a|ddr4a|arch|arch_inst|seq_if_inst|afi_cal_fail_sync_inst|dreg[0]
|
|
Info (332115): Data Arrival Time : 3.245
|
|
Info (332115): Data Required Time : 2.902
|
|
Info (332115): Slack : 0.343
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 0.347
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_clk}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 0.347
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_reset_sync|resync_chains[0].sync_r[2]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_snapshot[6]
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_clk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_clk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 5.052 5.052 R clock network delay
|
|
Info (332115): 5.052 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_reset_sync|resync_chains[0].sync_r[2]
|
|
Info (332115): 5.231 0.179 RR uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_reset_sync|resync_chains[0].sync_r[2]|q
|
|
Info (332115): 5.316 0.085 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_reset_sync|resync_chains[0].sync_r[2]~la_lab/laboutb[18]
|
|
Info (332115): 5.505 0.189 RR IC High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_snapshot[6]|clrn
|
|
Info (332115): 5.505 0.000 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_snapshot[6]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 7.035 7.035 R clock network delay
|
|
Info (332115): 5.073 -1.962 clock pessimism removed
|
|
Info (332115): 5.073 0.000 clock uncertainty
|
|
Info (332115): 5.158 0.085 uTh fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_snapshot[6]
|
|
Info (332115): Data Arrival Time : 5.505
|
|
Info (332115): Data Required Time : 5.158
|
|
Info (332115): Slack : 0.347
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 0.375
|
|
Info (20696): -to_clock [get_clocks {mem|ddr4a|ddr4a_core_cal_slave_clk}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 0.375
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : mem|ddr4b|ddr4b|cal_slave_component|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out
|
|
Info (332115): To Node : mem|ddr4b|ddr4b|cal_slave_component|ioaux_master_bridge|wr_reg_write
|
|
Info (332115): Launch Clock : mem|ddr4a|ddr4a_core_cal_slave_clk
|
|
Info (332115): Latch Clock : mem|ddr4a|ddr4a_core_cal_slave_clk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 5.958 5.958 R clock network delay
|
|
Info (332115): 5.958 0.000 mem|ddr4b|ddr4b|cal_slave_component|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out
|
|
Info (332115): 6.145 0.187 RR uTco mem|ddr4b|ddr4b|cal_slave_component|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out|q
|
|
Info (332115): 6.271 0.126 RR CELL High Speed mem|ddr4b|ddr4b|cal_slave_component|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~la_mlab/laboutb[11]
|
|
Info (332115): 6.429 0.158 RR IC High Speed mem|ddr4b|ddr4b|cal_slave_component|ioaux_master_bridge|wr_reg_write|clrn
|
|
Info (332115): 6.429 0.000 RR CELL High Speed mem|ddr4b|ddr4b|cal_slave_component|ioaux_master_bridge|wr_reg_write
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 6.978 6.978 R clock network delay
|
|
Info (332115): 5.958 -1.020 clock pessimism removed
|
|
Info (332115): 5.958 0.000 clock uncertainty
|
|
Info (332115): 6.054 0.096 uTh mem|ddr4b|ddr4b|cal_slave_component|ioaux_master_bridge|wr_reg_write
|
|
Info (332115): Data Arrival Time : 6.429
|
|
Info (332115): Data Required Time : 6.054
|
|
Info (332115): Slack : 0.375
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 0.378
|
|
Info (20696): -to_clock [get_clocks {PCIE_REFCLK}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 0.378
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].avmm_reset_sync_inst|resync_chains[0].sync_r[1]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_read_cycles_cnt[1]
|
|
Info (332115): Launch Clock : PCIE_REFCLK
|
|
Info (332115): Latch Clock : PCIE_REFCLK
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 5.059 5.059 R clock network delay
|
|
Info (332115): 5.059 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].avmm_reset_sync_inst|resync_chains[0].sync_r[1]
|
|
Info (332115): 5.236 0.177 RR uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].avmm_reset_sync_inst|resync_chains[0].sync_r[1]|q
|
|
Info (332115): 5.325 0.089 RR CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].avmm_reset_sync_inst|resync_chains[0].sync_r[1]~la_lab/laboutt[10]
|
|
Info (332115): 5.505 0.180 RR IC High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_read_cycles_cnt[1]|clrn
|
|
Info (332115): 5.505 0.000 RR CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_read_cycles_cnt[1]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 5.619 5.619 R clock network delay
|
|
Info (332115): 5.058 -0.561 clock pessimism removed
|
|
Info (332115): 5.058 0.000 clock uncertainty
|
|
Info (332115): 5.127 0.069 uTh fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_read_cycles_cnt[1]
|
|
Info (332115): Data Arrival Time : 5.505
|
|
Info (332115): Data Required Time : 5.127
|
|
Info (332115): Slack : 0.378
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 0.395
|
|
Info (20696): -to_clock [get_clocks {DDR4_RefClk}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 0.395
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|use_counter_lock.counter_lock_gen_master.pll_ref_clk_reset_n_sync_rrr
|
|
Info (332115): To Node : mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|counter_lock
|
|
Info (332115): Launch Clock : DDR4_RefClk
|
|
Info (332115): Latch Clock : DDR4_RefClk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 4.025 4.025 R clock network delay
|
|
Info (332115): 4.025 0.000 mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|use_counter_lock.counter_lock_gen_master.pll_ref_clk_reset_n_sync_rrr
|
|
Info (332115): 4.214 0.189 RR uTco mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|use_counter_lock.counter_lock_gen_master.pll_ref_clk_reset_n_sync_rrr|q
|
|
Info (332115): 4.336 0.122 RR CELL High Speed mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|use_counter_lock.counter_lock_gen_master.pll_ref_clk_reset_n_sync_rrr~la_mlab/laboutb[4]
|
|
Info (332115): 4.497 0.161 RR IC High Speed mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|counter_lock|clrn
|
|
Info (332115): 4.497 0.000 RR CELL High Speed mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|counter_lock
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 4.350 4.350 R clock network delay
|
|
Info (332115): 4.026 -0.324 clock pessimism removed
|
|
Info (332115): 4.026 0.000 clock uncertainty
|
|
Info (332115): 4.102 0.076 uTh mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|counter_lock
|
|
Info (332115): Data Arrival Time : 4.497
|
|
Info (332115): Data Required Time : 4.102
|
|
Info (332115): Slack : 0.395
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 0.412
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|wys~CORE_CLK_OUT}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 0.412
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_rst_sync.syncrstn_avmm_sriov.app_rstn_altpcie_reset_delay_sync_altpcie_a10_hip_hwtcl|sync_rst[1]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_sriov_2.sriov2.lmi_burst_intf|hip_lmi_addr_o[4]
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|wys~CORE_CLK_OUT
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|wys~CORE_CLK_OUT
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 7.858 7.858 R clock network delay
|
|
Info (332115): 7.858 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_rst_sync.syncrstn_avmm_sriov.app_rstn_altpcie_reset_delay_sync_altpcie_a10_hip_hwtcl|sync_rst[1]
|
|
Info (332115): 8.038 0.180 RR uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_rst_sync.syncrstn_avmm_sriov.app_rstn_altpcie_reset_delay_sync_altpcie_a10_hip_hwtcl|sync_rst[1]|q
|
|
Info (332115): 8.126 0.088 RR CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_rst_sync.syncrstn_avmm_sriov.app_rstn_altpcie_reset_delay_sync_altpcie_a10_hip_hwtcl|sync_rst[1]~la_mlab/laboutt[9]
|
|
Info (332115): 8.384 0.258 RR IC High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_sriov_2.sriov2.lmi_burst_intf|hip_lmi_addr_o[4]|clrn
|
|
Info (332115): 8.384 0.000 RR CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_sriov_2.sriov2.lmi_burst_intf|hip_lmi_addr_o[4]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 9.276 9.276 R clock network delay
|
|
Info (332115): 7.880 -1.396 clock pessimism removed
|
|
Info (332115): 7.972 0.092 uTh fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_sriov_2.sriov2.lmi_burst_intf|hip_lmi_addr_o[4]
|
|
Info (332115): Data Arrival Time : 8.384
|
|
Info (332115): Data Required Time : 7.972
|
|
Info (332115): Slack : 0.412
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 0.422
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|rx_pma_clk}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 0.422
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_reset_sync|resync_chains[0].sync_r[2]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_error_high
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|rx_pma_clk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|rx_pma_clk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 5.014 5.014 R clock network delay
|
|
Info (332115): 5.014 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_reset_sync|resync_chains[0].sync_r[2]
|
|
Info (332115): 5.194 0.180 RR uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_reset_sync|resync_chains[0].sync_r[2]|q
|
|
Info (332115): 5.279 0.085 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_reset_sync|resync_chains[0].sync_r[2]~la_lab/laboutb[18]
|
|
Info (332115): 5.547 0.268 RR IC High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_error_high|clrn
|
|
Info (332115): 5.547 0.000 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_error_high
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 6.999 6.999 R clock network delay
|
|
Info (332115): 5.037 -1.962 clock pessimism removed
|
|
Info (332115): 5.037 0.000 clock uncertainty
|
|
Info (332115): 5.125 0.088 uTh fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_error_high
|
|
Info (332115): Data Arrival Time : 5.547
|
|
Info (332115): Data Required Time : 5.125
|
|
Info (332115): Slack : 0.422
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 0.432
|
|
Info (20696): -to_clock [get_clocks {u0|dcp_iopll|dcp_iopll|clk100}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 0.432
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|gen_ccip_ports[0].inst_remote_green_stp|inst_stp_ep|inst_SLD_HUB_cont_sys|sld_hub_controller_system_without_sldep_0|sld_hub_controller_system_without_sldep_0|link|mm_mgmt|debug_reset
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|gen_ccip_ports[0].inst_remote_green_stp|inst_stp_ep|inst_SLD_HUB_cont_sys|sld_hub_controller_system_without_sldep_0|sld_hub_controller_system_without_sldep_0|fabric|mgmt_demux|inpipe|out_payload[1]
|
|
Info (332115): Launch Clock : u0|dcp_iopll|dcp_iopll|clk100
|
|
Info (332115): Latch Clock : u0|dcp_iopll|dcp_iopll|clk100
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 8.260 8.260 R clock network delay
|
|
Info (332115): 8.260 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|gen_ccip_ports[0].inst_remote_green_stp|inst_stp_ep|inst_SLD_HUB_cont_sys|sld_hub_controller_system_without_sldep_0|sld_hub_controller_system_without_sldep_0|link|mm_mgmt|debug_reset
|
|
Info (332115): 8.437 0.177 RR uTco fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|gen_ccip_ports[0].inst_remote_green_stp|inst_stp_ep|inst_SLD_HUB_cont_sys|sld_hub_controller_system_without_sldep_0|sld_hub_controller_system_without_sldep_0|link|mm_mgmt|debug_reset|q
|
|
Info (332115): 8.525 0.088 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|gen_ccip_ports[0].inst_remote_green_stp|inst_stp_ep|inst_SLD_HUB_cont_sys|sld_hub_controller_system_without_sldep_0|sld_hub_controller_system_without_sldep_0|link|mm_mgmt|debug_reset~la_lab/laboutt[1]
|
|
Info (332115): 8.768 0.243 RR IC High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|gen_ccip_ports[0].inst_remote_green_stp|inst_stp_ep|inst_SLD_HUB_cont_sys|sld_hub_controller_system_without_sldep_0|sld_hub_controller_system_without_sldep_0|fabric|mgmt_demux|inpipe|out_payload[1]|clrn
|
|
Info (332115): 8.768 0.000 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|gen_ccip_ports[0].inst_remote_green_stp|inst_stp_ep|inst_SLD_HUB_cont_sys|sld_hub_controller_system_without_sldep_0|sld_hub_controller_system_without_sldep_0|fabric|mgmt_demux|inpipe|out_payload[1]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 9.588 9.588 R clock network delay
|
|
Info (332115): 8.260 -1.328 clock pessimism removed
|
|
Info (332115): 8.260 0.000 clock uncertainty
|
|
Info (332115): 8.336 0.076 uTh fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|gen_ccip_ports[0].inst_remote_green_stp|inst_stp_ep|inst_SLD_HUB_cont_sys|sld_hub_controller_system_without_sldep_0|sld_hub_controller_system_without_sldep_0|fabric|mgmt_demux|inpipe|out_payload[1]
|
|
Info (332115): Data Arrival Time : 8.768
|
|
Info (332115): Data Required Time : 8.336
|
|
Info (332115): Slack : 0.432
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 0.452
|
|
Info (20696): -to_clock [get_clocks {u0|dcp_iopll|dcp_iopll|clk25}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 0.452
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|generic_quad_spi_controller2_0|generic_quad_spi_controller2_0|asmi2_inst_qspi_ctrl|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|generic_quad_spi_controller2_0|generic_quad_spi_controller2_0|asmi2_inst_qspi_ctrl|asmi2_qspi_interface_0|read_cnt_q[2]
|
|
Info (332115): Launch Clock : u0|dcp_iopll|dcp_iopll|clk25
|
|
Info (332115): Latch Clock : u0|dcp_iopll|dcp_iopll|clk25
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 8.376 8.376 R clock network delay
|
|
Info (332115): 8.376 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|generic_quad_spi_controller2_0|generic_quad_spi_controller2_0|asmi2_inst_qspi_ctrl|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out
|
|
Info (332115): 8.573 0.197 RR uTco fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|generic_quad_spi_controller2_0|generic_quad_spi_controller2_0|asmi2_inst_qspi_ctrl|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out|q
|
|
Info (332115): 8.665 0.092 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|generic_quad_spi_controller2_0|generic_quad_spi_controller2_0|asmi2_inst_qspi_ctrl|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~la_mlab/laboutb[5]
|
|
Info (332115): 8.910 0.245 RR IC High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|generic_quad_spi_controller2_0|generic_quad_spi_controller2_0|asmi2_inst_qspi_ctrl|asmi2_qspi_interface_0|read_cnt_q[2]|clrn
|
|
Info (332115): 8.910 0.000 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|generic_quad_spi_controller2_0|generic_quad_spi_controller2_0|asmi2_inst_qspi_ctrl|asmi2_qspi_interface_0|read_cnt_q[2]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 9.747 9.747 R clock network delay
|
|
Info (332115): 8.376 -1.371 clock pessimism removed
|
|
Info (332115): 8.376 0.000 clock uncertainty
|
|
Info (332115): 8.458 0.082 uTh fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|generic_quad_spi_controller2_0|generic_quad_spi_controller2_0|asmi2_inst_qspi_ctrl|asmi2_qspi_interface_0|read_cnt_q[2]
|
|
Info (332115): Data Arrival Time : 8.910
|
|
Info (332115): Data Required Time : 8.458
|
|
Info (332115): Slack : 0.452
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 0.462
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|rx_pma_clk}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 0.462
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_reset_sync|resync_chains[0].sync_r[2]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_cnt_edge_reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|rx_pma_clk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|rx_pma_clk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 4.934 4.934 R clock network delay
|
|
Info (332115): 4.934 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_reset_sync|resync_chains[0].sync_r[2]
|
|
Info (332115): 5.114 0.180 RR uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_reset_sync|resync_chains[0].sync_r[2]|q
|
|
Info (332115): 5.199 0.085 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_reset_sync|resync_chains[0].sync_r[2]~la_mlab/laboutb[2]
|
|
Info (332115): 5.530 0.331 RR IC High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_cnt_edge_reg|clrn
|
|
Info (332115): 5.530 0.000 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_cnt_edge_reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 6.926 6.926 R clock network delay
|
|
Info (332115): 4.980 -1.946 clock pessimism removed
|
|
Info (332115): 4.980 0.000 clock uncertainty
|
|
Info (332115): 5.068 0.088 uTh fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_cnt_edge_reg
|
|
Info (332115): Data Arrival Time : 5.530
|
|
Info (332115): Data Required Time : 5.068
|
|
Info (332115): Slack : 0.462
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 0.479
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|rx_pma_clk}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 0.479
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_reset_sync|resync_chains[0].sync_r[2]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_bit_count[3]
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|rx_pma_clk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|rx_pma_clk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 5.045 5.045 R clock network delay
|
|
Info (332115): 5.045 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_reset_sync|resync_chains[0].sync_r[2]
|
|
Info (332115): 5.226 0.181 RR uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_reset_sync|resync_chains[0].sync_r[2]|q
|
|
Info (332115): 5.318 0.092 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_reset_sync|resync_chains[0].sync_r[2]~la_mlab/laboutb[5]
|
|
Info (332115): 5.653 0.335 RR IC High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_bit_count[3]|clrn
|
|
Info (332115): 5.653 0.000 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_bit_count[3]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 7.027 7.027 R clock network delay
|
|
Info (332115): 5.083 -1.944 clock pessimism removed
|
|
Info (332115): 5.083 0.000 clock uncertainty
|
|
Info (332115): 5.174 0.091 uTh fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_bit_count[3]
|
|
Info (332115): Data Arrival Time : 5.653
|
|
Info (332115): Data Required Time : 5.174
|
|
Info (332115): Slack : 0.479
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 0.928
|
|
Info (20696): -to_clock [get_clocks {altera_reserved_tck}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 0.928
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|host_link_jtag|jtag|normal.jtag_dc_streaming|synchronizer|dreg[1]
|
|
Info (332115): To Node : auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|host_link_jtag|jtag|normal.jtag_dc_streaming|sink_crosser|output_stage|full1
|
|
Info (332115): Launch Clock : altera_reserved_tck
|
|
Info (332115): Latch Clock : altera_reserved_tck
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 3.438 3.438 R clock network delay
|
|
Info (332115): 3.438 0.000 auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|host_link_jtag|jtag|normal.jtag_dc_streaming|synchronizer|dreg[1]
|
|
Info (332115): 3.628 0.190 RR uTco auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|host_link_jtag|jtag|normal.jtag_dc_streaming|synchronizer|dreg[1]|q
|
|
Info (332115): 3.754 0.126 RR CELL High Speed auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|host_link_jtag|jtag|normal.jtag_dc_streaming|synchronizer|dreg[1]~la_lab/laboutt[0]
|
|
Info (332115): 4.474 0.720 RR IC High Speed auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|host_link_jtag|jtag|normal.jtag_dc_streaming|sink_crosser|output_stage|full1|clrn
|
|
Info (332115): 4.474 0.000 RR CELL High Speed auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|host_link_jtag|jtag|normal.jtag_dc_streaming|sink_crosser|output_stage|full1
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 4.297 4.297 R clock network delay
|
|
Info (332115): 3.444 -0.853 clock pessimism removed
|
|
Info (332115): 3.444 0.000 clock uncertainty
|
|
Info (332115): 3.546 0.102 uTh auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|host_link_jtag|jtag|normal.jtag_dc_streaming|sink_crosser|output_stage|full1
|
|
Info (332115): Data Arrival Time : 4.474
|
|
Info (332115): Data Required Time : 3.546
|
|
Info (332115): Slack : 0.928
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 2.050
|
|
Info (20696): -to_clock [get_clocks {fspi_sclk}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 2.050
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|SPISlaveToAvalonMasterBridge_reset_clk_domain_synch|data_out
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MISOctl|loadstsinkdata
|
|
Info (332115): Launch Clock : u0|dcp_iopll|dcp_iopll|clk1x
|
|
Info (332115): Latch Clock : fspi_sclk
|
|
Info (332115): Exception : dcp_bbs.sdc:3057: set_multicycle_path -hold -from [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|SPISlaveToAvalonMasterBridge_reset_clk_domain_synch|data_out}] -to [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MISOctl|*}] 1
|
|
Info (332115): Multicycle - Setup Start : 2
|
|
Info (332115): Multicycle - Hold Start : 1
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 8.234 8.234 R clock network delay
|
|
Info (332115): 8.234 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|SPISlaveToAvalonMasterBridge_reset_clk_domain_synch|data_out
|
|
Info (332115): 8.436 0.202 RR uTco fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|SPISlaveToAvalonMasterBridge_reset_clk_domain_synch|data_out|q
|
|
Info (332115): 8.528 0.092 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|SPISlaveToAvalonMasterBridge_reset_clk_domain_synch|data_out~la_mlab/laboutt[1]
|
|
Info (332115): 8.913 0.385 RR IC High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MOSIctl|i5|dataf
|
|
Info (332115): 8.950 0.037 RF CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MOSIctl|i5|combout
|
|
Info (332115): 8.952 0.002 FF CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MOSIctl|i5~la_mlab/laboutt[19]
|
|
Info (332115): 9.081 0.129 FF IC High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MISOctl|loadstsinkdata|clrn
|
|
Info (332115): 9.081 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MISOctl|loadstsinkdata
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 6.641 6.641 R clock network delay
|
|
Info (332115): 6.951 0.310 clock uncertainty
|
|
Info (332115): 7.031 0.080 uTh fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MISOctl|loadstsinkdata
|
|
Info (332115): Data Arrival Time : 9.081
|
|
Info (332115): Data Required Time : 7.031
|
|
Info (332115): Slack : 2.050
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 4.987
|
|
Info (20696): -to_clock [get_clocks {filtered_sclk_negedge}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 4.987
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MOSIctl|sync_spi_reset|dreg[0]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MOSIctl|wrshiftreg[1]
|
|
Info (332115): Launch Clock : u0|dcp_iopll|dcp_iopll|clk1x
|
|
Info (332115): Latch Clock : filtered_sclk_negedge
|
|
Info (332115): Exception : dcp_bbs.sdc:3065: set_multicycle_path -hold -from [get_keepers {*sync_spi_reset|dreg*}] -to [get_keepers {*SPIPhy_MOSIctl|wrshiftreg*}] 1
|
|
Info (332115): Multicycle - Setup Start : 3
|
|
Info (332115): Multicycle - Hold Start : 1
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 245.000 245.000 launch edge time
|
|
Info (332115): 253.226 8.226 R clock network delay
|
|
Info (332115): 253.226 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MOSIctl|sync_spi_reset|dreg[0]
|
|
Info (332115): 253.427 0.201 RR uTco fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MOSIctl|sync_spi_reset|dreg[0]|q
|
|
Info (332115): 253.512 0.085 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MOSIctl|sync_spi_reset|dreg[0]~la_mlab/laboutt[6]
|
|
Info (332115): 255.674 2.162 RR IC High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MOSIctl|wrshiftreg[1]|clrn
|
|
Info (332115): 255.674 0.000 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MOSIctl|wrshiftreg[1]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 250.000 250.000 latch edge time
|
|
Info (332115): 250.282 0.282 R clock network delay
|
|
Info (332115): 250.582 0.300 clock uncertainty
|
|
Info (332115): 250.687 0.105 uTh fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MOSIctl|wrshiftreg[1]
|
|
Info (332115): Data Arrival Time : 255.674
|
|
Info (332115): Data Required Time : 250.687
|
|
Info (332115): Slack : 4.987
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 8.470
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|rx_pma_clk}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 8.470
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|rx_pma_clk
|
|
Info (332115): Exception : dcp_bbs.sdc:3195: set_min_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pma_rxpma_rstb}] -10.000
|
|
Info (332115): Min Delay Exception : -10.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 1.946 1.946 R clock network delay
|
|
Info (332115): 1.946 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): 3.359 1.413 FF uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|rx_pma_rstb3
|
|
Info (332115): 3.359 0.000 FF IC fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_pma_rxpma_rstb
|
|
Info (332115): 3.359 0.000 FF CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): -10.000 -10.000 latch edge time
|
|
Info (332115): -5.231 4.769 R clock network delay
|
|
Info (332115): -5.111 0.120 clock uncertainty
|
|
Info (332115): -5.111 0.000 uTh fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Data Arrival Time : 3.359
|
|
Info (332115): Data Required Time : -5.111
|
|
Info (332115): Slack : 8.470
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 8.473
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|rx_pma_clk}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 8.473
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|rx_pma_clk
|
|
Info (332115): Exception : dcp_bbs.sdc:3195: set_min_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pma_rxpma_rstb}] -10.000
|
|
Info (332115): Min Delay Exception : -10.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 1.946 1.946 R clock network delay
|
|
Info (332115): 1.946 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): 3.362 1.416 FF uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|rx_pma_rstb2
|
|
Info (332115): 3.362 0.000 FF IC fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_pma_rxpma_rstb
|
|
Info (332115): 3.362 0.000 FF CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): -10.000 -10.000 latch edge time
|
|
Info (332115): -5.231 4.769 R clock network delay
|
|
Info (332115): -5.111 0.120 clock uncertainty
|
|
Info (332115): -5.111 0.000 uTh fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Data Arrival Time : 3.362
|
|
Info (332115): Data Required Time : -5.111
|
|
Info (332115): Slack : 8.473
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 8.730
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|rx_pma_clk}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 8.730
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|rx_pma_clk
|
|
Info (332115): Exception : dcp_bbs.sdc:3195: set_min_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pma_rxpma_rstb}] -10.000
|
|
Info (332115): Min Delay Exception : -10.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 1.946 1.946 R clock network delay
|
|
Info (332115): 1.946 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): 3.618 1.672 FF uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|rx_pma_rstb4
|
|
Info (332115): 3.619 0.001 FF IC fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_pma_rxpma_rstb
|
|
Info (332115): 3.619 0.000 FF CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): -10.000 -10.000 latch edge time
|
|
Info (332115): -5.231 4.769 R clock network delay
|
|
Info (332115): -5.111 0.120 clock uncertainty
|
|
Info (332115): -5.111 0.000 uTh fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Data Arrival Time : 3.619
|
|
Info (332115): Data Required Time : -5.111
|
|
Info (332115): Slack : 8.730
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 8.768
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|rx_pma_clk}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 8.768
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|rx_pma_clk
|
|
Info (332115): Exception : dcp_bbs.sdc:3195: set_min_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pma_rxpma_rstb}] -10.000
|
|
Info (332115): Min Delay Exception : -10.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 1.946 1.946 R clock network delay
|
|
Info (332115): 1.946 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): 3.733 1.787 FF uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|rx_pma_rstb5
|
|
Info (332115): 3.733 0.000 FF IC fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_pma_rxpma_rstb
|
|
Info (332115): 3.733 0.000 FF CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): -10.000 -10.000 latch edge time
|
|
Info (332115): -5.155 4.845 R clock network delay
|
|
Info (332115): -5.035 0.120 clock uncertainty
|
|
Info (332115): -5.035 0.000 uTh fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Data Arrival Time : 3.733
|
|
Info (332115): Data Required Time : -5.035
|
|
Info (332115): Slack : 8.768
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 8.782
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|rx_pma_clk}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 8.782
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|rx_pma_clk
|
|
Info (332115): Exception : dcp_bbs.sdc:3195: set_min_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pma_rxpma_rstb}] -10.000
|
|
Info (332115): Min Delay Exception : -10.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 1.946 1.946 R clock network delay
|
|
Info (332115): 1.946 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): 3.585 1.639 FF uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|rx_pma_rstb1
|
|
Info (332115): 3.585 0.000 FF IC fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_pma_rxpma_rstb
|
|
Info (332115): 3.585 0.000 FF CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): -10.000 -10.000 latch edge time
|
|
Info (332115): -5.317 4.683 R clock network delay
|
|
Info (332115): -5.197 0.120 clock uncertainty
|
|
Info (332115): -5.197 0.000 uTh fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Data Arrival Time : 3.585
|
|
Info (332115): Data Required Time : -5.197
|
|
Info (332115): Slack : 8.782
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 8.835
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|rx_pma_clk}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 8.835
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|rx_pma_clk
|
|
Info (332115): Exception : dcp_bbs.sdc:3195: set_min_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pma_rxpma_rstb}] -10.000
|
|
Info (332115): Min Delay Exception : -10.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 1.946 1.946 R clock network delay
|
|
Info (332115): 1.946 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): 3.800 1.854 FF uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|rx_pma_rstb6
|
|
Info (332115): 3.800 0.000 FF IC fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_pma_rxpma_rstb
|
|
Info (332115): 3.800 0.000 FF CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): -10.000 -10.000 latch edge time
|
|
Info (332115): -5.155 4.845 R clock network delay
|
|
Info (332115): -5.035 0.120 clock uncertainty
|
|
Info (332115): -5.035 0.000 uTh fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Data Arrival Time : 3.800
|
|
Info (332115): Data Required Time : -5.035
|
|
Info (332115): Slack : 8.835
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 9.306
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|rx_pma_clk}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 9.306
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|rx_pma_clk
|
|
Info (332115): Exception : dcp_bbs.sdc:3195: set_min_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pma_rxpma_rstb}] -10.000
|
|
Info (332115): Min Delay Exception : -10.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 1.946 1.946 R clock network delay
|
|
Info (332115): 1.946 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): 4.271 2.325 FF uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|rx_pma_rstb7
|
|
Info (332115): 4.271 0.000 FF IC fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_pma_rxpma_rstb
|
|
Info (332115): 4.271 0.000 FF CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): -10.000 -10.000 latch edge time
|
|
Info (332115): -5.155 4.845 R clock network delay
|
|
Info (332115): -5.035 0.120 clock uncertainty
|
|
Info (332115): -5.035 0.000 uTh fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Data Arrival Time : 4.271
|
|
Info (332115): Data Required Time : -5.035
|
|
Info (332115): Slack : 9.306
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 9.383
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_pma_clk}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 9.383
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_pma_clk
|
|
Info (332115): Exception : dcp_bbs.sdc:3195: set_min_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pma_rxpma_rstb}] -10.000
|
|
Info (332115): Min Delay Exception : -10.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 1.946 1.946 R clock network delay
|
|
Info (332115): 1.946 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): 3.860 1.914 FF uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|rx_pma_rstb0
|
|
Info (332115): 3.861 0.001 FF IC fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_pma_rxpma_rstb
|
|
Info (332115): 3.861 0.000 FF CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): -10.000 -10.000 latch edge time
|
|
Info (332115): -5.317 4.683 R clock network delay
|
|
Info (332115): -5.542 -0.225 clock pessimism removed
|
|
Info (332115): -5.522 0.020 clock uncertainty
|
|
Info (332115): -5.522 0.000 uTh fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Data Arrival Time : 3.861
|
|
Info (332115): Data Required Time : -5.522
|
|
Info (332115): Slack : 9.383
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 10.089
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|rx_fref}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 10.089
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|rx_fref
|
|
Info (332115): Exception : dcp_bbs.sdc:3195: set_min_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pma_rxpma_rstb}] -10.000
|
|
Info (332115): Min Delay Exception : -10.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 1.946 1.946 R clock network delay
|
|
Info (332115): 1.946 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): 3.455 1.509 RR uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|rx_pma_rstb3
|
|
Info (332115): 3.455 0.000 RR IC fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_pma_rxpma_rstb
|
|
Info (332115): 3.455 0.000 RR CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): -10.000 -10.000 latch edge time
|
|
Info (332115): -6.520 3.480 R clock network delay
|
|
Info (332115): -6.400 0.120 clock uncertainty
|
|
Info (332115): -6.634 -0.234 uTh fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Data Arrival Time : 3.455
|
|
Info (332115): Data Required Time : -6.634
|
|
Info (332115): Slack : 10.089
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 10.106
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|rx_fref}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 10.106
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|rx_fref
|
|
Info (332115): Exception : dcp_bbs.sdc:3195: set_min_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pma_rxpma_rstb}] -10.000
|
|
Info (332115): Min Delay Exception : -10.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 1.946 1.946 R clock network delay
|
|
Info (332115): 1.946 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): 3.472 1.526 RR uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|rx_pma_rstb2
|
|
Info (332115): 3.472 0.000 RR IC fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_pma_rxpma_rstb
|
|
Info (332115): 3.472 0.000 RR CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): -10.000 -10.000 latch edge time
|
|
Info (332115): -6.520 3.480 R clock network delay
|
|
Info (332115): -6.400 0.120 clock uncertainty
|
|
Info (332115): -6.634 -0.234 uTh fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Data Arrival Time : 3.472
|
|
Info (332115): Data Required Time : -6.634
|
|
Info (332115): Slack : 10.106
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 10.310
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|rx_fref}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 10.310
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|rx_fref
|
|
Info (332115): Exception : dcp_bbs.sdc:3195: set_min_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pma_rxpma_rstb}] -10.000
|
|
Info (332115): Min Delay Exception : -10.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 1.946 1.946 R clock network delay
|
|
Info (332115): 1.946 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): 3.675 1.729 RR uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|rx_pma_rstb4
|
|
Info (332115): 3.676 0.001 RR IC fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_pma_rxpma_rstb
|
|
Info (332115): 3.676 0.000 RR CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): -10.000 -10.000 latch edge time
|
|
Info (332115): -6.520 3.480 R clock network delay
|
|
Info (332115): -6.400 0.120 clock uncertainty
|
|
Info (332115): -6.634 -0.234 uTh fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Data Arrival Time : 3.676
|
|
Info (332115): Data Required Time : -6.634
|
|
Info (332115): Slack : 10.310
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 10.337
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|rx_fref}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 10.337
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|rx_fref
|
|
Info (332115): Exception : dcp_bbs.sdc:3195: set_min_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pma_rxpma_rstb}] -10.000
|
|
Info (332115): Min Delay Exception : -10.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 1.946 1.946 R clock network delay
|
|
Info (332115): 1.946 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): 3.779 1.833 RR uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|rx_pma_rstb5
|
|
Info (332115): 3.779 0.000 RR IC fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_pma_rxpma_rstb
|
|
Info (332115): 3.779 0.000 RR CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): -10.000 -10.000 latch edge time
|
|
Info (332115): -6.444 3.556 R clock network delay
|
|
Info (332115): -6.324 0.120 clock uncertainty
|
|
Info (332115): -6.558 -0.234 uTh fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Data Arrival Time : 3.779
|
|
Info (332115): Data Required Time : -6.558
|
|
Info (332115): Slack : 10.337
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 10.377
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|rx_fref}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 10.377
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|rx_fref
|
|
Info (332115): Exception : dcp_bbs.sdc:3195: set_min_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pma_rxpma_rstb}] -10.000
|
|
Info (332115): Min Delay Exception : -10.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 1.946 1.946 R clock network delay
|
|
Info (332115): 1.946 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): 3.657 1.711 RR uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|rx_pma_rstb1
|
|
Info (332115): 3.657 0.000 RR IC fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_pma_rxpma_rstb
|
|
Info (332115): 3.657 0.000 RR CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): -10.000 -10.000 latch edge time
|
|
Info (332115): -6.606 3.394 R clock network delay
|
|
Info (332115): -6.486 0.120 clock uncertainty
|
|
Info (332115): -6.720 -0.234 uTh fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Data Arrival Time : 3.657
|
|
Info (332115): Data Required Time : -6.720
|
|
Info (332115): Slack : 10.377
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 10.433
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|rx_fref}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 10.433
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|rx_fref
|
|
Info (332115): Exception : dcp_bbs.sdc:3195: set_min_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pma_rxpma_rstb}] -10.000
|
|
Info (332115): Min Delay Exception : -10.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 1.946 1.946 R clock network delay
|
|
Info (332115): 1.946 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): 3.875 1.929 RR uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|rx_pma_rstb6
|
|
Info (332115): 3.875 0.000 RR IC fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_pma_rxpma_rstb
|
|
Info (332115): 3.875 0.000 RR CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): -10.000 -10.000 latch edge time
|
|
Info (332115): -6.444 3.556 R clock network delay
|
|
Info (332115): -6.324 0.120 clock uncertainty
|
|
Info (332115): -6.558 -0.234 uTh fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Data Arrival Time : 3.875
|
|
Info (332115): Data Required Time : -6.558
|
|
Info (332115): Slack : 10.433
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 10.837
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|rx_fref}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 10.837
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|rx_fref
|
|
Info (332115): Exception : dcp_bbs.sdc:3195: set_min_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pma_rxpma_rstb}] -10.000
|
|
Info (332115): Min Delay Exception : -10.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 1.946 1.946 R clock network delay
|
|
Info (332115): 1.946 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): 4.279 2.333 RR uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|rx_pma_rstb7
|
|
Info (332115): 4.279 0.000 RR IC fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_pma_rxpma_rstb
|
|
Info (332115): 4.279 0.000 RR CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): -10.000 -10.000 latch edge time
|
|
Info (332115): -6.444 3.556 R clock network delay
|
|
Info (332115): -6.324 0.120 clock uncertainty
|
|
Info (332115): -6.558 -0.234 uTh fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Data Arrival Time : 4.279
|
|
Info (332115): Data Required Time : -6.558
|
|
Info (332115): Slack : 10.837
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 12.463
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 12.463
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332115): Exception : dcp_bbs.sdc:3195: set_min_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pma_rxpma_rstb}] -10.000
|
|
Info (332115): Min Delay Exception : -10.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 1.946 1.946 R clock network delay
|
|
Info (332115): 1.946 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): 3.938 1.992 RR uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|rx_pma_rstb0
|
|
Info (332115): 3.939 0.001 RR IC fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_pma_rxpma_rstb
|
|
Info (332115): 3.939 0.000 RR CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): -10.000 -10.000 latch edge time
|
|
Info (332115): -6.606 3.394 R clock network delay
|
|
Info (332115): -8.320 -1.714 clock pessimism removed
|
|
Info (332115): -8.290 0.030 clock uncertainty
|
|
Info (332115): -8.524 -0.234 uTh fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Data Arrival Time : 3.939
|
|
Info (332115): Data Required Time : -8.524
|
|
Info (332115): Slack : 12.463
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 52.212
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|tx_coreclkin}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 52.212
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_avmm_csr_enabled.embedded_debug_soft_csr|g_control_reg.r_tx_digitalreset
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_10g_tx_pcs.inst_twentynm_hssi_10g_tx_pcs~pld_10g_krfec_tx_pld_rst_n_fifo.reg
|
|
Info (332115): Launch Clock : SYS_RefClk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|tx_coreclkin
|
|
Info (332115): Exception : dcp_bbs.sdc:3193: set_min_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_10g_krfec_tx_pld_rst_n}] -50.000
|
|
Info (332115): Min Delay Exception : -50.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 4.336 4.336 R clock network delay
|
|
Info (332115): 4.336 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_avmm_csr_enabled.embedded_debug_soft_csr|g_control_reg.r_tx_digitalreset
|
|
Info (332115): 4.558 0.222 FF uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_avmm_csr_enabled.embedded_debug_soft_csr|g_control_reg.r_tx_digitalreset|q
|
|
Info (332115): 4.622 0.064 FF CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_avmm_csr_enabled.embedded_debug_soft_csr|g_control_reg.r_tx_digitalreset~la_mlab/laboutb[17]
|
|
Info (332115): 4.871 0.249 FF IC Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0|datad
|
|
Info (332115): 4.999 0.128 FR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0|combout
|
|
Info (332115): 5.001 0.002 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0~la_mlab/laboutb[18]
|
|
Info (332115): 7.295 2.294 RR IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_tx_pld_pcs_interface.inst_twentynm_hssi_tx_pld_pcs_interface|pld_10g_krfec_tx_pld_rst_n
|
|
Info (332115): 7.295 0.000 RR CELL fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_10g_tx_pcs.inst_twentynm_hssi_10g_tx_pcs~pld_10g_krfec_tx_pld_rst_n_fifo.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): -50.000 -50.000 latch edge time
|
|
Info (332115): -44.983 5.017 R clock network delay
|
|
Info (332115): -44.914 0.069 clock uncertainty
|
|
Info (332115): -44.917 -0.003 uTh fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_10g_tx_pcs.inst_twentynm_hssi_10g_tx_pcs~pld_10g_krfec_tx_pld_rst_n_fifo.reg
|
|
Info (332115): Data Arrival Time : 7.295
|
|
Info (332115): Data Required Time : -44.917
|
|
Info (332115): Slack : 52.212
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 52.569
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|tx_coreclkin}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 52.569
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_avmm_csr_enabled.embedded_debug_soft_csr|g_control_reg.r_tx_digitalreset_override
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_10g_tx_pcs.inst_twentynm_hssi_10g_tx_pcs~pld_10g_krfec_tx_pld_rst_n_fifo.reg
|
|
Info (332115): Launch Clock : SYS_RefClk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|tx_coreclkin
|
|
Info (332115): Exception : dcp_bbs.sdc:3193: set_min_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_10g_krfec_tx_pld_rst_n}] -50.000
|
|
Info (332115): Min Delay Exception : -50.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 4.349 4.349 R clock network delay
|
|
Info (332115): 4.349 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_avmm_csr_enabled.embedded_debug_soft_csr|g_control_reg.r_tx_digitalreset_override
|
|
Info (332115): 4.552 0.203 FF uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_avmm_csr_enabled.embedded_debug_soft_csr|g_control_reg.r_tx_digitalreset_override|q
|
|
Info (332115): 4.552 0.000 FF CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0|datae
|
|
Info (332115): 4.937 0.385 FR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0|combout
|
|
Info (332115): 4.939 0.002 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0~la_lab/laboutb[16]
|
|
Info (332115): 7.524 2.585 RR IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_tx_pld_pcs_interface.inst_twentynm_hssi_tx_pld_pcs_interface|pld_10g_krfec_tx_pld_rst_n
|
|
Info (332115): 7.524 0.000 RR CELL fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_10g_tx_pcs.inst_twentynm_hssi_10g_tx_pcs~pld_10g_krfec_tx_pld_rst_n_fifo.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): -50.000 -50.000 latch edge time
|
|
Info (332115): -45.111 4.889 R clock network delay
|
|
Info (332115): -45.042 0.069 clock uncertainty
|
|
Info (332115): -45.045 -0.003 uTh fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_10g_tx_pcs.inst_twentynm_hssi_10g_tx_pcs~pld_10g_krfec_tx_pld_rst_n_fifo.reg
|
|
Info (332115): Data Arrival Time : 7.524
|
|
Info (332115): Data Required Time : -45.045
|
|
Info (332115): Slack : 52.569
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 52.721
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|tx_coreclkin}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 52.721
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_avmm_csr_enabled.embedded_debug_soft_csr|g_control_reg.r_tx_digitalreset_override
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_10g_tx_pcs.inst_twentynm_hssi_10g_tx_pcs~pld_10g_krfec_tx_pld_rst_n_fifo.reg
|
|
Info (332115): Launch Clock : SYS_RefClk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|tx_coreclkin
|
|
Info (332115): Exception : dcp_bbs.sdc:3193: set_min_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_10g_krfec_tx_pld_rst_n}] -50.000
|
|
Info (332115): Min Delay Exception : -50.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 4.349 4.349 R clock network delay
|
|
Info (332115): 4.349 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_avmm_csr_enabled.embedded_debug_soft_csr|g_control_reg.r_tx_digitalreset_override
|
|
Info (332115): 4.560 0.211 FF uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_avmm_csr_enabled.embedded_debug_soft_csr|g_control_reg.r_tx_digitalreset_override|q
|
|
Info (332115): 4.560 0.000 FF CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0|datae
|
|
Info (332115): 4.944 0.384 FR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0|combout
|
|
Info (332115): 4.946 0.002 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0~la_lab/laboutt[8]
|
|
Info (332115): 7.675 2.729 RR IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_tx_pld_pcs_interface.inst_twentynm_hssi_tx_pld_pcs_interface|pld_10g_krfec_tx_pld_rst_n
|
|
Info (332115): 7.675 0.000 RR CELL fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_10g_tx_pcs.inst_twentynm_hssi_10g_tx_pcs~pld_10g_krfec_tx_pld_rst_n_fifo.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): -50.000 -50.000 latch edge time
|
|
Info (332115): -45.112 4.888 R clock network delay
|
|
Info (332115): -45.043 0.069 clock uncertainty
|
|
Info (332115): -45.046 -0.003 uTh fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_10g_tx_pcs.inst_twentynm_hssi_10g_tx_pcs~pld_10g_krfec_tx_pld_rst_n_fifo.reg
|
|
Info (332115): Data Arrival Time : 7.675
|
|
Info (332115): Data Required Time : -45.046
|
|
Info (332115): Slack : 52.721
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 52.779
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|tx_coreclkin}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 52.779
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_avmm_csr_enabled.embedded_debug_soft_csr|g_control_reg.r_tx_digitalreset_override
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_10g_tx_pcs.inst_twentynm_hssi_10g_tx_pcs~pld_10g_krfec_tx_pld_rst_n_fifo.reg
|
|
Info (332115): Launch Clock : SYS_RefClk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|tx_coreclkin
|
|
Info (332115): Exception : dcp_bbs.sdc:3193: set_min_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_10g_krfec_tx_pld_rst_n}] -50.000
|
|
Info (332115): Min Delay Exception : -50.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 4.310 4.310 R clock network delay
|
|
Info (332115): 4.310 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_avmm_csr_enabled.embedded_debug_soft_csr|g_control_reg.r_tx_digitalreset_override
|
|
Info (332115): 4.493 0.183 FF uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_avmm_csr_enabled.embedded_debug_soft_csr|g_control_reg.r_tx_digitalreset_override|q
|
|
Info (332115): 4.554 0.061 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_avmm_csr_enabled.embedded_debug_soft_csr|g_control_reg.r_tx_digitalreset_override~la_lab/laboutt[13]
|
|
Info (332115): 4.928 0.374 FF IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0|dataa
|
|
Info (332115): 5.128 0.200 FR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0|combout
|
|
Info (332115): 5.130 0.002 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0~la_mlab/laboutb[18]
|
|
Info (332115): 7.721 2.591 RR IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_tx_pld_pcs_interface.inst_twentynm_hssi_tx_pld_pcs_interface|pld_10g_krfec_tx_pld_rst_n
|
|
Info (332115): 7.721 0.000 RR CELL fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_10g_tx_pcs.inst_twentynm_hssi_10g_tx_pcs~pld_10g_krfec_tx_pld_rst_n_fifo.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): -50.000 -50.000 latch edge time
|
|
Info (332115): -45.124 4.876 R clock network delay
|
|
Info (332115): -45.055 0.069 clock uncertainty
|
|
Info (332115): -45.058 -0.003 uTh fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_10g_tx_pcs.inst_twentynm_hssi_10g_tx_pcs~pld_10g_krfec_tx_pld_rst_n_fifo.reg
|
|
Info (332115): Data Arrival Time : 7.721
|
|
Info (332115): Data Required Time : -45.058
|
|
Info (332115): Slack : 52.779
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 53.594
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|tx_pma_clk}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 53.594
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_avmm_csr_enabled.embedded_debug_soft_csr|g_control_reg.r_tx_digitalreset
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_tx_pld_pcs_interface.inst_twentynm_hssi_tx_pld_pcs_interface~pld_pmaif_tx_pld_rst_n_reg.reg
|
|
Info (332115): Launch Clock : SYS_RefClk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|tx_pma_clk
|
|
Info (332115): Exception : dcp_bbs.sdc:3191: set_min_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pmaif_tx_pld_rst_n}] -50.000
|
|
Info (332115): Min Delay Exception : -50.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 4.336 4.336 R clock network delay
|
|
Info (332115): 4.336 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_avmm_csr_enabled.embedded_debug_soft_csr|g_control_reg.r_tx_digitalreset
|
|
Info (332115): 4.558 0.222 FF uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_avmm_csr_enabled.embedded_debug_soft_csr|g_control_reg.r_tx_digitalreset|q
|
|
Info (332115): 4.622 0.064 FF CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_avmm_csr_enabled.embedded_debug_soft_csr|g_control_reg.r_tx_digitalreset~la_mlab/laboutb[17]
|
|
Info (332115): 4.871 0.249 FF IC Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0|datad
|
|
Info (332115): 4.999 0.128 FR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0|combout
|
|
Info (332115): 5.001 0.002 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0~la_mlab/laboutb[18]
|
|
Info (332115): 7.140 2.139 RR IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_tx_pld_pcs_interface.inst_twentynm_hssi_tx_pld_pcs_interface|pld_pmaif_tx_pld_rst_n
|
|
Info (332115): 7.140 0.000 RR CELL fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_tx_pld_pcs_interface.inst_twentynm_hssi_tx_pld_pcs_interface~pld_pmaif_tx_pld_rst_n_reg.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): -50.000 -50.000 latch edge time
|
|
Info (332115): -46.634 3.366 R clock network delay
|
|
Info (332115): -46.564 0.070 clock uncertainty
|
|
Info (332115): -46.454 0.110 uTh fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_tx_pld_pcs_interface.inst_twentynm_hssi_tx_pld_pcs_interface~pld_pmaif_tx_pld_rst_n_reg.reg
|
|
Info (332115): Data Arrival Time : 7.140
|
|
Info (332115): Data Required Time : -46.454
|
|
Info (332115): Slack : 53.594
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 53.775
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|tx_pma_clk}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 53.775
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_avmm_csr_enabled.embedded_debug_soft_csr|g_control_reg.r_tx_digitalreset_override
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs~pld_8g_g3_tx_pld_rst_n_reg.reg
|
|
Info (332115): Launch Clock : SYS_RefClk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|tx_pma_clk
|
|
Info (332115): Exception : dcp_bbs.sdc:3192: set_min_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_8g_g3_tx_pld_rst_n}] -50.000
|
|
Info (332115): Min Delay Exception : -50.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 4.349 4.349 R clock network delay
|
|
Info (332115): 4.349 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_avmm_csr_enabled.embedded_debug_soft_csr|g_control_reg.r_tx_digitalreset_override
|
|
Info (332115): 4.552 0.203 FF uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_avmm_csr_enabled.embedded_debug_soft_csr|g_control_reg.r_tx_digitalreset_override|q
|
|
Info (332115): 4.552 0.000 FF CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0|datae
|
|
Info (332115): 4.937 0.385 FR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0|combout
|
|
Info (332115): 4.939 0.002 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0~la_lab/laboutb[16]
|
|
Info (332115): 7.524 2.585 RR IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_tx_pld_pcs_interface.inst_twentynm_hssi_tx_pld_pcs_interface|pld_8g_g3_tx_pld_rst_n
|
|
Info (332115): 7.524 0.000 RR CELL fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs~pld_8g_g3_tx_pld_rst_n_reg.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): -50.000 -50.000 latch edge time
|
|
Info (332115): -46.634 3.366 R clock network delay
|
|
Info (332115): -46.564 0.070 clock uncertainty
|
|
Info (332115): -46.251 0.313 uTh fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs~pld_8g_g3_tx_pld_rst_n_reg.reg
|
|
Info (332115): Data Arrival Time : 7.524
|
|
Info (332115): Data Required Time : -46.251
|
|
Info (332115): Slack : 53.775
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 53.964
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|tx_pma_clk}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 53.964
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_avmm_csr_enabled.embedded_debug_soft_csr|g_control_reg.r_tx_digitalreset_override
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs~pld_8g_g3_tx_pld_rst_n_reg.reg
|
|
Info (332115): Launch Clock : SYS_RefClk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|tx_pma_clk
|
|
Info (332115): Exception : dcp_bbs.sdc:3192: set_min_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_8g_g3_tx_pld_rst_n}] -50.000
|
|
Info (332115): Min Delay Exception : -50.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 4.349 4.349 R clock network delay
|
|
Info (332115): 4.349 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_avmm_csr_enabled.embedded_debug_soft_csr|g_control_reg.r_tx_digitalreset_override
|
|
Info (332115): 4.560 0.211 FF uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_avmm_csr_enabled.embedded_debug_soft_csr|g_control_reg.r_tx_digitalreset_override|q
|
|
Info (332115): 4.560 0.000 FF CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0|datae
|
|
Info (332115): 4.944 0.384 FR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0|combout
|
|
Info (332115): 4.946 0.002 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0~la_lab/laboutt[8]
|
|
Info (332115): 7.677 2.731 RR IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_tx_pld_pcs_interface.inst_twentynm_hssi_tx_pld_pcs_interface|pld_8g_g3_tx_pld_rst_n
|
|
Info (332115): 7.677 0.000 RR CELL fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs~pld_8g_g3_tx_pld_rst_n_reg.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): -50.000 -50.000 latch edge time
|
|
Info (332115): -46.670 3.330 R clock network delay
|
|
Info (332115): -46.600 0.070 clock uncertainty
|
|
Info (332115): -46.287 0.313 uTh fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs~pld_8g_g3_tx_pld_rst_n_reg.reg
|
|
Info (332115): Data Arrival Time : 7.677
|
|
Info (332115): Data Required Time : -46.287
|
|
Info (332115): Slack : 53.964
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 54.008
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|tx_pma_clk}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 54.008
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_avmm_csr_enabled.embedded_debug_soft_csr|g_control_reg.r_tx_digitalreset_override
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs~pld_8g_g3_tx_pld_rst_n_reg.reg
|
|
Info (332115): Launch Clock : SYS_RefClk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|tx_pma_clk
|
|
Info (332115): Exception : dcp_bbs.sdc:3192: set_min_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_8g_g3_tx_pld_rst_n}] -50.000
|
|
Info (332115): Min Delay Exception : -50.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 4.310 4.310 R clock network delay
|
|
Info (332115): 4.310 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_avmm_csr_enabled.embedded_debug_soft_csr|g_control_reg.r_tx_digitalreset_override
|
|
Info (332115): 4.493 0.183 FF uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_avmm_csr_enabled.embedded_debug_soft_csr|g_control_reg.r_tx_digitalreset_override|q
|
|
Info (332115): 4.554 0.061 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_avmm_csr_enabled.embedded_debug_soft_csr|g_control_reg.r_tx_digitalreset_override~la_lab/laboutt[13]
|
|
Info (332115): 4.928 0.374 FF IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0|dataa
|
|
Info (332115): 5.128 0.200 FR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0|combout
|
|
Info (332115): 5.130 0.002 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0~la_mlab/laboutb[18]
|
|
Info (332115): 7.721 2.591 RR IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_tx_pld_pcs_interface.inst_twentynm_hssi_tx_pld_pcs_interface|pld_8g_g3_tx_pld_rst_n
|
|
Info (332115): 7.721 0.000 RR CELL fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs~pld_8g_g3_tx_pld_rst_n_reg.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): -50.000 -50.000 latch edge time
|
|
Info (332115): -46.670 3.330 R clock network delay
|
|
Info (332115): -46.600 0.070 clock uncertainty
|
|
Info (332115): -46.287 0.313 uTh fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs~pld_8g_g3_tx_pld_rst_n_reg.reg
|
|
Info (332115): Data Arrival Time : 7.721
|
|
Info (332115): Data Required Time : -46.287
|
|
Info (332115): Slack : 54.008
|
|
Info (332115): ===================================================================
|
|
Info: Analyzing Slow 900mV 0C Model
|
|
Info (332146): Worst-case setup slack is -1.333
|
|
Info (332119): Slack End Point TNS Clock
|
|
Info (332119): ========= =================== =====================
|
|
Info (332119): -1.333 -12442.463 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk1
|
|
Info (332119): 0.079 0.000 mem|ddr4b|ddr4b_phy_clk_l_1
|
|
Info (332119): 0.090 0.000 mem|ddr4b|ddr4b_phy_clk_l_0
|
|
Info (332119): 0.100 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|wys~CORE_CLK_OUT
|
|
Info (332119): 0.118 0.000 mem|ddr4a|ddr4a_phy_clk_l_2
|
|
Info (332119): 0.192 0.000 mem|ddr4a|ddr4a_phy_clk_l_1
|
|
Info (332119): 0.213 0.000 mem|ddr4a|ddr4a_core_usr_clk
|
|
Info (332119): 0.280 0.000 mem|ddr4b|ddr4b_phy_clk_l_2
|
|
Info (332119): 0.494 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_bonding_clocks[0]
|
|
Info (332119): 0.633 0.000 mem|ddr4a|ddr4a_phy_clk_l_0
|
|
Info (332119): 0.704 0.000 u0|dcp_iopll|dcp_iopll|clk100
|
|
Info (332119): 0.720 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|pld_clk
|
|
Info (332119): 0.729 0.000 u0|dcp_iopll|dcp_iopll|clk1x
|
|
Info (332119): 1.172 0.000 PCIE_REFCLK
|
|
Info (332119): 1.467 0.000 mem|ddr4a|ddr4a_core_cal_slave_clk
|
|
Info (332119): 1.727 0.000 SYS_RefClk
|
|
Info (332119): 2.222 0.000 DDR4_RefClk
|
|
Info (332119): 2.320 0.000 ETH_RefClk
|
|
Info (332119): 2.323 0.000 hssi_pll_r_0_outclk0
|
|
Info (332119): 2.357 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_clk
|
|
Info (332119): 2.357 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|rx_pma_clk
|
|
Info (332119): 2.366 0.000 hssi_pll_t_outclk0
|
|
Info (332119): 2.482 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|rx_pma_clk
|
|
Info (332119): 2.547 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|rx_pma_clk
|
|
Info (332119): 2.946 0.000 hssi_pll_r_0_outclk1
|
|
Info (332119): 3.017 0.000 hssi_pll_t_outclk1
|
|
Info (332119): 3.295 0.000 vl_qph_user_clk_clkpsc_clk1
|
|
Info (332119): 3.838 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|avmmclk
|
|
Info (332119): 3.882 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|avmmclk
|
|
Info (332119): 4.004 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|avmmclk
|
|
Info (332119): 4.810 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|avmmclk
|
|
Info (332119): 4.844 0.000 fspi_sclk
|
|
Info (332119): 4.877 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|avmmclk
|
|
Info (332119): 5.308 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|avmmclk
|
|
Info (332119): 5.596 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|tx_pma_div_clk
|
|
Info (332119): 5.604 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|avmmclk
|
|
Info (332119): 5.662 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_div_clk
|
|
Info (332119): 5.843 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|avmmclk
|
|
Info (332119): 6.128 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|avmmclk
|
|
Info (332119): 6.423 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|avmmclk
|
|
Info (332119): 6.631 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|avmmclk
|
|
Info (332119): 7.562 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|avmmclk
|
|
Info (332119): 7.840 0.000 vl_qph_user_clk_clkpsc_clk0
|
|
Info (332119): 8.509 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk0
|
|
Info (332119): 10.925 0.000 pr_clk_enable_dclk_reg2_user_clk
|
|
Info (332119): 18.344 0.000 u0|dcp_iopll|dcp_iopll|clk25
|
|
Info (332119): 19.258 0.000 u0|dcp_iopll|dcp_iopll|clk50
|
|
Info (332119): 19.572 0.000 filtered_sclk_negedge
|
|
Info (332119): 40.720 0.000 altera_reserved_tck
|
|
Info (332146): Worst-case hold slack is 0.031
|
|
Info (332119): Slack End Point TNS Clock
|
|
Info (332119): ========= =================== =====================
|
|
Info (332119): 0.031 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk1
|
|
Info (332119): 0.038 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|wys~CORE_CLK_OUT
|
|
Info (332119): 0.041 0.000 u0|dcp_iopll|dcp_iopll|clk1x
|
|
Info (332119): 0.044 0.000 SYS_RefClk
|
|
Info (332119): 0.045 0.000 u0|dcp_iopll|dcp_iopll|clk25
|
|
Info (332119): 0.048 0.000 altera_reserved_tck
|
|
Info (332119): 0.048 0.000 mem|ddr4a|ddr4a_core_usr_clk
|
|
Info (332119): 0.049 0.000 u0|dcp_iopll|dcp_iopll|clk100
|
|
Info (332119): 0.052 0.000 PCIE_REFCLK
|
|
Info (332119): 0.057 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_clk
|
|
Info (332119): 0.057 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|rx_pma_clk
|
|
Info (332119): 0.058 0.000 filtered_sclk_negedge
|
|
Info (332119): 0.059 0.000 DDR4_RefClk
|
|
Info (332119): 0.059 0.000 mem|ddr4a|ddr4a_core_cal_slave_clk
|
|
Info (332119): 0.064 0.000 ETH_RefClk
|
|
Info (332119): 0.064 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_div_clk
|
|
Info (332119): 0.064 0.000 hssi_pll_t_outclk1
|
|
Info (332119): 0.067 0.000 hssi_pll_r_0_outclk0
|
|
Info (332119): 0.072 0.000 u0|dcp_iopll|dcp_iopll|clk50
|
|
Info (332119): 0.076 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|tx_pma_div_clk
|
|
Info (332119): 0.076 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|rx_pma_clk
|
|
Info (332119): 0.080 0.000 hssi_pll_r_0_outclk1
|
|
Info (332119): 0.086 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|rx_pma_clk
|
|
Info (332119): 0.093 0.000 hssi_pll_t_outclk0
|
|
Info (332119): 0.097 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk0
|
|
Info (332119): 0.101 0.000 fspi_sclk
|
|
Info (332119): 0.138 0.000 mem|ddr4a|ddr4a_phy_clk_l_2
|
|
Info (332119): 0.181 0.000 mem|ddr4a|ddr4a_phy_clk_l_1
|
|
Info (332119): 0.183 0.000 mem|ddr4b|ddr4b_phy_clk_l_1
|
|
Info (332119): 0.189 0.000 mem|ddr4b|ddr4b_phy_clk_l_2
|
|
Info (332119): 0.212 0.000 mem|ddr4b|ddr4b_phy_clk_l_0
|
|
Info (332119): 0.254 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_bonding_clocks[0]
|
|
Info (332119): 0.271 0.000 mem|ddr4a|ddr4a_phy_clk_l_0
|
|
Info (332119): 0.483 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|pld_clk
|
|
Info (332119): 0.588 0.000 vl_qph_user_clk_clkpsc_clk0
|
|
Info (332119): 0.588 0.000 vl_qph_user_clk_clkpsc_clk1
|
|
Info (332119): 0.593 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|avmmclk
|
|
Info (332119): 0.651 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|avmmclk
|
|
Info (332119): 0.725 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|avmmclk
|
|
Info (332119): 0.773 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|avmmclk
|
|
Info (332119): 0.853 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|avmmclk
|
|
Info (332119): 0.910 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|avmmclk
|
|
Info (332119): 0.913 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|avmmclk
|
|
Info (332119): 1.028 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|avmmclk
|
|
Info (332119): 1.124 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|avmmclk
|
|
Info (332119): 1.325 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|avmmclk
|
|
Info (332119): 1.379 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|avmmclk
|
|
Info (332119): 1.623 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|avmmclk
|
|
Info (332119): 6.632 0.000 pr_clk_enable_dclk_reg2_user_clk
|
|
Info (332146): Worst-case recovery slack is 0.376
|
|
Info (332119): Slack End Point TNS Clock
|
|
Info (332119): ========= =================== =====================
|
|
Info (332119): 0.376 0.000 mem|ddr4a|ddr4a_core_usr_clk
|
|
Info (332119): 0.629 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|wys~CORE_CLK_OUT
|
|
Info (332119): 1.061 0.000 u0|dcp_iopll|dcp_iopll|clk1x
|
|
Info (332119): 1.371 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk1
|
|
Info (332119): 1.376 0.000 u0|dcp_iopll|dcp_iopll|clk100
|
|
Info (332119): 2.005 0.000 SYS_RefClk
|
|
Info (332119): 2.256 0.000 filtered_sclk_negedge
|
|
Info (332119): 2.494 0.000 mem|ddr4a|ddr4a_core_cal_slave_clk
|
|
Info (332119): 2.678 0.000 u0|dcp_iopll|dcp_iopll|clk25
|
|
Info (332119): 2.861 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|rx_pma_clk
|
|
Info (332119): 2.868 0.000 DDR4_RefClk
|
|
Info (332119): 2.950 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_clk
|
|
Info (332119): 2.952 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|rx_pma_clk
|
|
Info (332119): 3.043 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|rx_pma_clk
|
|
Info (332119): 4.758 0.000 fspi_sclk
|
|
Info (332119): 5.127 0.000 PCIE_REFCLK
|
|
Info (332119): 14.223 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|rx_fref
|
|
Info (332119): 14.760 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|rx_fref
|
|
Info (332119): 14.882 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|rx_fref
|
|
Info (332119): 14.897 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|rx_fref
|
|
Info (332119): 14.926 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|rx_fref
|
|
Info (332119): 15.202 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|rx_fref
|
|
Info (332119): 15.221 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|rx_fref
|
|
Info (332119): 16.104 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|rx_pma_clk
|
|
Info (332119): 16.446 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332119): 16.641 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|rx_pma_clk
|
|
Info (332119): 16.763 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|rx_pma_clk
|
|
Info (332119): 16.776 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_pma_clk
|
|
Info (332119): 16.778 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|rx_pma_clk
|
|
Info (332119): 16.807 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|rx_pma_clk
|
|
Info (332119): 17.083 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|rx_pma_clk
|
|
Info (332119): 17.102 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|rx_pma_clk
|
|
Info (332119): 40.236 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|tx_pma_clk
|
|
Info (332119): 40.457 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|tx_pma_clk
|
|
Info (332119): 40.482 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|tx_pma_clk
|
|
Info (332119): 40.947 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|tx_pma_clk
|
|
Info (332119): 42.449 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|tx_coreclkin
|
|
Info (332119): 42.863 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|tx_coreclkin
|
|
Info (332119): 42.904 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|tx_coreclkin
|
|
Info (332119): 43.017 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|tx_coreclkin
|
|
Info (332119): 97.347 0.000 altera_reserved_tck
|
|
Info (332146): Worst-case removal slack is 0.142
|
|
Info (332119): Slack End Point TNS Clock
|
|
Info (332119): ========= =================== =====================
|
|
Info (332119): 0.142 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|wys~CORE_CLK_OUT
|
|
Info (332119): 0.188 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk1
|
|
Info (332119): 0.313 0.000 u0|dcp_iopll|dcp_iopll|clk1x
|
|
Info (332119): 0.325 0.000 SYS_RefClk
|
|
Info (332119): 0.340 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_clk
|
|
Info (332119): 0.342 0.000 mem|ddr4a|ddr4a_core_usr_clk
|
|
Info (332119): 0.356 0.000 u0|dcp_iopll|dcp_iopll|clk100
|
|
Info (332119): 0.370 0.000 PCIE_REFCLK
|
|
Info (332119): 0.381 0.000 mem|ddr4a|ddr4a_core_cal_slave_clk
|
|
Info (332119): 0.402 0.000 DDR4_RefClk
|
|
Info (332119): 0.411 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|rx_pma_clk
|
|
Info (332119): 0.427 0.000 u0|dcp_iopll|dcp_iopll|clk25
|
|
Info (332119): 0.434 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|rx_pma_clk
|
|
Info (332119): 0.461 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|rx_pma_clk
|
|
Info (332119): 0.867 0.000 altera_reserved_tck
|
|
Info (332119): 1.793 0.000 fspi_sclk
|
|
Info (332119): 4.837 0.000 filtered_sclk_negedge
|
|
Info (332119): 8.547 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|rx_pma_clk
|
|
Info (332119): 8.547 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|rx_pma_clk
|
|
Info (332119): 8.844 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|rx_pma_clk
|
|
Info (332119): 8.875 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|rx_pma_clk
|
|
Info (332119): 8.896 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|rx_pma_clk
|
|
Info (332119): 8.952 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|rx_pma_clk
|
|
Info (332119): 9.486 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|rx_pma_clk
|
|
Info (332119): 9.513 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_pma_clk
|
|
Info (332119): 10.242 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|rx_fref
|
|
Info (332119): 10.258 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|rx_fref
|
|
Info (332119): 10.501 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|rx_fref
|
|
Info (332119): 10.516 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|rx_fref
|
|
Info (332119): 10.570 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|rx_fref
|
|
Info (332119): 10.623 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|rx_fref
|
|
Info (332119): 11.094 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|rx_fref
|
|
Info (332119): 12.749 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332119): 51.952 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|tx_coreclkin
|
|
Info (332119): 52.441 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|tx_coreclkin
|
|
Info (332119): 52.465 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|tx_coreclkin
|
|
Info (332119): 52.500 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|tx_coreclkin
|
|
Info (332119): 53.433 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|tx_pma_clk
|
|
Info (332119): 53.678 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|tx_pma_clk
|
|
Info (332119): 53.750 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|tx_pma_clk
|
|
Info (332119): 53.808 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|tx_pma_clk
|
|
Info (332146): Worst-case minimum pulse width slack is 0.092
|
|
Info (332119): Slack End Point TNS Clock
|
|
Info (332119): ========= =================== =====================
|
|
Info (332119): 0.092 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|atx0|altera_xcvr_atx_pll_ip_inst|mcgb_serial_clk
|
|
Info (332119): 0.124 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|twentynm_atx_pll_inst~O_CLK0_8G
|
|
Info (332119): 0.142 0.000 DDR4A_DQS_P[3]_IN
|
|
Info (332119): 0.142 0.000 DDR4A_DQS_P[4]_IN
|
|
Info (332119): 0.142 0.000 DDR4B_DQS_P[3]_IN
|
|
Info (332119): 0.142 0.000 DDR4B_DQS_P[4]_IN
|
|
Info (332119): 0.143 0.000 DDR4A_DQS_P[0]_IN
|
|
Info (332119): 0.143 0.000 DDR4A_DQS_P[1]_IN
|
|
Info (332119): 0.143 0.000 DDR4A_DQS_P[2]_IN
|
|
Info (332119): 0.143 0.000 DDR4A_DQS_P[5]_IN
|
|
Info (332119): 0.143 0.000 DDR4A_DQS_P[6]_IN
|
|
Info (332119): 0.143 0.000 DDR4A_DQS_P[7]_IN
|
|
Info (332119): 0.143 0.000 DDR4B_DQS_P[0]_IN
|
|
Info (332119): 0.143 0.000 DDR4B_DQS_P[1]_IN
|
|
Info (332119): 0.143 0.000 DDR4B_DQS_P[2]_IN
|
|
Info (332119): 0.143 0.000 DDR4B_DQS_P[5]_IN
|
|
Info (332119): 0.143 0.000 DDR4B_DQS_P[6]_IN
|
|
Info (332119): 0.143 0.000 DDR4B_DQS_P[7]_IN
|
|
Info (332119): 0.200 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_serial_clk
|
|
Info (332119): 0.432 0.000 mem|ddr4a|ddr4a_wf_clk_0
|
|
Info (332119): 0.432 0.000 mem|ddr4a|ddr4a_wf_clk_2
|
|
Info (332119): 0.432 0.000 mem|ddr4b|ddr4b_wf_clk_0
|
|
Info (332119): 0.432 0.000 mem|ddr4b|ddr4b_wf_clk_2
|
|
Info (332119): 0.433 0.000 mem|ddr4a|ddr4a_wf_clk_1
|
|
Info (332119): 0.433 0.000 mem|ddr4b|ddr4b_wf_clk_1
|
|
Info (332119): 0.437 0.000 mem|ddr4a|ddr4a_vco_clk
|
|
Info (332119): 0.445 0.000 mem|ddr4a|ddr4a_wf_clk_10
|
|
Info (332119): 0.445 0.000 mem|ddr4a|ddr4a_wf_clk_5
|
|
Info (332119): 0.445 0.000 mem|ddr4a|ddr4a_wf_clk_8
|
|
Info (332119): 0.445 0.000 mem|ddr4b|ddr4b_wf_clk_3
|
|
Info (332119): 0.445 0.000 mem|ddr4b|ddr4b_wf_clk_5
|
|
Info (332119): 0.445 0.000 mem|ddr4b|ddr4b_wf_clk_8
|
|
Info (332119): 0.446 0.000 mem|ddr4a|ddr4a_wf_clk_3
|
|
Info (332119): 0.446 0.000 mem|ddr4a|ddr4a_wf_clk_4
|
|
Info (332119): 0.446 0.000 mem|ddr4a|ddr4a_wf_clk_6
|
|
Info (332119): 0.446 0.000 mem|ddr4a|ddr4a_wf_clk_7
|
|
Info (332119): 0.446 0.000 mem|ddr4a|ddr4a_wf_clk_9
|
|
Info (332119): 0.446 0.000 mem|ddr4b|ddr4b_wf_clk_10
|
|
Info (332119): 0.446 0.000 mem|ddr4b|ddr4b_wf_clk_4
|
|
Info (332119): 0.446 0.000 mem|ddr4b|ddr4b_wf_clk_6
|
|
Info (332119): 0.446 0.000 mem|ddr4b|ddr4b_wf_clk_7
|
|
Info (332119): 0.446 0.000 mem|ddr4b|ddr4b_wf_clk_9
|
|
Info (332119): 0.464 0.000 mem|ddr4a|ddr4a_vco_clk_1
|
|
Info (332119): 0.464 0.000 mem|ddr4a|ddr4a_vco_clk_2
|
|
Info (332119): 0.464 0.000 mem|ddr4b|ddr4b_vco_clk_0
|
|
Info (332119): 0.464 0.000 mem|ddr4b|ddr4b_vco_clk_1
|
|
Info (332119): 0.464 0.000 mem|ddr4b|ddr4b_vco_clk_2
|
|
Info (332119): 0.574 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_bonding_clocks[0]
|
|
Info (332119): 0.773 0.000 mem|ddr4a|ddr4a_phy_clk_0
|
|
Info (332119): 0.773 0.000 mem|ddr4a|ddr4a_phy_clk_1
|
|
Info (332119): 0.773 0.000 mem|ddr4a|ddr4a_phy_clk_2
|
|
Info (332119): 0.773 0.000 mem|ddr4b|ddr4b_phy_clk_0
|
|
Info (332119): 0.773 0.000 mem|ddr4b|ddr4b_phy_clk_1
|
|
Info (332119): 0.773 0.000 mem|ddr4b|ddr4b_phy_clk_2
|
|
Info (332119): 0.807 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_pma_clk
|
|
Info (332119): 0.807 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|rx_pma_clk
|
|
Info (332119): 0.807 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|rx_pma_clk
|
|
Info (332119): 0.807 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|rx_pma_clk
|
|
Info (332119): 0.807 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|rx_pma_clk
|
|
Info (332119): 0.807 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|rx_pma_clk
|
|
Info (332119): 0.807 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|rx_pma_clk
|
|
Info (332119): 0.807 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|rx_pma_clk
|
|
Info (332119): 0.826 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_clk
|
|
Info (332119): 0.826 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|rx_clk
|
|
Info (332119): 0.826 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|rx_clk
|
|
Info (332119): 0.826 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|rx_clk
|
|
Info (332119): 0.826 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|rx_clk
|
|
Info (332119): 0.826 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|rx_clk
|
|
Info (332119): 0.826 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|rx_clk
|
|
Info (332119): 0.826 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|rx_clk
|
|
Info (332119): 0.828 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_pcs_clk_div_by_4[0]
|
|
Info (332119): 0.828 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_pcs_clk_div_by_4[1]
|
|
Info (332119): 0.828 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_pcs_clk_div_by_4[2]
|
|
Info (332119): 0.828 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_pcs_clk_div_by_4[3]
|
|
Info (332119): 0.828 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_pcs_clk_div_by_4[4]
|
|
Info (332119): 0.828 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_pcs_clk_div_by_4[5]
|
|
Info (332119): 0.828 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_pcs_clk_div_by_4[6]
|
|
Info (332119): 0.828 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_pcs_clk_div_by_4[7]
|
|
Info (332119): 0.838 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|rx_pcs_clk_div_by_4[0]
|
|
Info (332119): 0.838 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|rx_pcs_clk_div_by_4[1]
|
|
Info (332119): 0.838 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|rx_pcs_clk_div_by_4[2]
|
|
Info (332119): 0.838 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|rx_pcs_clk_div_by_4[3]
|
|
Info (332119): 0.838 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|rx_pcs_clk_div_by_4[4]
|
|
Info (332119): 0.838 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|rx_pcs_clk_div_by_4[5]
|
|
Info (332119): 0.838 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|rx_pcs_clk_div_by_4[6]
|
|
Info (332119): 0.838 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|rx_pcs_clk_div_by_4[7]
|
|
Info (332119): 0.879 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|hip_cmn_clk[0]
|
|
Info (332119): 0.880 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|pll_pcie_clk
|
|
Info (332119): 1.227 0.000 ETH_RefClk
|
|
Info (332119): 1.406 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|tx_coreclkin
|
|
Info (332119): 1.406 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|tx_coreclkin
|
|
Info (332119): 1.406 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|tx_coreclkin
|
|
Info (332119): 1.406 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|tx_coreclkin
|
|
Info (332119): 1.430 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|wys~CORE_CLK_OUT
|
|
Info (332119): 1.456 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_coreclkin
|
|
Info (332119): 1.456 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|rx_coreclkin
|
|
Info (332119): 1.456 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|rx_coreclkin
|
|
Info (332119): 1.456 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|rx_coreclkin
|
|
Info (332119): 1.489 0.000 mem|ddr4a|ddr4a_core_usr_clk
|
|
Info (332119): 1.558 0.000 hssi_pll_t_outclk0
|
|
Info (332119): 1.564 0.000 hssi_pll_r_0_outclk0
|
|
Info (332119): 1.573 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|tx_pma_clk
|
|
Info (332119): 1.573 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|tx_pma_clk
|
|
Info (332119): 1.573 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|tx_pma_clk
|
|
Info (332119): 1.573 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|tx_pma_clk
|
|
Info (332119): 1.697 0.000 DDR4_RefClk
|
|
Info (332119): 1.714 0.000 mem|ddr4a|ddr4a_phy_clk_l_0
|
|
Info (332119): 1.714 0.000 mem|ddr4a|ddr4a_phy_clk_l_1
|
|
Info (332119): 1.714 0.000 mem|ddr4a|ddr4a_phy_clk_l_2
|
|
Info (332119): 1.714 0.000 mem|ddr4b|ddr4b_phy_clk_l_0
|
|
Info (332119): 1.714 0.000 mem|ddr4b|ddr4b_phy_clk_l_1
|
|
Info (332119): 1.714 0.000 mem|ddr4b|ddr4b_phy_clk_l_2
|
|
Info (332119): 1.744 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_clk
|
|
Info (332119): 1.744 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|rx_pma_clk
|
|
Info (332119): 1.744 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|rx_pma_clk
|
|
Info (332119): 1.744 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|rx_pma_clk
|
|
Info (332119): 1.806 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|pld_clk
|
|
Info (332119): 1.829 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk1
|
|
Info (332119): 1.837 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|pma_hclk_by2
|
|
Info (332119): 1.837 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|pma_hclk_by2
|
|
Info (332119): 1.837 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|pma_hclk_by2
|
|
Info (332119): 1.837 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|pma_hclk_by2
|
|
Info (332119): 1.837 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|pma_hclk_by2
|
|
Info (332119): 1.837 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|pma_hclk_by2
|
|
Info (332119): 1.837 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|pma_hclk_by2
|
|
Info (332119): 1.837 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|pma_hclk_by2
|
|
Info (332119): 1.863 0.000 hssi_pll_r_0_outclk1
|
|
Info (332119): 1.863 0.000 hssi_pll_t_outclk1
|
|
Info (332119): 2.038 0.000 u0|dcp_iopll|dcp_iopll|clk1x
|
|
Info (332119): 2.191 0.000 vl_qph_user_clk_clkpsc_clk1
|
|
Info (332119): 2.902 0.000 mem|ddr4a|ddr4a_core_cal_slave_clk
|
|
Info (332119): 3.092 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_div_clk
|
|
Info (332119): 3.134 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|tx_pma_div_clk
|
|
Info (332119): 3.792 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_clkout
|
|
Info (332119): 3.856 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|tx_clk
|
|
Info (332119): 3.856 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|tx_clk
|
|
Info (332119): 3.856 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|tx_clk
|
|
Info (332119): 3.856 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|tx_clk
|
|
Info (332119): 3.856 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|tx_clk
|
|
Info (332119): 3.856 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|tx_clk
|
|
Info (332119): 3.856 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|tx_clk
|
|
Info (332119): 3.856 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|tx_clk
|
|
Info (332119): 4.447 0.000 vl_qph_user_clk_clkpsc_clk0
|
|
Info (332119): 4.456 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk0
|
|
Info (332119): 4.523 0.000 SYS_RefClk
|
|
Info (332119): 4.560 0.000 u0|dcp_iopll|dcp_iopll|clk100
|
|
Info (332119): 4.561 0.000 PCIE_REFCLK
|
|
Info (332119): 4.825 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332119): 4.839 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|rx_fref
|
|
Info (332119): 4.839 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|rx_fref
|
|
Info (332119): 4.839 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|rx_fref
|
|
Info (332119): 4.839 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|rx_fref
|
|
Info (332119): 4.839 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|rx_fref
|
|
Info (332119): 4.839 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|rx_fref
|
|
Info (332119): 4.839 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|rx_fref
|
|
Info (332119): 4.856 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|avmmclk
|
|
Info (332119): 4.856 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|avmmclk
|
|
Info (332119): 4.856 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|avmmclk
|
|
Info (332119): 4.856 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|avmmclk
|
|
Info (332119): 4.856 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|avmmclk
|
|
Info (332119): 4.856 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|avmmclk
|
|
Info (332119): 4.856 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|avmmclk
|
|
Info (332119): 4.856 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|avmmclk
|
|
Info (332119): 4.856 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|avmmclk
|
|
Info (332119): 4.856 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|avmmclk
|
|
Info (332119): 4.856 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|avmmclk
|
|
Info (332119): 4.856 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|avmmclk
|
|
Info (332119): 4.857 0.000 pr_clk_enable_dclk_reg2_user_clk
|
|
Info (332119): 4.930 0.000 filtered_sclk_negedge
|
|
Info (332119): 9.941 0.000 u0|dcp_iopll|dcp_iopll|clk50
|
|
Info (332119): 19.601 0.000 u0|dcp_iopll|dcp_iopll|clk25
|
|
Info (332119): 19.858 0.000 flash_oe_clk
|
|
Info (332119): 49.803 0.000 altera_reserved_tck
|
|
Info (332119): 124.831 0.000 fspi_sclk
|
|
Info (332119): 500.000 0.000 altera_ts_clk
|
|
Warning (332182): No path is found satisfying assignment "set_max_skew -from [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|tcm_control_out|pio_0|data_out[0]}] -to [get_pins {fpga_top|inst_green_bs|ddr4*_reset_sync|resync_chains[0].synchronizer_nocut|*|clrn}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 ". This assignment will be ignored.
|
|
Info (332115): Worst-case slack is 2.417 for "set_max_skew -from [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Tx_fifo|C1Tx_fifo.inst_async_C1Tx_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Tx_fifo|C1Tx_fifo.inst_async_C1Tx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 "
|
|
Info (332115): Worst-case slack is 2.419 for "set_max_skew -from [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Tx_fifo|C0Tx_fifo.inst_async_C0Tx_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Tx_fifo|C0Tx_fifo.inst_async_C0Tx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 "
|
|
Info (332115): Worst-case slack is 2.598 for "set_max_skew -from [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_CfgTx_fifo|CfgTx_fifo.inst_async_CfgTx_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_CfgTx_fifo|CfgTx_fifo.inst_async_CfgTx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 "
|
|
Info (332115): Worst-case slack is 2.635 for "set_max_skew -from [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Rx_fifo|C0Rx_fifo.inst_async_C0Rx_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Rx_fifo|C0Rx_fifo.inst_async_C0Rx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 "
|
|
Info (332115): Worst-case slack is 2.692 for "set_max_skew -from [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Rx_fifo|C1Rx_fifo.inst_async_C1Rx_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Rx_fifo|C1Rx_fifo.inst_async_C1Rx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 "
|
|
Info (332115): Worst-case slack is 2.756 for "set_max_skew -from [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_msix_top|msix_brid|msix_dcfifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_msix_top|msix_brid|msix_dcfifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 "
|
|
Info (332115): Worst-case slack is 2.954 for "set_max_skew -from [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 "
|
|
Info (332115): Worst-case slack is 2.993 for "set_max_skew -from [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 "
|
|
Info (332115): Worst-case slack is 2.993 for "set_max_skew -from [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Tx_fifo|C0Tx_fifo.inst_async_C0Tx_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Tx_fifo|C0Tx_fifo.inst_async_C0Tx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 "
|
|
Info (332115): Worst-case slack is 3.025 for "set_max_skew -from [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 "
|
|
Info (332115): Worst-case slack is 3.031 for "set_max_skew -from [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 "
|
|
Info (332115): Worst-case slack is 3.087 for "set_max_skew -from [get_keepers {fpga_top|inst_blue_ccip_interface_reg|pck_cp2af_softReset_T0_q}] -to [get_pins {fpga_top|inst_green_bs|ddr4*_reset_sync|resync_chains[0].synchronizer_nocut|*|clrn}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 "
|
|
Info (332115): Worst-case slack is 3.116 for "set_max_skew -from [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 "
|
|
Info (332115): Worst-case slack is 3.127 for "set_max_skew -from [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 "
|
|
Info (332115): Worst-case slack is 3.204 for "set_max_skew -from [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 "
|
|
Info (332115): Worst-case slack is 3.213 for "set_max_skew -from [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Rx_fifo|C0Rx_fifo.inst_async_C0Rx_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Rx_fifo|C0Rx_fifo.inst_async_C0Rx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 "
|
|
Info (332115): Worst-case slack is 3.237 for "set_max_skew -from [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 "
|
|
Info (332115): Worst-case slack is 3.249 for "set_max_skew -from [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_CfgTx_fifo|CfgTx_fifo.inst_async_CfgTx_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_CfgTx_fifo|CfgTx_fifo.inst_async_CfgTx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 "
|
|
Info (332115): Worst-case slack is 3.318 for "set_max_skew -from [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Tx_fifo|C1Tx_fifo.inst_async_C1Tx_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Tx_fifo|C1Tx_fifo.inst_async_C1Tx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 "
|
|
Info (332115): Worst-case slack is 3.347 for "set_max_skew -from [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 "
|
|
Info (332115): Worst-case slack is 3.404 for "set_max_skew -from [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_msix_top|msix_brid|msix_dcfifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_msix_top|msix_brid|msix_dcfifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 "
|
|
Info (332115): Worst-case slack is 3.405 for "set_max_skew -from [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Rx_fifo|C1Rx_fifo.inst_async_C1Rx_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Rx_fifo|C1Rx_fifo.inst_async_C1Rx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 "
|
|
Info (332115): Worst-case slack is 3.416 for "set_max_skew -from [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 "
|
|
Info (332115): Worst-case slack is 3.444 for "set_max_skew -from [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|ddr_backchannel|mm_clock_crossing_bridge_0|rsp_fifo|out_rd_ptr_gray[*]}] -to [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|ddr_backchannel|mm_clock_crossing_bridge_0|rsp_fifo|read_crosser|sync[*].u|din_s1}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 "
|
|
Info (332115): Worst-case slack is 3.449 for "set_max_skew -from [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|ddr_backchannel|mm_clock_crossing_bridge_0|cmd_fifo|in_wr_ptr_gray[*]}] -to [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|ddr_backchannel|mm_clock_crossing_bridge_0|cmd_fifo|write_crosser|sync[*].u|din_s1}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 "
|
|
Info (332115): Worst-case slack is 7.379 for "set_max_skew -from [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|ddr_backchannel|mm_clock_crossing_bridge_0|rsp_fifo|in_wr_ptr_gray[*]}] -to [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|ddr_backchannel|mm_clock_crossing_bridge_0|rsp_fifo|write_crosser|sync[*].u|din_s1}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 "
|
|
Info (332115): Worst-case slack is 7.393 for "set_max_skew -from [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|ddr_backchannel|mm_clock_crossing_bridge_0|cmd_fifo|out_rd_ptr_gray[*]}] -to [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|ddr_backchannel|mm_clock_crossing_bridge_0|cmd_fifo|read_crosser|sync[*].u|din_s1}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 "
|
|
Info (332115): Worst-case slack is 7.413 for "set_max_skew -from [get_registers {auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|stfabric|t2h0_fifo|in_wr_ptr_gray[*]}] -to [get_registers {auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|stfabric|t2h0_fifo|write_crosser|sync[*].u|din_s1}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 "
|
|
Info (332115): Worst-case slack is 7.444 for "set_max_skew -from [get_registers {auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|stfabric|t2h0_fifo|out_rd_ptr_gray[*]}] -to [get_registers {auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|stfabric|t2h0_fifo|read_crosser|sync[*].u|din_s1}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 "
|
|
Info (332115): Worst-case slack is 7.470 for "set_max_skew -from [get_registers {auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|stfabric|h2t0_fifo|in_wr_ptr_gray[*]}] -to [get_registers {auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|stfabric|h2t0_fifo|write_crosser|sync[*].u|din_s1}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 "
|
|
Info (332115): Worst-case slack is 7.512 for "set_max_skew -from [get_registers {auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|stfabric|h2t0_fifo|out_rd_ptr_gray[*]}] -to [get_registers {auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|stfabric|h2t0_fifo|read_crosser|sync[*].u|din_s1}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 "
|
|
Info (332163): Slow 900mV 0C Model Net Delay Summary
|
|
Info (332163): Name Slack Req Actual From To Type
|
|
Info (332163): ============= ====== ====== ====== =============== =============== ====
|
|
Info (332163): set_net_delay 1.516 3.001 1.485 [get_pins -compatibility_mode {*|out_rd_ptr_gray[*]*}]
|
|
Info (332163): [get_registers {*|platform_utils_dcfifo_synchronizer_bundle:read_crosser|platform_utils_std_synchronizer_nocut:sync[*].u|din_s1}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 2.262 3.200 0.938 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Rx_fifo|C1Rx_fifo.inst_async_C1Rx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Rx_fifo|C1Rx_fifo.inst_async_C1Rx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 2.284 3.200 0.916 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Tx_fifo|C1Tx_fifo.inst_async_C1Tx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Tx_fifo|C1Tx_fifo.inst_async_C1Tx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 2.288 3.636 1.348 [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 2.294 3.200 0.906 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Tx_fifo|C0Tx_fifo.inst_async_C0Tx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Tx_fifo|C0Tx_fifo.inst_async_C0Tx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 2.323 4.000 1.677 [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser|async_clock_crosser.clock_xer|out_data_toggle_flopped}]
|
|
Info (332163): [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser|async_clock_crosser.clock_xer|out_to_in_synchronizer|din_s1}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 2.470 3.200 0.730 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Rx_fifo|C0Rx_fifo.inst_async_C0Rx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Rx_fifo|C0Rx_fifo.inst_async_C0Rx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 2.482 3.200 0.718 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_CfgTx_fifo|CfgTx_fifo.inst_async_CfgTx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_CfgTx_fifo|CfgTx_fifo.inst_async_CfgTx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 2.488 3.001 0.513 [get_pins -compatibility_mode {*|in_wr_ptr_gray[*]*}]
|
|
Info (332163): [get_registers {*|platform_utils_dcfifo_synchronizer_bundle:write_crosser|platform_utils_std_synchronizer_nocut:sync[*].u|din_s1}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 2.525 3.200 0.675 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_msix_top|msix_brid|msix_dcfifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_msix_top|msix_brid|msix_dcfifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 2.573 3.200 0.627 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Tx_fifo|C0Tx_fifo.inst_async_C0Tx_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Tx_fifo|C0Tx_fifo.inst_async_C0Tx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 2.574 3.200 0.626 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Rx_fifo|C0Rx_fifo.inst_async_C0Rx_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Rx_fifo|C0Rx_fifo.inst_async_C0Rx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 2.575 3.636 1.061 [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 2.651 3.200 0.549 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_CfgTx_fifo|CfgTx_fifo.inst_async_CfgTx_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_CfgTx_fifo|CfgTx_fifo.inst_async_CfgTx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 2.651 3.636 0.985 [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 2.671 3.636 0.965 [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 2.673 3.200 0.527 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Tx_fifo|C1Tx_fifo.inst_async_C1Tx_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Tx_fifo|C1Tx_fifo.inst_async_C1Tx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 2.682 4.000 1.318 [get_registers {*altera_avalon_st_clock_crosser:*|in_data_buffer*}]
|
|
Info (332163): [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_004|async_clock_crosser.clock_xer|out_data_buffer*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 2.694 3.200 0.506 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Rx_fifo|C1Rx_fifo.inst_async_C1Rx_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Rx_fifo|C1Rx_fifo.inst_async_C1Rx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 2.702 3.200 0.498 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_msix_top|msix_brid|msix_dcfifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_msix_top|msix_brid|msix_dcfifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 2.704 4.000 1.296 [get_registers {*altera_avalon_st_clock_crosser:*|in_data_buffer*}]
|
|
Info (332163): [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_005|async_clock_crosser.clock_xer|out_data_buffer*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 2.733 3.636 0.903 [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 2.849 4.000 1.151 [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_003|async_clock_crosser.clock_xer|out_data_toggle_flopped}]
|
|
Info (332163): [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_003|async_clock_crosser.clock_xer|out_to_in_synchronizer|din_s1}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 2.930 3.636 0.706 [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|delayed_wrptr_g*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 2.941 4.000 1.059 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Rx_fifo|C0Rx_fifo.inst_async_C0Rx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Rx_fifo|C0Rx_fifo.inst_async_C0Rx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 2.961 4.000 1.039 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Tx_fifo|C1Tx_fifo.inst_async_C1Tx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Tx_fifo|C1Tx_fifo.inst_async_C1Tx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 2.964 4.000 1.036 [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_001|async_clock_crosser.clock_xer|out_data_toggle_flopped}]
|
|
Info (332163): [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_001|async_clock_crosser.clock_xer|out_to_in_synchronizer|din_s1}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 2.970 4.000 1.030 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Tx_fifo|C0Tx_fifo.inst_async_C0Tx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Tx_fifo|C0Tx_fifo.inst_async_C0Tx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 2.973 4.000 1.027 [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 3.009 4.000 0.991 [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_004|async_clock_crosser.clock_xer|in_data_toggle}]
|
|
Info (332163): [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_004|async_clock_crosser.clock_xer|in_to_out_synchronizer|din_s1}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 3.010 3.636 0.626 [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|*rdptr_g*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 3.060 4.000 0.940 [get_registers {*altera_avalon_st_clock_crosser:*|in_data_buffer*}]
|
|
Info (332163): [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_006|async_clock_crosser.clock_xer|out_data_buffer*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 3.066 4.000 0.934 [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 3.073 3.636 0.563 [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|delayed_wrptr_g*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 3.081 3.636 0.555 [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|*rdptr_g*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 3.132 3.636 0.504 [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|*rdptr_g*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 3.188 4.000 0.812 [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 3.197 4.000 0.803 [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 3.242 4.000 0.758 [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 3.248 4.000 0.752 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_CfgTx_fifo|CfgTx_fifo.inst_async_CfgTx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_CfgTx_fifo|CfgTx_fifo.inst_async_CfgTx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 3.287 4.000 0.713 [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|delayed_wrptr_g*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 3.290 4.000 0.710 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Rx_fifo|C1Rx_fifo.inst_async_C1Rx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Rx_fifo|C1Rx_fifo.inst_async_C1Rx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 3.351 4.000 0.649 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Tx_fifo|C1Tx_fifo.inst_async_C1Tx_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Tx_fifo|C1Tx_fifo.inst_async_C1Tx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 3.357 4.000 0.643 [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_002|async_clock_crosser.clock_xer|out_data_toggle_flopped}]
|
|
Info (332163): [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_002|async_clock_crosser.clock_xer|out_to_in_synchronizer|din_s1}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 3.381 4.000 0.619 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_msix_top|msix_brid|msix_dcfifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_msix_top|msix_brid|msix_dcfifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 3.382 4.000 0.618 [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|*rdptr_g*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 3.398 4.000 0.602 [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_005|async_clock_crosser.clock_xer|in_data_toggle}]
|
|
Info (332163): [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_005|async_clock_crosser.clock_xer|in_to_out_synchronizer|din_s1}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 3.402 4.000 0.598 [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_007|async_clock_crosser.clock_xer|in_data_toggle}]
|
|
Info (332163): [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_007|async_clock_crosser.clock_xer|in_to_out_synchronizer|din_s1}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 3.402 4.000 0.598 [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|*rdptr_g*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 3.457 4.000 0.543 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_CfgTx_fifo|CfgTx_fifo.inst_async_CfgTx_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_CfgTx_fifo|CfgTx_fifo.inst_async_CfgTx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 3.471 4.000 0.529 [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|delayed_wrptr_g*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 3.472 4.000 0.528 [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|delayed_wrptr_g*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 3.498 4.000 0.502 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Rx_fifo|C0Rx_fifo.inst_async_C0Rx_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Rx_fifo|C0Rx_fifo.inst_async_C0Rx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 3.506 4.000 0.494 [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_006|async_clock_crosser.clock_xer|in_data_toggle}]
|
|
Info (332163): [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_006|async_clock_crosser.clock_xer|in_to_out_synchronizer|din_s1}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 3.515 4.000 0.485 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Tx_fifo|C0Tx_fifo.inst_async_C0Tx_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Tx_fifo|C0Tx_fifo.inst_async_C0Tx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 3.520 4.000 0.480 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_msix_top|msix_brid|msix_dcfifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_msix_top|msix_brid|msix_dcfifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 3.585 4.000 0.415 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Rx_fifo|C1Rx_fifo.inst_async_C1Rx_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Rx_fifo|C1Rx_fifo.inst_async_C1Rx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 3.699 4.000 0.301 [get_pins -compatibility_mode {*|out_rd_ptr_gray[*]*}]
|
|
Info (332163): [get_registers {*|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer_nocut:sync[*].u|din_s1}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 3.726 4.000 0.274 [get_pins -compatibility_mode {*|in_wr_ptr_gray[*]*}]
|
|
Info (332163): [get_registers {*|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer_nocut:sync[*].u|din_s1}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 5.818 8.000 2.182 [get_registers {*altera_avalon_st_clock_crosser:*|in_data_buffer*}]
|
|
Info (332163): [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_003|async_clock_crosser.clock_xer|out_data_buffer*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 5.971 8.000 2.029 [get_registers {*altera_avalon_st_clock_crosser:*|in_data_buffer*}]
|
|
Info (332163): [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_002|async_clock_crosser.clock_xer|out_data_buffer*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 6.643 8.000 1.357 [get_registers {auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|host_link_jtag|jtag|normal.jtag_dc_streaming|sink_crosser|out_data_toggle_flopped}]
|
|
Info (332163): [get_registers {auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|host_link_jtag|jtag|normal.jtag_dc_streaming|sink_crosser|out_to_in_synchronizer|din_s1}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 7.119 8.000 0.881 [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_006|async_clock_crosser.clock_xer|out_data_toggle_flopped}]
|
|
Info (332163): [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_006|async_clock_crosser.clock_xer|out_to_in_synchronizer|din_s1}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 7.131 8.000 0.869 [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_002|async_clock_crosser.clock_xer|in_data_toggle}]
|
|
Info (332163): [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_002|async_clock_crosser.clock_xer|in_to_out_synchronizer|din_s1}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 7.406 8.000 0.594 [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_003|async_clock_crosser.clock_xer|in_data_toggle}]
|
|
Info (332163): [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_003|async_clock_crosser.clock_xer|in_to_out_synchronizer|din_s1}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 7.489 8.000 0.511 [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_007|async_clock_crosser.clock_xer|out_data_toggle_flopped}]
|
|
Info (332163): [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_007|async_clock_crosser.clock_xer|out_to_in_synchronizer|din_s1}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 30.546 32.000 1.454 [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser|async_clock_crosser.clock_xer|in_data_toggle}]
|
|
Info (332163): [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser|async_clock_crosser.clock_xer|in_to_out_synchronizer|din_s1}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 30.554 32.000 1.446 [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_005|async_clock_crosser.clock_xer|out_data_toggle_flopped}]
|
|
Info (332163): [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_005|async_clock_crosser.clock_xer|out_to_in_synchronizer|din_s1}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 30.807 32.000 1.193 [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_004|async_clock_crosser.clock_xer|out_data_toggle_flopped}]
|
|
Info (332163): [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_004|async_clock_crosser.clock_xer|out_to_in_synchronizer|din_s1}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 30.912 32.000 1.088 [get_registers {*altera_avalon_st_clock_crosser:*|in_data_buffer*}]
|
|
Info (332163): [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_001|async_clock_crosser.clock_xer|out_data_buffer*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 31.044 32.000 0.956 [get_registers {*altera_avalon_st_clock_crosser:*|in_data_buffer*}]
|
|
Info (332163): [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser|async_clock_crosser.clock_xer|out_data_buffer*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 31.322 32.000 0.678 [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_001|async_clock_crosser.clock_xer|in_data_toggle}]
|
|
Info (332163): [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_001|async_clock_crosser.clock_xer|in_to_out_synchronizer|din_s1}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 74.352 80.000 5.648 [get_registers {auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|host_link_jtag|jtag|normal.jtag_dc_streaming|sink_crosser|in_data_toggle}]
|
|
Info (332163): [get_registers {auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|host_link_jtag|jtag|normal.jtag_dc_streaming|sink_crosser|in_to_out_synchronizer|din_s1}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 79.022 80.000 0.978 [get_registers {*altera_avalon_st_clock_crosser:*|in_data_buffer*}]
|
|
Info (332163): [get_registers {auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|host_link_jtag|jtag|normal.jtag_dc_streaming|sink_crosser|out_data_buffer*}]
|
|
Info (332163): max
|
|
Info (332114): Report Metastability: Found 403 synchronizer chains.
|
|
Info (332114): Design MTBF is not calculated because the design doesn't meet its timing requirements.
|
|
Info (332115): Report Timing: Found 1 setup paths (1 violated). Worst case slack is -1.333
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk1}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is -1.333 (VIOLATED)
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|execute|fpu_unit|fpu_fpga|fp_cvt|pipe_reg1|value_d[64]
|
|
Info (332115): To Node : fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|execute|fpu_unit|fpu_fpga|fp_cvt|pipe_reg2|value_d[129]
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk1
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk1
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 6.510 6.510 R clock network delay
|
|
Info (332115): 6.510 0.000 fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|execute|fpu_unit|fpu_fpga|fp_cvt|pipe_reg1|value_d[64]
|
|
Info (332115): 6.742 0.232 RR uTco fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|execute|fpu_unit|fpu_fpga|fp_cvt|pipe_reg1|value_d[64]|q
|
|
Info (332115): 6.878 0.136 RR CELL High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|execute|fpu_unit|fpu_fpga|fp_cvt|pipe_reg1|value_d[64]~la_lab/laboutb[18]
|
|
Info (332115): 7.041 0.163 RR IC High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|execute|fpu_unit|fpu_fpga|fp_cvt|LessThan_23~0|dataa
|
|
Info (332115): 7.330 0.289 RR CELL High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|execute|fpu_unit|fpu_fpga|fp_cvt|LessThan_23~0|combout
|
|
Info (332115): 7.334 0.004 RR CELL High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|execute|fpu_unit|fpu_fpga|fp_cvt|LessThan_23~0~la_lab/laboutb[1]
|
|
Info (332115): 7.499 0.165 RR IC High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|execute|fpu_unit|fpu_fpga|fp_cvt|denorm_shamt[3][2]~55|datad
|
|
Info (332115): 7.661 0.162 RR CELL High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|execute|fpu_unit|fpu_fpga|fp_cvt|denorm_shamt[3][2]~55|combout
|
|
Info (332115): 7.665 0.004 RR CELL High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|execute|fpu_unit|fpu_fpga|fp_cvt|denorm_shamt[3][2]~55~la_lab/laboutb[12]
|
|
Info (332115): 7.995 0.330 RR IC High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|execute|fpu_unit|fpu_fpga|fp_cvt|denorm_shamt[3][0]~57|dataf
|
|
Info (332115): 8.047 0.052 RF CELL High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|execute|fpu_unit|fpu_fpga|fp_cvt|denorm_shamt[3][0]~57|combout
|
|
Info (332115): 8.052 0.005 FF CELL High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|execute|fpu_unit|fpu_fpga|fp_cvt|denorm_shamt[3][0]~57~la_mlab/laboutt[1]
|
|
Info (332115): 8.225 0.173 FF IC High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|execute|fpu_unit|fpu_fpga|fp_cvt|denorm_shamt[3][0]~61|dataf
|
|
Info (332115): 8.275 0.050 FR CELL High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|execute|fpu_unit|fpu_fpga|fp_cvt|denorm_shamt[3][0]~61|combout
|
|
Info (332115): 8.280 0.005 RR CELL High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|execute|fpu_unit|fpu_fpga|fp_cvt|denorm_shamt[3][0]~61~la_lab/laboutt[1]
|
|
Info (332115): 8.781 0.501 RR IC High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|execute|fpu_unit|fpu_fpga|fp_cvt|shift_right_3~24|datad
|
|
Info (332115): 8.971 0.190 RR CELL High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|execute|fpu_unit|fpu_fpga|fp_cvt|shift_right_3~24|combout
|
|
Info (332115): 8.976 0.005 RR CELL High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|execute|fpu_unit|fpu_fpga|fp_cvt|shift_right_3~24~la_mlab/laboutb[0]
|
|
Info (332115): 9.124 0.148 RR IC High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|execute|fpu_unit|fpu_fpga|fp_cvt|shift_right_3~57|datad
|
|
Info (332115): 9.291 0.167 RR CELL High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|execute|fpu_unit|fpu_fpga|fp_cvt|shift_right_3~57|combout
|
|
Info (332115): 9.295 0.004 RR CELL High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|execute|fpu_unit|fpu_fpga|fp_cvt|shift_right_3~57~la_lab/laboutb[6]
|
|
Info (332115): 9.736 0.441 RR IC High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|execute|fpu_unit|fpu_fpga|fp_cvt|reduce_or_7~8|datab
|
|
Info (332115): 10.010 0.274 RR CELL High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|execute|fpu_unit|fpu_fpga|fp_cvt|reduce_or_7~8|combout
|
|
Info (332115): 10.015 0.005 RR CELL High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|execute|fpu_unit|fpu_fpga|fp_cvt|reduce_or_7~8~la_mlab/laboutb[1]
|
|
Info (332115): 10.191 0.176 RR IC High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|execute|fpu_unit|fpu_fpga|fp_cvt|reduce_or_7~14|datac
|
|
Info (332115): 10.356 0.165 RF CELL High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|execute|fpu_unit|fpu_fpga|fp_cvt|reduce_or_7~14|combout
|
|
Info (332115): 10.360 0.004 FF CELL High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|execute|fpu_unit|fpu_fpga|fp_cvt|reduce_or_7~14~la_lab/laboutb[8]
|
|
Info (332115): 10.675 0.315 FF IC High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|execute|fpu_unit|fpu_fpga|fp_cvt|reduce_or_7~15|datad
|
|
Info (332115): 10.861 0.186 FF CELL High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|execute|fpu_unit|fpu_fpga|fp_cvt|reduce_or_7~15|combout
|
|
Info (332115): 10.866 0.005 FF CELL High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|execute|fpu_unit|fpu_fpga|fp_cvt|reduce_or_7~15~la_mlab/laboutt[5]
|
|
Info (332115): 11.025 0.159 FF IC High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|execute|fpu_unit|fpu_fpga|fp_cvt|[3].fp_rounding|Mux_1~0|datae
|
|
Info (332115): 11.229 0.204 FR CELL High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|execute|fpu_unit|fpu_fpga|fp_cvt|[3].fp_rounding|Mux_1~0|combout
|
|
Info (332115): 11.234 0.005 RR CELL High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|execute|fpu_unit|fpu_fpga|fp_cvt|[3].fp_rounding|Mux_1~0~la_mlab/laboutt[14]
|
|
Info (332115): 11.393 0.159 RR IC High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|execute|fpu_unit|fpu_fpga|fp_cvt|[3].fp_rounding|add_0~37|datad
|
|
Info (332115): 12.134 0.741 RF CELL High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|execute|fpu_unit|fpu_fpga|fp_cvt|[3].fp_rounding|add_0~121|cout
|
|
Info (332115): 12.152 0.018 FF IC High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|execute|fpu_unit|fpu_fpga|fp_cvt|[3].fp_rounding|add_0~85|cin
|
|
Info (332115): 12.278 0.126 FF CELL High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|execute|fpu_unit|fpu_fpga|fp_cvt|[3].fp_rounding|add_0~77|cout
|
|
Info (332115): 12.278 0.000 FF CELL High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|execute|fpu_unit|fpu_fpga|fp_cvt|[3].fp_rounding|add_0~81|cin
|
|
Info (332115): 12.314 0.036 FR CELL High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|execute|fpu_unit|fpu_fpga|fp_cvt|[3].fp_rounding|add_0~13|cout
|
|
Info (332115): 12.314 0.000 RR CELL High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|execute|fpu_unit|fpu_fpga|fp_cvt|[3].fp_rounding|add_0~17|cin
|
|
Info (332115): 12.340 0.026 RF CELL High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|execute|fpu_unit|fpu_fpga|fp_cvt|[3].fp_rounding|add_0~21|cout
|
|
Info (332115): 12.340 0.000 FF CELL High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|execute|fpu_unit|fpu_fpga|fp_cvt|[3].fp_rounding|add_0~25|cin
|
|
Info (332115): 12.376 0.036 FR CELL High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|execute|fpu_unit|fpu_fpga|fp_cvt|[3].fp_rounding|add_0~29|cout
|
|
Info (332115): 12.376 0.000 RR CELL High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|execute|fpu_unit|fpu_fpga|fp_cvt|[3].fp_rounding|add_0~1|cin
|
|
Info (332115): 12.622 0.246 RF CELL High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|execute|fpu_unit|fpu_fpga|fp_cvt|[3].fp_rounding|add_0~5|sumout
|
|
Info (332115): 12.622 0.000 FF CELL High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|execute|fpu_unit|fpu_fpga|fp_cvt|pipe_reg2|value_d[129]|d
|
|
Info (332115): 12.622 0.000 FF CELL High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|execute|fpu_unit|fpu_fpga|fp_cvt|pipe_reg2|value_d[129]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 4.545 4.545 latch edge time
|
|
Info (332115): 9.923 5.378 R clock network delay
|
|
Info (332115): 11.038 1.115 clock pessimism removed
|
|
Info (332115): 11.008 -0.030 clock uncertainty
|
|
Info (332115): 11.289 0.281 uTsu fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|execute|fpu_unit|fpu_fpga|fp_cvt|pipe_reg2|value_d[129]
|
|
Info (332115): Data Arrival Time : 12.622
|
|
Info (332115): Data Required Time : 11.289
|
|
Info (332115): Slack : -1.333 (VIOLATED)
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 0.079
|
|
Info (20696): -to_clock [get_clocks {mem|ddr4b|ddr4b_phy_clk_l_1}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 0.079
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : mem|ddr4b_avmm_chkr|clearing
|
|
Info (332115): To Node : mem|ddr4b|ddr4b|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[1].lane_gen[3].lane_inst~phy_reg1
|
|
Info (332115): Launch Clock : mem|ddr4a|ddr4a_core_usr_clk
|
|
Info (332115): Latch Clock : mem|ddr4b|ddr4b_phy_clk_l_1
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.117 0.117 launch edge time
|
|
Info (332115): 3.735 3.618 R clock network delay
|
|
Info (332115): 3.735 0.000 mem|ddr4b_avmm_chkr|clearing
|
|
Info (332115): 3.965 0.230 RR uTco mem|ddr4b_avmm_chkr|clearing|q
|
|
Info (332115): 4.103 0.138 RR CELL High Speed mem|ddr4b_avmm_chkr|clearing~la_lab/laboutb[17]
|
|
Info (332115): 5.333 1.230 RR IC High Speed mem|ddr4b_avmm_chkr|avm_writedata[0]~260|dataf
|
|
Info (332115): 5.389 0.056 RF CELL High Speed mem|ddr4b_avmm_chkr|avm_writedata[0]~260|combout
|
|
Info (332115): 5.393 0.004 FF CELL High Speed mem|ddr4b_avmm_chkr|avm_writedata[0]~260~la_lab/laboutb[5]
|
|
Info (332115): 6.543 1.150 FF IC High Speed mem|ddr4b|ddr4b|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[1].lane_gen[3].lane_inst|data_from_core[76]
|
|
Info (332115): 6.543 0.000 FF CELL mem|ddr4b|ddr4b|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[1].lane_gen[3].lane_inst~phy_reg1
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 3.869 3.869 latch edge time
|
|
Info (332115): 6.440 2.571 R clock network delay
|
|
Info (332115): 6.549 0.109 clock pessimism removed
|
|
Info (332115): 6.260 -0.289 clock uncertainty
|
|
Info (332115): 6.622 0.362 uTsu mem|ddr4b|ddr4b|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[1].lane_gen[3].lane_inst~phy_reg1
|
|
Info (332115): Data Arrival Time : 6.543
|
|
Info (332115): Data Required Time : 6.622
|
|
Info (332115): Slack : 0.079
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 0.090
|
|
Info (20696): -to_clock [get_clocks {mem|ddr4b|ddr4b_phy_clk_l_0}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 0.090
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : mem|ddr4b_bridge|ddr_avmm_bridge|cmd_burstcount[4]
|
|
Info (332115): To Node : mem|ddr4b|ddr4b|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[1].tile_ctrl_inst~hmc_reg1
|
|
Info (332115): Launch Clock : mem|ddr4a|ddr4a_core_usr_clk
|
|
Info (332115): Latch Clock : mem|ddr4b|ddr4b_phy_clk_l_0
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.117 0.117 launch edge time
|
|
Info (332115): 3.746 3.629 R clock network delay
|
|
Info (332115): 3.746 0.000 mem|ddr4b_bridge|ddr_avmm_bridge|cmd_burstcount[4]
|
|
Info (332115): 3.984 0.238 RR uTco mem|ddr4b_bridge|ddr_avmm_bridge|cmd_burstcount[4]|q
|
|
Info (332115): 4.178 0.194 RR CELL High Speed mem|ddr4b_bridge|ddr_avmm_bridge|cmd_burstcount[4]~la_mlab/laboutb[12]
|
|
Info (332115): 4.585 0.407 RR IC High Speed mem|ddr4b_avmm_chkr|LessThan_0~0|datad
|
|
Info (332115): 4.772 0.187 RF CELL High Speed mem|ddr4b_avmm_chkr|LessThan_0~0|combout
|
|
Info (332115): 4.777 0.005 FF CELL High Speed mem|ddr4b_avmm_chkr|LessThan_0~0~la_mlab/laboutt[17]
|
|
Info (332115): 5.088 0.311 FF IC High Speed mem|ddr4b_avmm_chkr|start_error|datad
|
|
Info (332115): 5.250 0.162 FR CELL High Speed mem|ddr4b_avmm_chkr|start_error|combout
|
|
Info (332115): 5.254 0.004 RR CELL High Speed mem|ddr4b_avmm_chkr|start_error~la_lab/laboutt[0]
|
|
Info (332115): 5.580 0.326 RR IC High Speed mem|ddr4b_emif_read_mux~0|datad
|
|
Info (332115): 5.720 0.140 RR CELL High Speed mem|ddr4b_emif_read_mux~0|combout
|
|
Info (332115): 5.724 0.004 RR CELL High Speed mem|ddr4b_emif_read_mux~0~la_lab/laboutt[7]
|
|
Info (332115): 6.472 0.748 RR IC High Speed mem|ddr4b|ddr4b|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[1].tile_ctrl_inst|core2ctl_avl0[0]
|
|
Info (332115): 6.472 0.000 RR CELL mem|ddr4b|ddr4b|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[1].tile_ctrl_inst~hmc_reg1
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 3.869 3.869 latch edge time
|
|
Info (332115): 6.498 2.629 R clock network delay
|
|
Info (332115): 6.607 0.109 clock pessimism removed
|
|
Info (332115): 6.318 -0.289 clock uncertainty
|
|
Info (332115): 6.562 0.244 uTsu mem|ddr4b|ddr4b|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[1].tile_ctrl_inst~hmc_reg1
|
|
Info (332115): Data Arrival Time : 6.472
|
|
Info (332115): Data Required Time : 6.562
|
|
Info (332115): Slack : 0.090
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 0.100
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|wys~CORE_CLK_OUT}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 0.100
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~pld_clk.reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_sriov_2.sriov2.sriov_bridge|altpcie_pcie_sriov2_top_inst|altpcie_sriov2_cfg_dataflow_inst|altpcie_sriov2_cfg_fn0_regset_inst|link_cap_reg_speed[3]
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|pld_clk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|wys~CORE_CLK_OUT
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 9.890 9.890 R clock network delay
|
|
Info (332115): 9.890 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~pld_clk.reg
|
|
Info (332115): 11.886 1.996 FF uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|ltssm_state[0]
|
|
Info (332115): 13.058 1.172 FF IC High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_sriov_2.sriov2.sriov_bridge|altpcie_pcie_sriov2_top_inst|altpcie_sriov2_cfg_dataflow_inst|altpcie_sriov2_cfg_fn0_regset_inst|link_cap_reg_speed[3]~0|datae
|
|
Info (332115): 13.260 0.202 FR CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_sriov_2.sriov2.sriov_bridge|altpcie_pcie_sriov2_top_inst|altpcie_sriov2_cfg_dataflow_inst|altpcie_sriov2_cfg_fn0_regset_inst|link_cap_reg_speed[3]~0|combout
|
|
Info (332115): 13.265 0.005 RR CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_sriov_2.sriov2.sriov_bridge|altpcie_pcie_sriov2_top_inst|altpcie_sriov2_cfg_dataflow_inst|altpcie_sriov2_cfg_fn0_regset_inst|link_cap_reg_speed[3]~0~la_mlab/laboutb[14]
|
|
Info (332115): 13.447 0.182 RR IC High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_sriov_2.sriov2.sriov_bridge|altpcie_pcie_sriov2_top_inst|altpcie_sriov2_cfg_dataflow_inst|altpcie_sriov2_cfg_fn0_regset_inst|link_cap_reg_speed[3]|ena
|
|
Info (332115): 13.447 0.000 RR CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_sriov_2.sriov2.sriov_bridge|altpcie_pcie_sriov2_top_inst|altpcie_sriov2_cfg_dataflow_inst|altpcie_sriov2_cfg_fn0_regset_inst|link_cap_reg_speed[3]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 4.000 4.000 latch edge time
|
|
Info (332115): 12.081 8.081 R clock network delay
|
|
Info (332115): 13.519 1.438 clock pessimism removed
|
|
Info (332115): 13.497 -0.022 clock uncertainty
|
|
Info (332115): 13.547 0.050 uTsu fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_sriov_2.sriov2.sriov_bridge|altpcie_pcie_sriov2_top_inst|altpcie_sriov2_cfg_dataflow_inst|altpcie_sriov2_cfg_fn0_regset_inst|link_cap_reg_speed[3]
|
|
Info (332115): Data Arrival Time : 13.447
|
|
Info (332115): Data Required Time : 13.547
|
|
Info (332115): Slack : 0.100
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 0.118
|
|
Info (20696): -to_clock [get_clocks {mem|ddr4a|ddr4a_phy_clk_l_2}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 0.118
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : mem|ddr4a_avmm_chkr|clearing
|
|
Info (332115): To Node : mem|ddr4a|ddr4a|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[0].lane_gen[0].lane_inst~phy_reg1
|
|
Info (332115): Launch Clock : mem|ddr4a|ddr4a_core_usr_clk
|
|
Info (332115): Latch Clock : mem|ddr4a|ddr4a_phy_clk_l_2
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.117 0.117 launch edge time
|
|
Info (332115): 3.843 3.726 R clock network delay
|
|
Info (332115): 3.843 0.000 mem|ddr4a_avmm_chkr|clearing
|
|
Info (332115): 4.074 0.231 FF uTco mem|ddr4a_avmm_chkr|clearing|q
|
|
Info (332115): 4.164 0.090 FF CELL High Speed mem|ddr4a_avmm_chkr|clearing~la_mlab/laboutt[13]
|
|
Info (332115): 4.792 0.628 FF IC High Speed mem|ddr4a_avmm_chkr|avm_writedata[131]~26|datad
|
|
Info (332115): 4.956 0.164 FR CELL High Speed mem|ddr4a_avmm_chkr|avm_writedata[131]~26|combout
|
|
Info (332115): 4.960 0.004 RR CELL High Speed mem|ddr4a_avmm_chkr|avm_writedata[131]~26~la_lab/laboutt[16]
|
|
Info (332115): 6.687 1.727 RR IC High Speed mem|ddr4a|ddr4a|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[0].lane_gen[0].lane_inst|data_from_core[50]
|
|
Info (332115): 6.687 0.000 RR CELL mem|ddr4a|ddr4a|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[0].lane_gen[0].lane_inst~phy_reg1
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 3.869 3.869 latch edge time
|
|
Info (332115): 6.547 2.678 R clock network delay
|
|
Info (332115): 6.737 0.190 clock pessimism removed
|
|
Info (332115): 6.448 -0.289 clock uncertainty
|
|
Info (332115): 6.805 0.357 uTsu mem|ddr4a|ddr4a|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[0].lane_gen[0].lane_inst~phy_reg1
|
|
Info (332115): Data Arrival Time : 6.687
|
|
Info (332115): Data Required Time : 6.805
|
|
Info (332115): Slack : 0.118
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 0.192
|
|
Info (20696): -to_clock [get_clocks {mem|ddr4a|ddr4a_phy_clk_l_1}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 0.192
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : mem|ddr4a_avmm_chkr|clearing
|
|
Info (332115): To Node : mem|ddr4a|ddr4a|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[1].lane_gen[3].lane_inst~phy_reg1
|
|
Info (332115): Launch Clock : mem|ddr4a|ddr4a_core_usr_clk
|
|
Info (332115): Latch Clock : mem|ddr4a|ddr4a_phy_clk_l_1
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.117 0.117 launch edge time
|
|
Info (332115): 3.843 3.726 R clock network delay
|
|
Info (332115): 3.843 0.000 mem|ddr4a_avmm_chkr|clearing
|
|
Info (332115): 4.074 0.231 RR uTco mem|ddr4a_avmm_chkr|clearing|q
|
|
Info (332115): 4.221 0.147 RR CELL High Speed mem|ddr4a_avmm_chkr|clearing~la_mlab/laboutt[13]
|
|
Info (332115): 5.297 1.076 RR IC High Speed mem|ddr4a_avmm_chkr|avm_writedata[416]~262|dataf
|
|
Info (332115): 5.350 0.053 RF CELL High Speed mem|ddr4a_avmm_chkr|avm_writedata[416]~262|combout
|
|
Info (332115): 5.354 0.004 FF CELL High Speed mem|ddr4a_avmm_chkr|avm_writedata[416]~262~la_lab/laboutb[9]
|
|
Info (332115): 6.626 1.272 FF IC High Speed mem|ddr4a|ddr4a|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[1].lane_gen[3].lane_inst|data_from_core[78]
|
|
Info (332115): 6.626 0.000 FF CELL mem|ddr4a|ddr4a|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[1].lane_gen[3].lane_inst~phy_reg1
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 3.869 3.869 latch edge time
|
|
Info (332115): 6.553 2.684 R clock network delay
|
|
Info (332115): 6.743 0.190 clock pessimism removed
|
|
Info (332115): 6.454 -0.289 clock uncertainty
|
|
Info (332115): 6.818 0.364 uTsu mem|ddr4a|ddr4a|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[1].lane_gen[3].lane_inst~phy_reg1
|
|
Info (332115): Data Arrival Time : 6.626
|
|
Info (332115): Data Required Time : 6.818
|
|
Info (332115): Slack : 0.192
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 0.213
|
|
Info (20696): -to_clock [get_clocks {mem|ddr4a|ddr4a_core_usr_clk}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 0.213
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : mem|ddr4b|ddr4b|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[0].lane_gen[2].lane_inst~phy_reg1
|
|
Info (332115): To Node : mem|u0|ram_2port_0|altera_syncram_component|auto_generated|altsyncram1|lutrama19~reg0
|
|
Info (332115): Launch Clock : mem|ddr4b|ddr4b_phy_clk_l_2
|
|
Info (332115): Latch Clock : mem|ddr4a|ddr4a_core_usr_clk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.117 0.117 launch edge time
|
|
Info (332115): 3.480 3.363 R clock network delay
|
|
Info (332115): 3.480 0.000 mem|ddr4b|ddr4b|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[0].lane_gen[2].lane_inst~phy_reg1
|
|
Info (332115): 4.434 0.954 FF uTco mem|ddr4b|ddr4b|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[0].lane_gen[2].lane_inst|data_to_core[56]
|
|
Info (332115): 6.234 1.800 FF IC High Speed mem|u0|ram_2port_0|altera_syncram_component|auto_generated|altsyncram1|lutrama19|portadatain[0]
|
|
Info (332115): 6.234 0.000 FF CELL High Speed mem|u0|ram_2port_0|altera_syncram_component|auto_generated|altsyncram1|lutrama19~reg0
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 3.869 3.869 latch edge time
|
|
Info (332115): 6.589 2.720 R clock network delay
|
|
Info (332115): 6.698 0.109 clock pessimism removed
|
|
Info (332115): 6.430 -0.268 clock uncertainty
|
|
Info (332115): 6.447 0.017 uTsu mem|u0|ram_2port_0|altera_syncram_component|auto_generated|altsyncram1|lutrama19~reg0
|
|
Info (332115): Data Arrival Time : 6.234
|
|
Info (332115): Data Required Time : 6.447
|
|
Info (332115): Slack : 0.213
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 0.280
|
|
Info (20696): -to_clock [get_clocks {mem|ddr4b|ddr4b_phy_clk_l_2}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 0.280
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : mem|ddr4b_avmm_chkr|clearing
|
|
Info (332115): To Node : mem|ddr4b|ddr4b|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[0].lane_gen[0].lane_inst~phy_reg1
|
|
Info (332115): Launch Clock : mem|ddr4a|ddr4a_core_usr_clk
|
|
Info (332115): Latch Clock : mem|ddr4b|ddr4b_phy_clk_l_2
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.117 0.117 launch edge time
|
|
Info (332115): 3.735 3.618 R clock network delay
|
|
Info (332115): 3.735 0.000 mem|ddr4b_avmm_chkr|clearing
|
|
Info (332115): 3.965 0.230 RR uTco mem|ddr4b_avmm_chkr|clearing|q
|
|
Info (332115): 4.103 0.138 RR CELL High Speed mem|ddr4b_avmm_chkr|clearing~la_lab/laboutb[17]
|
|
Info (332115): 5.070 0.967 RR IC High Speed mem|ddr4b_avmm_chkr|avm_writedata[0]~22|datad
|
|
Info (332115): 5.212 0.142 RF CELL High Speed mem|ddr4b_avmm_chkr|avm_writedata[0]~22|combout
|
|
Info (332115): 5.216 0.004 FF CELL High Speed mem|ddr4b_avmm_chkr|avm_writedata[0]~22~la_lab/laboutb[18]
|
|
Info (332115): 6.325 1.109 FF IC High Speed mem|ddr4b|ddr4b|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[0].lane_gen[0].lane_inst|data_from_core[94]
|
|
Info (332115): 6.325 0.000 FF CELL mem|ddr4b|ddr4b|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[0].lane_gen[0].lane_inst~phy_reg1
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 3.869 3.869 latch edge time
|
|
Info (332115): 6.435 2.566 R clock network delay
|
|
Info (332115): 6.544 0.109 clock pessimism removed
|
|
Info (332115): 6.255 -0.289 clock uncertainty
|
|
Info (332115): 6.605 0.350 uTsu mem|ddr4b|ddr4b|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[0].lane_gen[0].lane_inst~phy_reg1
|
|
Info (332115): Data Arrival Time : 6.325
|
|
Info (332115): Data Required Time : 6.605
|
|
Info (332115): Slack : 0.280
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 0.494
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_bonding_clocks[0]}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 0.494
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|sta_rx_clk2_by4_1
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs~byte_deserializer_pcs_clk_div_by_4_txclk_reg.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|rx_clk (INVERTED)
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_bonding_clocks[0]
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 1.000 1.000 launch edge time
|
|
Info (332115): 5.276 4.276 F clock network delay
|
|
Info (332115): 5.276 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|sta_rx_clk2_by4_1
|
|
Info (332115): 5.276 0.000 FF CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs~byte_deserializer_pcs_clk_div_by_4_txclk_reg.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 2.000 2.000 latch edge time
|
|
Info (332115): 4.392 2.392 R clock network delay
|
|
Info (332115): 5.816 1.424 clock pessimism removed
|
|
Info (332115): 5.770 -0.046 uTsu fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs~byte_deserializer_pcs_clk_div_by_4_txclk_reg.reg
|
|
Info (332115): Data Arrival Time : 5.276
|
|
Info (332115): Data Required Time : 5.770
|
|
Info (332115): Slack : 0.494
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 0.633
|
|
Info (20696): -to_clock [get_clocks {mem|ddr4a|ddr4a_phy_clk_l_0}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 0.633
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : mem|ddr4a_bridge|ddr_avmm_bridge|cmd_burstcount[5]
|
|
Info (332115): To Node : mem|ddr4a|ddr4a|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[1].tile_ctrl_inst~hmc_reg1
|
|
Info (332115): Launch Clock : mem|ddr4a|ddr4a_core_usr_clk
|
|
Info (332115): Latch Clock : mem|ddr4a|ddr4a_phy_clk_l_0
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.117 0.117 launch edge time
|
|
Info (332115): 3.847 3.730 R clock network delay
|
|
Info (332115): 3.847 0.000 mem|ddr4a_bridge|ddr_avmm_bridge|cmd_burstcount[5]
|
|
Info (332115): 4.088 0.241 RR uTco mem|ddr4a_bridge|ddr_avmm_bridge|cmd_burstcount[5]|q
|
|
Info (332115): 4.282 0.194 RR CELL High Speed mem|ddr4a_bridge|ddr_avmm_bridge|cmd_burstcount[5]~la_mlab/laboutb[15]
|
|
Info (332115): 4.623 0.341 RR IC High Speed mem|ddr4a_avmm_chkr|LessThan_0~0|datab
|
|
Info (332115): 4.881 0.258 RF CELL High Speed mem|ddr4a_avmm_chkr|LessThan_0~0|combout
|
|
Info (332115): 4.885 0.004 FF CELL High Speed mem|ddr4a_avmm_chkr|LessThan_0~0~la_lab/laboutb[6]
|
|
Info (332115): 5.070 0.185 FF IC High Speed mem|ddr4a_avmm_chkr|start_error|datac
|
|
Info (332115): 5.252 0.182 FR CELL High Speed mem|ddr4a_avmm_chkr|start_error|combout
|
|
Info (332115): 5.257 0.005 RR CELL High Speed mem|ddr4a_avmm_chkr|start_error~la_mlab/laboutt[6]
|
|
Info (332115): 5.419 0.162 RR IC High Speed mem|ddr4a_avmm_chkr|avm_write~1|datae
|
|
Info (332115): 5.568 0.149 RR CELL High Speed mem|ddr4a_avmm_chkr|avm_write~1|combout
|
|
Info (332115): 5.573 0.005 RR CELL High Speed mem|ddr4a_avmm_chkr|avm_write~1~la_mlab/laboutt[9]
|
|
Info (332115): 6.648 1.075 RR IC High Speed mem|ddr4a|ddr4a|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[1].tile_ctrl_inst|core2ctl_avl0[1]
|
|
Info (332115): 6.648 0.000 RR CELL mem|ddr4a|ddr4a|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[1].tile_ctrl_inst~hmc_reg1
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 3.869 3.869 latch edge time
|
|
Info (332115): 6.610 2.741 R clock network delay
|
|
Info (332115): 7.211 0.601 clock pessimism removed
|
|
Info (332115): 7.019 -0.192 clock uncertainty
|
|
Info (332115): 7.281 0.262 uTsu mem|ddr4a|ddr4a|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[1].tile_ctrl_inst~hmc_reg1
|
|
Info (332115): Data Arrival Time : 6.648
|
|
Info (332115): Data Required Time : 7.281
|
|
Info (332115): Slack : 0.633
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 0.704
|
|
Info (20696): -to_clock [get_clocks {u0|dcp_iopll|dcp_iopll|clk100}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 0.704
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_bitstream_host|alt_pr_bitstream_controller_v2|pr_data_reg[3]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_bitstream_host|alt_pr_bitstream_controller_v2|pr_data_reg2[3]
|
|
Info (332115): Launch Clock : u0|dcp_iopll|dcp_iopll|clk100
|
|
Info (332115): Latch Clock : u0|dcp_iopll|dcp_iopll|clk100 (INVERTED)
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 9.726 9.726 R clock network delay
|
|
Info (332115): 9.726 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_bitstream_host|alt_pr_bitstream_controller_v2|pr_data_reg[3]
|
|
Info (332115): 9.956 0.230 RR uTco fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_bitstream_host|alt_pr_bitstream_controller_v2|pr_data_reg[3]|q
|
|
Info (332115): 10.087 0.131 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_bitstream_host|alt_pr_bitstream_controller_v2|pr_data_reg[3]~la_lab/laboutb[2]
|
|
Info (332115): 13.946 3.859 RR IC Mixed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_bitstream_host|alt_pr_bitstream_controller_v2|pr_data_reg2[3]|d
|
|
Info (332115): 13.946 0.000 RR CELL Low Power fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_bitstream_host|alt_pr_bitstream_controller_v2|pr_data_reg2[3]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 5.000 5.000 latch edge time
|
|
Info (332115): 13.269 8.269 F clock network delay
|
|
Info (332115): 14.515 1.246 clock pessimism removed
|
|
Info (332115): 14.345 -0.170 clock uncertainty
|
|
Info (332115): 14.650 0.305 uTsu fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_bitstream_host|alt_pr_bitstream_controller_v2|pr_data_reg2[3]
|
|
Info (332115): Data Arrival Time : 13.946
|
|
Info (332115): Data Required Time : 14.650
|
|
Info (332115): Slack : 0.704
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 0.720
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|pld_clk}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 0.720
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_sriov_2.sriov2.sriov_bridge|altpcie_pcie_sriov2_top_inst|altpcie_sriov2_tx_data_bridge_inst|TxStData_hip_o[209]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~pld_clk.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|wys~CORE_CLK_OUT
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|pld_clk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 9.498 9.498 R clock network delay
|
|
Info (332115): 9.498 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_sriov_2.sriov2.sriov_bridge|altpcie_pcie_sriov2_top_inst|altpcie_sriov2_tx_data_bridge_inst|TxStData_hip_o[209]
|
|
Info (332115): 9.771 0.273 FF uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_sriov_2.sriov2.sriov_bridge|altpcie_pcie_sriov2_top_inst|altpcie_sriov2_tx_data_bridge_inst|TxStData_hip_o[209]|q
|
|
Info (332115): 9.886 0.115 FF CELL Low Power fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_sriov_2.sriov2.sriov_bridge|altpcie_pcie_sriov2_top_inst|altpcie_sriov2_tx_data_bridge_inst|TxStData_hip_o[209]~la_mlab/laboutt[18]
|
|
Info (332115): 12.871 2.985 FF IC Mixed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|tx_st_data[209]
|
|
Info (332115): 12.871 0.000 FF CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~pld_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 4.000 4.000 latch edge time
|
|
Info (332115): 12.282 8.282 R clock network delay
|
|
Info (332115): 13.621 1.339 clock pessimism removed
|
|
Info (332115): 13.602 -0.019 clock uncertainty
|
|
Info (332115): 13.591 -0.011 uTsu fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~pld_clk.reg
|
|
Info (332115): Data Arrival Time : 12.871
|
|
Info (332115): Data Required Time : 13.591
|
|
Info (332115): Slack : 0.720
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 0.729
|
|
Info (20696): -to_clock [get_clocks {u0|dcp_iopll|dcp_iopll|clk1x}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 0.729
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|ReqAddr_q[11]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|TxCfgRdData[9]
|
|
Info (332115): Launch Clock : u0|dcp_iopll|dcp_iopll|clk1x
|
|
Info (332115): Latch Clock : u0|dcp_iopll|dcp_iopll|clk1x
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 9.756 9.756 R clock network delay
|
|
Info (332115): 9.756 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|ReqAddr_q[11]
|
|
Info (332115): 10.033 0.277 RR uTco fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|ReqAddr_q[11]|q
|
|
Info (332115): 10.198 0.165 RR CELL Low Power fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|ReqAddr_q[11]~la_lab/laboutt[6]
|
|
Info (332115): 10.641 0.443 RR IC Mixed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|Mux_1983~2|dataa
|
|
Info (332115): 10.972 0.331 RR CELL Low Power fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|Mux_1983~2|combout
|
|
Info (332115): 10.976 0.004 RR CELL Low Power fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|Mux_1983~2~la_lab/laboutb[8]
|
|
Info (332115): 11.273 0.297 RR IC Low Power fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|Mux_1983~12|datab
|
|
Info (332115): 11.587 0.314 RR CELL Low Power fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|Mux_1983~12|combout
|
|
Info (332115): 11.593 0.006 RR CELL Low Power fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|Mux_1983~12~la_mlab/laboutt[5]
|
|
Info (332115): 12.159 0.566 RR IC Low Power fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|Mux_2111~682|dataa
|
|
Info (332115): 12.481 0.322 RR CELL Low Power fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|Mux_2111~682|combout
|
|
Info (332115): 12.487 0.006 RR CELL Low Power fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|Mux_2111~682~la_mlab/laboutt[5]
|
|
Info (332115): 12.647 0.160 RR IC Low Power fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|Mux_2111~217|dataa
|
|
Info (332115): 12.964 0.317 RR CELL Low Power fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|Mux_2111~217|combout
|
|
Info (332115): 12.970 0.006 RR CELL Low Power fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|Mux_2111~217~la_mlab/laboutt[9]
|
|
Info (332115): 13.451 0.481 RR IC Low Power fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|Mux_2111~225|datad
|
|
Info (332115): 13.667 0.216 RR CELL Low Power fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|Mux_2111~225|combout
|
|
Info (332115): 13.673 0.006 RR CELL Low Power fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|Mux_2111~225~la_mlab/laboutt[16]
|
|
Info (332115): 13.850 0.177 RR IC Low Power fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|i1006~62|datab
|
|
Info (332115): 14.166 0.316 RR CELL Low Power fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|i1006~62|combout
|
|
Info (332115): 14.166 0.000 RR CELL Low Power fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|TxCfgRdData[9]|d
|
|
Info (332115): 14.166 0.000 RR CELL Low Power fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|TxCfgRdData[9]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 5.000 5.000 latch edge time
|
|
Info (332115): 13.366 8.366 R clock network delay
|
|
Info (332115): 14.706 1.340 clock pessimism removed
|
|
Info (332115): 14.556 -0.150 clock uncertainty
|
|
Info (332115): 14.895 0.339 uTsu fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|TxCfgRdData[9]
|
|
Info (332115): Data Arrival Time : 14.166
|
|
Info (332115): Data Required Time : 14.895
|
|
Info (332115): Slack : 0.729
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 1.172
|
|
Info (20696): -to_clock [get_clocks {PCIE_REFCLK}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 1.172
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|rom_rtl_0|auto_generated|ram_block1a35~reg0
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|cpu_memory[90][15]
|
|
Info (332115): Launch Clock : PCIE_REFCLK
|
|
Info (332115): Latch Clock : PCIE_REFCLK
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 5.743 5.743 R clock network delay
|
|
Info (332115): 5.743 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|rom_rtl_0|auto_generated|ram_block1a35~reg0
|
|
Info (332115): 7.850 2.107 FF uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|rom_rtl_0|auto_generated|ram_block1a35|portadataout[0]
|
|
Info (332115): 8.563 0.713 FF IC Mixed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|Select_36~16|dataf
|
|
Info (332115): 8.625 0.062 FR CELL Low Power fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|Select_36~16|combout
|
|
Info (332115): 8.629 0.004 RR CELL Low Power fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|Select_36~16~la_lab/laboutt[4]
|
|
Info (332115): 11.521 2.892 RR IC Mixed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|cpu_memory[90][31]~45|datad
|
|
Info (332115): 11.720 0.199 RR CELL Low Power fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|cpu_memory[90][31]~45|combout
|
|
Info (332115): 11.725 0.005 RR CELL Low Power fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|cpu_memory[90][31]~45~la_mlab/laboutb[18]
|
|
Info (332115): 14.478 2.753 RR IC Mixed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|cpu_memory[90][15]|ena
|
|
Info (332115): 14.478 0.000 RR CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|cpu_memory[90][15]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 10.000 10.000 latch edge time
|
|
Info (332115): 15.113 5.113 R clock network delay
|
|
Info (332115): 15.640 0.527 clock pessimism removed
|
|
Info (332115): 15.600 -0.040 clock uncertainty
|
|
Info (332115): 15.650 0.050 uTsu fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|cpu_memory[90][15]
|
|
Info (332115): Data Arrival Time : 14.478
|
|
Info (332115): Data Required Time : 15.650
|
|
Info (332115): Slack : 1.172
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 1.467
|
|
Info (20696): -to_clock [get_clocks {mem|ddr4a|ddr4a_core_cal_slave_clk}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 1.467
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : mem|ddr4b|ddr4b|arch|arch_inst|io_aux_inst|io_aux~soft_ram_reg
|
|
Info (332115): To Node : mem|ddr4b|ddr4b|cal_slave_component|ioaux_master_bridge|cmd_writedata[1]
|
|
Info (332115): Launch Clock : mem|ddr4a|ddr4a_core_cal_slave_clk
|
|
Info (332115): Latch Clock : mem|ddr4a|ddr4a_core_cal_slave_clk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 7.489 7.489 R clock network delay
|
|
Info (332115): 7.489 0.000 mem|ddr4b|ddr4b|arch|arch_inst|io_aux_inst|io_aux~soft_ram_reg
|
|
Info (332115): 8.359 0.870 FF uTco mem|ddr4b|ddr4b|arch|arch_inst|io_aux_inst|io_aux|soft_ram_write_data[1]
|
|
Info (332115): 12.159 3.800 FF IC High Speed mem|ddr4b|ddr4b|cal_slave_component|ioaux_master_bridge|cmd_writedata[1]|asdata
|
|
Info (332115): 12.159 0.000 FF CELL High Speed mem|ddr4b|ddr4b|cal_slave_component|ioaux_master_bridge|cmd_writedata[1]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 6.566 6.566 latch edge time
|
|
Info (332115): 12.618 6.052 R clock network delay
|
|
Info (332115): 13.555 0.937 clock pessimism removed
|
|
Info (332115): 13.505 -0.050 clock uncertainty
|
|
Info (332115): 13.626 0.121 uTsu mem|ddr4b|ddr4b|cal_slave_component|ioaux_master_bridge|cmd_writedata[1]
|
|
Info (332115): Data Arrival Time : 12.159
|
|
Info (332115): Data Required Time : 13.626
|
|
Info (332115): Slack : 1.467
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 1.727
|
|
Info (20696): -to_clock [get_clocks {SYS_RefClk}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 1.727
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_cb_host|alt_pr_cb_controller_v2|freeze_reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi.f2a_prmgmt_freeze
|
|
Info (332115): Launch Clock : u0|dcp_iopll|dcp_iopll|clk100
|
|
Info (332115): Latch Clock : SYS_RefClk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 9.694 9.694 R clock network delay
|
|
Info (332115): 9.694 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_cb_host|alt_pr_cb_controller_v2|freeze_reg
|
|
Info (332115): 9.930 0.236 RR uTco fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_cb_host|alt_pr_cb_controller_v2|freeze_reg|q
|
|
Info (332115): 10.099 0.169 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_cb_host|alt_pr_cb_controller_v2|freeze_reg~la_lab/laboutt[8]
|
|
Info (332115): 12.809 2.710 RR IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|i617~0|datae
|
|
Info (332115): 12.943 0.134 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|i617~0|combout
|
|
Info (332115): 12.943 0.000 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi.f2a_prmgmt_freeze|d
|
|
Info (332115): 12.943 0.000 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi.f2a_prmgmt_freeze
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 10.000 10.000 latch edge time
|
|
Info (332115): 14.382 4.382 R clock network delay
|
|
Info (332115): 14.644 0.262 clock pessimism removed
|
|
Info (332115): 14.334 -0.310 clock uncertainty
|
|
Info (332115): 14.670 0.336 uTsu fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi.f2a_prmgmt_freeze
|
|
Info (332115): Data Arrival Time : 12.943
|
|
Info (332115): Data Required Time : 14.670
|
|
Info (332115): Slack : 1.727
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 2.222
|
|
Info (20696): -to_clock [get_clocks {DDR4_RefClk}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 2.222
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|use_counter_lock.counter_lock_gen_master.cpa_count_to_lock[1]
|
|
Info (332115): To Node : mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|use_counter_lock.counter_lock_gen_master.cpa_count_to_lock[16]~LRTM_3
|
|
Info (332115): Launch Clock : DDR4_RefClk
|
|
Info (332115): Latch Clock : DDR4_RefClk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 4.325 4.325 R clock network delay
|
|
Info (332115): 4.325 0.000 mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|use_counter_lock.counter_lock_gen_master.cpa_count_to_lock[1]
|
|
Info (332115): 4.555 0.230 RR uTco mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|use_counter_lock.counter_lock_gen_master.cpa_count_to_lock[1]|q
|
|
Info (332115): 4.677 0.122 RR CELL High Speed mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|use_counter_lock.counter_lock_gen_master.cpa_count_to_lock[1]~la_lab/laboutt[1]
|
|
Info (332115): 4.834 0.157 RR IC High Speed mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|add_0~61|datac
|
|
Info (332115): 5.587 0.753 RR CELL High Speed mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|add_0~21|cin
|
|
Info (332115): 5.621 0.034 RF CELL High Speed mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|add_0~17|cout
|
|
Info (332115): 5.621 0.000 FF CELL High Speed mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|add_0~13|cin
|
|
Info (332115): 5.657 0.036 FR CELL High Speed mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|add_0~9|cout
|
|
Info (332115): 5.657 0.000 RR CELL High Speed mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|add_0~5|cin
|
|
Info (332115): 5.904 0.247 RF CELL High Speed mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|add_0~1|sumout
|
|
Info (332115): 5.908 0.004 FF CELL High Speed mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|add_0~1~la_lab/laboutb[10]
|
|
Info (332115): 6.043 0.135 FF IC High Speed mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|use_counter_lock.counter_lock_gen_master.cpa_count_to_lock[16]~LRTM_3|d
|
|
Info (332115): 6.043 0.000 FF CELL High Speed mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|use_counter_lock.counter_lock_gen_master.cpa_count_to_lock[16]~LRTM_3
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 3.752 3.752 latch edge time
|
|
Info (332115): 7.746 3.994 R clock network delay
|
|
Info (332115): 8.060 0.314 clock pessimism removed
|
|
Info (332115): 8.030 -0.030 clock uncertainty
|
|
Info (332115): 8.265 0.235 uTsu mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|use_counter_lock.counter_lock_gen_master.cpa_count_to_lock[16]~LRTM_3
|
|
Info (332115): Data Arrival Time : 6.043
|
|
Info (332115): Data Required Time : 8.265
|
|
Info (332115): Slack : 2.222
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 2.320
|
|
Info (20696): -to_clock [get_clocks {ETH_RefClk}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 2.320
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[6].ct0|dout_r[4]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[6].ct0|dout_r[5]
|
|
Info (332115): Launch Clock : ETH_RefClk
|
|
Info (332115): Latch Clock : ETH_RefClk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 5.556 5.556 R clock network delay
|
|
Info (332115): 5.556 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[6].ct0|dout_r[4]
|
|
Info (332115): 5.819 0.263 RR uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[6].ct0|dout_r[4]|q
|
|
Info (332115): 6.024 0.205 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[6].ct0|dout_r[4]~la_lab/laboutb[19]
|
|
Info (332115): 6.280 0.256 RR IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[6].ct0|t5|dout|datab
|
|
Info (332115): 6.611 0.331 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[6].ct0|t5|dout|combout
|
|
Info (332115): 6.611 0.000 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[6].ct0|dout_r[5]|d
|
|
Info (332115): 6.611 0.000 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[6].ct0|dout_r[5]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 3.103 3.103 latch edge time
|
|
Info (332115): 8.070 4.967 R clock network delay
|
|
Info (332115): 8.659 0.589 clock pessimism removed
|
|
Info (332115): 8.619 -0.040 clock uncertainty
|
|
Info (332115): 8.931 0.312 uTsu fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[6].ct0|dout_r[5]
|
|
Info (332115): Data Arrival Time : 6.611
|
|
Info (332115): Data Required Time : 8.931
|
|
Info (332115): Slack : 2.320
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 2.323
|
|
Info (20696): -to_clock [get_clocks {hssi_pll_r_0_outclk0}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 2.323
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[2].ct0|dout_r[0]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[2].ct0|dout_r[1]
|
|
Info (332115): Launch Clock : hssi_pll_r_0_outclk0
|
|
Info (332115): Latch Clock : hssi_pll_r_0_outclk0
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 5.057 5.057 R clock network delay
|
|
Info (332115): 5.057 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[2].ct0|dout_r[0]
|
|
Info (332115): 5.331 0.274 RR uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[2].ct0|dout_r[0]|q
|
|
Info (332115): 5.536 0.205 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[2].ct0|dout_r[0]~la_lab/laboutb[7]
|
|
Info (332115): 5.799 0.263 RR IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[2].ct0|t1|dout|datab
|
|
Info (332115): 6.131 0.332 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[2].ct0|t1|dout|combout
|
|
Info (332115): 6.131 0.000 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[2].ct0|dout_r[1]|d
|
|
Info (332115): 6.131 0.000 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[2].ct0|dout_r[1]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 3.200 3.200 latch edge time
|
|
Info (332115): 7.737 4.537 R clock network delay
|
|
Info (332115): 8.257 0.520 clock pessimism removed
|
|
Info (332115): 8.147 -0.110 clock uncertainty
|
|
Info (332115): 8.454 0.307 uTsu fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[2].ct0|dout_r[1]
|
|
Info (332115): Data Arrival Time : 6.131
|
|
Info (332115): Data Required Time : 8.454
|
|
Info (332115): Slack : 2.323
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 2.357
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_clk}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 2.357
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_prbs_done_sync|resync_chains[0].sync_r[1]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_snapshot[6]
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_clk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_clk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 7.219 7.219 R clock network delay
|
|
Info (332115): 7.219 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_prbs_done_sync|resync_chains[0].sync_r[1]
|
|
Info (332115): 7.449 0.230 RR uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_prbs_done_sync|resync_chains[0].sync_r[1]|q
|
|
Info (332115): 7.625 0.176 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_prbs_done_sync|resync_chains[0].sync_r[1]~la_lab/laboutb[3]
|
|
Info (332115): 8.141 0.516 RR IC High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_snapshot[1]~0|datac
|
|
Info (332115): 8.302 0.161 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_snapshot[1]~0|combout
|
|
Info (332115): 8.306 0.004 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_snapshot[1]~0~la_lab/laboutt[7]
|
|
Info (332115): 8.712 0.406 RR IC High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_snapshot[6]|ena
|
|
Info (332115): 8.712 0.000 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_snapshot[6]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 3.878 3.878 latch edge time
|
|
Info (332115): 9.026 5.148 R clock network delay
|
|
Info (332115): 11.049 2.023 clock pessimism removed
|
|
Info (332115): 11.019 -0.030 clock uncertainty
|
|
Info (332115): 11.069 0.050 uTsu fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_snapshot[6]
|
|
Info (332115): Data Arrival Time : 8.712
|
|
Info (332115): Data Required Time : 11.069
|
|
Info (332115): Slack : 2.357
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 2.357
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|rx_pma_clk}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 2.357
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_prbs_reset_sync|resync_chains[0].sync_r[2]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_snapshot[6]
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|rx_pma_clk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|rx_pma_clk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 7.246 7.246 R clock network delay
|
|
Info (332115): 7.246 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_prbs_reset_sync|resync_chains[0].sync_r[2]
|
|
Info (332115): 7.476 0.230 RR uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_prbs_reset_sync|resync_chains[0].sync_r[2]|q
|
|
Info (332115): 7.594 0.118 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_prbs_reset_sync|resync_chains[0].sync_r[2]~la_lab/laboutt[14]
|
|
Info (332115): 8.050 0.456 RR IC High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_snapshot[0]~0|dataa
|
|
Info (332115): 8.314 0.264 RF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_snapshot[0]~0|combout
|
|
Info (332115): 8.318 0.004 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_snapshot[0]~0~la_lab/laboutt[8]
|
|
Info (332115): 8.750 0.432 FF IC High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_snapshot[6]|ena
|
|
Info (332115): 8.750 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_snapshot[6]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 3.878 3.878 latch edge time
|
|
Info (332115): 9.049 5.171 R clock network delay
|
|
Info (332115): 11.082 2.033 clock pessimism removed
|
|
Info (332115): 11.052 -0.030 clock uncertainty
|
|
Info (332115): 11.107 0.055 uTsu fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_snapshot[6]
|
|
Info (332115): Data Arrival Time : 8.750
|
|
Info (332115): Data Required Time : 11.107
|
|
Info (332115): Slack : 2.357
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 2.366
|
|
Info (20696): -to_clock [get_clocks {hssi_pll_t_outclk0}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 2.366
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[3].ct0|dout_r[0]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[3].ct0|dout_r[1]
|
|
Info (332115): Launch Clock : hssi_pll_t_outclk0
|
|
Info (332115): Latch Clock : hssi_pll_t_outclk0
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 4.737 4.737 R clock network delay
|
|
Info (332115): 4.737 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[3].ct0|dout_r[0]
|
|
Info (332115): 5.004 0.267 RR uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[3].ct0|dout_r[0]|q
|
|
Info (332115): 5.144 0.140 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[3].ct0|dout_r[0]~la_lab/laboutt[2]
|
|
Info (332115): 5.399 0.255 RR IC Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[3].ct0|t1|dout|datab
|
|
Info (332115): 5.730 0.331 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[3].ct0|t1|dout|combout
|
|
Info (332115): 5.730 0.000 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[3].ct0|dout_r[1]|d
|
|
Info (332115): 5.730 0.000 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[3].ct0|dout_r[1]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 3.200 3.200 latch edge time
|
|
Info (332115): 7.465 4.265 R clock network delay
|
|
Info (332115): 7.937 0.472 clock pessimism removed
|
|
Info (332115): 7.827 -0.110 clock uncertainty
|
|
Info (332115): 8.096 0.269 uTsu fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[3].ct0|dout_r[1]
|
|
Info (332115): Data Arrival Time : 5.730
|
|
Info (332115): Data Required Time : 8.096
|
|
Info (332115): Slack : 2.366
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 2.482
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|rx_pma_clk}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 2.482
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_prbs_reset_sync|resync_chains[0].sync_r[2]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_snapshot[1]
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|rx_pma_clk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|rx_pma_clk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 7.156 7.156 R clock network delay
|
|
Info (332115): 7.156 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_prbs_reset_sync|resync_chains[0].sync_r[2]
|
|
Info (332115): 7.396 0.240 RR uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_prbs_reset_sync|resync_chains[0].sync_r[2]|q
|
|
Info (332115): 7.592 0.196 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_prbs_reset_sync|resync_chains[0].sync_r[2]~la_mlab/laboutb[12]
|
|
Info (332115): 8.217 0.625 RR IC High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_snapshot[5]~0|datad
|
|
Info (332115): 8.363 0.146 RF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_snapshot[5]~0|combout
|
|
Info (332115): 8.367 0.004 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_snapshot[5]~0~la_lab/laboutb[0]
|
|
Info (332115): 8.524 0.157 FF IC High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_snapshot[1]|ena
|
|
Info (332115): 8.524 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_snapshot[1]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 3.878 3.878 latch edge time
|
|
Info (332115): 8.952 5.074 R clock network delay
|
|
Info (332115): 10.986 2.034 clock pessimism removed
|
|
Info (332115): 10.956 -0.030 clock uncertainty
|
|
Info (332115): 11.006 0.050 uTsu fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_snapshot[1]
|
|
Info (332115): Data Arrival Time : 8.524
|
|
Info (332115): Data Required Time : 11.006
|
|
Info (332115): Slack : 2.482
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 2.547
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|rx_pma_clk}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 2.547
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_prbs_err_sync|resync_chains[0].sync_r[1]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_count[0]
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|rx_pma_clk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|rx_pma_clk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 7.206 7.206 R clock network delay
|
|
Info (332115): 7.206 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_prbs_err_sync|resync_chains[0].sync_r[1]
|
|
Info (332115): 7.436 0.230 RR uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_prbs_err_sync|resync_chains[0].sync_r[1]|q
|
|
Info (332115): 7.554 0.118 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_prbs_err_sync|resync_chains[0].sync_r[1]~la_mlab/laboutt[14]
|
|
Info (332115): 7.900 0.346 RR IC High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|add_2~1|datab
|
|
Info (332115): 8.411 0.511 RF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|add_2~1|sumout
|
|
Info (332115): 8.415 0.004 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|add_2~1~la_lab/laboutb[1]
|
|
Info (332115): 8.611 0.196 FF IC High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|i58~0|datad
|
|
Info (332115): 8.797 0.186 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|i58~0|combout
|
|
Info (332115): 8.797 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_count[0]|d
|
|
Info (332115): 8.797 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_count[0]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 3.878 3.878 latch edge time
|
|
Info (332115): 9.011 5.133 R clock network delay
|
|
Info (332115): 11.084 2.073 clock pessimism removed
|
|
Info (332115): 11.054 -0.030 clock uncertainty
|
|
Info (332115): 11.344 0.290 uTsu fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_count[0]
|
|
Info (332115): Data Arrival Time : 8.797
|
|
Info (332115): Data Required Time : 11.344
|
|
Info (332115): Slack : 2.547
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 2.946
|
|
Info (20696): -to_clock [get_clocks {hssi_pll_r_0_outclk1}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 2.946
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[0].ct0|dout_r[0]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[0].ct0|dout_r[2]
|
|
Info (332115): Launch Clock : hssi_pll_r_0_outclk1
|
|
Info (332115): Latch Clock : hssi_pll_r_0_outclk1
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 5.033 5.033 R clock network delay
|
|
Info (332115): 5.033 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[0].ct0|dout_r[0]
|
|
Info (332115): 5.299 0.266 RR uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[0].ct0|dout_r[0]|q
|
|
Info (332115): 5.504 0.205 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[0].ct0|dout_r[0]~la_lab/laboutb[15]
|
|
Info (332115): 5.777 0.273 RR IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[0].ct0|t2|dout|dataa
|
|
Info (332115): 6.109 0.332 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[0].ct0|t2|dout|combout
|
|
Info (332115): 6.109 0.000 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[0].ct0|dout_r[2]|d
|
|
Info (332115): 6.109 0.000 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[0].ct0|dout_r[2]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 3.800 3.800 latch edge time
|
|
Info (332115): 8.311 4.511 R clock network delay
|
|
Info (332115): 8.833 0.522 clock pessimism removed
|
|
Info (332115): 8.723 -0.110 clock uncertainty
|
|
Info (332115): 9.055 0.332 uTsu fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[0].ct0|dout_r[2]
|
|
Info (332115): Data Arrival Time : 6.109
|
|
Info (332115): Data Required Time : 9.055
|
|
Info (332115): Slack : 2.946
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 3.017
|
|
Info (20696): -to_clock [get_clocks {hssi_pll_t_outclk1}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 3.017
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[1].ct0|dout_r[5]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[1].ct0|dout_r[5]
|
|
Info (332115): Launch Clock : hssi_pll_t_outclk1
|
|
Info (332115): Latch Clock : hssi_pll_t_outclk1
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 4.658 4.658 R clock network delay
|
|
Info (332115): 4.658 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[1].ct0|dout_r[5]
|
|
Info (332115): 4.898 0.240 RR uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[1].ct0|dout_r[5]|q
|
|
Info (332115): 5.068 0.170 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[1].ct0|dout_r[5]~la_mlab/laboutt[16]
|
|
Info (332115): 5.396 0.328 RR IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[1].ct0|t5|dout|datae
|
|
Info (332115): 5.553 0.157 RF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[1].ct0|t5|dout|combout
|
|
Info (332115): 5.553 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[1].ct0|dout_r[5]|d
|
|
Info (332115): 5.553 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[1].ct0|dout_r[5]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 3.800 3.800 latch edge time
|
|
Info (332115): 7.996 4.196 R clock network delay
|
|
Info (332115): 8.458 0.462 clock pessimism removed
|
|
Info (332115): 8.348 -0.110 clock uncertainty
|
|
Info (332115): 8.570 0.222 uTsu fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[1].ct0|dout_r[5]
|
|
Info (332115): Data Arrival Time : 5.553
|
|
Info (332115): Data Required Time : 8.570
|
|
Info (332115): Slack : 3.017
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 3.295
|
|
Info (20696): -to_clock [get_clocks {vl_qph_user_clk_clkpsc_clk1}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 3.295
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[0]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[1]
|
|
Info (332115): Launch Clock : vl_qph_user_clk_clkpsc_clk1
|
|
Info (332115): Latch Clock : vl_qph_user_clk_clkpsc_clk1
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 6.991 6.991 R clock network delay
|
|
Info (332115): 6.991 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[0]
|
|
Info (332115): 7.240 0.249 RR uTco fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[0]|q
|
|
Info (332115): 7.361 0.121 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[0]~la_mlab/laboutb[9]
|
|
Info (332115): 8.202 0.841 RR IC Mixed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[1]~2|dataa
|
|
Info (332115): 8.477 0.275 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[1]~2|combout
|
|
Info (332115): 8.477 0.000 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[1]|d
|
|
Info (332115): 8.477 0.000 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[1]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 4.545 4.545 latch edge time
|
|
Info (332115): 10.323 5.778 R clock network delay
|
|
Info (332115): 11.531 1.208 clock pessimism removed
|
|
Info (332115): 11.501 -0.030 clock uncertainty
|
|
Info (332115): 11.772 0.271 uTsu fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[1]
|
|
Info (332115): Data Arrival Time : 8.477
|
|
Info (332115): Data Required Time : 11.772
|
|
Info (332115): Slack : 3.295
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 3.838
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|avmmclk}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 3.838
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|reconfig_read
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Launch Clock : SYS_RefClk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|avmmclk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 4.777 4.777 R clock network delay
|
|
Info (332115): 4.777 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|reconfig_read
|
|
Info (332115): 5.024 0.247 FF uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|reconfig_read|q
|
|
Info (332115): 5.158 0.134 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|reconfig_read~la_mlab/laboutb[4]
|
|
Info (332115): 6.570 1.412 FF IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|avmm_read[1]~1|dataa
|
|
Info (332115): 6.806 0.236 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|avmm_read[1]~1|combout
|
|
Info (332115): 6.810 0.004 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|avmm_read[1]~1~la_lab/laboutt[7]
|
|
Info (332115): 11.236 4.426 FF IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst|avmmread
|
|
Info (332115): 11.236 0.000 FF CELL fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 10.000 10.000 latch edge time
|
|
Info (332115): 14.624 4.624 R clock network delay
|
|
Info (332115): 14.886 0.262 clock pessimism removed
|
|
Info (332115): 14.856 -0.030 clock uncertainty
|
|
Info (332115): 15.074 0.218 uTsu fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Arrival Time : 11.236
|
|
Info (332115): Data Required Time : 15.074
|
|
Info (332115): Slack : 3.838
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 3.882
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|avmmclk}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 3.882
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|reconfig_address[11]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Launch Clock : SYS_RefClk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|avmmclk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 4.762 4.762 R clock network delay
|
|
Info (332115): 4.762 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|reconfig_address[11]
|
|
Info (332115): 4.995 0.233 RR uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|reconfig_address[11]|q
|
|
Info (332115): 5.142 0.147 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|reconfig_address[11]~la_mlab/laboutb[9]
|
|
Info (332115): 6.546 1.404 RR IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|avmm_write[2]~2|datab
|
|
Info (332115): 6.838 0.292 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|avmm_write[2]~2|combout
|
|
Info (332115): 6.842 0.004 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|avmm_write[2]~2~la_lab/laboutb[4]
|
|
Info (332115): 10.983 4.141 RR IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst|avmmwrite
|
|
Info (332115): 10.983 0.000 RR CELL fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 10.000 10.000 latch edge time
|
|
Info (332115): 14.617 4.617 R clock network delay
|
|
Info (332115): 14.879 0.262 clock pessimism removed
|
|
Info (332115): 14.849 -0.030 clock uncertainty
|
|
Info (332115): 14.865 0.016 uTsu fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Arrival Time : 10.983
|
|
Info (332115): Data Required Time : 14.865
|
|
Info (332115): Slack : 3.882
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 4.004
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|avmmclk}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 4.004
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|reconfig_read
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Launch Clock : SYS_RefClk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|avmmclk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 4.777 4.777 R clock network delay
|
|
Info (332115): 4.777 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|reconfig_read
|
|
Info (332115): 5.024 0.247 RR uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|reconfig_read|q
|
|
Info (332115): 5.207 0.183 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|reconfig_read~la_mlab/laboutb[4]
|
|
Info (332115): 6.645 1.438 RR IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|avmm_read[0]~0|dataa
|
|
Info (332115): 6.935 0.290 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|avmm_read[0]~0|combout
|
|
Info (332115): 6.939 0.004 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|avmm_read[0]~0~la_lab/laboutt[4]
|
|
Info (332115): 11.106 4.167 RR IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst|avmmread
|
|
Info (332115): 11.106 0.000 RR CELL fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 10.000 10.000 latch edge time
|
|
Info (332115): 14.637 4.637 R clock network delay
|
|
Info (332115): 14.899 0.262 clock pessimism removed
|
|
Info (332115): 14.869 -0.030 clock uncertainty
|
|
Info (332115): 15.110 0.241 uTsu fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Arrival Time : 11.106
|
|
Info (332115): Data Required Time : 15.110
|
|
Info (332115): Slack : 4.004
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 4.810
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|avmmclk}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 4.810
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_address[3]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Launch Clock : PCIE_REFCLK
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|avmmclk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 5.720 5.720 R clock network delay
|
|
Info (332115): 5.720 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_address[3]
|
|
Info (332115): 5.985 0.265 RR uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_address[3]|q
|
|
Info (332115): 6.213 0.228 RR CELL Low Power fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_address[3]~la_lab/laboutt[19]
|
|
Info (332115): 7.253 1.040 RR IC Mixed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i1697|dataf
|
|
Info (332115): 7.297 0.044 RR CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i1697|combout
|
|
Info (332115): 7.301 0.004 RR CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i1697~la_lab/laboutb[0]
|
|
Info (332115): 10.954 3.653 RR IC Mixed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst|avmmaddress[3]
|
|
Info (332115): 10.954 0.000 RR CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 10.000 10.000 latch edge time
|
|
Info (332115): 15.329 5.329 R clock network delay
|
|
Info (332115): 15.839 0.510 clock pessimism removed
|
|
Info (332115): 15.799 -0.040 clock uncertainty
|
|
Info (332115): 15.764 -0.035 uTsu fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Arrival Time : 10.954
|
|
Info (332115): Data Required Time : 15.764
|
|
Info (332115): Slack : 4.810
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 4.844
|
|
Info (20696): -to_clock [get_clocks {fspi_sclk}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 4.844
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_altera_avalon_st_packets_to_bytes_inst_for_spichain|the_altera_avalon_st_packets_to_bytes|out_data[6]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MISOctl|rdshiftreg[0]
|
|
Info (332115): Launch Clock : u0|dcp_iopll|dcp_iopll|clk1x
|
|
Info (332115): Latch Clock : fspi_sclk
|
|
Info (332115): Exception : dcp_bbs.sdc:3006: set_multicycle_path -setup -to [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MISOctl|rdshiftreg*}] 2
|
|
Info (332115): Multicycle - Setup Start : 2
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 240.000 240.000 launch edge time
|
|
Info (332115): 249.700 9.700 R clock network delay
|
|
Info (332115): 249.700 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_altera_avalon_st_packets_to_bytes_inst_for_spichain|the_altera_avalon_st_packets_to_bytes|out_data[6]
|
|
Info (332115): 249.930 0.230 RR uTco fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_altera_avalon_st_packets_to_bytes_inst_for_spichain|the_altera_avalon_st_packets_to_bytes|out_data[6]|q
|
|
Info (332115): 250.099 0.169 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_altera_avalon_st_packets_to_bytes_inst_for_spichain|the_altera_avalon_st_packets_to_bytes|out_data[6]~la_lab/laboutb[8]
|
|
Info (332115): 250.353 0.254 RR IC High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_altera_avalon_st_idle_inserter|i15~1|datab
|
|
Info (332115): 250.636 0.283 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_altera_avalon_st_idle_inserter|i15~1|combout
|
|
Info (332115): 250.640 0.004 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_altera_avalon_st_idle_inserter|i15~1~la_lab/laboutb[5]
|
|
Info (332115): 250.814 0.174 RR IC High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MISOctl|i36~7|dataa
|
|
Info (332115): 251.100 0.286 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MISOctl|i36~7|combout
|
|
Info (332115): 251.100 0.000 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MISOctl|rdshiftreg[0]|d
|
|
Info (332115): 251.100 0.000 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MISOctl|rdshiftreg[0]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 250.000 250.000 latch edge time
|
|
Info (332115): 255.958 5.958 R clock network delay
|
|
Info (332115): 255.648 -0.310 clock uncertainty
|
|
Info (332115): 255.944 0.296 uTsu fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MISOctl|rdshiftreg[0]
|
|
Info (332115): Data Arrival Time : 251.100
|
|
Info (332115): Data Required Time : 255.944
|
|
Info (332115): Slack : 4.844
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 4.877
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|avmmclk}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 4.877
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|reconfig_read
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Launch Clock : SYS_RefClk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|avmmclk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 4.777 4.777 R clock network delay
|
|
Info (332115): 4.777 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|reconfig_read
|
|
Info (332115): 5.024 0.247 RR uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|reconfig_read|q
|
|
Info (332115): 5.207 0.183 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|reconfig_read~la_mlab/laboutb[4]
|
|
Info (332115): 6.563 1.356 RR IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|avmm_read[3]~3|datab
|
|
Info (332115): 6.840 0.277 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|avmm_read[3]~3|combout
|
|
Info (332115): 6.845 0.005 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|avmm_read[3]~3~la_mlab/laboutt[2]
|
|
Info (332115): 10.326 3.481 RR IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst|avmmread
|
|
Info (332115): 10.326 0.000 RR CELL fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 10.000 10.000 latch edge time
|
|
Info (332115): 14.730 4.730 R clock network delay
|
|
Info (332115): 14.992 0.262 clock pessimism removed
|
|
Info (332115): 14.962 -0.030 clock uncertainty
|
|
Info (332115): 15.203 0.241 uTsu fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Arrival Time : 10.326
|
|
Info (332115): Data Required Time : 15.203
|
|
Info (332115): Slack : 4.877
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 5.308
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|avmmclk}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 5.308
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_writedata[4]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Launch Clock : PCIE_REFCLK
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|avmmclk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 5.696 5.696 R clock network delay
|
|
Info (332115): 5.696 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_writedata[4]
|
|
Info (332115): 5.935 0.239 FF uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_writedata[4]|q
|
|
Info (332115): 6.028 0.093 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_writedata[4]~la_lab/laboutt[5]
|
|
Info (332115): 6.999 0.971 FF IC Mixed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i1496~4|datac
|
|
Info (332115): 7.210 0.211 FF CELL Low Power fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i1496~4|combout
|
|
Info (332115): 7.215 0.005 FF CELL Low Power fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i1496~4~la_mlab/laboutt[14]
|
|
Info (332115): 10.454 3.239 FF IC Mixed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst|avmmwritedata[4]
|
|
Info (332115): 10.454 0.000 FF CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 10.000 10.000 latch edge time
|
|
Info (332115): 15.350 5.350 R clock network delay
|
|
Info (332115): 15.860 0.510 clock pessimism removed
|
|
Info (332115): 15.820 -0.040 clock uncertainty
|
|
Info (332115): 15.762 -0.058 uTsu fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Arrival Time : 10.454
|
|
Info (332115): Data Required Time : 15.762
|
|
Info (332115): Slack : 5.308
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 5.596
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|tx_pma_div_clk}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 5.596
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[5].ct0|dout_r[5]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[5].ct0|dout_r[5]
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|tx_pma_div_clk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|tx_pma_div_clk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 8.772 8.772 R clock network delay
|
|
Info (332115): 8.772 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[5].ct0|dout_r[5]
|
|
Info (332115): 9.002 0.230 RR uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[5].ct0|dout_r[5]|q
|
|
Info (332115): 9.171 0.169 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[5].ct0|dout_r[5]~la_lab/laboutb[8]
|
|
Info (332115): 9.623 0.452 RR IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[5].ct0|t5|dout|datae
|
|
Info (332115): 9.770 0.147 RF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[5].ct0|t5|dout|combout
|
|
Info (332115): 9.770 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[5].ct0|dout_r[5]|d
|
|
Info (332115): 9.770 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[5].ct0|dout_r[5]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 6.399 6.399 latch edge time
|
|
Info (332115): 13.204 6.805 R clock network delay
|
|
Info (332115): 15.172 1.968 clock pessimism removed
|
|
Info (332115): 15.152 -0.020 clock uncertainty
|
|
Info (332115): 15.366 0.214 uTsu fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[5].ct0|dout_r[5]
|
|
Info (332115): Data Arrival Time : 9.770
|
|
Info (332115): Data Required Time : 15.366
|
|
Info (332115): Slack : 5.596
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 5.604
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|avmmclk}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 5.604
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|g_arb[5].arbiter_inst|grant[0]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Launch Clock : PCIE_REFCLK
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|avmmclk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 5.714 5.714 R clock network delay
|
|
Info (332115): 5.714 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|g_arb[5].arbiter_inst|grant[0]
|
|
Info (332115): 5.993 0.279 FF uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|g_arb[5].arbiter_inst|grant[0]|q
|
|
Info (332115): 6.139 0.146 FF CELL Low Power fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|g_arb[5].arbiter_inst|grant[0]~la_mlab/laboutb[11]
|
|
Info (332115): 6.890 0.751 FF IC Low Power fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i1215|dataf
|
|
Info (332115): 6.941 0.051 FF CELL Low Power fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i1215|combout
|
|
Info (332115): 6.945 0.004 FF CELL Low Power fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i1215~la_lab/laboutt[2]
|
|
Info (332115): 10.107 3.162 FF IC Mixed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst|avmmaddress[1]
|
|
Info (332115): 10.107 0.000 FF CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 10.000 10.000 latch edge time
|
|
Info (332115): 15.315 5.315 R clock network delay
|
|
Info (332115): 15.825 0.510 clock pessimism removed
|
|
Info (332115): 15.785 -0.040 clock uncertainty
|
|
Info (332115): 15.711 -0.074 uTsu fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Arrival Time : 10.107
|
|
Info (332115): Data Required Time : 15.711
|
|
Info (332115): Slack : 5.604
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 5.662
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_div_clk}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 5.662
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[4].ct0|dout_r[5]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[4].sn0|ff_launch[0]
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_div_clk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_div_clk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 10.445 10.445 R clock network delay
|
|
Info (332115): 10.445 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[4].ct0|dout_r[5]
|
|
Info (332115): 10.680 0.235 RR uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[4].ct0|dout_r[5]|q
|
|
Info (332115): 10.849 0.169 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[4].ct0|dout_r[5]~la_lab/laboutt[16]
|
|
Info (332115): 11.114 0.265 RR IC High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[4].sn0|ff_launch[0]|d
|
|
Info (332115): 11.114 0.000 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[4].sn0|ff_launch[0]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 6.399 6.399 latch edge time
|
|
Info (332115): 14.229 7.830 R clock network delay
|
|
Info (332115): 16.787 2.558 clock pessimism removed
|
|
Info (332115): 16.757 -0.030 clock uncertainty
|
|
Info (332115): 16.776 0.019 uTsu fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[4].sn0|ff_launch[0]
|
|
Info (332115): Data Arrival Time : 11.114
|
|
Info (332115): Data Required Time : 16.776
|
|
Info (332115): Slack : 5.662
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 5.843
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|avmmclk}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 5.843
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_address[2]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Launch Clock : PCIE_REFCLK
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|avmmclk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 5.720 5.720 R clock network delay
|
|
Info (332115): 5.720 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_address[2]
|
|
Info (332115): 5.986 0.266 FF uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_address[2]|q
|
|
Info (332115): 6.095 0.109 FF CELL Low Power fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_address[2]~la_lab/laboutb[13]
|
|
Info (332115): 7.141 1.046 FF IC Mixed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i984|datac
|
|
Info (332115): 7.312 0.171 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i984|combout
|
|
Info (332115): 7.317 0.005 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i984~la_mlab/laboutt[0]
|
|
Info (332115): 10.017 2.700 FF IC Mixed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst|avmmaddress[2]
|
|
Info (332115): 10.017 0.000 FF CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 10.000 10.000 latch edge time
|
|
Info (332115): 15.336 5.336 R clock network delay
|
|
Info (332115): 15.846 0.510 clock pessimism removed
|
|
Info (332115): 15.806 -0.040 clock uncertainty
|
|
Info (332115): 15.860 0.054 uTsu fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Arrival Time : 10.017
|
|
Info (332115): Data Required Time : 15.860
|
|
Info (332115): Slack : 5.843
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 6.128
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|avmmclk}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 6.128
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_address[5]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Launch Clock : PCIE_REFCLK
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|avmmclk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 5.720 5.720 R clock network delay
|
|
Info (332115): 5.720 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_address[5]
|
|
Info (332115): 5.987 0.267 FF uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_address[5]|q
|
|
Info (332115): 6.133 0.146 FF CELL Low Power fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_address[5]~la_lab/laboutb[7]
|
|
Info (332115): 7.062 0.929 FF IC Mixed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i763|dataf
|
|
Info (332115): 7.107 0.045 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i763|combout
|
|
Info (332115): 7.111 0.004 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i763~la_lab/laboutt[3]
|
|
Info (332115): 9.633 2.522 FF IC High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst|avmmaddress[5]
|
|
Info (332115): 9.633 0.000 FF CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 10.000 10.000 latch edge time
|
|
Info (332115): 15.354 5.354 R clock network delay
|
|
Info (332115): 15.864 0.510 clock pessimism removed
|
|
Info (332115): 15.824 -0.040 clock uncertainty
|
|
Info (332115): 15.761 -0.063 uTsu fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Arrival Time : 9.633
|
|
Info (332115): Data Required Time : 15.761
|
|
Info (332115): Slack : 6.128
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 6.423
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|avmmclk}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 6.423
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|channel_count[0]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Launch Clock : PCIE_REFCLK
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|avmmclk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 5.707 5.707 R clock network delay
|
|
Info (332115): 5.707 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|channel_count[0]
|
|
Info (332115): 5.941 0.234 RR uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|channel_count[0]|q
|
|
Info (332115): 6.059 0.118 RR CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|channel_count[0]~la_mlab/laboutt[10]
|
|
Info (332115): 7.018 0.959 RR IC Mixed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i480~0|datac
|
|
Info (332115): 7.205 0.187 RF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i480~0|combout
|
|
Info (332115): 7.210 0.005 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i480~0~la_mlab/laboutb[15]
|
|
Info (332115): 9.441 2.231 FF IC High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst|avmmwrite
|
|
Info (332115): 9.441 0.000 FF CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 10.000 10.000 latch edge time
|
|
Info (332115): 15.355 5.355 R clock network delay
|
|
Info (332115): 15.865 0.510 clock pessimism removed
|
|
Info (332115): 15.825 -0.040 clock uncertainty
|
|
Info (332115): 15.864 0.039 uTsu fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Arrival Time : 9.441
|
|
Info (332115): Data Required Time : 15.864
|
|
Info (332115): Slack : 6.423
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 6.631
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|avmmclk}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 6.631
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|g_arb[1].arbiter_inst|grant[0]~DUPLICATE
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Launch Clock : PCIE_REFCLK
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|avmmclk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 5.688 5.688 R clock network delay
|
|
Info (332115): 5.688 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|g_arb[1].arbiter_inst|grant[0]~DUPLICATE
|
|
Info (332115): 5.933 0.245 FF uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|g_arb[1].arbiter_inst|grant[0]~DUPLICATE|q
|
|
Info (332115): 6.059 0.126 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|g_arb[1].arbiter_inst|grant[0]~DUPLICATE~la_mlab/laboutb[16]
|
|
Info (332115): 6.625 0.566 FF IC Mixed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i276|dataa
|
|
Info (332115): 6.869 0.244 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i276|combout
|
|
Info (332115): 6.874 0.005 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i276~la_mlab/laboutb[9]
|
|
Info (332115): 9.337 2.463 FF IC Mixed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst|avmmaddress[2]
|
|
Info (332115): 9.337 0.000 FF CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 10.000 10.000 latch edge time
|
|
Info (332115): 15.427 5.427 R clock network delay
|
|
Info (332115): 15.954 0.527 clock pessimism removed
|
|
Info (332115): 15.914 -0.040 clock uncertainty
|
|
Info (332115): 15.968 0.054 uTsu fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Arrival Time : 9.337
|
|
Info (332115): Data Required Time : 15.968
|
|
Info (332115): Slack : 6.631
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 7.562
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|avmmclk}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 7.562
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_writedata[3]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Launch Clock : PCIE_REFCLK
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|avmmclk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 5.696 5.696 R clock network delay
|
|
Info (332115): 5.696 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_writedata[3]
|
|
Info (332115): 5.999 0.303 FF uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_writedata[3]|q
|
|
Info (332115): 6.076 0.077 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_writedata[3]~la_lab/laboutt[17]
|
|
Info (332115): 6.978 0.902 FF IC Mixed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i80~3|datae
|
|
Info (332115): 7.101 0.123 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i80~3|combout
|
|
Info (332115): 7.106 0.005 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i80~3~la_mlab/laboutb[8]
|
|
Info (332115): 8.474 1.368 FF IC High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst|avmmwritedata[3]
|
|
Info (332115): 8.474 0.000 FF CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 10.000 10.000 latch edge time
|
|
Info (332115): 15.417 5.417 R clock network delay
|
|
Info (332115): 15.944 0.527 clock pessimism removed
|
|
Info (332115): 15.904 -0.040 clock uncertainty
|
|
Info (332115): 16.036 0.132 uTsu fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Arrival Time : 8.474
|
|
Info (332115): Data Required Time : 16.036
|
|
Info (332115): Slack : 7.562
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 7.840
|
|
Info (20696): -to_clock [get_clocks {vl_qph_user_clk_clkpsc_clk0}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 7.840
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[0]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[1]
|
|
Info (332115): Launch Clock : vl_qph_user_clk_clkpsc_clk0
|
|
Info (332115): Latch Clock : vl_qph_user_clk_clkpsc_clk0
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 6.855 6.855 R clock network delay
|
|
Info (332115): 6.855 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[0]
|
|
Info (332115): 7.104 0.249 RR uTco fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[0]|q
|
|
Info (332115): 7.225 0.121 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[0]~la_mlab/laboutb[9]
|
|
Info (332115): 8.066 0.841 RR IC Mixed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[1]~2|dataa
|
|
Info (332115): 8.341 0.275 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[1]~2|combout
|
|
Info (332115): 8.341 0.000 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[1]|d
|
|
Info (332115): 8.341 0.000 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[1]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 9.090 9.090 latch edge time
|
|
Info (332115): 14.767 5.677 R clock network delay
|
|
Info (332115): 15.940 1.173 clock pessimism removed
|
|
Info (332115): 15.910 -0.030 clock uncertainty
|
|
Info (332115): 16.181 0.271 uTsu fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[1]
|
|
Info (332115): Data Arrival Time : 8.341
|
|
Info (332115): Data Required Time : 16.181
|
|
Info (332115): Slack : 7.840
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 8.509
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk0}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 8.509
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_green_bs|uClk_usrDiv2_q1
|
|
Info (332115): To Node : fpga_top|inst_green_bs|uClk_usrDiv2_q2
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk0
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk0
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 6.521 6.521 R clock network delay
|
|
Info (332115): 6.521 0.000 fpga_top|inst_green_bs|uClk_usrDiv2_q1
|
|
Info (332115): 6.800 0.279 RR uTco fpga_top|inst_green_bs|uClk_usrDiv2_q1|q
|
|
Info (332115): 6.800 0.000 RR CELL High Speed fpga_top|inst_green_bs|uClk_usrDiv2_q2~0|datae
|
|
Info (332115): 7.289 0.489 RF CELL High Speed fpga_top|inst_green_bs|uClk_usrDiv2_q2~0|combout
|
|
Info (332115): 7.289 0.000 FF CELL High Speed fpga_top|inst_green_bs|uClk_usrDiv2_q2|d
|
|
Info (332115): 7.289 0.000 FF CELL High Speed fpga_top|inst_green_bs|uClk_usrDiv2_q2
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 9.090 9.090 latch edge time
|
|
Info (332115): 14.480 5.390 R clock network delay
|
|
Info (332115): 15.611 1.131 clock pessimism removed
|
|
Info (332115): 15.581 -0.030 clock uncertainty
|
|
Info (332115): 15.798 0.217 uTsu fpga_top|inst_green_bs|uClk_usrDiv2_q2
|
|
Info (332115): Data Arrival Time : 7.289
|
|
Info (332115): Data Required Time : 15.798
|
|
Info (332115): Slack : 8.509
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 10.925
|
|
Info (20696): -to_clock [get_clocks {pr_clk_enable_dclk_reg2_user_clk}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 10.925
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_cb_host|alt_pr_cb_controller_v2|pr_request_reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_cb_host|alt_pr_cb_controller_v2|alt_pr_cb_interface|m_prblock~cs_css/pr_clk_core.reg
|
|
Info (332115): Launch Clock : u0|dcp_iopll|dcp_iopll|clk100
|
|
Info (332115): Latch Clock : pr_clk_enable_dclk_reg2_user_clk
|
|
Info (332115): Exception : dcp_bbs.sdc:3118: set_multicycle_path -setup -from [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_cb_host|alt_pr_cb_controller_v2|pr_request_reg}] -to [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_cb_host|alt_pr_cb_controller_v2|alt_pr_cb_interface|m_prblock~cs_css/pr_clk_core.reg}] 2
|
|
Info (332115): Multicycle - Setup Start : 2
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 9.694 9.694 R clock network delay
|
|
Info (332115): 9.694 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_cb_host|alt_pr_cb_controller_v2|pr_request_reg
|
|
Info (332115): 9.997 0.303 FF uTco fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_cb_host|alt_pr_cb_controller_v2|pr_request_reg|q
|
|
Info (332115): 10.123 0.126 FF CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_cb_host|alt_pr_cb_controller_v2|pr_request_reg~la_lab/laboutt[0]
|
|
Info (332115): 15.366 5.243 FF IC High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_cb_host|alt_pr_cb_controller_v2|alt_pr_cb_interface|m_prblock|prrequest
|
|
Info (332115): 15.366 0.000 FF CELL fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_cb_host|alt_pr_cb_controller_v2|alt_pr_cb_interface|m_prblock~cs_css/pr_clk_core.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 15.000 15.000 latch edge time
|
|
Info (332115): 24.398 9.398 R clock network delay
|
|
Info (332115): 25.644 1.246 clock pessimism removed
|
|
Info (332115): 25.474 -0.170 clock uncertainty
|
|
Info (332115): 26.291 0.817 uTsu fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_cb_host|alt_pr_cb_controller_v2|alt_pr_cb_interface|m_prblock~cs_css/pr_clk_core.reg
|
|
Info (332115): Data Arrival Time : 15.366
|
|
Info (332115): Data Required Time : 26.291
|
|
Info (332115): Slack : 10.925
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 18.344
|
|
Info (20696): -to_clock [get_clocks {u0|dcp_iopll|dcp_iopll|clk25}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 18.344
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|generic_quad_spi_controller2_0|generic_quad_spi_controller2_0|asmi2_inst_qspi_ctrl|asmi2_cmd_generator_0|state.ST_SEND_ADDR
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|generic_quad_spi_controller2_0|generic_quad_spi_controller2_0|asmi2_inst_qspi_ctrl|asmi2_qspi_interface_0|dataout_reg[0]~RTM_7
|
|
Info (332115): Launch Clock : u0|dcp_iopll|dcp_iopll|clk25
|
|
Info (332115): Latch Clock : u0|dcp_iopll|dcp_iopll|clk25 (INVERTED)
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 9.939 9.939 R clock network delay
|
|
Info (332115): 9.939 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|generic_quad_spi_controller2_0|generic_quad_spi_controller2_0|asmi2_inst_qspi_ctrl|asmi2_cmd_generator_0|state.ST_SEND_ADDR
|
|
Info (332115): 10.177 0.238 RR uTco fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|generic_quad_spi_controller2_0|generic_quad_spi_controller2_0|asmi2_inst_qspi_ctrl|asmi2_cmd_generator_0|state.ST_SEND_ADDR|q
|
|
Info (332115): 10.299 0.122 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|generic_quad_spi_controller2_0|generic_quad_spi_controller2_0|asmi2_inst_qspi_ctrl|asmi2_cmd_generator_0|state.ST_SEND_ADDR~la_lab/laboutb[13]
|
|
Info (332115): 10.826 0.527 RR IC High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|generic_quad_spi_controller2_0|generic_quad_spi_controller2_0|asmi2_inst_qspi_ctrl|asmi2_cmd_generator_0|Select_8~0|datac
|
|
Info (332115): 11.000 0.174 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|generic_quad_spi_controller2_0|generic_quad_spi_controller2_0|asmi2_inst_qspi_ctrl|asmi2_cmd_generator_0|Select_8~0|combout
|
|
Info (332115): 11.004 0.004 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|generic_quad_spi_controller2_0|generic_quad_spi_controller2_0|asmi2_inst_qspi_ctrl|asmi2_cmd_generator_0|Select_8~0~la_lab/laboutt[4]
|
|
Info (332115): 11.202 0.198 RR IC High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|generic_quad_spi_controller2_0|generic_quad_spi_controller2_0|asmi2_inst_qspi_ctrl|asmi2_qspi_interface_0|dataout_reg[1]~0|dataf
|
|
Info (332115): 11.247 0.045 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|generic_quad_spi_controller2_0|generic_quad_spi_controller2_0|asmi2_inst_qspi_ctrl|asmi2_qspi_interface_0|dataout_reg[1]~0|combout
|
|
Info (332115): 11.251 0.004 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|generic_quad_spi_controller2_0|generic_quad_spi_controller2_0|asmi2_inst_qspi_ctrl|asmi2_qspi_interface_0|dataout_reg[1]~0~la_lab/laboutb[18]
|
|
Info (332115): 11.558 0.307 RR IC High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|generic_quad_spi_controller2_0|generic_quad_spi_controller2_0|asmi2_inst_qspi_ctrl|asmi2_qspi_interface_0|dataout_reg[0]~RTM_7|d
|
|
Info (332115): 11.558 0.000 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|generic_quad_spi_controller2_0|generic_quad_spi_controller2_0|asmi2_inst_qspi_ctrl|asmi2_qspi_interface_0|dataout_reg[0]~RTM_7
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 20.000 20.000 latch edge time
|
|
Info (332115): 28.449 8.449 F clock network delay
|
|
Info (332115): 29.849 1.400 clock pessimism removed
|
|
Info (332115): 29.629 -0.220 clock uncertainty
|
|
Info (332115): 29.902 0.273 uTsu fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|generic_quad_spi_controller2_0|generic_quad_spi_controller2_0|asmi2_inst_qspi_ctrl|asmi2_qspi_interface_0|dataout_reg[0]~RTM_7
|
|
Info (332115): Data Arrival Time : 11.558
|
|
Info (332115): Data Required Time : 29.902
|
|
Info (332115): Slack : 18.344
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 19.258
|
|
Info (20696): -to_clock [get_clocks {u0|dcp_iopll|dcp_iopll|clk50}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 19.258
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_green_bs|pClkDiv4_q1
|
|
Info (332115): To Node : fpga_top|inst_green_bs|pClkDiv4_q2
|
|
Info (332115): Launch Clock : u0|dcp_iopll|dcp_iopll|clk50
|
|
Info (332115): Latch Clock : u0|dcp_iopll|dcp_iopll|clk50
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 9.908 9.908 R clock network delay
|
|
Info (332115): 9.908 0.000 fpga_top|inst_green_bs|pClkDiv4_q1
|
|
Info (332115): 10.180 0.272 RR uTco fpga_top|inst_green_bs|pClkDiv4_q1|q
|
|
Info (332115): 10.180 0.000 RR CELL High Speed fpga_top|inst_green_bs|pClkDiv4_q2~0|datae
|
|
Info (332115): 10.673 0.493 RF CELL High Speed fpga_top|inst_green_bs|pClkDiv4_q2~0|combout
|
|
Info (332115): 10.673 0.000 FF CELL High Speed fpga_top|inst_green_bs|pClkDiv4_q2|d
|
|
Info (332115): 10.673 0.000 FF CELL High Speed fpga_top|inst_green_bs|pClkDiv4_q2
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 20.000 20.000 latch edge time
|
|
Info (332115): 28.466 8.466 R clock network delay
|
|
Info (332115): 29.908 1.442 clock pessimism removed
|
|
Info (332115): 29.718 -0.190 clock uncertainty
|
|
Info (332115): 29.931 0.213 uTsu fpga_top|inst_green_bs|pClkDiv4_q2
|
|
Info (332115): Data Arrival Time : 10.673
|
|
Info (332115): Data Required Time : 29.931
|
|
Info (332115): Slack : 19.258
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 19.572
|
|
Info (20696): -to_clock [get_clocks {filtered_sclk_negedge}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 19.572
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MOSIctl|filtered_mosi_out
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MOSIctl|wrshiftreg[0]
|
|
Info (332115): Launch Clock : u0|dcp_iopll|dcp_iopll|clk1x
|
|
Info (332115): Latch Clock : filtered_sclk_negedge
|
|
Info (332115): Exception : dcp_bbs.sdc:3138: set_max_delay -from [get_keepers {*filtered_mosi*}] 30.000
|
|
Info (332115): Max Delay Exception : 30.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 9.703 9.703 R clock network delay
|
|
Info (332115): 9.703 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MOSIctl|filtered_mosi_out
|
|
Info (332115): 9.999 0.296 FF uTco fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MOSIctl|filtered_mosi_out|q
|
|
Info (332115): 10.076 0.077 FF CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MOSIctl|filtered_mosi_out~la_lab/laboutb[5]
|
|
Info (332115): 10.499 0.423 FF IC High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MOSIctl|wrshiftreg[0]|asdata
|
|
Info (332115): 10.499 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MOSIctl|wrshiftreg[0]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 30.000 30.000 latch edge time
|
|
Info (332115): 30.227 0.227 R clock network delay
|
|
Info (332115): 29.927 -0.300 clock uncertainty
|
|
Info (332115): 30.071 0.144 uTsu fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MOSIctl|wrshiftreg[0]
|
|
Info (332115): Data Arrival Time : 10.499
|
|
Info (332115): Data Required Time : 30.071
|
|
Info (332115): Slack : 19.572
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 40.720
|
|
Info (20696): -to_clock [get_clocks {altera_reserved_tck}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 40.720
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|nios2_gen2_0|nios2_gen2_0|cpu|the_tcm_nios2_gen2_0_altera_nios2_gen2_unit_191_dbuc52a_nios2_oci|the_tcm_nios2_gen2_0_altera_nios2_gen2_unit_191_dbuc52a_debug_slave_wrapper|the_tcm_nios2_gen2_0_altera_nios2_gen2_unit_191_dbuc52a_debug_slave_tck|sr[0]
|
|
Info (332115): To Node : auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|jtagpins|int_tdo_reg~LRTM_5
|
|
Info (332115): Launch Clock : altera_reserved_tck
|
|
Info (332115): Latch Clock : altera_reserved_tck (INVERTED)
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 6.022 6.022 R clock network delay
|
|
Info (332115): 6.022 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|nios2_gen2_0|nios2_gen2_0|cpu|the_tcm_nios2_gen2_0_altera_nios2_gen2_unit_191_dbuc52a_nios2_oci|the_tcm_nios2_gen2_0_altera_nios2_gen2_unit_191_dbuc52a_debug_slave_wrapper|the_tcm_nios2_gen2_0_altera_nios2_gen2_unit_191_dbuc52a_debug_slave_tck|sr[0]
|
|
Info (332115): 6.274 0.252 FF uTco fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|nios2_gen2_0|nios2_gen2_0|cpu|the_tcm_nios2_gen2_0_altera_nios2_gen2_unit_191_dbuc52a_nios2_oci|the_tcm_nios2_gen2_0_altera_nios2_gen2_unit_191_dbuc52a_debug_slave_wrapper|the_tcm_nios2_gen2_0_altera_nios2_gen2_unit_191_dbuc52a_debug_slave_tck|sr[0]|q
|
|
Info (332115): 6.351 0.077 FF CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|nios2_gen2_0|nios2_gen2_0|cpu|the_tcm_nios2_gen2_0_altera_nios2_gen2_unit_191_dbuc52a_nios2_oci|the_tcm_nios2_gen2_0_altera_nios2_gen2_unit_191_dbuc52a_debug_slave_wrapper|the_tcm_nios2_gen2_0_altera_nios2_gen2_unit_191_dbuc52a_debug_slave_tck|sr[0]~la_lab/laboutb[9]
|
|
Info (332115): 6.351 0.000 FF IC auto_fab_0|auto_export_alt_sld_fab_0_alt_sld_fab_0_splitter_send_2[0]|input
|
|
Info (332115): 6.351 0.000 FF CELL auto_fab_0|auto_export_alt_sld_fab_0_alt_sld_fab_0_splitter_send_2[0]
|
|
Info (332115): 13.134 6.783 FF IC High Speed auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|sldfabric|\jtag_hub_gen:real_sld_jtag_hub|i705~4|datab
|
|
Info (332115): 13.371 0.237 FF CELL High Speed auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|sldfabric|\jtag_hub_gen:real_sld_jtag_hub|i705~4|combout
|
|
Info (332115): 13.371 0.000 FF CELL High Speed auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|jtagpins|int_tdo_reg~LRTM_5|d
|
|
Info (332115): 13.371 0.000 FF CELL High Speed auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|jtagpins|int_tdo_reg~LRTM_5
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 50.000 50.000 latch edge time
|
|
Info (332115): 53.341 3.341 F clock network delay
|
|
Info (332115): 53.796 0.455 clock pessimism removed
|
|
Info (332115): 53.766 -0.030 clock uncertainty
|
|
Info (332115): 54.091 0.325 uTsu auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|jtagpins|int_tdo_reg~LRTM_5
|
|
Info (332115): Data Arrival Time : 13.371
|
|
Info (332115): Data Required Time : 54.091
|
|
Info (332115): Slack : 40.720
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.031
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk1}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.031
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[3].core|pipeline|issue|instr_demux|gpu_buffer|shift_reg[1][170]
|
|
Info (332115): To Node : fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[3].core|pipeline|execute|gpu_unit|pipe_reg|value_d[5]
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk1
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk1
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 5.426 5.426 R clock network delay
|
|
Info (332115): 5.426 0.000 fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[3].core|pipeline|issue|instr_demux|gpu_buffer|shift_reg[1][170]
|
|
Info (332115): 5.623 0.197 FF uTco fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[3].core|pipeline|issue|instr_demux|gpu_buffer|shift_reg[1][170]|q
|
|
Info (332115): 5.964 0.341 FF CELL High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[3].core|pipeline|execute|gpu_unit|pipe_reg|value_d[5]|d
|
|
Info (332115): 5.964 0.000 FF CELL High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[3].core|pipeline|execute|gpu_unit|pipe_reg|value_d[5]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 6.564 6.564 R clock network delay
|
|
Info (332115): 5.425 -1.139 clock pessimism removed
|
|
Info (332115): 5.425 0.000 clock uncertainty
|
|
Info (332115): 5.933 0.508 uTh fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[3].core|pipeline|execute|gpu_unit|pipe_reg|value_d[5]
|
|
Info (332115): Data Arrival Time : 5.964
|
|
Info (332115): Data Required Time : 5.933
|
|
Info (332115): Slack : 0.031
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.038
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|wys~CORE_CLK_OUT}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.038
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_sriov_2.sriov2.sriov_bridge|altpcie_pcie_sriov2_top_inst|altpcie_sriov2_cfg_dataflow_inst|gen_vf_regset_pf0.altpcie_sriov2_cfg_vf_regset_pf0_inst|vf_pci_status_reg_mod|altpcie_sriov2_cfg_vf_bar_check_error_status_fifo|read_ptr[0]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_sriov_2.sriov2.sriov_bridge|altpcie_pcie_sriov2_top_inst|altpcie_sriov2_cfg_dataflow_inst|gen_vf_regset_pf0.altpcie_sriov2_cfg_vf_regset_pf0_inst|vf_pci_status_reg_mod|altpcie_sriov2_cfg_vf_bar_check_error_status_fifo|reg_array_rtl_0|auto_generated|rdaddr_reg[0]
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|wys~CORE_CLK_OUT
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|wys~CORE_CLK_OUT
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 8.083 8.083 R clock network delay
|
|
Info (332115): 8.083 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_sriov_2.sriov2.sriov_bridge|altpcie_pcie_sriov2_top_inst|altpcie_sriov2_cfg_dataflow_inst|gen_vf_regset_pf0.altpcie_sriov2_cfg_vf_regset_pf0_inst|vf_pci_status_reg_mod|altpcie_sriov2_cfg_vf_bar_check_error_status_fifo|read_ptr[0]
|
|
Info (332115): 8.293 0.210 FF uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_sriov_2.sriov2.sriov_bridge|altpcie_pcie_sriov2_top_inst|altpcie_sriov2_cfg_dataflow_inst|gen_vf_regset_pf0.altpcie_sriov2_cfg_vf_regset_pf0_inst|vf_pci_status_reg_mod|altpcie_sriov2_cfg_vf_bar_check_error_status_fifo|read_ptr[0]|q
|
|
Info (332115): 8.293 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_sriov_2.sriov2.sriov_bridge|altpcie_pcie_sriov2_top_inst|altpcie_sriov2_cfg_dataflow_inst|gen_vf_regset_pf0.altpcie_sriov2_cfg_vf_regset_pf0_inst|vf_pci_status_reg_mod|altpcie_sriov2_cfg_vf_bar_check_error_status_fifo|i26~0|datad
|
|
Info (332115): 8.630 0.337 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_sriov_2.sriov2.sriov_bridge|altpcie_pcie_sriov2_top_inst|altpcie_sriov2_cfg_dataflow_inst|gen_vf_regset_pf0.altpcie_sriov2_cfg_vf_regset_pf0_inst|vf_pci_status_reg_mod|altpcie_sriov2_cfg_vf_bar_check_error_status_fifo|i26~0|combout
|
|
Info (332115): 8.630 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_sriov_2.sriov2.sriov_bridge|altpcie_pcie_sriov2_top_inst|altpcie_sriov2_cfg_dataflow_inst|gen_vf_regset_pf0.altpcie_sriov2_cfg_vf_regset_pf0_inst|vf_pci_status_reg_mod|altpcie_sriov2_cfg_vf_bar_check_error_status_fifo|reg_array_rtl_0|auto_generated|rdaddr_reg[0]|d
|
|
Info (332115): 8.630 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_sriov_2.sriov2.sriov_bridge|altpcie_pcie_sriov2_top_inst|altpcie_sriov2_cfg_dataflow_inst|gen_vf_regset_pf0.altpcie_sriov2_cfg_vf_regset_pf0_inst|vf_pci_status_reg_mod|altpcie_sriov2_cfg_vf_bar_check_error_status_fifo|reg_array_rtl_0|auto_generated|rdaddr_reg[0]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 9.575 9.575 R clock network delay
|
|
Info (332115): 8.083 -1.492 clock pessimism removed
|
|
Info (332115): 8.592 0.509 uTh fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_sriov_2.sriov2.sriov_bridge|altpcie_pcie_sriov2_top_inst|altpcie_sriov2_cfg_dataflow_inst|gen_vf_regset_pf0.altpcie_sriov2_cfg_vf_regset_pf0_inst|vf_pci_status_reg_mod|altpcie_sriov2_cfg_vf_bar_check_error_status_fifo|reg_array_rtl_0|auto_generated|rdaddr_reg[0]
|
|
Info (332115): Data Arrival Time : 8.630
|
|
Info (332115): Data Required Time : 8.592
|
|
Info (332115): Slack : 0.038
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.041
|
|
Info (20696): -to_clock [get_clocks {u0|dcp_iopll|dcp_iopll|clk1x}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.041
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|tcm_control_out_s1_translator|av_readdata_pre[2]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|nios2_gen2_0|nios2_gen2_0|cpu|av_ld_byte0_data[2]~RTM_71
|
|
Info (332115): Launch Clock : u0|dcp_iopll|dcp_iopll|clk1x
|
|
Info (332115): Latch Clock : u0|dcp_iopll|dcp_iopll|clk1x
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 8.288 8.288 R clock network delay
|
|
Info (332115): 8.288 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|tcm_control_out_s1_translator|av_readdata_pre[2]
|
|
Info (332115): 8.480 0.192 FF uTco fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|tcm_control_out_s1_translator|av_readdata_pre[2]|q
|
|
Info (332115): 8.577 0.097 FF CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|tcm_control_out_s1_translator|av_readdata_pre[2]~la_lab/laboutb[11]
|
|
Info (332115): 8.911 0.334 FF IC Mixed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|rsp_mux|src_payload[2]~15|dataf
|
|
Info (332115): 8.949 0.038 FF CELL Low Power fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|rsp_mux|src_payload[2]~15|combout
|
|
Info (332115): 8.949 0.000 FF CELL Low Power fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|nios2_gen2_0|nios2_gen2_0|cpu|av_ld_byte0_data[2]~RTM_71|d
|
|
Info (332115): 8.949 0.000 FF CELL Low Power fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|nios2_gen2_0|nios2_gen2_0|cpu|av_ld_byte0_data[2]~RTM_71
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 9.707 9.707 R clock network delay
|
|
Info (332115): 8.370 -1.337 clock pessimism removed
|
|
Info (332115): 8.370 0.000 clock uncertainty
|
|
Info (332115): 8.908 0.538 uTh fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|nios2_gen2_0|nios2_gen2_0|cpu|av_ld_byte0_data[2]~RTM_71
|
|
Info (332115): Data Arrival Time : 8.949
|
|
Info (332115): Data Required Time : 8.908
|
|
Info (332115): Slack : 0.041
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.044
|
|
Info (20696): -to_clock [get_clocks {SYS_RefClk}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.044
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|host_link_jtag|p2b|sent_esc
|
|
Info (332115): To Node : auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|host_link_jtag|p2b|sent_esc
|
|
Info (332115): Launch Clock : SYS_RefClk
|
|
Info (332115): Latch Clock : SYS_RefClk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 4.342 4.342 R clock network delay
|
|
Info (332115): 4.342 0.000 auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|host_link_jtag|p2b|sent_esc
|
|
Info (332115): 4.552 0.210 FF uTco auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|host_link_jtag|p2b|sent_esc|q
|
|
Info (332115): 4.552 0.000 FF CELL High Speed auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|host_link_jtag|p2b|sent_esc~0|datad
|
|
Info (332115): 4.889 0.337 FF CELL High Speed auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|host_link_jtag|p2b|sent_esc~0|combout
|
|
Info (332115): 4.889 0.000 FF CELL High Speed auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|host_link_jtag|p2b|sent_esc|d
|
|
Info (332115): 4.889 0.000 FF CELL High Speed auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|host_link_jtag|p2b|sent_esc
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 4.750 4.750 R clock network delay
|
|
Info (332115): 4.342 -0.408 clock pessimism removed
|
|
Info (332115): 4.342 0.000 clock uncertainty
|
|
Info (332115): 4.845 0.503 uTh auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|host_link_jtag|p2b|sent_esc
|
|
Info (332115): Data Arrival Time : 4.889
|
|
Info (332115): Data Required Time : 4.845
|
|
Info (332115): Slack : 0.044
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.045
|
|
Info (20696): -to_clock [get_clocks {u0|dcp_iopll|dcp_iopll|clk25}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.045
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|generic_quad_spi_controller2_0_avl_mem_agent_rdata_fifo|mem[1][2]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|generic_quad_spi_controller2_0_avl_mem_agent_rdata_fifo|mem[1][2]
|
|
Info (332115): Launch Clock : u0|dcp_iopll|dcp_iopll|clk25
|
|
Info (332115): Latch Clock : u0|dcp_iopll|dcp_iopll|clk25
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 8.469 8.469 R clock network delay
|
|
Info (332115): 8.469 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|generic_quad_spi_controller2_0_avl_mem_agent_rdata_fifo|mem[1][2]
|
|
Info (332115): 8.675 0.206 FF uTco fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|generic_quad_spi_controller2_0_avl_mem_agent_rdata_fifo|mem[1][2]|q
|
|
Info (332115): 8.675 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|generic_quad_spi_controller2_0_avl_mem_agent_rdata_fifo|i122~2|datad
|
|
Info (332115): 9.017 0.342 FF CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|generic_quad_spi_controller2_0_avl_mem_agent_rdata_fifo|i122~2|combout
|
|
Info (332115): 9.017 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|generic_quad_spi_controller2_0_avl_mem_agent_rdata_fifo|mem[1][2]|d
|
|
Info (332115): 9.017 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|generic_quad_spi_controller2_0_avl_mem_agent_rdata_fifo|mem[1][2]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 9.927 9.927 R clock network delay
|
|
Info (332115): 8.470 -1.457 clock pessimism removed
|
|
Info (332115): 8.470 0.000 clock uncertainty
|
|
Info (332115): 8.972 0.502 uTh fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|generic_quad_spi_controller2_0_avl_mem_agent_rdata_fifo|mem[1][2]
|
|
Info (332115): Data Arrival Time : 9.017
|
|
Info (332115): Data Required Time : 8.972
|
|
Info (332115): Slack : 0.045
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.048
|
|
Info (20696): -to_clock [get_clocks {altera_reserved_tck}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.048
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|jtag_uart_0|jtag_uart_0|tcm_jtag_uart_0_altera_avalon_jtag_uart_191_vk7uuay_alt_jtag_atlantic|count[4]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|jtag_uart_0|jtag_uart_0|tcm_jtag_uart_0_altera_avalon_jtag_uart_191_vk7uuay_alt_jtag_atlantic|count[5]
|
|
Info (332115): Launch Clock : altera_reserved_tck
|
|
Info (332115): Latch Clock : altera_reserved_tck
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 3.117 3.117 R clock network delay
|
|
Info (332115): 3.117 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|jtag_uart_0|jtag_uart_0|tcm_jtag_uart_0_altera_avalon_jtag_uart_191_vk7uuay_alt_jtag_atlantic|count[4]
|
|
Info (332115): 3.332 0.215 FF uTco fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|jtag_uart_0|jtag_uart_0|tcm_jtag_uart_0_altera_avalon_jtag_uart_191_vk7uuay_alt_jtag_atlantic|count[4]|q
|
|
Info (332115): 3.676 0.344 FF CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|jtag_uart_0|jtag_uart_0|tcm_jtag_uart_0_altera_avalon_jtag_uart_191_vk7uuay_alt_jtag_atlantic|count[5]|d
|
|
Info (332115): 3.676 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|jtag_uart_0|jtag_uart_0|tcm_jtag_uart_0_altera_avalon_jtag_uart_191_vk7uuay_alt_jtag_atlantic|count[5]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 3.812 3.812 R clock network delay
|
|
Info (332115): 3.122 -0.690 clock pessimism removed
|
|
Info (332115): 3.122 0.000 clock uncertainty
|
|
Info (332115): 3.628 0.506 uTh fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|jtag_uart_0|jtag_uart_0|tcm_jtag_uart_0_altera_avalon_jtag_uart_191_vk7uuay_alt_jtag_atlantic|count[5]
|
|
Info (332115): Data Arrival Time : 3.676
|
|
Info (332115): Data Required Time : 3.628
|
|
Info (332115): Slack : 0.048
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.048
|
|
Info (20696): -to_clock [get_clocks {mem|ddr4a|ddr4a_core_usr_clk}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.048
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : mem|ddr4b_tcm_readissued
|
|
Info (332115): To Node : mem|ddr4b_tcm_readissued
|
|
Info (332115): Launch Clock : mem|ddr4a|ddr4a_core_usr_clk
|
|
Info (332115): Latch Clock : mem|ddr4a|ddr4a_core_usr_clk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.117 0.117 launch edge time
|
|
Info (332115): 2.838 2.721 R clock network delay
|
|
Info (332115): 2.838 0.000 mem|ddr4b_tcm_readissued
|
|
Info (332115): 3.030 0.192 FF uTco mem|ddr4b_tcm_readissued|q
|
|
Info (332115): 3.030 0.000 FF CELL High Speed mem|i145~0|datad
|
|
Info (332115): 3.362 0.332 FF CELL High Speed mem|i145~0|combout
|
|
Info (332115): 3.362 0.000 FF CELL High Speed mem|ddr4b_tcm_readissued|d
|
|
Info (332115): 3.362 0.000 FF CELL High Speed mem|ddr4b_tcm_readissued
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.117 0.117 latch edge time
|
|
Info (332115): 3.746 3.629 R clock network delay
|
|
Info (332115): 2.838 -0.908 clock pessimism removed
|
|
Info (332115): 2.838 0.000 clock uncertainty
|
|
Info (332115): 3.314 0.476 uTh mem|ddr4b_tcm_readissued
|
|
Info (332115): Data Arrival Time : 3.362
|
|
Info (332115): Data Required Time : 3.314
|
|
Info (332115): Slack : 0.048
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.049
|
|
Info (20696): -to_clock [get_clocks {u0|dcp_iopll|dcp_iopll|clk100}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.049
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|gen_ccip_ports[0].inst_remote_green_stp|inst_stp_ep|inst_SLD_HUB_cont_sys|sld_hub_controller_system_without_sldep_0|sld_hub_controller_system_without_sldep_0|hub_controller|core|resp_data[7]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|gen_ccip_ports[0].inst_remote_green_stp|inst_stp_ep|inst_SLD_HUB_cont_sys|sld_hub_controller_system_without_sldep_0|sld_hub_controller_system_without_sldep_0|hub_controller|core|resp_data[7]
|
|
Info (332115): Launch Clock : u0|dcp_iopll|dcp_iopll|clk100
|
|
Info (332115): Latch Clock : u0|dcp_iopll|dcp_iopll|clk100
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 8.366 8.366 R clock network delay
|
|
Info (332115): 8.366 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|gen_ccip_ports[0].inst_remote_green_stp|inst_stp_ep|inst_SLD_HUB_cont_sys|sld_hub_controller_system_without_sldep_0|sld_hub_controller_system_without_sldep_0|hub_controller|core|resp_data[7]
|
|
Info (332115): 8.558 0.192 FF uTco fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|gen_ccip_ports[0].inst_remote_green_stp|inst_stp_ep|inst_SLD_HUB_cont_sys|sld_hub_controller_system_without_sldep_0|sld_hub_controller_system_without_sldep_0|hub_controller|core|resp_data[7]|q
|
|
Info (332115): 8.558 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|gen_ccip_ports[0].inst_remote_green_stp|inst_stp_ep|inst_SLD_HUB_cont_sys|sld_hub_controller_system_without_sldep_0|sld_hub_controller_system_without_sldep_0|hub_controller|core|resp_data[7]~3|datad
|
|
Info (332115): 8.891 0.333 FF CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|gen_ccip_ports[0].inst_remote_green_stp|inst_stp_ep|inst_SLD_HUB_cont_sys|sld_hub_controller_system_without_sldep_0|sld_hub_controller_system_without_sldep_0|hub_controller|core|resp_data[7]~3|combout
|
|
Info (332115): 8.891 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|gen_ccip_ports[0].inst_remote_green_stp|inst_stp_ep|inst_SLD_HUB_cont_sys|sld_hub_controller_system_without_sldep_0|sld_hub_controller_system_without_sldep_0|hub_controller|core|resp_data[7]|d
|
|
Info (332115): 8.891 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|gen_ccip_ports[0].inst_remote_green_stp|inst_stp_ep|inst_SLD_HUB_cont_sys|sld_hub_controller_system_without_sldep_0|sld_hub_controller_system_without_sldep_0|hub_controller|core|resp_data[7]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 9.773 9.773 R clock network delay
|
|
Info (332115): 8.366 -1.407 clock pessimism removed
|
|
Info (332115): 8.366 0.000 clock uncertainty
|
|
Info (332115): 8.842 0.476 uTh fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|gen_ccip_ports[0].inst_remote_green_stp|inst_stp_ep|inst_SLD_HUB_cont_sys|sld_hub_controller_system_without_sldep_0|sld_hub_controller_system_without_sldep_0|hub_controller|core|resp_data[7]
|
|
Info (332115): Data Arrival Time : 8.891
|
|
Info (332115): Data Required Time : 8.842
|
|
Info (332115): Slack : 0.049
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.052
|
|
Info (20696): -to_clock [get_clocks {PCIE_REFCLK}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.052
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|timer_threshold[6]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|timer_threshold[6]
|
|
Info (332115): Launch Clock : PCIE_REFCLK
|
|
Info (332115): Latch Clock : PCIE_REFCLK
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 5.121 5.121 R clock network delay
|
|
Info (332115): 5.121 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|timer_threshold[6]
|
|
Info (332115): 5.317 0.196 FF uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|timer_threshold[6]|q
|
|
Info (332115): 5.317 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|Select_41~0|datad
|
|
Info (332115): 5.654 0.337 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|Select_41~0|combout
|
|
Info (332115): 5.654 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|timer_threshold[6]|d
|
|
Info (332115): 5.654 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|timer_threshold[6]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 5.707 5.707 R clock network delay
|
|
Info (332115): 5.121 -0.586 clock pessimism removed
|
|
Info (332115): 5.121 0.000 clock uncertainty
|
|
Info (332115): 5.602 0.481 uTh fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|timer_threshold[6]
|
|
Info (332115): Data Arrival Time : 5.654
|
|
Info (332115): Data Required Time : 5.602
|
|
Info (332115): Slack : 0.052
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.057
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_clk}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.057
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[7].ct0|dout_r[2]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[7].ct0|dout_r[5]
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_clk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_clk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 5.146 5.146 R clock network delay
|
|
Info (332115): 5.146 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[7].ct0|dout_r[2]
|
|
Info (332115): 5.340 0.194 FF uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[7].ct0|dout_r[2]|q
|
|
Info (332115): 5.437 0.097 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[7].ct0|dout_r[2]~la_lab/laboutb[3]
|
|
Info (332115): 5.649 0.212 FF IC High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[7].ct0|t5|dout|dataf
|
|
Info (332115): 5.683 0.034 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[7].ct0|t5|dout|combout
|
|
Info (332115): 5.683 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[7].ct0|dout_r[5]|d
|
|
Info (332115): 5.683 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[7].ct0|dout_r[5]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 7.215 7.215 R clock network delay
|
|
Info (332115): 5.146 -2.069 clock pessimism removed
|
|
Info (332115): 5.146 0.000 clock uncertainty
|
|
Info (332115): 5.626 0.480 uTh fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[7].ct0|dout_r[5]
|
|
Info (332115): Data Arrival Time : 5.683
|
|
Info (332115): Data Required Time : 5.626
|
|
Info (332115): Slack : 0.057
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.057
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|rx_pma_clk}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.057
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_prbs_err_sync|resync_chains[0].sync_r[0]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_prbs_err_sync|resync_chains[0].sync_r[1]
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|rx_pma_clk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|rx_pma_clk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 5.073 5.073 R clock network delay
|
|
Info (332115): 5.073 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_prbs_err_sync|resync_chains[0].sync_r[0]
|
|
Info (332115): 5.264 0.191 FF uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_prbs_err_sync|resync_chains[0].sync_r[0]|q
|
|
Info (332115): 5.608 0.344 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_prbs_err_sync|resync_chains[0].sync_r[1]|d
|
|
Info (332115): 5.608 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_prbs_err_sync|resync_chains[0].sync_r[1]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 7.156 7.156 R clock network delay
|
|
Info (332115): 5.073 -2.083 clock pessimism removed
|
|
Info (332115): 5.073 0.000 clock uncertainty
|
|
Info (332115): 5.551 0.478 uTh fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_prbs_err_sync|resync_chains[0].sync_r[1]
|
|
Info (332115): Data Arrival Time : 5.608
|
|
Info (332115): Data Required Time : 5.551
|
|
Info (332115): Slack : 0.057
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.058
|
|
Info (20696): -to_clock [get_clocks {filtered_sclk_negedge}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.058
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MOSIctl|wrshiftreg[5]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MOSIctl|wrshiftreg[6]
|
|
Info (332115): Launch Clock : filtered_sclk_negedge
|
|
Info (332115): Latch Clock : filtered_sclk_negedge
|
|
Info (332115): Exception : dcp_bbs.sdc:3041: set_multicycle_path -hold -to [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MOSIctl|wrshiftreg[6]}] 1
|
|
Info (332115): Multicycle - Setup Start : 2
|
|
Info (332115): Multicycle - Hold Start : 1
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 0.227 0.227 R clock network delay
|
|
Info (332115): 0.227 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MOSIctl|wrshiftreg[5]
|
|
Info (332115): 0.440 0.213 FF uTco fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MOSIctl|wrshiftreg[5]|q
|
|
Info (332115): 0.779 0.339 FF CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MOSIctl|wrshiftreg[6]|d
|
|
Info (332115): 0.779 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MOSIctl|wrshiftreg[6]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 0.275 0.275 R clock network delay
|
|
Info (332115): 0.233 -0.042 clock pessimism removed
|
|
Info (332115): 0.721 0.488 uTh fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MOSIctl|wrshiftreg[6]
|
|
Info (332115): Data Arrival Time : 0.779
|
|
Info (332115): Data Required Time : 0.721
|
|
Info (332115): Slack : 0.058
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.059
|
|
Info (20696): -to_clock [get_clocks {DDR4_RefClk}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.059
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|use_counter_lock.counter_lock_gen_master.pll_ref_clk_reset_n_sync_rr
|
|
Info (332115): To Node : mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|use_counter_lock.counter_lock_gen_master.pll_ref_clk_reset_n_sync_rrr
|
|
Info (332115): Launch Clock : DDR4_RefClk
|
|
Info (332115): Latch Clock : DDR4_RefClk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 3.994 3.994 R clock network delay
|
|
Info (332115): 3.994 0.000 mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|use_counter_lock.counter_lock_gen_master.pll_ref_clk_reset_n_sync_rr
|
|
Info (332115): 4.185 0.191 FF uTco mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|use_counter_lock.counter_lock_gen_master.pll_ref_clk_reset_n_sync_rr|q
|
|
Info (332115): 4.529 0.344 FF CELL High Speed mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|use_counter_lock.counter_lock_gen_master.pll_ref_clk_reset_n_sync_rrr|d
|
|
Info (332115): 4.529 0.000 FF CELL High Speed mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|use_counter_lock.counter_lock_gen_master.pll_ref_clk_reset_n_sync_rrr
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 4.328 4.328 R clock network delay
|
|
Info (332115): 3.993 -0.335 clock pessimism removed
|
|
Info (332115): 3.993 0.000 clock uncertainty
|
|
Info (332115): 4.470 0.477 uTh mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|use_counter_lock.counter_lock_gen_master.pll_ref_clk_reset_n_sync_rrr
|
|
Info (332115): Data Arrival Time : 4.529
|
|
Info (332115): Data Required Time : 4.470
|
|
Info (332115): Slack : 0.059
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.059
|
|
Info (20696): -to_clock [get_clocks {mem|ddr4a|ddr4a_core_cal_slave_clk}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.059
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : mem|ddr4b|ddr4b|arch|arch_inst|non_hps.core_clks_rsts_inst|per_if_cal_slave_reset_sync[8]
|
|
Info (332115): To Node : mem|ddr4b|ddr4b|arch|arch_inst|non_hps.core_clks_rsts_inst|per_if_cal_slave_reset_sync[9]
|
|
Info (332115): Launch Clock : mem|ddr4a|ddr4a_core_cal_slave_clk
|
|
Info (332115): Latch Clock : mem|ddr4a|ddr4a_core_cal_slave_clk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 6.051 6.051 R clock network delay
|
|
Info (332115): 6.051 0.000 mem|ddr4b|ddr4b|arch|arch_inst|non_hps.core_clks_rsts_inst|per_if_cal_slave_reset_sync[8]
|
|
Info (332115): 6.242 0.191 FF uTco mem|ddr4b|ddr4b|arch|arch_inst|non_hps.core_clks_rsts_inst|per_if_cal_slave_reset_sync[8]|q
|
|
Info (332115): 6.587 0.345 FF CELL High Speed mem|ddr4b|ddr4b|arch|arch_inst|non_hps.core_clks_rsts_inst|per_if_cal_slave_reset_sync[9]|d
|
|
Info (332115): 6.587 0.000 FF CELL High Speed mem|ddr4b|ddr4b|arch|arch_inst|non_hps.core_clks_rsts_inst|per_if_cal_slave_reset_sync[9]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 7.147 7.147 R clock network delay
|
|
Info (332115): 6.051 -1.096 clock pessimism removed
|
|
Info (332115): 6.051 0.000 clock uncertainty
|
|
Info (332115): 6.528 0.477 uTh mem|ddr4b|ddr4b|arch|arch_inst|non_hps.core_clks_rsts_inst|per_if_cal_slave_reset_sync[9]
|
|
Info (332115): Data Arrival Time : 6.587
|
|
Info (332115): Data Required Time : 6.528
|
|
Info (332115): Slack : 0.059
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.064
|
|
Info (20696): -to_clock [get_clocks {ETH_RefClk}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.064
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[6].ct0|dout_r[2]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[6].ct0|dout_r[5]
|
|
Info (332115): Launch Clock : ETH_RefClk
|
|
Info (332115): Latch Clock : ETH_RefClk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 4.967 4.967 R clock network delay
|
|
Info (332115): 4.967 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[6].ct0|dout_r[2]
|
|
Info (332115): 5.184 0.217 FF uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[6].ct0|dout_r[2]|q
|
|
Info (332115): 5.295 0.111 FF CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[6].ct0|dout_r[2]~la_lab/laboutb[3]
|
|
Info (332115): 5.510 0.215 FF IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[6].ct0|t5|dout|dataf
|
|
Info (332115): 5.548 0.038 FF CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[6].ct0|t5|dout|combout
|
|
Info (332115): 5.548 0.000 FF CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[6].ct0|dout_r[5]|d
|
|
Info (332115): 5.548 0.000 FF CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[6].ct0|dout_r[5]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 5.556 5.556 R clock network delay
|
|
Info (332115): 4.967 -0.589 clock pessimism removed
|
|
Info (332115): 4.967 0.000 clock uncertainty
|
|
Info (332115): 5.484 0.517 uTh fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[6].ct0|dout_r[5]
|
|
Info (332115): Data Arrival Time : 5.548
|
|
Info (332115): Data Required Time : 5.484
|
|
Info (332115): Slack : 0.064
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.064
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_div_clk}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.064
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[4].ct0|dout_r[3]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[4].ct0|dout_r[3]
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_div_clk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_div_clk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 7.830 7.830 R clock network delay
|
|
Info (332115): 7.830 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[4].ct0|dout_r[3]
|
|
Info (332115): 8.023 0.193 FF uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[4].ct0|dout_r[3]|q
|
|
Info (332115): 8.023 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[4].ct0|t3|dout|datae
|
|
Info (332115): 8.375 0.352 FR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[4].ct0|t3|dout|combout
|
|
Info (332115): 8.375 0.000 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[4].ct0|dout_r[3]|d
|
|
Info (332115): 8.375 0.000 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[4].ct0|dout_r[3]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 10.445 10.445 R clock network delay
|
|
Info (332115): 7.830 -2.615 clock pessimism removed
|
|
Info (332115): 7.830 0.000 clock uncertainty
|
|
Info (332115): 8.311 0.481 uTh fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[4].ct0|dout_r[3]
|
|
Info (332115): Data Arrival Time : 8.375
|
|
Info (332115): Data Required Time : 8.311
|
|
Info (332115): Slack : 0.064
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.064
|
|
Info (20696): -to_clock [get_clocks {hssi_pll_t_outclk1}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.064
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[1].ct0|dout_r[4]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[1].ct0|dout_r[4]
|
|
Info (332115): Launch Clock : hssi_pll_t_outclk1
|
|
Info (332115): Latch Clock : hssi_pll_t_outclk1
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 4.196 4.196 R clock network delay
|
|
Info (332115): 4.196 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[1].ct0|dout_r[4]
|
|
Info (332115): 4.394 0.198 FF uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[1].ct0|dout_r[4]|q
|
|
Info (332115): 4.394 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[1].ct0|t4|dout|datae
|
|
Info (332115): 4.749 0.355 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[1].ct0|t4|dout|combout
|
|
Info (332115): 4.749 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[1].ct0|dout_r[4]|d
|
|
Info (332115): 4.749 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[1].ct0|dout_r[4]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 4.658 4.658 R clock network delay
|
|
Info (332115): 4.196 -0.462 clock pessimism removed
|
|
Info (332115): 4.196 0.000 clock uncertainty
|
|
Info (332115): 4.685 0.489 uTh fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[1].ct0|dout_r[4]
|
|
Info (332115): Data Arrival Time : 4.749
|
|
Info (332115): Data Required Time : 4.685
|
|
Info (332115): Slack : 0.064
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.067
|
|
Info (20696): -to_clock [get_clocks {hssi_pll_r_0_outclk0}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.067
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[2].ct0|dout_r[1]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[2].ct0|dout_r[1]
|
|
Info (332115): Launch Clock : hssi_pll_r_0_outclk0
|
|
Info (332115): Latch Clock : hssi_pll_r_0_outclk0
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 4.537 4.537 R clock network delay
|
|
Info (332115): 4.537 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[2].ct0|dout_r[1]
|
|
Info (332115): 4.761 0.224 FF uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[2].ct0|dout_r[1]|q
|
|
Info (332115): 4.761 0.000 FF CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[2].ct0|t1|dout|datad
|
|
Info (332115): 5.141 0.380 FF CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[2].ct0|t1|dout|combout
|
|
Info (332115): 5.141 0.000 FF CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[2].ct0|dout_r[1]|d
|
|
Info (332115): 5.141 0.000 FF CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[2].ct0|dout_r[1]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 5.057 5.057 R clock network delay
|
|
Info (332115): 4.537 -0.520 clock pessimism removed
|
|
Info (332115): 4.537 0.000 clock uncertainty
|
|
Info (332115): 5.074 0.537 uTh fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[2].ct0|dout_r[1]
|
|
Info (332115): Data Arrival Time : 5.141
|
|
Info (332115): Data Required Time : 5.074
|
|
Info (332115): Slack : 0.067
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.072
|
|
Info (20696): -to_clock [get_clocks {u0|dcp_iopll|dcp_iopll|clk50}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.072
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_green_bs|pClkDiv4_q2
|
|
Info (332115): To Node : fpga_top|inst_green_bs|pClkDiv4_q1
|
|
Info (332115): Launch Clock : u0|dcp_iopll|dcp_iopll|clk50
|
|
Info (332115): Latch Clock : u0|dcp_iopll|dcp_iopll|clk50
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 8.466 8.466 R clock network delay
|
|
Info (332115): 8.466 0.000 fpga_top|inst_green_bs|pClkDiv4_q2
|
|
Info (332115): 8.657 0.191 FF uTco fpga_top|inst_green_bs|pClkDiv4_q2|q
|
|
Info (332115): 8.716 0.059 FF CELL High Speed fpga_top|inst_green_bs|pClkDiv4_q2~la_mlab/laboutb[17]
|
|
Info (332115): 8.924 0.208 FF IC High Speed fpga_top|inst_green_bs|pClkDiv4_q1|asdata
|
|
Info (332115): 8.924 0.000 FF CELL High Speed fpga_top|inst_green_bs|pClkDiv4_q1
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 9.908 9.908 R clock network delay
|
|
Info (332115): 8.466 -1.442 clock pessimism removed
|
|
Info (332115): 8.466 0.000 clock uncertainty
|
|
Info (332115): 8.852 0.386 uTh fpga_top|inst_green_bs|pClkDiv4_q1
|
|
Info (332115): Data Arrival Time : 8.924
|
|
Info (332115): Data Required Time : 8.852
|
|
Info (332115): Slack : 0.072
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.076
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|tx_pma_div_clk}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.076
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[5].ct0|dout_r[1]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[5].ct0|dout_r[1]
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|tx_pma_div_clk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|tx_pma_div_clk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 6.805 6.805 R clock network delay
|
|
Info (332115): 6.805 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[5].ct0|dout_r[1]
|
|
Info (332115): 6.994 0.189 FF uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[5].ct0|dout_r[1]|q
|
|
Info (332115): 6.994 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[5].ct0|t1|dout|datae
|
|
Info (332115): 7.345 0.351 FR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[5].ct0|t1|dout|combout
|
|
Info (332115): 7.345 0.000 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[5].ct0|dout_r[1]|d
|
|
Info (332115): 7.345 0.000 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[5].ct0|dout_r[1]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 8.772 8.772 R clock network delay
|
|
Info (332115): 6.804 -1.968 clock pessimism removed
|
|
Info (332115): 6.804 0.000 clock uncertainty
|
|
Info (332115): 7.269 0.465 uTh fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[5].ct0|dout_r[1]
|
|
Info (332115): Data Arrival Time : 7.345
|
|
Info (332115): Data Required Time : 7.269
|
|
Info (332115): Slack : 0.076
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.076
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|rx_pma_clk}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.076
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_prbs_done_sync|resync_chains[0].sync_r[0]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_prbs_done_sync|resync_chains[0].sync_r[1]
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|rx_pma_clk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|rx_pma_clk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 5.133 5.133 R clock network delay
|
|
Info (332115): 5.133 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_prbs_done_sync|resync_chains[0].sync_r[0]
|
|
Info (332115): 5.324 0.191 FF uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_prbs_done_sync|resync_chains[0].sync_r[0]|q
|
|
Info (332115): 5.386 0.062 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_prbs_done_sync|resync_chains[0].sync_r[0]~la_mlab/laboutt[13]
|
|
Info (332115): 5.571 0.185 FF IC High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_prbs_done_sync|resync_chains[0].sync_r[1]|asdata
|
|
Info (332115): 5.571 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_prbs_done_sync|resync_chains[0].sync_r[1]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 7.206 7.206 R clock network delay
|
|
Info (332115): 5.133 -2.073 clock pessimism removed
|
|
Info (332115): 5.133 0.000 clock uncertainty
|
|
Info (332115): 5.495 0.362 uTh fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_prbs_done_sync|resync_chains[0].sync_r[1]
|
|
Info (332115): Data Arrival Time : 5.571
|
|
Info (332115): Data Required Time : 5.495
|
|
Info (332115): Slack : 0.076
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.080
|
|
Info (20696): -to_clock [get_clocks {hssi_pll_r_0_outclk1}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.080
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[0].ct0|dout_r[1]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[0].ct0|dout_r[1]
|
|
Info (332115): Launch Clock : hssi_pll_r_0_outclk1
|
|
Info (332115): Latch Clock : hssi_pll_r_0_outclk1
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 4.511 4.511 R clock network delay
|
|
Info (332115): 4.511 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[0].ct0|dout_r[1]
|
|
Info (332115): 4.729 0.218 FF uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[0].ct0|dout_r[1]|q
|
|
Info (332115): 4.729 0.000 FF CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[0].ct0|t1|dout|datad
|
|
Info (332115): 5.109 0.380 FF CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[0].ct0|t1|dout|combout
|
|
Info (332115): 5.109 0.000 FF CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[0].ct0|dout_r[1]|d
|
|
Info (332115): 5.109 0.000 FF CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[0].ct0|dout_r[1]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 5.033 5.033 R clock network delay
|
|
Info (332115): 4.511 -0.522 clock pessimism removed
|
|
Info (332115): 4.511 0.000 clock uncertainty
|
|
Info (332115): 5.029 0.518 uTh fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[0].ct0|dout_r[1]
|
|
Info (332115): Data Arrival Time : 5.109
|
|
Info (332115): Data Required Time : 5.029
|
|
Info (332115): Slack : 0.080
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.086
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|rx_pma_clk}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.086
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_prbs_err_sync|resync_chains[0].sync_r[1]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_consecutive_error[2]
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|rx_pma_clk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|rx_pma_clk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 5.171 5.171 R clock network delay
|
|
Info (332115): 5.171 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_prbs_err_sync|resync_chains[0].sync_r[1]
|
|
Info (332115): 5.362 0.191 FF uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_prbs_err_sync|resync_chains[0].sync_r[1]|q
|
|
Info (332115): 5.425 0.063 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_prbs_err_sync|resync_chains[0].sync_r[1]~la_mlab/laboutt[6]
|
|
Info (332115): 5.629 0.204 FF IC High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_consecutive_error[2]~1|datac
|
|
Info (332115): 5.743 0.114 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_consecutive_error[2]~1|combout
|
|
Info (332115): 5.743 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_consecutive_error[2]|d
|
|
Info (332115): 5.743 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_consecutive_error[2]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 7.251 7.251 R clock network delay
|
|
Info (332115): 5.192 -2.059 clock pessimism removed
|
|
Info (332115): 5.192 0.000 clock uncertainty
|
|
Info (332115): 5.657 0.465 uTh fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_consecutive_error[2]
|
|
Info (332115): Data Arrival Time : 5.743
|
|
Info (332115): Data Required Time : 5.657
|
|
Info (332115): Slack : 0.086
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.093
|
|
Info (20696): -to_clock [get_clocks {hssi_pll_t_outclk0}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.093
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[3].ct0|dout_r[2]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[3].ct0|dout_r[2]
|
|
Info (332115): Launch Clock : hssi_pll_t_outclk0
|
|
Info (332115): Latch Clock : hssi_pll_t_outclk0
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 4.265 4.265 R clock network delay
|
|
Info (332115): 4.265 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[3].ct0|dout_r[2]
|
|
Info (332115): 4.484 0.219 FF uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[3].ct0|dout_r[2]|q
|
|
Info (332115): 4.484 0.000 FF CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[3].ct0|t2|dout|datae
|
|
Info (332115): 4.878 0.394 FR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[3].ct0|t2|dout|combout
|
|
Info (332115): 4.878 0.000 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[3].ct0|dout_r[2]|d
|
|
Info (332115): 4.878 0.000 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[3].ct0|dout_r[2]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 4.737 4.737 R clock network delay
|
|
Info (332115): 4.265 -0.472 clock pessimism removed
|
|
Info (332115): 4.265 0.000 clock uncertainty
|
|
Info (332115): 4.785 0.520 uTh fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[3].ct0|dout_r[2]
|
|
Info (332115): Data Arrival Time : 4.878
|
|
Info (332115): Data Required Time : 4.785
|
|
Info (332115): Slack : 0.093
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.097
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk0}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.097
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_green_bs|uClk_usrDiv2_q1
|
|
Info (332115): To Node : fpga_top|inst_green_bs|uClk_usrDiv2_q2
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk0
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk0
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 5.390 5.390 R clock network delay
|
|
Info (332115): 5.390 0.000 fpga_top|inst_green_bs|uClk_usrDiv2_q1
|
|
Info (332115): 5.587 0.197 FF uTco fpga_top|inst_green_bs|uClk_usrDiv2_q1|q
|
|
Info (332115): 5.587 0.000 FF CELL High Speed fpga_top|inst_green_bs|uClk_usrDiv2_q2~0|datae
|
|
Info (332115): 5.969 0.382 FR CELL High Speed fpga_top|inst_green_bs|uClk_usrDiv2_q2~0|combout
|
|
Info (332115): 5.969 0.000 RR CELL High Speed fpga_top|inst_green_bs|uClk_usrDiv2_q2|d
|
|
Info (332115): 5.969 0.000 RR CELL High Speed fpga_top|inst_green_bs|uClk_usrDiv2_q2
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 6.521 6.521 R clock network delay
|
|
Info (332115): 5.390 -1.131 clock pessimism removed
|
|
Info (332115): 5.390 0.000 clock uncertainty
|
|
Info (332115): 5.872 0.482 uTh fpga_top|inst_green_bs|uClk_usrDiv2_q2
|
|
Info (332115): Data Arrival Time : 5.969
|
|
Info (332115): Data Required Time : 5.872
|
|
Info (332115): Slack : 0.097
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.101
|
|
Info (20696): -to_clock [get_clocks {fspi_sclk}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.101
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MISOctl|sync_miso_ack|dreg[0]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MISOctl|loadstsinkdata
|
|
Info (332115): Launch Clock : fspi_sclk
|
|
Info (332115): Latch Clock : fspi_sclk
|
|
Info (332115): Exception : dcp_bbs.sdc:3032: set_multicycle_path -hold -to [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MISOctl|loadstsinkdata}] 1
|
|
Info (332115): Multicycle - Setup Start : 2
|
|
Info (332115): Multicycle - Hold Start : 1
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 5.961 5.961 R clock network delay
|
|
Info (332115): 5.961 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MISOctl|sync_miso_ack|dreg[0]
|
|
Info (332115): 6.151 0.190 FF uTco fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MISOctl|sync_miso_ack|dreg[0]|q
|
|
Info (332115): 6.214 0.063 FF CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MISOctl|sync_miso_ack|dreg[0]~la_mlab/laboutt[10]
|
|
Info (332115): 6.413 0.199 FF IC High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MISOctl|i20~0|datad
|
|
Info (332115): 6.533 0.120 FR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MISOctl|i20~0|combout
|
|
Info (332115): 6.533 0.000 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MISOctl|loadstsinkdata|d
|
|
Info (332115): 6.533 0.000 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MISOctl|loadstsinkdata
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 6.940 6.940 R clock network delay
|
|
Info (332115): 5.962 -0.978 clock pessimism removed
|
|
Info (332115): 5.962 0.000 clock uncertainty
|
|
Info (332115): 6.432 0.470 uTh fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MISOctl|loadstsinkdata
|
|
Info (332115): Data Arrival Time : 6.533
|
|
Info (332115): Data Required Time : 6.432
|
|
Info (332115): Slack : 0.101
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.138
|
|
Info (20696): -to_clock [get_clocks {mem|ddr4a|ddr4a_phy_clk_l_2}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.138
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : mem|ddr4a_bridge|ddr_avmm_bridge|cmd_writedata[20]
|
|
Info (332115): To Node : mem|ddr4a|ddr4a|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[0].lane_gen[2].lane_inst~phy_reg1
|
|
Info (332115): Launch Clock : mem|ddr4a|ddr4a_core_usr_clk
|
|
Info (332115): Latch Clock : mem|ddr4a|ddr4a_phy_clk_l_2
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.117 0.117 launch edge time
|
|
Info (332115): 2.915 2.798 R clock network delay
|
|
Info (332115): 2.915 0.000 mem|ddr4a_bridge|ddr_avmm_bridge|cmd_writedata[20]
|
|
Info (332115): 3.104 0.189 FF uTco mem|ddr4a_bridge|ddr_avmm_bridge|cmd_writedata[20]|q
|
|
Info (332115): 3.163 0.059 FF CELL High Speed mem|ddr4a_bridge|ddr_avmm_bridge|cmd_writedata[20]~la_lab/laboutt[6]
|
|
Info (332115): 3.286 0.123 FF IC High Speed mem|ddr4a_avmm_chkr|avm_writedata[20]~160|datab
|
|
Info (332115): 3.457 0.171 FF CELL High Speed mem|ddr4a_avmm_chkr|avm_writedata[20]~160|combout
|
|
Info (332115): 3.458 0.001 FF CELL High Speed mem|ddr4a_avmm_chkr|avm_writedata[20]~160~la_lab/laboutb[17]
|
|
Info (332115): 4.422 0.964 FF IC High Speed mem|ddr4a|ddr4a|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[0].lane_gen[2].lane_inst|data_from_core[48]
|
|
Info (332115): 4.422 0.000 FF CELL mem|ddr4a|ddr4a|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[0].lane_gen[2].lane_inst~phy_reg1
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.117 0.117 latch edge time
|
|
Info (332115): 3.607 3.490 R clock network delay
|
|
Info (332115): 3.417 -0.190 clock pessimism removed
|
|
Info (332115): 3.737 0.320 clock uncertainty
|
|
Info (332115): 4.284 0.547 uTh mem|ddr4a|ddr4a|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[0].lane_gen[2].lane_inst~phy_reg1
|
|
Info (332115): Data Arrival Time : 4.422
|
|
Info (332115): Data Required Time : 4.284
|
|
Info (332115): Slack : 0.138
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.181
|
|
Info (20696): -to_clock [get_clocks {mem|ddr4a|ddr4a_phy_clk_l_1}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.181
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : mem|ddr4a_bridge|ddr_avmm_bridge|cmd_writedata[121]
|
|
Info (332115): To Node : mem|ddr4a|ddr4a|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[2].lane_gen[2].lane_inst~phy_reg1
|
|
Info (332115): Launch Clock : mem|ddr4a|ddr4a_core_usr_clk
|
|
Info (332115): Latch Clock : mem|ddr4a|ddr4a_phy_clk_l_1
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.117 0.117 launch edge time
|
|
Info (332115): 2.914 2.797 R clock network delay
|
|
Info (332115): 2.914 0.000 mem|ddr4a_bridge|ddr_avmm_bridge|cmd_writedata[121]
|
|
Info (332115): 3.103 0.189 FF uTco mem|ddr4a_bridge|ddr_avmm_bridge|cmd_writedata[121]|q
|
|
Info (332115): 3.200 0.097 FF CELL High Speed mem|ddr4a_bridge|ddr_avmm_bridge|cmd_writedata[121]~la_lab/laboutt[11]
|
|
Info (332115): 3.580 0.380 FF IC High Speed mem|ddr4a_avmm_chkr|avm_writedata[121]~457|datac
|
|
Info (332115): 3.695 0.115 FF CELL High Speed mem|ddr4a_avmm_chkr|avm_writedata[121]~457|combout
|
|
Info (332115): 3.696 0.001 FF CELL High Speed mem|ddr4a_avmm_chkr|avm_writedata[121]~457~la_lab/laboutb[3]
|
|
Info (332115): 4.476 0.780 FF IC High Speed mem|ddr4a|ddr4a|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[2].lane_gen[2].lane_inst|data_from_core[81]
|
|
Info (332115): 4.476 0.000 FF CELL mem|ddr4a|ddr4a|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[2].lane_gen[2].lane_inst~phy_reg1
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.117 0.117 latch edge time
|
|
Info (332115): 3.617 3.500 R clock network delay
|
|
Info (332115): 3.427 -0.190 clock pessimism removed
|
|
Info (332115): 3.747 0.320 clock uncertainty
|
|
Info (332115): 4.295 0.548 uTh mem|ddr4a|ddr4a|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[2].lane_gen[2].lane_inst~phy_reg1
|
|
Info (332115): Data Arrival Time : 4.476
|
|
Info (332115): Data Required Time : 4.295
|
|
Info (332115): Slack : 0.181
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.183
|
|
Info (20696): -to_clock [get_clocks {mem|ddr4b|ddr4b_phy_clk_l_1}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.183
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : mem|ddr4b_bridge|ddr_avmm_bridge|cmd_writedata[488]
|
|
Info (332115): To Node : mem|ddr4b|ddr4b|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[2].lane_gen[0].lane_inst~phy_reg1
|
|
Info (332115): Launch Clock : mem|ddr4a|ddr4a_core_usr_clk
|
|
Info (332115): Latch Clock : mem|ddr4b|ddr4b_phy_clk_l_1
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.117 0.117 launch edge time
|
|
Info (332115): 2.869 2.752 R clock network delay
|
|
Info (332115): 2.869 0.000 mem|ddr4b_bridge|ddr_avmm_bridge|cmd_writedata[488]
|
|
Info (332115): 3.056 0.187 FF uTco mem|ddr4b_bridge|ddr_avmm_bridge|cmd_writedata[488]|q
|
|
Info (332115): 3.115 0.059 FF CELL High Speed mem|ddr4b_bridge|ddr_avmm_bridge|cmd_writedata[488]~la_lab/laboutb[9]
|
|
Info (332115): 3.576 0.461 FF IC High Speed mem|ddr4b_avmm_chkr|avm_writedata[0]~327|datad
|
|
Info (332115): 3.691 0.115 FF CELL High Speed mem|ddr4b_avmm_chkr|avm_writedata[0]~327|combout
|
|
Info (332115): 3.692 0.001 FF CELL High Speed mem|ddr4b_avmm_chkr|avm_writedata[0]~327~la_lab/laboutb[8]
|
|
Info (332115): 4.421 0.729 FF IC High Speed mem|ddr4b|ddr4b|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[2].lane_gen[0].lane_inst|data_from_core[71]
|
|
Info (332115): 4.421 0.000 FF CELL mem|ddr4b|ddr4b|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[2].lane_gen[0].lane_inst~phy_reg1
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.117 0.117 latch edge time
|
|
Info (332115): 3.491 3.374 R clock network delay
|
|
Info (332115): 3.382 -0.109 clock pessimism removed
|
|
Info (332115): 3.702 0.320 clock uncertainty
|
|
Info (332115): 4.238 0.536 uTh mem|ddr4b|ddr4b|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[2].lane_gen[0].lane_inst~phy_reg1
|
|
Info (332115): Data Arrival Time : 4.421
|
|
Info (332115): Data Required Time : 4.238
|
|
Info (332115): Slack : 0.183
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.189
|
|
Info (20696): -to_clock [get_clocks {mem|ddr4b|ddr4b_phy_clk_l_2}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.189
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : mem|ddr4b_bridge|ddr_avmm_bridge|cmd_writedata[201]
|
|
Info (332115): To Node : mem|ddr4b|ddr4b|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[0].lane_gen[1].lane_inst~phy_reg1
|
|
Info (332115): Launch Clock : mem|ddr4a|ddr4a_core_usr_clk
|
|
Info (332115): Latch Clock : mem|ddr4b|ddr4b_phy_clk_l_2
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.117 0.117 launch edge time
|
|
Info (332115): 2.846 2.729 R clock network delay
|
|
Info (332115): 2.846 0.000 mem|ddr4b_bridge|ddr_avmm_bridge|cmd_writedata[201]
|
|
Info (332115): 3.034 0.188 FF uTco mem|ddr4b_bridge|ddr_avmm_bridge|cmd_writedata[201]|q
|
|
Info (332115): 3.093 0.059 FF CELL High Speed mem|ddr4b_bridge|ddr_avmm_bridge|cmd_writedata[201]~la_lab/laboutb[14]
|
|
Info (332115): 3.584 0.491 FF IC High Speed mem|ddr4b_avmm_chkr|avm_writedata[0]~75|datac
|
|
Info (332115): 3.696 0.112 FF CELL High Speed mem|ddr4b_avmm_chkr|avm_writedata[0]~75|combout
|
|
Info (332115): 3.697 0.001 FF CELL High Speed mem|ddr4b_avmm_chkr|avm_writedata[0]~75~la_lab/laboutb[9]
|
|
Info (332115): 4.421 0.724 FF IC High Speed mem|ddr4b|ddr4b|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[0].lane_gen[1].lane_inst|data_from_core[83]
|
|
Info (332115): 4.421 0.000 FF CELL mem|ddr4b|ddr4b|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[0].lane_gen[1].lane_inst~phy_reg1
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.117 0.117 latch edge time
|
|
Info (332115): 3.473 3.356 R clock network delay
|
|
Info (332115): 3.364 -0.109 clock pessimism removed
|
|
Info (332115): 3.684 0.320 clock uncertainty
|
|
Info (332115): 4.232 0.548 uTh mem|ddr4b|ddr4b|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[0].lane_gen[1].lane_inst~phy_reg1
|
|
Info (332115): Data Arrival Time : 4.421
|
|
Info (332115): Data Required Time : 4.232
|
|
Info (332115): Slack : 0.189
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.212
|
|
Info (20696): -to_clock [get_clocks {mem|ddr4b|ddr4b_phy_clk_l_0}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.212
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : mem|ddr4b_bridge|ddr_avmm_bridge|cmd_address[23]
|
|
Info (332115): To Node : mem|ddr4b|ddr4b|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[1].tile_ctrl_inst~hmc_reg1
|
|
Info (332115): Launch Clock : mem|ddr4a|ddr4a_core_usr_clk
|
|
Info (332115): Latch Clock : mem|ddr4b|ddr4b_phy_clk_l_0
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.117 0.117 launch edge time
|
|
Info (332115): 2.842 2.725 R clock network delay
|
|
Info (332115): 2.842 0.000 mem|ddr4b_bridge|ddr_avmm_bridge|cmd_address[23]
|
|
Info (332115): 3.032 0.190 FF uTco mem|ddr4b_bridge|ddr_avmm_bridge|cmd_address[23]|q
|
|
Info (332115): 3.091 0.059 FF CELL High Speed mem|ddr4b_bridge|ddr_avmm_bridge|cmd_address[23]~la_mlab/laboutb[13]
|
|
Info (332115): 3.516 0.425 FF IC High Speed mem|ddr4b_emif_address_mux[23]~23|datab
|
|
Info (332115): 3.687 0.171 FF CELL High Speed mem|ddr4b_emif_address_mux[23]~23|combout
|
|
Info (332115): 3.689 0.002 FF CELL High Speed mem|ddr4b_emif_address_mux[23]~23~la_mlab/laboutt[12]
|
|
Info (332115): 4.528 0.839 FF IC High Speed mem|ddr4b|ddr4b|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[1].tile_ctrl_inst|core2ctl_avl0[25]
|
|
Info (332115): 4.528 0.000 FF CELL mem|ddr4b|ddr4b|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[1].tile_ctrl_inst~hmc_reg1
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.117 0.117 latch edge time
|
|
Info (332115): 3.516 3.399 R clock network delay
|
|
Info (332115): 3.407 -0.109 clock pessimism removed
|
|
Info (332115): 3.727 0.320 clock uncertainty
|
|
Info (332115): 4.316 0.589 uTh mem|ddr4b|ddr4b|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[1].tile_ctrl_inst~hmc_reg1
|
|
Info (332115): Data Arrival Time : 4.528
|
|
Info (332115): Data Required Time : 4.316
|
|
Info (332115): Slack : 0.212
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.254
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_bonding_clocks[0]}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.254
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|sta_rx_clk2_by4_1
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs~byte_deserializer_pcs_clk_div_by_4_txclk_reg.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|rx_clk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_bonding_clocks[0]
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 2.780 2.780 R clock network delay
|
|
Info (332115): 2.780 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|sta_rx_clk2_by4_1
|
|
Info (332115): 2.780 0.000 RR CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs~byte_deserializer_pcs_clk_div_by_4_txclk_reg.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 3.816 3.816 R clock network delay
|
|
Info (332115): 2.392 -1.424 clock pessimism removed
|
|
Info (332115): 2.526 0.134 uTh fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs~byte_deserializer_pcs_clk_div_by_4_txclk_reg.reg
|
|
Info (332115): Data Arrival Time : 2.780
|
|
Info (332115): Data Required Time : 2.526
|
|
Info (332115): Slack : 0.254
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.271
|
|
Info (20696): -to_clock [get_clocks {mem|ddr4a|ddr4a_phy_clk_l_0}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.271
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : mem|ddr4a_bridge|ddr_avmm_bridge|cmd_address[14]
|
|
Info (332115): To Node : mem|ddr4a|ddr4a|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[1].tile_ctrl_inst~hmc_reg1
|
|
Info (332115): Launch Clock : mem|ddr4a|ddr4a_core_usr_clk
|
|
Info (332115): Latch Clock : mem|ddr4a|ddr4a_phy_clk_l_0
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.117 0.117 launch edge time
|
|
Info (332115): 2.932 2.815 R clock network delay
|
|
Info (332115): 2.932 0.000 mem|ddr4a_bridge|ddr_avmm_bridge|cmd_address[14]
|
|
Info (332115): 3.121 0.189 FF uTco mem|ddr4a_bridge|ddr_avmm_bridge|cmd_address[14]|q
|
|
Info (332115): 3.180 0.059 FF CELL High Speed mem|ddr4a_bridge|ddr_avmm_bridge|cmd_address[14]~la_lab/laboutt[1]
|
|
Info (332115): 3.287 0.107 FF IC High Speed mem|ddr4a_avmm_chkr|avm_address[14]~14|datac
|
|
Info (332115): 3.400 0.113 FF CELL High Speed mem|ddr4a_avmm_chkr|avm_address[14]~14|combout
|
|
Info (332115): 3.401 0.001 FF CELL High Speed mem|ddr4a_avmm_chkr|avm_address[14]~14~la_lab/laboutt[3]
|
|
Info (332115): 4.124 0.723 FF IC High Speed mem|ddr4a|ddr4a|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[1].tile_ctrl_inst|core2ctl_avl0[16]
|
|
Info (332115): 4.124 0.000 FF CELL mem|ddr4a|ddr4a|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[1].tile_ctrl_inst~hmc_reg1
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.117 0.117 latch edge time
|
|
Info (332115): 3.644 3.527 R clock network delay
|
|
Info (332115): 3.043 -0.601 clock pessimism removed
|
|
Info (332115): 3.266 0.223 clock uncertainty
|
|
Info (332115): 3.853 0.587 uTh mem|ddr4a|ddr4a|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[1].tile_ctrl_inst~hmc_reg1
|
|
Info (332115): Data Arrival Time : 4.124
|
|
Info (332115): Data Required Time : 3.853
|
|
Info (332115): Slack : 0.271
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.483
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|pld_clk}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.483
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_sriov_2.sriov2.sriov_bridge|altpcie_pcie_sriov2_top_inst|altpcie_sriov2_tx_data_bridge_inst|TxStData_hip_o[19]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~pld_clk.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|wys~CORE_CLK_OUT
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|pld_clk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 8.056 8.056 R clock network delay
|
|
Info (332115): 8.056 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_sriov_2.sriov2.sriov_bridge|altpcie_pcie_sriov2_top_inst|altpcie_sriov2_tx_data_bridge_inst|TxStData_hip_o[19]
|
|
Info (332115): 8.247 0.191 FF uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_sriov_2.sriov2.sriov_bridge|altpcie_pcie_sriov2_top_inst|altpcie_sriov2_tx_data_bridge_inst|TxStData_hip_o[19]|q
|
|
Info (332115): 8.305 0.058 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_sriov_2.sriov2.sriov_bridge|altpcie_pcie_sriov2_top_inst|altpcie_sriov2_tx_data_bridge_inst|TxStData_hip_o[19]~la_mlab/laboutt[9]
|
|
Info (332115): 9.257 0.952 FF IC High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|tx_st_data[19]
|
|
Info (332115): 9.257 0.000 FF CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~pld_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 9.890 9.890 R clock network delay
|
|
Info (332115): 8.551 -1.339 clock pessimism removed
|
|
Info (332115): 8.618 0.067 clock uncertainty
|
|
Info (332115): 8.774 0.156 uTh fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~pld_clk.reg
|
|
Info (332115): Data Arrival Time : 9.257
|
|
Info (332115): Data Required Time : 8.774
|
|
Info (332115): Slack : 0.483
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.588
|
|
Info (20696): -to_clock [get_clocks {vl_qph_user_clk_clkpsc_clk0}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.588
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[3]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[3]
|
|
Info (332115): Launch Clock : vl_qph_user_clk_clkpsc_clk0
|
|
Info (332115): Latch Clock : vl_qph_user_clk_clkpsc_clk0
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 5.677 5.677 R clock network delay
|
|
Info (332115): 5.677 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[3]
|
|
Info (332115): 5.882 0.205 FF uTco fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[3]|q
|
|
Info (332115): 5.941 0.059 FF CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[3]~la_mlab/laboutb[6]
|
|
Info (332115): 6.613 0.672 FF IC High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[3]~0|datac
|
|
Info (332115): 6.750 0.137 FF CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[3]~0|combout
|
|
Info (332115): 6.750 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[3]|d
|
|
Info (332115): 6.750 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[3]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 6.855 6.855 R clock network delay
|
|
Info (332115): 5.677 -1.178 clock pessimism removed
|
|
Info (332115): 5.677 0.000 clock uncertainty
|
|
Info (332115): 6.162 0.485 uTh fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[3]
|
|
Info (332115): Data Arrival Time : 6.750
|
|
Info (332115): Data Required Time : 6.162
|
|
Info (332115): Slack : 0.588
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.588
|
|
Info (20696): -to_clock [get_clocks {vl_qph_user_clk_clkpsc_clk1}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.588
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[3]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[3]
|
|
Info (332115): Launch Clock : vl_qph_user_clk_clkpsc_clk1
|
|
Info (332115): Latch Clock : vl_qph_user_clk_clkpsc_clk1
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 5.778 5.778 R clock network delay
|
|
Info (332115): 5.778 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[3]
|
|
Info (332115): 5.983 0.205 FF uTco fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[3]|q
|
|
Info (332115): 6.042 0.059 FF CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[3]~la_mlab/laboutb[6]
|
|
Info (332115): 6.714 0.672 FF IC High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[3]~0|datac
|
|
Info (332115): 6.851 0.137 FF CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[3]~0|combout
|
|
Info (332115): 6.851 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[3]|d
|
|
Info (332115): 6.851 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[3]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 6.991 6.991 R clock network delay
|
|
Info (332115): 5.778 -1.213 clock pessimism removed
|
|
Info (332115): 5.778 0.000 clock uncertainty
|
|
Info (332115): 6.263 0.485 uTh fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[3]
|
|
Info (332115): Data Arrival Time : 6.851
|
|
Info (332115): Data Required Time : 6.263
|
|
Info (332115): Slack : 0.588
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.593
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|avmmclk}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.593
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|channel_count[2]~RTMDUPLICATE
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Launch Clock : PCIE_REFCLK
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|avmmclk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 5.098 5.098 R clock network delay
|
|
Info (332115): 5.098 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|channel_count[2]~RTMDUPLICATE
|
|
Info (332115): 5.290 0.192 RR uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|channel_count[2]~RTMDUPLICATE|q
|
|
Info (332115): 5.379 0.089 RR CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|channel_count[2]~RTMDUPLICATE~la_mlab/laboutt[2]
|
|
Info (332115): 5.534 0.155 RR IC High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i8~0|datab
|
|
Info (332115): 5.712 0.178 RF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i8~0|combout
|
|
Info (332115): 5.714 0.002 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i8~0~la_mlab/laboutb[15]
|
|
Info (332115): 6.540 0.826 FF IC Mixed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst|avmmwrite
|
|
Info (332115): 6.540 0.000 FF CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 6.148 6.148 R clock network delay
|
|
Info (332115): 5.621 -0.527 clock pessimism removed
|
|
Info (332115): 5.661 0.040 clock uncertainty
|
|
Info (332115): 5.947 0.286 uTh fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Arrival Time : 6.540
|
|
Info (332115): Data Required Time : 5.947
|
|
Info (332115): Slack : 0.593
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.651
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|avmmclk}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.651
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|reconfig_address[8]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Launch Clock : SYS_RefClk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|avmmclk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 4.328 4.328 R clock network delay
|
|
Info (332115): 4.328 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|reconfig_address[8]
|
|
Info (332115): 4.528 0.200 FF uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|reconfig_address[8]|q
|
|
Info (332115): 4.630 0.102 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|reconfig_address[8]~la_mlab/laboutt[19]
|
|
Info (332115): 5.976 1.346 FF IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst|avmmaddress[8]
|
|
Info (332115): 5.976 0.000 FF CELL fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 5.145 5.145 R clock network delay
|
|
Info (332115): 4.883 -0.262 clock pessimism removed
|
|
Info (332115): 4.913 0.030 clock uncertainty
|
|
Info (332115): 5.325 0.412 uTh fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Arrival Time : 5.976
|
|
Info (332115): Data Required Time : 5.325
|
|
Info (332115): Slack : 0.651
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.725
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|avmmclk}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.725
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|g_arb[1].arbiter_inst|grant[0]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Launch Clock : PCIE_REFCLK
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|avmmclk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 5.103 5.103 R clock network delay
|
|
Info (332115): 5.103 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|g_arb[1].arbiter_inst|grant[0]
|
|
Info (332115): 5.294 0.191 FF uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|g_arb[1].arbiter_inst|grant[0]|q
|
|
Info (332115): 5.352 0.058 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|g_arb[1].arbiter_inst|grant[0]~la_mlab/laboutb[17]
|
|
Info (332115): 5.654 0.302 FF IC Mixed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i316~3|datab
|
|
Info (332115): 5.827 0.173 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i316~3|combout
|
|
Info (332115): 5.829 0.002 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i316~3~la_mlab/laboutb[17]
|
|
Info (332115): 6.865 1.036 FF IC High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst|avmmwritedata[3]
|
|
Info (332115): 6.865 0.000 FF CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 6.159 6.159 R clock network delay
|
|
Info (332115): 5.632 -0.527 clock pessimism removed
|
|
Info (332115): 5.672 0.040 clock uncertainty
|
|
Info (332115): 6.140 0.468 uTh fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Arrival Time : 6.865
|
|
Info (332115): Data Required Time : 6.140
|
|
Info (332115): Slack : 0.725
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.773
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|avmmclk}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.773
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|reconfig_address[8]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Launch Clock : SYS_RefClk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|avmmclk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 4.328 4.328 R clock network delay
|
|
Info (332115): 4.328 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|reconfig_address[8]
|
|
Info (332115): 4.528 0.200 FF uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|reconfig_address[8]|q
|
|
Info (332115): 4.630 0.102 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|reconfig_address[8]~la_mlab/laboutt[19]
|
|
Info (332115): 6.106 1.476 FF IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst|avmmaddress[8]
|
|
Info (332115): 6.106 0.000 FF CELL fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 5.153 5.153 R clock network delay
|
|
Info (332115): 4.891 -0.262 clock pessimism removed
|
|
Info (332115): 4.921 0.030 clock uncertainty
|
|
Info (332115): 5.333 0.412 uTh fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Arrival Time : 6.106
|
|
Info (332115): Data Required Time : 5.333
|
|
Info (332115): Slack : 0.773
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.853
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|avmmclk}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.853
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_address[4]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Launch Clock : PCIE_REFCLK
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|avmmclk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 5.133 5.133 R clock network delay
|
|
Info (332115): 5.133 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_address[4]
|
|
Info (332115): 5.352 0.219 FF uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_address[4]|q
|
|
Info (332115): 5.423 0.071 FF CELL Low Power fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_address[4]~la_lab/laboutb[1]
|
|
Info (332115): 5.939 0.516 FF IC Mixed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i522|dataf
|
|
Info (332115): 5.974 0.035 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i522|combout
|
|
Info (332115): 5.975 0.001 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i522~la_lab/laboutt[16]
|
|
Info (332115): 6.874 0.899 FF IC High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst|avmmaddress[4]
|
|
Info (332115): 6.874 0.000 FF CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 6.084 6.084 R clock network delay
|
|
Info (332115): 5.574 -0.510 clock pessimism removed
|
|
Info (332115): 5.614 0.040 clock uncertainty
|
|
Info (332115): 6.021 0.407 uTh fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Arrival Time : 6.874
|
|
Info (332115): Data Required Time : 6.021
|
|
Info (332115): Slack : 0.853
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.910
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|avmmclk}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.910
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|g_arb[3].arbiter_inst|grant[0]~DUPLICATE
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Launch Clock : PCIE_REFCLK
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|avmmclk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 5.103 5.103 R clock network delay
|
|
Info (332115): 5.103 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|g_arb[3].arbiter_inst|grant[0]~DUPLICATE
|
|
Info (332115): 5.295 0.192 FF uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|g_arb[3].arbiter_inst|grant[0]~DUPLICATE|q
|
|
Info (332115): 5.354 0.059 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|g_arb[3].arbiter_inst|grant[0]~DUPLICATE~la_mlab/laboutb[6]
|
|
Info (332115): 5.767 0.413 FF IC Mixed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i768|datac
|
|
Info (332115): 5.907 0.140 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i768|combout
|
|
Info (332115): 5.909 0.002 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i768~la_mlab/laboutt[14]
|
|
Info (332115): 6.971 1.062 FF IC High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst|avmmaddress[6]
|
|
Info (332115): 6.971 0.000 FF CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 6.083 6.083 R clock network delay
|
|
Info (332115): 5.573 -0.510 clock pessimism removed
|
|
Info (332115): 5.613 0.040 clock uncertainty
|
|
Info (332115): 6.061 0.448 uTh fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Arrival Time : 6.971
|
|
Info (332115): Data Required Time : 6.061
|
|
Info (332115): Slack : 0.910
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.913
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|avmmclk}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.913
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|reconfig_address[8]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Launch Clock : SYS_RefClk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|avmmclk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 4.328 4.328 R clock network delay
|
|
Info (332115): 4.328 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|reconfig_address[8]
|
|
Info (332115): 4.528 0.200 FF uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|reconfig_address[8]|q
|
|
Info (332115): 4.630 0.102 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|reconfig_address[8]~la_mlab/laboutt[19]
|
|
Info (332115): 6.260 1.630 FF IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst|avmmaddress[8]
|
|
Info (332115): 6.260 0.000 FF CELL fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 5.167 5.167 R clock network delay
|
|
Info (332115): 4.905 -0.262 clock pessimism removed
|
|
Info (332115): 4.935 0.030 clock uncertainty
|
|
Info (332115): 5.347 0.412 uTh fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Arrival Time : 6.260
|
|
Info (332115): Data Required Time : 5.347
|
|
Info (332115): Slack : 0.913
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 1.028
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|avmmclk}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 1.028
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_writedata[3]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Launch Clock : PCIE_REFCLK
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|avmmclk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 5.111 5.111 R clock network delay
|
|
Info (332115): 5.111 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_writedata[3]
|
|
Info (332115): 5.306 0.195 FF uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_writedata[3]|q
|
|
Info (332115): 5.365 0.059 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_writedata[3]~la_lab/laboutt[17]
|
|
Info (332115): 6.021 0.656 FF IC Mixed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i1024~3|dataf
|
|
Info (332115): 6.054 0.033 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i1024~3|combout
|
|
Info (332115): 6.056 0.002 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i1024~3~la_mlab/laboutb[19]
|
|
Info (332115): 7.088 1.032 FF IC High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst|avmmwritedata[3]
|
|
Info (332115): 7.088 0.000 FF CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 6.062 6.062 R clock network delay
|
|
Info (332115): 5.552 -0.510 clock pessimism removed
|
|
Info (332115): 5.592 0.040 clock uncertainty
|
|
Info (332115): 6.060 0.468 uTh fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Arrival Time : 7.088
|
|
Info (332115): Data Required Time : 6.060
|
|
Info (332115): Slack : 1.028
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 1.124
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|avmmclk}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 1.124
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|channel_count[2]~RTM_1
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Launch Clock : PCIE_REFCLK
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|avmmclk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 5.104 5.104 R clock network delay
|
|
Info (332115): 5.104 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|channel_count[2]~RTM_1
|
|
Info (332115): 5.292 0.188 FF uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|channel_count[2]~RTM_1|q
|
|
Info (332115): 5.351 0.059 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|channel_count[2]~RTM_1~la_lab/laboutb[14]
|
|
Info (332115): 5.828 0.477 FF IC Mixed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i1188~0|dataf
|
|
Info (332115): 5.860 0.032 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i1188~0|combout
|
|
Info (332115): 5.862 0.002 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i1188~0~la_mlab/laboutt[14]
|
|
Info (332115): 6.979 1.117 FF IC Mixed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst|avmmwrite
|
|
Info (332115): 6.979 0.000 FF CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 6.039 6.039 R clock network delay
|
|
Info (332115): 5.529 -0.510 clock pessimism removed
|
|
Info (332115): 5.569 0.040 clock uncertainty
|
|
Info (332115): 5.855 0.286 uTh fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Arrival Time : 6.979
|
|
Info (332115): Data Required Time : 5.855
|
|
Info (332115): Slack : 1.124
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 1.325
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|avmmclk}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 1.325
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_writedata[3]~DUPLICATE
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Launch Clock : PCIE_REFCLK
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|avmmclk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 5.111 5.111 R clock network delay
|
|
Info (332115): 5.111 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_writedata[3]~DUPLICATE
|
|
Info (332115): 5.303 0.192 FF uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_writedata[3]~DUPLICATE|q
|
|
Info (332115): 5.399 0.096 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_writedata[3]~DUPLICATE~la_lab/laboutt[16]
|
|
Info (332115): 5.615 0.216 FF IC High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i1732~3|datac
|
|
Info (332115): 5.730 0.115 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i1732~3|combout
|
|
Info (332115): 5.731 0.001 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i1732~3~la_lab/laboutt[2]
|
|
Info (332115): 7.376 1.645 FF IC Mixed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst|avmmwritedata[3]
|
|
Info (332115): 7.376 0.000 FF CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 6.053 6.053 R clock network delay
|
|
Info (332115): 5.543 -0.510 clock pessimism removed
|
|
Info (332115): 5.583 0.040 clock uncertainty
|
|
Info (332115): 6.051 0.468 uTh fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Arrival Time : 7.376
|
|
Info (332115): Data Required Time : 6.051
|
|
Info (332115): Slack : 1.325
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 1.379
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|avmmclk}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 1.379
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|reconfig_writedata[6]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Launch Clock : SYS_RefClk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|avmmclk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 4.328 4.328 R clock network delay
|
|
Info (332115): 4.328 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|reconfig_writedata[6]
|
|
Info (332115): 4.521 0.193 FF uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|reconfig_writedata[6]|q
|
|
Info (332115): 4.583 0.062 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|reconfig_writedata[6]~la_mlab/laboutb[9]
|
|
Info (332115): 6.879 2.296 FF IC High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst|avmmwritedata[6]
|
|
Info (332115): 6.879 0.000 FF CELL fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 5.289 5.289 R clock network delay
|
|
Info (332115): 5.027 -0.262 clock pessimism removed
|
|
Info (332115): 5.057 0.030 clock uncertainty
|
|
Info (332115): 5.500 0.443 uTh fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Arrival Time : 6.879
|
|
Info (332115): Data Required Time : 5.500
|
|
Info (332115): Slack : 1.379
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 1.623
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|avmmclk}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 1.623
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_writedata[1]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Launch Clock : PCIE_REFCLK
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|avmmclk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 5.111 5.111 R clock network delay
|
|
Info (332115): 5.111 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_writedata[1]
|
|
Info (332115): 5.305 0.194 FF uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_writedata[1]|q
|
|
Info (332115): 5.405 0.100 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_writedata[1]~la_lab/laboutb[8]
|
|
Info (332115): 5.666 0.261 FF IC High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i1496~1|datae
|
|
Info (332115): 5.786 0.120 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i1496~1|combout
|
|
Info (332115): 5.787 0.001 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i1496~1~la_lab/laboutt[18]
|
|
Info (332115): 7.671 1.884 FF IC Mixed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst|avmmwritedata[1]
|
|
Info (332115): 7.671 0.000 FF CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 6.078 6.078 R clock network delay
|
|
Info (332115): 5.568 -0.510 clock pessimism removed
|
|
Info (332115): 5.608 0.040 clock uncertainty
|
|
Info (332115): 6.048 0.440 uTh fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Arrival Time : 7.671
|
|
Info (332115): Data Required Time : 6.048
|
|
Info (332115): Slack : 1.623
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 6.632
|
|
Info (20696): -to_clock [get_clocks {pr_clk_enable_dclk_reg2_user_clk}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 6.632
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_cb_host|alt_pr_cb_controller_v2|pr_request_reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_cb_host|alt_pr_cb_controller_v2|alt_pr_cb_interface|m_prblock~cs_css/pr_clk_core.reg
|
|
Info (332115): Launch Clock : u0|dcp_iopll|dcp_iopll|clk100
|
|
Info (332115): Latch Clock : pr_clk_enable_dclk_reg2_user_clk
|
|
Info (332115): Exception : dcp_bbs.sdc:3119: set_multicycle_path -hold -from [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_cb_host|alt_pr_cb_controller_v2|pr_request_reg}] -to [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_cb_host|alt_pr_cb_controller_v2|alt_pr_cb_interface|m_prblock~cs_css/pr_clk_core.reg}] 1
|
|
Info (332115): Multicycle - Setup Start : 2
|
|
Info (332115): Multicycle - Hold Start : 1
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 10.000 10.000 launch edge time
|
|
Info (332115): 18.293 8.293 R clock network delay
|
|
Info (332115): 18.293 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_cb_host|alt_pr_cb_controller_v2|pr_request_reg
|
|
Info (332115): 18.488 0.195 FF uTco fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_cb_host|alt_pr_cb_controller_v2|pr_request_reg|q
|
|
Info (332115): 18.584 0.096 FF CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_cb_host|alt_pr_cb_controller_v2|pr_request_reg~la_lab/laboutt[0]
|
|
Info (332115): 22.724 4.140 FF IC High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_cb_host|alt_pr_cb_controller_v2|alt_pr_cb_interface|m_prblock|prrequest
|
|
Info (332115): 22.724 0.000 FF CELL fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_cb_host|alt_pr_cb_controller_v2|alt_pr_cb_interface|m_prblock~cs_css/pr_clk_core.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 5.000 5.000 latch edge time
|
|
Info (332115): 16.157 11.157 R clock network delay
|
|
Info (332115): 14.911 -1.246 clock pessimism removed
|
|
Info (332115): 15.081 0.170 clock uncertainty
|
|
Info (332115): 16.092 1.011 uTh fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_cb_host|alt_pr_cb_controller_v2|alt_pr_cb_interface|m_prblock~cs_css/pr_clk_core.reg
|
|
Info (332115): Data Arrival Time : 22.724
|
|
Info (332115): Data Required Time : 16.092
|
|
Info (332115): Slack : 6.632
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 0.376
|
|
Info (20696): -to_clock [get_clocks {mem|ddr4a|ddr4a_core_usr_clk}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 0.376
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_green_bs|ddr4a_reset_sync|resync_chains[0].synchronizer_nocut|dreg[0]
|
|
Info (332115): To Node : fpga_top|inst_green_bs|ddr4a_avmm_bridge|ddr_avmm_bridge|rsp_readdata[450]
|
|
Info (332115): Launch Clock : mem|ddr4a|ddr4a_core_usr_clk
|
|
Info (332115): Latch Clock : mem|ddr4a|ddr4a_core_usr_clk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.117 0.117 launch edge time
|
|
Info (332115): 3.785 3.668 R clock network delay
|
|
Info (332115): 3.785 0.000 fpga_top|inst_green_bs|ddr4a_reset_sync|resync_chains[0].synchronizer_nocut|dreg[0]
|
|
Info (332115): 4.081 0.296 RR uTco fpga_top|inst_green_bs|ddr4a_reset_sync|resync_chains[0].synchronizer_nocut|dreg[0]|q
|
|
Info (332115): 4.222 0.141 RR CELL High Speed fpga_top|inst_green_bs|ddr4a_reset_sync|resync_chains[0].synchronizer_nocut|dreg[0]~la_lab/laboutb[6]
|
|
Info (332115): 6.908 2.686 RR IC High Speed fpga_top|inst_green_bs|ddr4a_avmm_bridge|ddr_avmm_bridge|rsp_readdata[450]|clrn
|
|
Info (332115): 6.908 0.000 RR CELL High Speed fpga_top|inst_green_bs|ddr4a_avmm_bridge|ddr_avmm_bridge|rsp_readdata[450]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 3.869 3.869 latch edge time
|
|
Info (332115): 6.717 2.848 R clock network delay
|
|
Info (332115): 7.477 0.760 clock pessimism removed
|
|
Info (332115): 7.447 -0.030 clock uncertainty
|
|
Info (332115): 7.284 -0.163 uTsu fpga_top|inst_green_bs|ddr4a_avmm_bridge|ddr_avmm_bridge|rsp_readdata[450]
|
|
Info (332115): Data Arrival Time : 6.908
|
|
Info (332115): Data Required Time : 7.284
|
|
Info (332115): Slack : 0.376
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 0.629
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|wys~CORE_CLK_OUT}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 0.629
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_sriov_2.sriov2.sriov_bridge|rs_hip|npor_sync_pld_clk
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_sriov_2.sriov2.sriov_bridge|rs_hip|recovery_cnt[0]
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|wys~CORE_CLK_OUT
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|wys~CORE_CLK_OUT
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 9.585 9.585 R clock network delay
|
|
Info (332115): 9.585 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_sriov_2.sriov2.sriov_bridge|rs_hip|npor_sync_pld_clk
|
|
Info (332115): 9.852 0.267 RR uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_sriov_2.sriov2.sriov_bridge|rs_hip|npor_sync_pld_clk|q
|
|
Info (332115): 10.072 0.220 RR CELL Low Power fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_sriov_2.sriov2.sriov_bridge|rs_hip|npor_sync_pld_clk~la_lab/laboutb[8]
|
|
Info (332115): 12.702 2.630 RR IC Mixed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_sriov_2.sriov2.sriov_bridge|rs_hip|recovery_cnt[0]|clrn
|
|
Info (332115): 12.702 0.000 RR CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_sriov_2.sriov2.sriov_bridge|rs_hip|recovery_cnt[0]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 4.000 4.000 latch edge time
|
|
Info (332115): 12.133 8.133 R clock network delay
|
|
Info (332115): 13.472 1.339 clock pessimism removed
|
|
Info (332115): 13.331 -0.141 uTsu fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_sriov_2.sriov2.sriov_bridge|rs_hip|recovery_cnt[0]
|
|
Info (332115): Data Arrival Time : 12.702
|
|
Info (332115): Data Required Time : 13.331
|
|
Info (332115): Slack : 0.629
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 1.061
|
|
Info (20696): -to_clock [get_clocks {u0|dcp_iopll|dcp_iopll|clk1x}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 1.061
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|c32ui_SystemReset_n
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|tcm_to_bmc_mm_bridge_s0_agent_rdata_fifo|infer_mem_rtl_0|auto_generated|ram_block1a7~reg0
|
|
Info (332115): Launch Clock : u0|dcp_iopll|dcp_iopll|clk1x
|
|
Info (332115): Latch Clock : u0|dcp_iopll|dcp_iopll|clk1x
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 9.726 9.726 R clock network delay
|
|
Info (332115): 9.726 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|c32ui_SystemReset_n
|
|
Info (332115): 9.956 0.230 RR uTco fpga_top|inst_fiu_top|inst_ccip_fabric_top|c32ui_SystemReset_n|q
|
|
Info (332115): 10.075 0.119 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|c32ui_SystemReset_n~la_lab/laboutb[18]
|
|
Info (332115): 11.617 1.542 RR IC Mixed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|tcm_master_reset~0|dataf
|
|
Info (332115): 11.676 0.059 RF CELL Low Power fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|tcm_master_reset~0|combout
|
|
Info (332115): 11.681 0.005 FF CELL Low Power fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|tcm_master_reset~0~la_mlab/laboutb[10]
|
|
Info (332115): 12.915 1.234 FF IC Mixed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|tcm_to_bmc_mm_bridge_s0_agent_rdata_fifo|infer_mem_rtl_0|auto_generated|ram_block1a7|clr0
|
|
Info (332115): 12.915 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|tcm_to_bmc_mm_bridge_s0_agent_rdata_fifo|infer_mem_rtl_0|auto_generated|ram_block1a7~reg0
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 5.000 5.000 latch edge time
|
|
Info (332115): 13.316 8.316 R clock network delay
|
|
Info (332115): 14.639 1.323 clock pessimism removed
|
|
Info (332115): 14.489 -0.150 clock uncertainty
|
|
Info (332115): 13.976 -0.513 uTsu fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|tcm_to_bmc_mm_bridge_s0_agent_rdata_fifo|infer_mem_rtl_0|auto_generated|ram_block1a7~reg0
|
|
Info (332115): Data Arrival Time : 12.915
|
|
Info (332115): Data Required Time : 13.976
|
|
Info (332115): Slack : 1.061
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 1.371
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk1}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 1.371
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[3].core|pipeline|execute|fpu_unit|fpu_fpga|fp_div|[3].reset_relay|reset_r[0]
|
|
Info (332115): To Node : fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[3].core|pipeline|execute|fpu_unit|fpu_fpga|fp_div|[3].fdiv|memoryC2_uid118_invTables_lutmem_dmem|auto_generated|altsyncram1|ram_block2a11~reg0
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk1
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk1
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 6.506 6.506 R clock network delay
|
|
Info (332115): 6.506 0.000 fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[3].core|pipeline|execute|fpu_unit|fpu_fpga|fp_div|[3].reset_relay|reset_r[0]
|
|
Info (332115): 6.742 0.236 FF uTco fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[3].core|pipeline|execute|fpu_unit|fpu_fpga|fp_div|[3].reset_relay|reset_r[0]|q
|
|
Info (332115): 6.889 0.147 FF CELL High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[3].core|pipeline|execute|fpu_unit|fpu_fpga|fp_div|[3].reset_relay|reset_r[0]~la_mlab/laboutb[15]
|
|
Info (332115): 8.933 2.044 FF IC High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[3].core|pipeline|execute|fpu_unit|fpu_fpga|fp_div|[3].fdiv|memoryC2_uid118_invTables_lutmem_dmem|auto_generated|altsyncram1|ram_block2a11|clr0
|
|
Info (332115): 8.933 0.000 FF CELL High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[3].core|pipeline|execute|fpu_unit|fpu_fpga|fp_div|[3].fdiv|memoryC2_uid118_invTables_lutmem_dmem|auto_generated|altsyncram1|ram_block2a11~reg0
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 4.545 4.545 latch edge time
|
|
Info (332115): 9.855 5.310 R clock network delay
|
|
Info (332115): 10.839 0.984 clock pessimism removed
|
|
Info (332115): 10.809 -0.030 clock uncertainty
|
|
Info (332115): 10.304 -0.505 uTsu fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[3].core|pipeline|execute|fpu_unit|fpu_fpga|fp_div|[3].fdiv|memoryC2_uid118_invTables_lutmem_dmem|auto_generated|altsyncram1|ram_block2a11~reg0
|
|
Info (332115): Data Arrival Time : 8.933
|
|
Info (332115): Data Required Time : 10.304
|
|
Info (332115): Slack : 1.371
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 1.376
|
|
Info (20696): -to_clock [get_clocks {u0|dcp_iopll|dcp_iopll|clk100}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 1.376
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|c32ui_SystemReset_n
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|ddr_backchannel|mm_clock_crossing_bridge_0|cmd_fifo|mem_rtl_0|auto_generated|ram_block1a23~reg1
|
|
Info (332115): Launch Clock : u0|dcp_iopll|dcp_iopll|clk1x
|
|
Info (332115): Latch Clock : u0|dcp_iopll|dcp_iopll|clk100
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 5.000 5.000 launch edge time
|
|
Info (332115): 14.726 9.726 R clock network delay
|
|
Info (332115): 14.726 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|c32ui_SystemReset_n
|
|
Info (332115): 14.956 0.230 RR uTco fpga_top|inst_fiu_top|inst_ccip_fabric_top|c32ui_SystemReset_n|q
|
|
Info (332115): 15.075 0.119 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|c32ui_SystemReset_n~la_lab/laboutb[18]
|
|
Info (332115): 16.617 1.542 RR IC Mixed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|tcm_master_reset~0|dataf
|
|
Info (332115): 16.676 0.059 RF CELL Low Power fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|tcm_master_reset~0|combout
|
|
Info (332115): 16.681 0.005 FF CELL Low Power fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|tcm_master_reset~0~la_mlab/laboutb[10]
|
|
Info (332115): 17.243 0.562 FF IC Mixed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|ddr_backchannel|mm_clock_crossing_bridge_0|cmd_fifo|mem_rtl_0|auto_generated|ram_block1a23|clr0
|
|
Info (332115): 17.243 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|ddr_backchannel|mm_clock_crossing_bridge_0|cmd_fifo|mem_rtl_0|auto_generated|ram_block1a23~reg1
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 10.000 10.000 latch edge time
|
|
Info (332115): 18.380 8.380 R clock network delay
|
|
Info (332115): 19.303 0.923 clock pessimism removed
|
|
Info (332115): 19.143 -0.160 clock uncertainty
|
|
Info (332115): 18.619 -0.524 uTsu fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|ddr_backchannel|mm_clock_crossing_bridge_0|cmd_fifo|mem_rtl_0|auto_generated|ram_block1a23~reg1
|
|
Info (332115): Data Arrival Time : 17.243
|
|
Info (332115): Data Required Time : 18.619
|
|
Info (332115): Slack : 1.376
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 2.005
|
|
Info (20696): -to_clock [get_clocks {SYS_RefClk}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 2.005
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_cb_host|alt_pr_cb_controller_v2|freeze_reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|pr_freeze_rsync
|
|
Info (332115): Launch Clock : u0|dcp_iopll|dcp_iopll|clk100
|
|
Info (332115): Latch Clock : SYS_RefClk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 9.694 9.694 R clock network delay
|
|
Info (332115): 9.694 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_cb_host|alt_pr_cb_controller_v2|freeze_reg
|
|
Info (332115): 9.930 0.236 FF uTco fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_cb_host|alt_pr_cb_controller_v2|freeze_reg|q
|
|
Info (332115): 10.056 0.126 FF CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_cb_host|alt_pr_cb_controller_v2|freeze_reg~la_lab/laboutt[8]
|
|
Info (332115): 12.152 2.096 FF IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|pr_freeze_rsync|clrn
|
|
Info (332115): 12.152 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|pr_freeze_rsync
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 10.000 10.000 latch edge time
|
|
Info (332115): 14.347 4.347 R clock network delay
|
|
Info (332115): 14.609 0.262 clock pessimism removed
|
|
Info (332115): 14.299 -0.310 clock uncertainty
|
|
Info (332115): 14.157 -0.142 uTsu fpga_top|inst_fiu_top|inst_hssi_ctrl|pr_freeze_rsync
|
|
Info (332115): Data Arrival Time : 12.152
|
|
Info (332115): Data Required Time : 14.157
|
|
Info (332115): Slack : 2.005
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 2.256
|
|
Info (20696): -to_clock [get_clocks {filtered_sclk_negedge}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 2.256
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|SPISlaveToAvalonMasterBridge_reset_clk_domain_synch|data_out
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MOSIctl|stsourcedata[4]
|
|
Info (332115): Launch Clock : u0|dcp_iopll|dcp_iopll|clk1x
|
|
Info (332115): Latch Clock : filtered_sclk_negedge
|
|
Info (332115): Exception : dcp_bbs.sdc:3060: set_multicycle_path -setup -from [get_keepers {*SPISlaveToAvalonMasterBridge_reset_clk_domain_synch|data_out}] -to [get_keepers {*SPIPhy_MOSIctl|stsourcedata*}] 3
|
|
Info (332115): Multicycle - Setup Start : 3
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 235.000 235.000 launch edge time
|
|
Info (332115): 244.705 9.705 R clock network delay
|
|
Info (332115): 244.705 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|SPISlaveToAvalonMasterBridge_reset_clk_domain_synch|data_out
|
|
Info (332115): 244.960 0.255 RR uTco fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|SPISlaveToAvalonMasterBridge_reset_clk_domain_synch|data_out|q
|
|
Info (332115): 245.108 0.148 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|SPISlaveToAvalonMasterBridge_reset_clk_domain_synch|data_out~la_mlab/laboutt[1]
|
|
Info (332115): 247.525 2.417 RR IC Mixed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MOSIctl|stsourcedata[4]|clrn
|
|
Info (332115): 247.525 0.000 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MOSIctl|stsourcedata[4]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 250.000 250.000 latch edge time
|
|
Info (332115): 250.227 0.227 R clock network delay
|
|
Info (332115): 249.927 -0.300 clock uncertainty
|
|
Info (332115): 249.781 -0.146 uTsu fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MOSIctl|stsourcedata[4]
|
|
Info (332115): Data Arrival Time : 247.525
|
|
Info (332115): Data Required Time : 249.781
|
|
Info (332115): Slack : 2.256
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 2.494
|
|
Info (20696): -to_clock [get_clocks {mem|ddr4a|ddr4a_core_cal_slave_clk}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 2.494
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : mem|ddr4b|ddr4b|arch|arch_inst|non_hps.core_clks_rsts_inst|per_if_cal_slave_reset_sync[9]
|
|
Info (332115): To Node : mem|ddr4b|ddr4b|arch|arch_inst|io_aux_inst|io_aux~soft_ram_reg
|
|
Info (332115): Launch Clock : mem|ddr4a|ddr4a_core_cal_slave_clk
|
|
Info (332115): Latch Clock : mem|ddr4a|ddr4a_core_cal_slave_clk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 7.147 7.147 R clock network delay
|
|
Info (332115): 7.147 0.000 mem|ddr4b|ddr4b|arch|arch_inst|non_hps.core_clks_rsts_inst|per_if_cal_slave_reset_sync[9]
|
|
Info (332115): 7.386 0.239 RR uTco mem|ddr4b|ddr4b|arch|arch_inst|non_hps.core_clks_rsts_inst|per_if_cal_slave_reset_sync[9]|q
|
|
Info (332115): 7.556 0.170 RR CELL High Speed mem|ddr4b|ddr4b|arch|arch_inst|non_hps.core_clks_rsts_inst|per_if_cal_slave_reset_sync[9]~la_mlab/laboutb[8]
|
|
Info (332115): 11.129 3.573 RR IC Mixed mem|ddr4b|ddr4b|arch|arch_inst|io_aux_inst|io_aux|soft_ram_reset_n
|
|
Info (332115): 11.129 0.000 RR CELL mem|ddr4b|ddr4b|arch|arch_inst|io_aux_inst|io_aux~soft_ram_reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 6.566 6.566 latch edge time
|
|
Info (332115): 12.842 6.276 R clock network delay
|
|
Info (332115): 13.779 0.937 clock pessimism removed
|
|
Info (332115): 13.729 -0.050 clock uncertainty
|
|
Info (332115): 13.623 -0.106 uTsu mem|ddr4b|ddr4b|arch|arch_inst|io_aux_inst|io_aux~soft_ram_reg
|
|
Info (332115): Data Arrival Time : 11.129
|
|
Info (332115): Data Required Time : 13.623
|
|
Info (332115): Slack : 2.494
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 2.678
|
|
Info (20696): -to_clock [get_clocks {u0|dcp_iopll|dcp_iopll|clk25}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 2.678
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|c32ui_SystemReset_n
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|tcm_flash_reset_sync_reg[3]
|
|
Info (332115): Launch Clock : u0|dcp_iopll|dcp_iopll|clk1x
|
|
Info (332115): Latch Clock : u0|dcp_iopll|dcp_iopll|clk25
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 35.000 35.000 launch edge time
|
|
Info (332115): 44.726 9.726 R clock network delay
|
|
Info (332115): 44.726 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|c32ui_SystemReset_n
|
|
Info (332115): 44.956 0.230 RR uTco fpga_top|inst_fiu_top|inst_ccip_fabric_top|c32ui_SystemReset_n|q
|
|
Info (332115): 45.075 0.119 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|c32ui_SystemReset_n~la_lab/laboutb[18]
|
|
Info (332115): 46.377 1.302 RR IC Mixed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|tcm_flash_reset_sync_reg[3]|clrn
|
|
Info (332115): 46.377 0.000 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|tcm_flash_reset_sync_reg[3]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 40.000 40.000 latch edge time
|
|
Info (332115): 48.456 8.456 R clock network delay
|
|
Info (332115): 49.379 0.923 clock pessimism removed
|
|
Info (332115): 49.199 -0.180 clock uncertainty
|
|
Info (332115): 49.055 -0.144 uTsu fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|tcm_flash_reset_sync_reg[3]
|
|
Info (332115): Data Arrival Time : 46.377
|
|
Info (332115): Data Required Time : 49.055
|
|
Info (332115): Slack : 2.678
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 2.861
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|rx_pma_clk}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 2.861
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_reset_sync|resync_chains[0].sync_r[2]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_consecutive_error[2]
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|rx_pma_clk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|rx_pma_clk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 7.255 7.255 R clock network delay
|
|
Info (332115): 7.255 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_reset_sync|resync_chains[0].sync_r[2]
|
|
Info (332115): 7.487 0.232 RR uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_reset_sync|resync_chains[0].sync_r[2]|q
|
|
Info (332115): 7.633 0.146 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_reset_sync|resync_chains[0].sync_r[2]~la_mlab/laboutb[5]
|
|
Info (332115): 8.049 0.416 RR IC High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_consecutive_error[2]|clrn
|
|
Info (332115): 8.049 0.000 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_consecutive_error[2]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 3.878 3.878 latch edge time
|
|
Info (332115): 9.049 5.171 R clock network delay
|
|
Info (332115): 11.082 2.033 clock pessimism removed
|
|
Info (332115): 11.052 -0.030 clock uncertainty
|
|
Info (332115): 10.910 -0.142 uTsu fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_consecutive_error[2]
|
|
Info (332115): Data Arrival Time : 8.049
|
|
Info (332115): Data Required Time : 10.910
|
|
Info (332115): Slack : 2.861
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 2.868
|
|
Info (20696): -to_clock [get_clocks {DDR4_RefClk}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 2.868
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|use_counter_lock.counter_lock_gen_master.pll_ref_clk_reset_n_sync_rrr
|
|
Info (332115): To Node : mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|use_counter_lock.counter_lock_gen_master.cpa_count_to_lock[7]
|
|
Info (332115): Launch Clock : DDR4_RefClk
|
|
Info (332115): Latch Clock : DDR4_RefClk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 4.328 4.328 R clock network delay
|
|
Info (332115): 4.328 0.000 mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|use_counter_lock.counter_lock_gen_master.pll_ref_clk_reset_n_sync_rrr
|
|
Info (332115): 4.567 0.239 RR uTco mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|use_counter_lock.counter_lock_gen_master.pll_ref_clk_reset_n_sync_rrr|q
|
|
Info (332115): 4.737 0.170 RR CELL High Speed mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|use_counter_lock.counter_lock_gen_master.pll_ref_clk_reset_n_sync_rrr~la_mlab/laboutb[4]
|
|
Info (332115): 4.987 0.250 RR IC High Speed mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|use_counter_lock.counter_lock_gen_master.cpa_count_to_lock[7]|clrn
|
|
Info (332115): 4.987 0.000 RR CELL High Speed mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|use_counter_lock.counter_lock_gen_master.cpa_count_to_lock[7]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 3.752 3.752 latch edge time
|
|
Info (332115): 7.742 3.990 R clock network delay
|
|
Info (332115): 8.056 0.314 clock pessimism removed
|
|
Info (332115): 8.026 -0.030 clock uncertainty
|
|
Info (332115): 7.855 -0.171 uTsu mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|use_counter_lock.counter_lock_gen_master.cpa_count_to_lock[7]
|
|
Info (332115): Data Arrival Time : 4.987
|
|
Info (332115): Data Required Time : 7.855
|
|
Info (332115): Slack : 2.868
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 2.950
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_clk}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 2.950
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_reset_sync|resync_chains[0].sync_r[2]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_consecutive_error[0]
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_clk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_clk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 7.216 7.216 R clock network delay
|
|
Info (332115): 7.216 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_reset_sync|resync_chains[0].sync_r[2]
|
|
Info (332115): 7.450 0.234 RR uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_reset_sync|resync_chains[0].sync_r[2]|q
|
|
Info (332115): 7.569 0.119 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_reset_sync|resync_chains[0].sync_r[2]~la_lab/laboutb[18]
|
|
Info (332115): 7.928 0.359 RR IC High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_consecutive_error[0]|clrn
|
|
Info (332115): 7.928 0.000 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_consecutive_error[0]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 3.878 3.878 latch edge time
|
|
Info (332115): 9.028 5.150 R clock network delay
|
|
Info (332115): 11.051 2.023 clock pessimism removed
|
|
Info (332115): 11.021 -0.030 clock uncertainty
|
|
Info (332115): 10.878 -0.143 uTsu fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_consecutive_error[0]
|
|
Info (332115): Data Arrival Time : 7.928
|
|
Info (332115): Data Required Time : 10.878
|
|
Info (332115): Slack : 2.950
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 2.952
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|rx_pma_clk}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 2.952
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_reset_sync|resync_chains[0].sync_r[2]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_consecutive_error[3]
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|rx_pma_clk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|rx_pma_clk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 7.156 7.156 R clock network delay
|
|
Info (332115): 7.156 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_reset_sync|resync_chains[0].sync_r[2]
|
|
Info (332115): 7.388 0.232 RR uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_reset_sync|resync_chains[0].sync_r[2]|q
|
|
Info (332115): 7.506 0.118 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_reset_sync|resync_chains[0].sync_r[2]~la_mlab/laboutb[2]
|
|
Info (332115): 7.862 0.356 RR IC High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_consecutive_error[3]|clrn
|
|
Info (332115): 7.862 0.000 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_consecutive_error[3]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 3.878 3.878 latch edge time
|
|
Info (332115): 8.951 5.073 R clock network delay
|
|
Info (332115): 10.985 2.034 clock pessimism removed
|
|
Info (332115): 10.955 -0.030 clock uncertainty
|
|
Info (332115): 10.814 -0.141 uTsu fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_consecutive_error[3]
|
|
Info (332115): Data Arrival Time : 7.862
|
|
Info (332115): Data Required Time : 10.814
|
|
Info (332115): Slack : 2.952
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 3.043
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|rx_pma_clk}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 3.043
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_reset_sync|resync_chains[0].sync_r[2]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_bit_count[2]
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|rx_pma_clk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|rx_pma_clk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 7.203 7.203 R clock network delay
|
|
Info (332115): 7.203 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_reset_sync|resync_chains[0].sync_r[2]
|
|
Info (332115): 7.437 0.234 RR uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_reset_sync|resync_chains[0].sync_r[2]|q
|
|
Info (332115): 7.556 0.119 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_reset_sync|resync_chains[0].sync_r[2]~la_lab/laboutb[18]
|
|
Info (332115): 7.856 0.300 RR IC High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_bit_count[2]|clrn
|
|
Info (332115): 7.856 0.000 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_bit_count[2]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 3.878 3.878 latch edge time
|
|
Info (332115): 9.011 5.133 R clock network delay
|
|
Info (332115): 11.064 2.053 clock pessimism removed
|
|
Info (332115): 11.034 -0.030 clock uncertainty
|
|
Info (332115): 10.899 -0.135 uTsu fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_bit_count[2]
|
|
Info (332115): Data Arrival Time : 7.856
|
|
Info (332115): Data Required Time : 10.899
|
|
Info (332115): Slack : 3.043
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 4.758
|
|
Info (20696): -to_clock [get_clocks {fspi_sclk}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 4.758
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|SPISlaveToAvalonMasterBridge_reset_clk_domain_synch|data_out
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MISOctl|rdshiftreg[5]
|
|
Info (332115): Launch Clock : u0|dcp_iopll|dcp_iopll|clk1x
|
|
Info (332115): Latch Clock : fspi_sclk
|
|
Info (332115): Exception : dcp_bbs.sdc:3056: set_multicycle_path -setup -from [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|SPISlaveToAvalonMasterBridge_reset_clk_domain_synch|data_out}] -to [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MISOctl|*}] 2
|
|
Info (332115): Multicycle - Setup Start : 2
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 240.000 240.000 launch edge time
|
|
Info (332115): 249.705 9.705 R clock network delay
|
|
Info (332115): 249.705 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|SPISlaveToAvalonMasterBridge_reset_clk_domain_synch|data_out
|
|
Info (332115): 249.960 0.255 RR uTco fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|SPISlaveToAvalonMasterBridge_reset_clk_domain_synch|data_out|q
|
|
Info (332115): 250.108 0.148 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|SPISlaveToAvalonMasterBridge_reset_clk_domain_synch|data_out~la_mlab/laboutt[1]
|
|
Info (332115): 250.501 0.393 RR IC High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MOSIctl|i5|dataf
|
|
Info (332115): 250.550 0.049 RF CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MOSIctl|i5|combout
|
|
Info (332115): 250.555 0.005 FF CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MOSIctl|i5~la_mlab/laboutt[18]
|
|
Info (332115): 250.705 0.150 FF IC High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MISOctl|rdshiftreg[5]|clrn
|
|
Info (332115): 250.705 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MISOctl|rdshiftreg[5]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 250.000 250.000 latch edge time
|
|
Info (332115): 255.958 5.958 R clock network delay
|
|
Info (332115): 255.648 -0.310 clock uncertainty
|
|
Info (332115): 255.463 -0.185 uTsu fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MISOctl|rdshiftreg[5]
|
|
Info (332115): Data Arrival Time : 250.705
|
|
Info (332115): Data Required Time : 255.463
|
|
Info (332115): Slack : 4.758
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 5.127
|
|
Info (20696): -to_clock [get_clocks {PCIE_REFCLK}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 5.127
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|reset_pulse_inst|resync_chains[0].sync_r[2]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|cpu_memory[71][31]
|
|
Info (332115): Launch Clock : PCIE_REFCLK
|
|
Info (332115): Latch Clock : PCIE_REFCLK
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 5.719 5.719 R clock network delay
|
|
Info (332115): 5.719 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|reset_pulse_inst|resync_chains[0].sync_r[2]
|
|
Info (332115): 5.989 0.270 RR uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|reset_pulse_inst|resync_chains[0].sync_r[2]|q
|
|
Info (332115): 6.133 0.144 RR CELL Low Power fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|reset_pulse_inst|resync_chains[0].sync_r[2]~la_mlab/laboutb[13]
|
|
Info (332115): 10.236 4.103 RR IC Mixed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|cpu_memory[71][31]|clrn
|
|
Info (332115): 10.236 0.000 RR CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|cpu_memory[71][31]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 10.000 10.000 latch edge time
|
|
Info (332115): 15.146 5.146 R clock network delay
|
|
Info (332115): 15.576 0.430 clock pessimism removed
|
|
Info (332115): 15.536 -0.040 clock uncertainty
|
|
Info (332115): 15.363 -0.173 uTsu fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|cpu_memory[71][31]
|
|
Info (332115): Data Arrival Time : 10.236
|
|
Info (332115): Data Required Time : 15.363
|
|
Info (332115): Slack : 5.127
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 14.223
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|rx_fref}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 14.223
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|rx_fref
|
|
Info (332115): Exception : dcp_bbs.sdc:3148: set_max_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pma_rxpma_rstb}] 20.000
|
|
Info (332115): Max Delay Exception : 20.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 3.896 3.896 R clock network delay
|
|
Info (332115): 3.896 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): 6.947 3.051 RR uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|rx_pma_rstb7
|
|
Info (332115): 6.947 0.000 RR IC fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_pma_rxpma_rstb
|
|
Info (332115): 6.947 0.000 RR CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 20.000 20.000 latch edge time
|
|
Info (332115): 21.840 1.840 R clock network delay
|
|
Info (332115): 21.720 -0.120 clock uncertainty
|
|
Info (332115): 21.170 -0.550 uTsu fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Data Arrival Time : 6.947
|
|
Info (332115): Data Required Time : 21.170
|
|
Info (332115): Slack : 14.223
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 14.760
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|rx_fref}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 14.760
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|rx_fref
|
|
Info (332115): Exception : dcp_bbs.sdc:3148: set_max_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pma_rxpma_rstb}] 20.000
|
|
Info (332115): Max Delay Exception : 20.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 3.896 3.896 R clock network delay
|
|
Info (332115): 3.896 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): 6.410 2.514 RR uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|rx_pma_rstb6
|
|
Info (332115): 6.410 0.000 RR IC fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_pma_rxpma_rstb
|
|
Info (332115): 6.410 0.000 RR CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 20.000 20.000 latch edge time
|
|
Info (332115): 21.840 1.840 R clock network delay
|
|
Info (332115): 21.720 -0.120 clock uncertainty
|
|
Info (332115): 21.170 -0.550 uTsu fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Data Arrival Time : 6.410
|
|
Info (332115): Data Required Time : 21.170
|
|
Info (332115): Slack : 14.760
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 14.882
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|rx_fref}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 14.882
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|rx_fref
|
|
Info (332115): Exception : dcp_bbs.sdc:3148: set_max_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pma_rxpma_rstb}] 20.000
|
|
Info (332115): Max Delay Exception : 20.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 3.896 3.896 R clock network delay
|
|
Info (332115): 3.896 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): 6.288 2.392 RR uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|rx_pma_rstb5
|
|
Info (332115): 6.288 0.000 RR IC fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_pma_rxpma_rstb
|
|
Info (332115): 6.288 0.000 RR CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 20.000 20.000 latch edge time
|
|
Info (332115): 21.840 1.840 R clock network delay
|
|
Info (332115): 21.720 -0.120 clock uncertainty
|
|
Info (332115): 21.170 -0.550 uTsu fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Data Arrival Time : 6.288
|
|
Info (332115): Data Required Time : 21.170
|
|
Info (332115): Slack : 14.882
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 14.897
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|rx_fref}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 14.897
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|rx_fref
|
|
Info (332115): Exception : dcp_bbs.sdc:3148: set_max_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pma_rxpma_rstb}] 20.000
|
|
Info (332115): Max Delay Exception : 20.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 3.896 3.896 R clock network delay
|
|
Info (332115): 3.896 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): 6.156 2.260 RR uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|rx_pma_rstb1
|
|
Info (332115): 6.156 0.000 RR IC fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_pma_rxpma_rstb
|
|
Info (332115): 6.156 0.000 RR CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 20.000 20.000 latch edge time
|
|
Info (332115): 21.723 1.723 R clock network delay
|
|
Info (332115): 21.603 -0.120 clock uncertainty
|
|
Info (332115): 21.053 -0.550 uTsu fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Data Arrival Time : 6.156
|
|
Info (332115): Data Required Time : 21.053
|
|
Info (332115): Slack : 14.897
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 14.926
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|rx_fref}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 14.926
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|rx_fref
|
|
Info (332115): Exception : dcp_bbs.sdc:3148: set_max_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pma_rxpma_rstb}] 20.000
|
|
Info (332115): Max Delay Exception : 20.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 3.896 3.896 R clock network delay
|
|
Info (332115): 3.896 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): 6.181 2.285 RR uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|rx_pma_rstb4
|
|
Info (332115): 6.182 0.001 RR IC fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_pma_rxpma_rstb
|
|
Info (332115): 6.182 0.000 RR CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 20.000 20.000 latch edge time
|
|
Info (332115): 21.778 1.778 R clock network delay
|
|
Info (332115): 21.658 -0.120 clock uncertainty
|
|
Info (332115): 21.108 -0.550 uTsu fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Data Arrival Time : 6.182
|
|
Info (332115): Data Required Time : 21.108
|
|
Info (332115): Slack : 14.926
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 15.202
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|rx_fref}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 15.202
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|rx_fref
|
|
Info (332115): Exception : dcp_bbs.sdc:3148: set_max_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pma_rxpma_rstb}] 20.000
|
|
Info (332115): Max Delay Exception : 20.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 3.896 3.896 R clock network delay
|
|
Info (332115): 3.896 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): 5.906 2.010 RR uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|rx_pma_rstb2
|
|
Info (332115): 5.906 0.000 RR IC fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_pma_rxpma_rstb
|
|
Info (332115): 5.906 0.000 RR CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 20.000 20.000 latch edge time
|
|
Info (332115): 21.778 1.778 R clock network delay
|
|
Info (332115): 21.658 -0.120 clock uncertainty
|
|
Info (332115): 21.108 -0.550 uTsu fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Data Arrival Time : 5.906
|
|
Info (332115): Data Required Time : 21.108
|
|
Info (332115): Slack : 15.202
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 15.221
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|rx_fref}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 15.221
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|rx_fref
|
|
Info (332115): Exception : dcp_bbs.sdc:3148: set_max_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pma_rxpma_rstb}] 20.000
|
|
Info (332115): Max Delay Exception : 20.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 3.896 3.896 R clock network delay
|
|
Info (332115): 3.896 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): 5.887 1.991 RR uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|rx_pma_rstb3
|
|
Info (332115): 5.887 0.000 RR IC fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_pma_rxpma_rstb
|
|
Info (332115): 5.887 0.000 RR CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 20.000 20.000 latch edge time
|
|
Info (332115): 21.778 1.778 R clock network delay
|
|
Info (332115): 21.658 -0.120 clock uncertainty
|
|
Info (332115): 21.108 -0.550 uTsu fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Data Arrival Time : 5.887
|
|
Info (332115): Data Required Time : 21.108
|
|
Info (332115): Slack : 15.221
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 16.104
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|rx_pma_clk}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 16.104
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|rx_pma_clk
|
|
Info (332115): Exception : dcp_bbs.sdc:3148: set_max_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pma_rxpma_rstb}] 20.000
|
|
Info (332115): Max Delay Exception : 20.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 3.896 3.896 R clock network delay
|
|
Info (332115): 3.896 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): 6.947 3.051 RR uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|rx_pma_rstb7
|
|
Info (332115): 6.947 0.000 RR IC fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_pma_rxpma_rstb
|
|
Info (332115): 6.947 0.000 RR CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 20.000 20.000 latch edge time
|
|
Info (332115): 23.171 3.171 R clock network delay
|
|
Info (332115): 23.051 -0.120 clock uncertainty
|
|
Info (332115): 23.051 0.000 uTsu fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Data Arrival Time : 6.947
|
|
Info (332115): Data Required Time : 23.051
|
|
Info (332115): Slack : 16.104
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 16.446
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 16.446
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332115): Exception : dcp_bbs.sdc:3148: set_max_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pma_rxpma_rstb}] 20.000
|
|
Info (332115): Max Delay Exception : 20.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 3.896 3.896 R clock network delay
|
|
Info (332115): 3.896 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): 6.491 2.595 RR uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|rx_pma_rstb0
|
|
Info (332115): 6.492 0.001 RR IC fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_pma_rxpma_rstb
|
|
Info (332115): 6.492 0.000 RR CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 20.000 20.000 latch edge time
|
|
Info (332115): 21.723 1.723 R clock network delay
|
|
Info (332115): 23.518 1.795 clock pessimism removed
|
|
Info (332115): 23.488 -0.030 clock uncertainty
|
|
Info (332115): 22.938 -0.550 uTsu fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Data Arrival Time : 6.492
|
|
Info (332115): Data Required Time : 22.938
|
|
Info (332115): Slack : 16.446
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 16.641
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|rx_pma_clk}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 16.641
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|rx_pma_clk
|
|
Info (332115): Exception : dcp_bbs.sdc:3148: set_max_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pma_rxpma_rstb}] 20.000
|
|
Info (332115): Max Delay Exception : 20.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 3.896 3.896 R clock network delay
|
|
Info (332115): 3.896 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): 6.410 2.514 RR uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|rx_pma_rstb6
|
|
Info (332115): 6.410 0.000 RR IC fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_pma_rxpma_rstb
|
|
Info (332115): 6.410 0.000 RR CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 20.000 20.000 latch edge time
|
|
Info (332115): 23.171 3.171 R clock network delay
|
|
Info (332115): 23.051 -0.120 clock uncertainty
|
|
Info (332115): 23.051 0.000 uTsu fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Data Arrival Time : 6.410
|
|
Info (332115): Data Required Time : 23.051
|
|
Info (332115): Slack : 16.641
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 16.763
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|rx_pma_clk}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 16.763
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|rx_pma_clk
|
|
Info (332115): Exception : dcp_bbs.sdc:3148: set_max_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pma_rxpma_rstb}] 20.000
|
|
Info (332115): Max Delay Exception : 20.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 3.896 3.896 R clock network delay
|
|
Info (332115): 3.896 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): 6.288 2.392 RR uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|rx_pma_rstb5
|
|
Info (332115): 6.288 0.000 RR IC fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_pma_rxpma_rstb
|
|
Info (332115): 6.288 0.000 RR CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 20.000 20.000 latch edge time
|
|
Info (332115): 23.171 3.171 R clock network delay
|
|
Info (332115): 23.051 -0.120 clock uncertainty
|
|
Info (332115): 23.051 0.000 uTsu fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Data Arrival Time : 6.288
|
|
Info (332115): Data Required Time : 23.051
|
|
Info (332115): Slack : 16.763
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 16.776
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_pma_clk}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 16.776
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_pma_clk
|
|
Info (332115): Exception : dcp_bbs.sdc:3148: set_max_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pma_rxpma_rstb}] 20.000
|
|
Info (332115): Max Delay Exception : 20.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 3.896 3.896 R clock network delay
|
|
Info (332115): 3.896 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): 6.491 2.595 RR uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|rx_pma_rstb0
|
|
Info (332115): 6.492 0.001 RR IC fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_pma_rxpma_rstb
|
|
Info (332115): 6.492 0.000 RR CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 20.000 20.000 latch edge time
|
|
Info (332115): 23.054 3.054 R clock network delay
|
|
Info (332115): 23.288 0.234 clock pessimism removed
|
|
Info (332115): 23.268 -0.020 clock uncertainty
|
|
Info (332115): 23.268 0.000 uTsu fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Data Arrival Time : 6.492
|
|
Info (332115): Data Required Time : 23.268
|
|
Info (332115): Slack : 16.776
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 16.778
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|rx_pma_clk}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 16.778
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|rx_pma_clk
|
|
Info (332115): Exception : dcp_bbs.sdc:3148: set_max_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pma_rxpma_rstb}] 20.000
|
|
Info (332115): Max Delay Exception : 20.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 3.896 3.896 R clock network delay
|
|
Info (332115): 3.896 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): 6.156 2.260 RR uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|rx_pma_rstb1
|
|
Info (332115): 6.156 0.000 RR IC fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_pma_rxpma_rstb
|
|
Info (332115): 6.156 0.000 RR CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 20.000 20.000 latch edge time
|
|
Info (332115): 23.054 3.054 R clock network delay
|
|
Info (332115): 22.934 -0.120 clock uncertainty
|
|
Info (332115): 22.934 0.000 uTsu fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Data Arrival Time : 6.156
|
|
Info (332115): Data Required Time : 22.934
|
|
Info (332115): Slack : 16.778
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 16.807
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|rx_pma_clk}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 16.807
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|rx_pma_clk
|
|
Info (332115): Exception : dcp_bbs.sdc:3148: set_max_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pma_rxpma_rstb}] 20.000
|
|
Info (332115): Max Delay Exception : 20.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 3.896 3.896 R clock network delay
|
|
Info (332115): 3.896 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): 6.181 2.285 RR uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|rx_pma_rstb4
|
|
Info (332115): 6.182 0.001 RR IC fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_pma_rxpma_rstb
|
|
Info (332115): 6.182 0.000 RR CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 20.000 20.000 latch edge time
|
|
Info (332115): 23.109 3.109 R clock network delay
|
|
Info (332115): 22.989 -0.120 clock uncertainty
|
|
Info (332115): 22.989 0.000 uTsu fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Data Arrival Time : 6.182
|
|
Info (332115): Data Required Time : 22.989
|
|
Info (332115): Slack : 16.807
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 17.083
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|rx_pma_clk}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 17.083
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|rx_pma_clk
|
|
Info (332115): Exception : dcp_bbs.sdc:3148: set_max_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pma_rxpma_rstb}] 20.000
|
|
Info (332115): Max Delay Exception : 20.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 3.896 3.896 R clock network delay
|
|
Info (332115): 3.896 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): 5.906 2.010 RR uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|rx_pma_rstb2
|
|
Info (332115): 5.906 0.000 RR IC fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_pma_rxpma_rstb
|
|
Info (332115): 5.906 0.000 RR CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 20.000 20.000 latch edge time
|
|
Info (332115): 23.109 3.109 R clock network delay
|
|
Info (332115): 22.989 -0.120 clock uncertainty
|
|
Info (332115): 22.989 0.000 uTsu fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Data Arrival Time : 5.906
|
|
Info (332115): Data Required Time : 22.989
|
|
Info (332115): Slack : 17.083
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 17.102
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|rx_pma_clk}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 17.102
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|rx_pma_clk
|
|
Info (332115): Exception : dcp_bbs.sdc:3148: set_max_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pma_rxpma_rstb}] 20.000
|
|
Info (332115): Max Delay Exception : 20.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 3.896 3.896 R clock network delay
|
|
Info (332115): 3.896 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): 5.887 1.991 RR uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|rx_pma_rstb3
|
|
Info (332115): 5.887 0.000 RR IC fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_pma_rxpma_rstb
|
|
Info (332115): 5.887 0.000 RR CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 20.000 20.000 latch edge time
|
|
Info (332115): 23.109 3.109 R clock network delay
|
|
Info (332115): 22.989 -0.120 clock uncertainty
|
|
Info (332115): 22.989 0.000 uTsu fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Data Arrival Time : 5.887
|
|
Info (332115): Data Required Time : 22.989
|
|
Info (332115): Slack : 17.102
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 40.236
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|tx_pma_clk}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 40.236
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi_txdig_ena
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_tx_pld_pcs_interface.inst_twentynm_hssi_tx_pld_pcs_interface~pld_pmaif_tx_pld_rst_n_reg.reg
|
|
Info (332115): Launch Clock : SYS_RefClk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|tx_pma_clk
|
|
Info (332115): Exception : dcp_bbs.sdc:3144: set_max_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pmaif_tx_pld_rst_n}] 50.000
|
|
Info (332115): Max Delay Exception : 50.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 4.803 4.803 R clock network delay
|
|
Info (332115): 4.803 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi_txdig_ena
|
|
Info (332115): 5.103 0.300 RR uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi_txdig_ena|q
|
|
Info (332115): 5.225 0.122 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi_txdig_ena~la_mlab/laboutb[17]
|
|
Info (332115): 7.773 2.548 RR IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0|datac
|
|
Info (332115): 7.991 0.218 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0|combout
|
|
Info (332115): 7.996 0.005 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0~la_mlab/laboutb[18]
|
|
Info (332115): 11.639 3.643 RR IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_tx_pld_pcs_interface.inst_twentynm_hssi_tx_pld_pcs_interface|pld_pmaif_tx_pld_rst_n
|
|
Info (332115): 11.639 0.000 RR CELL fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_tx_pld_pcs_interface.inst_twentynm_hssi_tx_pld_pcs_interface~pld_pmaif_tx_pld_rst_n_reg.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 50.000 50.000 latch edge time
|
|
Info (332115): 52.291 2.291 R clock network delay
|
|
Info (332115): 52.221 -0.070 clock uncertainty
|
|
Info (332115): 51.875 -0.346 uTsu fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_tx_pld_pcs_interface.inst_twentynm_hssi_tx_pld_pcs_interface~pld_pmaif_tx_pld_rst_n_reg.reg
|
|
Info (332115): Data Arrival Time : 11.639
|
|
Info (332115): Data Required Time : 51.875
|
|
Info (332115): Slack : 40.236
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 40.457
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|tx_pma_clk}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 40.457
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi_txdig_ena
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs~pld_8g_g3_tx_pld_rst_n_reg.reg
|
|
Info (332115): Launch Clock : SYS_RefClk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|tx_pma_clk
|
|
Info (332115): Exception : dcp_bbs.sdc:3145: set_max_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_8g_g3_tx_pld_rst_n}] 50.000
|
|
Info (332115): Max Delay Exception : 50.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 4.803 4.803 R clock network delay
|
|
Info (332115): 4.803 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi_txdig_ena
|
|
Info (332115): 5.103 0.300 RR uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi_txdig_ena|q
|
|
Info (332115): 5.225 0.122 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi_txdig_ena~la_mlab/laboutb[17]
|
|
Info (332115): 7.641 2.416 RR IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0|datac
|
|
Info (332115): 7.859 0.218 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0|combout
|
|
Info (332115): 7.864 0.005 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0~la_mlab/laboutb[18]
|
|
Info (332115): 11.621 3.757 RR IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_tx_pld_pcs_interface.inst_twentynm_hssi_tx_pld_pcs_interface|pld_8g_g3_tx_pld_rst_n
|
|
Info (332115): 11.621 0.000 RR CELL fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs~pld_8g_g3_tx_pld_rst_n_reg.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 50.000 50.000 latch edge time
|
|
Info (332115): 52.322 2.322 R clock network delay
|
|
Info (332115): 52.252 -0.070 clock uncertainty
|
|
Info (332115): 52.078 -0.174 uTsu fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs~pld_8g_g3_tx_pld_rst_n_reg.reg
|
|
Info (332115): Data Arrival Time : 11.621
|
|
Info (332115): Data Required Time : 52.078
|
|
Info (332115): Slack : 40.457
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 40.482
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|tx_pma_clk}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 40.482
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi_txdig_ena
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_tx_pld_pcs_interface.inst_twentynm_hssi_tx_pld_pcs_interface~pld_pmaif_tx_pld_rst_n_reg.reg
|
|
Info (332115): Launch Clock : SYS_RefClk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|tx_pma_clk
|
|
Info (332115): Exception : dcp_bbs.sdc:3144: set_max_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pmaif_tx_pld_rst_n}] 50.000
|
|
Info (332115): Max Delay Exception : 50.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 4.803 4.803 R clock network delay
|
|
Info (332115): 4.803 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi_txdig_ena
|
|
Info (332115): 5.103 0.300 RR uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi_txdig_ena|q
|
|
Info (332115): 5.225 0.122 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi_txdig_ena~la_mlab/laboutb[17]
|
|
Info (332115): 7.554 2.329 RR IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0|datac
|
|
Info (332115): 7.753 0.199 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0|combout
|
|
Info (332115): 7.757 0.004 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0~la_lab/laboutt[8]
|
|
Info (332115): 11.393 3.636 RR IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_tx_pld_pcs_interface.inst_twentynm_hssi_tx_pld_pcs_interface|pld_pmaif_tx_pld_rst_n
|
|
Info (332115): 11.393 0.000 RR CELL fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_tx_pld_pcs_interface.inst_twentynm_hssi_tx_pld_pcs_interface~pld_pmaif_tx_pld_rst_n_reg.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 50.000 50.000 latch edge time
|
|
Info (332115): 52.291 2.291 R clock network delay
|
|
Info (332115): 52.221 -0.070 clock uncertainty
|
|
Info (332115): 51.875 -0.346 uTsu fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_tx_pld_pcs_interface.inst_twentynm_hssi_tx_pld_pcs_interface~pld_pmaif_tx_pld_rst_n_reg.reg
|
|
Info (332115): Data Arrival Time : 11.393
|
|
Info (332115): Data Required Time : 51.875
|
|
Info (332115): Slack : 40.482
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 40.947
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|tx_pma_clk}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 40.947
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi_txdig_ena
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs~pld_8g_g3_tx_pld_rst_n_reg.reg
|
|
Info (332115): Launch Clock : SYS_RefClk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|tx_pma_clk
|
|
Info (332115): Exception : dcp_bbs.sdc:3145: set_max_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_8g_g3_tx_pld_rst_n}] 50.000
|
|
Info (332115): Max Delay Exception : 50.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 4.803 4.803 R clock network delay
|
|
Info (332115): 4.803 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi_txdig_ena
|
|
Info (332115): 5.103 0.300 RR uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi_txdig_ena|q
|
|
Info (332115): 5.225 0.122 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi_txdig_ena~la_mlab/laboutb[17]
|
|
Info (332115): 7.532 2.307 RR IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0|dataa
|
|
Info (332115): 7.873 0.341 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0|combout
|
|
Info (332115): 7.877 0.004 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0~la_lab/laboutb[16]
|
|
Info (332115): 11.131 3.254 RR IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_tx_pld_pcs_interface.inst_twentynm_hssi_tx_pld_pcs_interface|pld_8g_g3_tx_pld_rst_n
|
|
Info (332115): 11.131 0.000 RR CELL fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs~pld_8g_g3_tx_pld_rst_n_reg.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 50.000 50.000 latch edge time
|
|
Info (332115): 52.322 2.322 R clock network delay
|
|
Info (332115): 52.252 -0.070 clock uncertainty
|
|
Info (332115): 52.078 -0.174 uTsu fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs~pld_8g_g3_tx_pld_rst_n_reg.reg
|
|
Info (332115): Data Arrival Time : 11.131
|
|
Info (332115): Data Required Time : 52.078
|
|
Info (332115): Slack : 40.947
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 42.449
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|tx_coreclkin}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 42.449
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi_txdig_ena
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_10g_tx_pcs.inst_twentynm_hssi_10g_tx_pcs~pld_10g_krfec_tx_pld_rst_n_fifo.reg
|
|
Info (332115): Launch Clock : SYS_RefClk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|tx_coreclkin
|
|
Info (332115): Exception : dcp_bbs.sdc:3146: set_max_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_10g_krfec_tx_pld_rst_n}] 50.000
|
|
Info (332115): Max Delay Exception : 50.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 4.803 4.803 R clock network delay
|
|
Info (332115): 4.803 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi_txdig_ena
|
|
Info (332115): 5.103 0.300 RR uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi_txdig_ena|q
|
|
Info (332115): 5.225 0.122 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi_txdig_ena~la_mlab/laboutb[17]
|
|
Info (332115): 7.773 2.548 RR IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0|datac
|
|
Info (332115): 7.991 0.218 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0|combout
|
|
Info (332115): 7.996 0.005 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0~la_mlab/laboutb[18]
|
|
Info (332115): 11.710 3.714 RR IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_tx_pld_pcs_interface.inst_twentynm_hssi_tx_pld_pcs_interface|pld_10g_krfec_tx_pld_rst_n
|
|
Info (332115): 11.710 0.000 RR CELL fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_10g_tx_pcs.inst_twentynm_hssi_10g_tx_pcs~pld_10g_krfec_tx_pld_rst_n_fifo.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 50.000 50.000 latch edge time
|
|
Info (332115): 54.442 4.442 R clock network delay
|
|
Info (332115): 54.402 -0.040 clock uncertainty
|
|
Info (332115): 54.159 -0.243 uTsu fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_10g_tx_pcs.inst_twentynm_hssi_10g_tx_pcs~pld_10g_krfec_tx_pld_rst_n_fifo.reg
|
|
Info (332115): Data Arrival Time : 11.710
|
|
Info (332115): Data Required Time : 54.159
|
|
Info (332115): Slack : 42.449
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 42.863
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|tx_coreclkin}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 42.863
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi_txdig_ena
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_10g_tx_pcs.inst_twentynm_hssi_10g_tx_pcs~pld_10g_krfec_tx_pld_rst_n_fifo.reg
|
|
Info (332115): Launch Clock : SYS_RefClk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|tx_coreclkin
|
|
Info (332115): Exception : dcp_bbs.sdc:3146: set_max_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_10g_krfec_tx_pld_rst_n}] 50.000
|
|
Info (332115): Max Delay Exception : 50.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 4.803 4.803 R clock network delay
|
|
Info (332115): 4.803 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi_txdig_ena
|
|
Info (332115): 5.103 0.300 RR uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi_txdig_ena|q
|
|
Info (332115): 5.225 0.122 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi_txdig_ena~la_mlab/laboutb[17]
|
|
Info (332115): 7.641 2.416 RR IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0|datac
|
|
Info (332115): 7.859 0.218 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0|combout
|
|
Info (332115): 7.864 0.005 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0~la_mlab/laboutb[18]
|
|
Info (332115): 11.407 3.543 RR IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_tx_pld_pcs_interface.inst_twentynm_hssi_tx_pld_pcs_interface|pld_10g_krfec_tx_pld_rst_n
|
|
Info (332115): 11.407 0.000 RR CELL fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_10g_tx_pcs.inst_twentynm_hssi_10g_tx_pcs~pld_10g_krfec_tx_pld_rst_n_fifo.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 50.000 50.000 latch edge time
|
|
Info (332115): 54.553 4.553 R clock network delay
|
|
Info (332115): 54.513 -0.040 clock uncertainty
|
|
Info (332115): 54.270 -0.243 uTsu fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_10g_tx_pcs.inst_twentynm_hssi_10g_tx_pcs~pld_10g_krfec_tx_pld_rst_n_fifo.reg
|
|
Info (332115): Data Arrival Time : 11.407
|
|
Info (332115): Data Required Time : 54.270
|
|
Info (332115): Slack : 42.863
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 42.904
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|tx_coreclkin}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 42.904
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi_txdig_ena
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_10g_tx_pcs.inst_twentynm_hssi_10g_tx_pcs~pld_10g_krfec_tx_pld_rst_n_fifo.reg
|
|
Info (332115): Launch Clock : SYS_RefClk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|tx_coreclkin
|
|
Info (332115): Exception : dcp_bbs.sdc:3146: set_max_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_10g_krfec_tx_pld_rst_n}] 50.000
|
|
Info (332115): Max Delay Exception : 50.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 4.803 4.803 R clock network delay
|
|
Info (332115): 4.803 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi_txdig_ena
|
|
Info (332115): 5.103 0.300 RR uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi_txdig_ena|q
|
|
Info (332115): 5.225 0.122 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi_txdig_ena~la_mlab/laboutb[17]
|
|
Info (332115): 7.554 2.329 RR IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0|datac
|
|
Info (332115): 7.753 0.199 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0|combout
|
|
Info (332115): 7.757 0.004 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0~la_lab/laboutt[8]
|
|
Info (332115): 11.282 3.525 RR IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_tx_pld_pcs_interface.inst_twentynm_hssi_tx_pld_pcs_interface|pld_10g_krfec_tx_pld_rst_n
|
|
Info (332115): 11.282 0.000 RR CELL fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_10g_tx_pcs.inst_twentynm_hssi_10g_tx_pcs~pld_10g_krfec_tx_pld_rst_n_fifo.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 50.000 50.000 latch edge time
|
|
Info (332115): 54.469 4.469 R clock network delay
|
|
Info (332115): 54.429 -0.040 clock uncertainty
|
|
Info (332115): 54.186 -0.243 uTsu fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_10g_tx_pcs.inst_twentynm_hssi_10g_tx_pcs~pld_10g_krfec_tx_pld_rst_n_fifo.reg
|
|
Info (332115): Data Arrival Time : 11.282
|
|
Info (332115): Data Required Time : 54.186
|
|
Info (332115): Slack : 42.904
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 43.017
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|tx_coreclkin}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 43.017
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi_txdig_ena
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_10g_tx_pcs.inst_twentynm_hssi_10g_tx_pcs~pld_10g_krfec_tx_pld_rst_n_fifo.reg
|
|
Info (332115): Launch Clock : SYS_RefClk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|tx_coreclkin
|
|
Info (332115): Exception : dcp_bbs.sdc:3146: set_max_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_10g_krfec_tx_pld_rst_n}] 50.000
|
|
Info (332115): Max Delay Exception : 50.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 4.803 4.803 R clock network delay
|
|
Info (332115): 4.803 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi_txdig_ena
|
|
Info (332115): 5.103 0.300 RR uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi_txdig_ena|q
|
|
Info (332115): 5.225 0.122 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi_txdig_ena~la_mlab/laboutb[17]
|
|
Info (332115): 7.532 2.307 RR IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0|dataa
|
|
Info (332115): 7.873 0.341 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0|combout
|
|
Info (332115): 7.877 0.004 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0~la_lab/laboutb[16]
|
|
Info (332115): 11.131 3.254 RR IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_tx_pld_pcs_interface.inst_twentynm_hssi_tx_pld_pcs_interface|pld_10g_krfec_tx_pld_rst_n
|
|
Info (332115): 11.131 0.000 RR CELL fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_10g_tx_pcs.inst_twentynm_hssi_10g_tx_pcs~pld_10g_krfec_tx_pld_rst_n_fifo.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 50.000 50.000 latch edge time
|
|
Info (332115): 54.431 4.431 R clock network delay
|
|
Info (332115): 54.391 -0.040 clock uncertainty
|
|
Info (332115): 54.148 -0.243 uTsu fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_10g_tx_pcs.inst_twentynm_hssi_10g_tx_pcs~pld_10g_krfec_tx_pld_rst_n_fifo.reg
|
|
Info (332115): Data Arrival Time : 11.131
|
|
Info (332115): Data Required Time : 54.148
|
|
Info (332115): Slack : 43.017
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 97.347
|
|
Info (20696): -to_clock [get_clocks {altera_reserved_tck}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 97.347
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|host_link_jtag|jtag|normal.jtag_dc_streaming|synchronizer|dreg[1]
|
|
Info (332115): To Node : auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|host_link_jtag|jtag|normal.jtag_dc_streaming|jtag_streaming|idle_inserter|received_esc
|
|
Info (332115): Launch Clock : altera_reserved_tck
|
|
Info (332115): Latch Clock : altera_reserved_tck
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 4.344 4.344 R clock network delay
|
|
Info (332115): 4.344 0.000 auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|host_link_jtag|jtag|normal.jtag_dc_streaming|synchronizer|dreg[1]
|
|
Info (332115): 4.592 0.248 RR uTco auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|host_link_jtag|jtag|normal.jtag_dc_streaming|synchronizer|dreg[1]|q
|
|
Info (332115): 4.781 0.189 RR CELL High Speed auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|host_link_jtag|jtag|normal.jtag_dc_streaming|synchronizer|dreg[1]~la_lab/laboutt[0]
|
|
Info (332115): 6.020 1.239 RR IC High Speed auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|host_link_jtag|jtag|normal.jtag_dc_streaming|jtag_streaming|idle_inserter|received_esc|clrn
|
|
Info (332115): 6.020 0.000 RR CELL High Speed auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|host_link_jtag|jtag|normal.jtag_dc_streaming|jtag_streaming|idle_inserter|received_esc
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 100.000 100.000 latch edge time
|
|
Info (332115): 103.347 3.347 R clock network delay
|
|
Info (332115): 103.545 0.198 clock pessimism removed
|
|
Info (332115): 103.515 -0.030 clock uncertainty
|
|
Info (332115): 103.367 -0.148 uTsu auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|host_link_jtag|jtag|normal.jtag_dc_streaming|jtag_streaming|idle_inserter|received_esc
|
|
Info (332115): Data Arrival Time : 6.020
|
|
Info (332115): Data Required Time : 103.367
|
|
Info (332115): Slack : 97.347
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 0.142
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|wys~CORE_CLK_OUT}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 0.142
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|c32ui_SystemReset_n
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_msix_top|msix_brid|msix_dcfifo|fifo_0|dcfifo_component|auto_generated|rdaclr|dffe7a[0]
|
|
Info (332115): Launch Clock : u0|dcp_iopll|dcp_iopll|clk1x
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|wys~CORE_CLK_OUT
|
|
Info (332115): Exception : dcp_bbs.sdc:3071: set_multicycle_path -hold -to [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_msix_top|msix_brid|msix_dcfifo|fifo_0|dcfifo_component|auto_generated|rdaclr|dffe7a[0]}] 1
|
|
Info (332115): Multicycle - Setup Start : 2
|
|
Info (332115): Multicycle - Hold Start : 1
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 8.331 8.331 R clock network delay
|
|
Info (332115): 8.331 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|c32ui_SystemReset_n
|
|
Info (332115): 8.520 0.189 RR uTco fpga_top|inst_fiu_top|inst_ccip_fabric_top|c32ui_SystemReset_n|q
|
|
Info (332115): 8.609 0.089 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|c32ui_SystemReset_n~la_lab/laboutb[18]
|
|
Info (332115): 10.059 1.450 RR IC Mixed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_msix_top|msix_brid|msix_dcfifo|fifo_0|dcfifo_component|auto_generated|rdaclr|dffe7a[0]|clrn
|
|
Info (332115): 10.059 0.000 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_msix_top|msix_brid|msix_dcfifo|fifo_0|dcfifo_component|auto_generated|rdaclr|dffe7a[0]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 9.531 9.531 R clock network delay
|
|
Info (332115): 9.831 0.300 clock uncertainty
|
|
Info (332115): 9.917 0.086 uTh fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_msix_top|msix_brid|msix_dcfifo|fifo_0|dcfifo_component|auto_generated|rdaclr|dffe7a[0]
|
|
Info (332115): Data Arrival Time : 10.059
|
|
Info (332115): Data Required Time : 9.917
|
|
Info (332115): Slack : 0.142
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 0.188
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk1}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 0.188
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[3].core|pipeline|execute|fpu_unit|fpu_fpga|fp_sqrt|[2].reset_relay|reset_r[0]
|
|
Info (332115): To Node : fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[3].core|pipeline|execute|fpu_unit|fpu_fpga|fp_sqrt|[2].fsqrt|mult_1~DATAOUTA0~reg0
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk1
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk1
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 5.386 5.386 R clock network delay
|
|
Info (332115): 5.386 0.000 fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[3].core|pipeline|execute|fpu_unit|fpu_fpga|fp_sqrt|[2].reset_relay|reset_r[0]
|
|
Info (332115): 5.577 0.191 FF uTco fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[3].core|pipeline|execute|fpu_unit|fpu_fpga|fp_sqrt|[2].reset_relay|reset_r[0]|q
|
|
Info (332115): 5.639 0.062 FF CELL High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[3].core|pipeline|execute|fpu_unit|fpu_fpga|fp_sqrt|[2].reset_relay|reset_r[0]~la_mlab/laboutt[9]
|
|
Info (332115): 5.779 0.140 FF IC High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[3].core|pipeline|execute|fpu_unit|fpu_fpga|fp_sqrt|[2].fsqrt|mult_1~DATAOUTA0|aclr[1]
|
|
Info (332115): 5.779 0.000 FF CELL High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[3].core|pipeline|execute|fpu_unit|fpu_fpga|fp_sqrt|[2].fsqrt|mult_1~DATAOUTA0~reg0
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 6.519 6.519 R clock network delay
|
|
Info (332115): 5.403 -1.116 clock pessimism removed
|
|
Info (332115): 5.403 0.000 clock uncertainty
|
|
Info (332115): 5.591 0.188 uTh fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[3].core|pipeline|execute|fpu_unit|fpu_fpga|fp_sqrt|[2].fsqrt|mult_1~DATAOUTA0~reg0
|
|
Info (332115): Data Arrival Time : 5.779
|
|
Info (332115): Data Required Time : 5.591
|
|
Info (332115): Slack : 0.188
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 0.313
|
|
Info (20696): -to_clock [get_clocks {u0|dcp_iopll|dcp_iopll|clk1x}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 0.313
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|rdaclr|dffe7a[0]
|
|
Info (332115): To Node : fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|fifo_ram|ram_block7a591~reg1
|
|
Info (332115): Launch Clock : u0|dcp_iopll|dcp_iopll|clk1x
|
|
Info (332115): Latch Clock : u0|dcp_iopll|dcp_iopll|clk1x
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 8.294 8.294 R clock network delay
|
|
Info (332115): 8.294 0.000 fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|rdaclr|dffe7a[0]
|
|
Info (332115): 8.491 0.197 RR uTco fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|rdaclr|dffe7a[0]|q
|
|
Info (332115): 8.588 0.097 RR CELL High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|rdaclr|dffe7a[0]~la_lab/laboutt[5]
|
|
Info (332115): 8.763 0.175 RR IC High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|fifo_ram|ram_block7a591|clr1
|
|
Info (332115): 8.763 0.000 RR CELL High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|fifo_ram|ram_block7a591~reg1
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 9.671 9.671 R clock network delay
|
|
Info (332115): 8.298 -1.373 clock pessimism removed
|
|
Info (332115): 8.298 0.000 clock uncertainty
|
|
Info (332115): 8.450 0.152 uTh fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|fifo_ram|ram_block7a591~reg1
|
|
Info (332115): Data Arrival Time : 8.763
|
|
Info (332115): Data Required Time : 8.450
|
|
Info (332115): Slack : 0.313
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 0.325
|
|
Info (20696): -to_clock [get_clocks {SYS_RefClk}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 0.325
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].avmm_reset_sync_inst|resync_chains[0].sync_r[1]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_read_r[0]
|
|
Info (332115): Launch Clock : SYS_RefClk
|
|
Info (332115): Latch Clock : SYS_RefClk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 4.364 4.364 R clock network delay
|
|
Info (332115): 4.364 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].avmm_reset_sync_inst|resync_chains[0].sync_r[1]
|
|
Info (332115): 4.552 0.188 RR uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].avmm_reset_sync_inst|resync_chains[0].sync_r[1]|q
|
|
Info (332115): 4.646 0.094 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].avmm_reset_sync_inst|resync_chains[0].sync_r[1]~la_lab/laboutb[14]
|
|
Info (332115): 4.790 0.144 RR IC High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_read_r[0]|clrn
|
|
Info (332115): 4.790 0.000 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_read_r[0]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 4.774 4.774 R clock network delay
|
|
Info (332115): 4.385 -0.389 clock pessimism removed
|
|
Info (332115): 4.385 0.000 clock uncertainty
|
|
Info (332115): 4.465 0.080 uTh fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_read_r[0]
|
|
Info (332115): Data Arrival Time : 4.790
|
|
Info (332115): Data Required Time : 4.465
|
|
Info (332115): Slack : 0.325
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 0.340
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_clk}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 0.340
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_reset_sync|resync_chains[0].sync_r[2]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_snapshot[6]
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_clk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_clk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 5.147 5.147 R clock network delay
|
|
Info (332115): 5.147 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_reset_sync|resync_chains[0].sync_r[2]
|
|
Info (332115): 5.339 0.192 RR uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_reset_sync|resync_chains[0].sync_r[2]|q
|
|
Info (332115): 5.428 0.089 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_reset_sync|resync_chains[0].sync_r[2]~la_lab/laboutb[18]
|
|
Info (332115): 5.595 0.167 RR IC High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_snapshot[6]|clrn
|
|
Info (332115): 5.595 0.000 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_snapshot[6]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 7.217 7.217 R clock network delay
|
|
Info (332115): 5.168 -2.049 clock pessimism removed
|
|
Info (332115): 5.168 0.000 clock uncertainty
|
|
Info (332115): 5.255 0.087 uTh fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_snapshot[6]
|
|
Info (332115): Data Arrival Time : 5.595
|
|
Info (332115): Data Required Time : 5.255
|
|
Info (332115): Slack : 0.340
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 0.342
|
|
Info (20696): -to_clock [get_clocks {mem|ddr4a|ddr4a_core_usr_clk}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 0.342
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|reset_sync_pri_sdc_anchor
|
|
Info (332115): To Node : mem|ddr4a|ddr4a|arch|arch_inst|seq_if_inst|afi_cal_fail_sync_inst|dreg[0]
|
|
Info (332115): Launch Clock : mem|ddr4a|ddr4a_core_usr_clk
|
|
Info (332115): Latch Clock : mem|ddr4a|ddr4a_core_usr_clk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.117 0.117 launch edge time
|
|
Info (332115): 2.931 2.814 R clock network delay
|
|
Info (332115): 2.931 0.000 mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|reset_sync_pri_sdc_anchor
|
|
Info (332115): 3.122 0.191 RR uTco mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|reset_sync_pri_sdc_anchor|q
|
|
Info (332115): 3.219 0.097 RR CELL High Speed mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|reset_sync_pri_sdc_anchor~la_mlab/laboutb[13]
|
|
Info (332115): 3.381 0.162 RR IC High Speed mem|ddr4a|ddr4a|arch|arch_inst|seq_if_inst|afi_cal_fail_sync_inst|dreg[0]|clrn
|
|
Info (332115): 3.381 0.000 RR CELL High Speed mem|ddr4a|ddr4a|arch|arch_inst|seq_if_inst|afi_cal_fail_sync_inst|dreg[0]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.117 0.117 latch edge time
|
|
Info (332115): 3.842 3.725 R clock network delay
|
|
Info (332115): 2.950 -0.892 clock pessimism removed
|
|
Info (332115): 2.950 0.000 clock uncertainty
|
|
Info (332115): 3.039 0.089 uTh mem|ddr4a|ddr4a|arch|arch_inst|seq_if_inst|afi_cal_fail_sync_inst|dreg[0]
|
|
Info (332115): Data Arrival Time : 3.381
|
|
Info (332115): Data Required Time : 3.039
|
|
Info (332115): Slack : 0.342
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 0.356
|
|
Info (20696): -to_clock [get_clocks {u0|dcp_iopll|dcp_iopll|clk100}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 0.356
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|tcm_control_out|pio_0|data_out[0]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_003|async_clock_crosser.clock_xer|out_data_buffer[29]
|
|
Info (332115): Launch Clock : u0|dcp_iopll|dcp_iopll|clk1x
|
|
Info (332115): Latch Clock : u0|dcp_iopll|dcp_iopll|clk100
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 8.313 8.313 R clock network delay
|
|
Info (332115): 8.313 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|tcm_control_out|pio_0|data_out[0]
|
|
Info (332115): 8.531 0.218 FF uTco fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|tcm_control_out|pio_0|data_out[0]|q
|
|
Info (332115): 8.602 0.071 FF CELL Low Power fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|tcm_control_out|pio_0|data_out[0]~la_lab/laboutt[17]
|
|
Info (332115): 9.438 0.836 FF IC Mixed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_003|async_clock_crosser.clock_xer|out_data_buffer[29]|clrn
|
|
Info (332115): 9.438 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_003|async_clock_crosser.clock_xer|out_data_buffer[29]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 9.762 9.762 R clock network delay
|
|
Info (332115): 8.839 -0.923 clock pessimism removed
|
|
Info (332115): 8.999 0.160 clock uncertainty
|
|
Info (332115): 9.082 0.083 uTh fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_003|async_clock_crosser.clock_xer|out_data_buffer[29]
|
|
Info (332115): Data Arrival Time : 9.438
|
|
Info (332115): Data Required Time : 9.082
|
|
Info (332115): Slack : 0.356
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 0.370
|
|
Info (20696): -to_clock [get_clocks {PCIE_REFCLK}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 0.370
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].avmm_reset_sync_inst|resync_chains[0].sync_r[1]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_read_cycles_cnt[1]
|
|
Info (332115): Launch Clock : PCIE_REFCLK
|
|
Info (332115): Latch Clock : PCIE_REFCLK
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 5.108 5.108 R clock network delay
|
|
Info (332115): 5.108 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].avmm_reset_sync_inst|resync_chains[0].sync_r[1]
|
|
Info (332115): 5.297 0.189 RR uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].avmm_reset_sync_inst|resync_chains[0].sync_r[1]|q
|
|
Info (332115): 5.391 0.094 RR CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].avmm_reset_sync_inst|resync_chains[0].sync_r[1]~la_lab/laboutt[10]
|
|
Info (332115): 5.551 0.160 RR IC High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_read_cycles_cnt[1]|clrn
|
|
Info (332115): 5.551 0.000 RR CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_read_cycles_cnt[1]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 5.693 5.693 R clock network delay
|
|
Info (332115): 5.108 -0.585 clock pessimism removed
|
|
Info (332115): 5.108 0.000 clock uncertainty
|
|
Info (332115): 5.181 0.073 uTh fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_read_cycles_cnt[1]
|
|
Info (332115): Data Arrival Time : 5.551
|
|
Info (332115): Data Required Time : 5.181
|
|
Info (332115): Slack : 0.370
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 0.381
|
|
Info (20696): -to_clock [get_clocks {mem|ddr4a|ddr4a_core_cal_slave_clk}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 0.381
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : mem|ddr4b|ddr4b|cal_slave_component|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out
|
|
Info (332115): To Node : mem|ddr4b|ddr4b|cal_slave_component|ioaux_master_bridge|wr_reg_write
|
|
Info (332115): Launch Clock : mem|ddr4a|ddr4a_core_cal_slave_clk
|
|
Info (332115): Latch Clock : mem|ddr4a|ddr4a_core_cal_slave_clk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 6.053 6.053 R clock network delay
|
|
Info (332115): 6.053 0.000 mem|ddr4b|ddr4b|cal_slave_component|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out
|
|
Info (332115): 6.252 0.199 RR uTco mem|ddr4b|ddr4b|cal_slave_component|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out|q
|
|
Info (332115): 6.386 0.134 RR CELL High Speed mem|ddr4b|ddr4b|cal_slave_component|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~la_mlab/laboutb[11]
|
|
Info (332115): 6.531 0.145 RR IC High Speed mem|ddr4b|ddr4b|cal_slave_component|ioaux_master_bridge|wr_reg_write|clrn
|
|
Info (332115): 6.531 0.000 RR CELL High Speed mem|ddr4b|ddr4b|cal_slave_component|ioaux_master_bridge|wr_reg_write
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 7.147 7.147 R clock network delay
|
|
Info (332115): 6.052 -1.095 clock pessimism removed
|
|
Info (332115): 6.052 0.000 clock uncertainty
|
|
Info (332115): 6.150 0.098 uTh mem|ddr4b|ddr4b|cal_slave_component|ioaux_master_bridge|wr_reg_write
|
|
Info (332115): Data Arrival Time : 6.531
|
|
Info (332115): Data Required Time : 6.150
|
|
Info (332115): Slack : 0.381
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 0.402
|
|
Info (20696): -to_clock [get_clocks {DDR4_RefClk}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 0.402
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|use_counter_lock.counter_lock_gen_master.pll_ref_clk_reset_n_sync_rrr
|
|
Info (332115): To Node : mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|use_counter_lock.counter_lock_gen_master.cpa_count_to_lock[16]~LRTM_3
|
|
Info (332115): Launch Clock : DDR4_RefClk
|
|
Info (332115): Latch Clock : DDR4_RefClk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 3.994 3.994 R clock network delay
|
|
Info (332115): 3.994 0.000 mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|use_counter_lock.counter_lock_gen_master.pll_ref_clk_reset_n_sync_rrr
|
|
Info (332115): 4.193 0.199 RR uTco mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|use_counter_lock.counter_lock_gen_master.pll_ref_clk_reset_n_sync_rrr|q
|
|
Info (332115): 4.322 0.129 RR CELL High Speed mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|use_counter_lock.counter_lock_gen_master.pll_ref_clk_reset_n_sync_rrr~la_mlab/laboutb[4]
|
|
Info (332115): 4.470 0.148 RR IC High Speed mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|use_counter_lock.counter_lock_gen_master.cpa_count_to_lock[16]~LRTM_3|clrn
|
|
Info (332115): 4.470 0.000 RR CELL High Speed mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|use_counter_lock.counter_lock_gen_master.cpa_count_to_lock[16]~LRTM_3
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 4.328 4.328 R clock network delay
|
|
Info (332115): 3.993 -0.335 clock pessimism removed
|
|
Info (332115): 3.993 0.000 clock uncertainty
|
|
Info (332115): 4.068 0.075 uTh mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|use_counter_lock.counter_lock_gen_master.cpa_count_to_lock[16]~LRTM_3
|
|
Info (332115): Data Arrival Time : 4.470
|
|
Info (332115): Data Required Time : 4.068
|
|
Info (332115): Slack : 0.402
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 0.411
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|rx_pma_clk}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 0.411
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_reset_sync|resync_chains[0].sync_r[2]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_snapshot[2]
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|rx_pma_clk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|rx_pma_clk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 5.131 5.131 R clock network delay
|
|
Info (332115): 5.131 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_reset_sync|resync_chains[0].sync_r[2]
|
|
Info (332115): 5.323 0.192 RR uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_reset_sync|resync_chains[0].sync_r[2]|q
|
|
Info (332115): 5.412 0.089 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_reset_sync|resync_chains[0].sync_r[2]~la_lab/laboutb[18]
|
|
Info (332115): 5.674 0.262 RR IC High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_snapshot[2]|clrn
|
|
Info (332115): 5.674 0.000 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_snapshot[2]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 7.206 7.206 R clock network delay
|
|
Info (332115): 5.153 -2.053 clock pessimism removed
|
|
Info (332115): 5.153 0.000 clock uncertainty
|
|
Info (332115): 5.263 0.110 uTh fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_snapshot[2]
|
|
Info (332115): Data Arrival Time : 5.674
|
|
Info (332115): Data Required Time : 5.263
|
|
Info (332115): Slack : 0.411
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 0.427
|
|
Info (20696): -to_clock [get_clocks {u0|dcp_iopll|dcp_iopll|clk25}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 0.427
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|c32ui_SystemReset_n
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|tcm_flash_reset_sync_reg[0]
|
|
Info (332115): Launch Clock : u0|dcp_iopll|dcp_iopll|clk1x
|
|
Info (332115): Latch Clock : u0|dcp_iopll|dcp_iopll|clk25
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 8.331 8.331 R clock network delay
|
|
Info (332115): 8.331 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|c32ui_SystemReset_n
|
|
Info (332115): 8.520 0.189 RR uTco fpga_top|inst_fiu_top|inst_ccip_fabric_top|c32ui_SystemReset_n|q
|
|
Info (332115): 8.609 0.089 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|c32ui_SystemReset_n~la_lab/laboutb[18]
|
|
Info (332115): 9.685 1.076 RR IC Mixed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|tcm_flash_reset_sync_reg[0]|clrn
|
|
Info (332115): 9.685 0.000 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|tcm_flash_reset_sync_reg[0]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 9.913 9.913 R clock network delay
|
|
Info (332115): 8.990 -0.923 clock pessimism removed
|
|
Info (332115): 9.170 0.180 clock uncertainty
|
|
Info (332115): 9.258 0.088 uTh fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|tcm_flash_reset_sync_reg[0]
|
|
Info (332115): Data Arrival Time : 9.685
|
|
Info (332115): Data Required Time : 9.258
|
|
Info (332115): Slack : 0.427
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 0.434
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|rx_pma_clk}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 0.434
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_reset_sync|resync_chains[0].sync_r[2]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_snapshot[5]
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|rx_pma_clk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|rx_pma_clk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 5.073 5.073 R clock network delay
|
|
Info (332115): 5.073 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_reset_sync|resync_chains[0].sync_r[2]
|
|
Info (332115): 5.265 0.192 RR uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_reset_sync|resync_chains[0].sync_r[2]|q
|
|
Info (332115): 5.354 0.089 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_reset_sync|resync_chains[0].sync_r[2]~la_mlab/laboutb[2]
|
|
Info (332115): 5.648 0.294 RR IC High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_snapshot[5]|clrn
|
|
Info (332115): 5.648 0.000 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_snapshot[5]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 7.157 7.157 R clock network delay
|
|
Info (332115): 5.123 -2.034 clock pessimism removed
|
|
Info (332115): 5.123 0.000 clock uncertainty
|
|
Info (332115): 5.214 0.091 uTh fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_snapshot[5]
|
|
Info (332115): Data Arrival Time : 5.648
|
|
Info (332115): Data Required Time : 5.214
|
|
Info (332115): Slack : 0.434
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 0.461
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|rx_pma_clk}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 0.461
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_reset_sync|resync_chains[0].sync_r[2]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_bit_count[1]
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|rx_pma_clk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|rx_pma_clk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 5.175 5.175 R clock network delay
|
|
Info (332115): 5.175 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_reset_sync|resync_chains[0].sync_r[2]
|
|
Info (332115): 5.367 0.192 RR uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_reset_sync|resync_chains[0].sync_r[2]|q
|
|
Info (332115): 5.464 0.097 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_reset_sync|resync_chains[0].sync_r[2]~la_mlab/laboutb[5]
|
|
Info (332115): 5.768 0.304 RR IC High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_bit_count[1]|clrn
|
|
Info (332115): 5.768 0.000 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_bit_count[1]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 7.246 7.246 R clock network delay
|
|
Info (332115): 5.213 -2.033 clock pessimism removed
|
|
Info (332115): 5.213 0.000 clock uncertainty
|
|
Info (332115): 5.307 0.094 uTh fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_bit_count[1]
|
|
Info (332115): Data Arrival Time : 5.768
|
|
Info (332115): Data Required Time : 5.307
|
|
Info (332115): Slack : 0.461
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 0.867
|
|
Info (20696): -to_clock [get_clocks {altera_reserved_tck}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 0.867
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|host_link_jtag|jtag|normal.jtag_dc_streaming|synchronizer|dreg[1]
|
|
Info (332115): To Node : auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|host_link_jtag|jtag|normal.jtag_dc_streaming|sink_crosser|in_to_out_synchronizer|dreg[1]
|
|
Info (332115): Launch Clock : altera_reserved_tck
|
|
Info (332115): Latch Clock : altera_reserved_tck
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 3.538 3.538 R clock network delay
|
|
Info (332115): 3.538 0.000 auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|host_link_jtag|jtag|normal.jtag_dc_streaming|synchronizer|dreg[1]
|
|
Info (332115): 3.741 0.203 RR uTco auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|host_link_jtag|jtag|normal.jtag_dc_streaming|synchronizer|dreg[1]|q
|
|
Info (332115): 3.874 0.133 RR CELL High Speed auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|host_link_jtag|jtag|normal.jtag_dc_streaming|synchronizer|dreg[1]~la_lab/laboutt[0]
|
|
Info (332115): 4.519 0.645 RR IC High Speed auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|host_link_jtag|jtag|normal.jtag_dc_streaming|sink_crosser|in_to_out_synchronizer|dreg[1]|clrn
|
|
Info (332115): 4.519 0.000 RR CELL High Speed auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|host_link_jtag|jtag|normal.jtag_dc_streaming|sink_crosser|in_to_out_synchronizer|dreg[1]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 4.344 4.344 R clock network delay
|
|
Info (332115): 3.544 -0.800 clock pessimism removed
|
|
Info (332115): 3.544 0.000 clock uncertainty
|
|
Info (332115): 3.652 0.108 uTh auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|host_link_jtag|jtag|normal.jtag_dc_streaming|sink_crosser|in_to_out_synchronizer|dreg[1]
|
|
Info (332115): Data Arrival Time : 4.519
|
|
Info (332115): Data Required Time : 3.652
|
|
Info (332115): Slack : 0.867
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 1.793
|
|
Info (20696): -to_clock [get_clocks {fspi_sclk}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 1.793
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|SPISlaveToAvalonMasterBridge_reset_clk_domain_synch|data_out
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MISOctl|loadstsinkdata
|
|
Info (332115): Launch Clock : u0|dcp_iopll|dcp_iopll|clk1x
|
|
Info (332115): Latch Clock : fspi_sclk
|
|
Info (332115): Exception : dcp_bbs.sdc:3057: set_multicycle_path -hold -from [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|SPISlaveToAvalonMasterBridge_reset_clk_domain_synch|data_out}] -to [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MISOctl|*}] 1
|
|
Info (332115): Multicycle - Setup Start : 2
|
|
Info (332115): Multicycle - Hold Start : 1
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 8.311 8.311 R clock network delay
|
|
Info (332115): 8.311 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|SPISlaveToAvalonMasterBridge_reset_clk_domain_synch|data_out
|
|
Info (332115): 8.523 0.212 RR uTco fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|SPISlaveToAvalonMasterBridge_reset_clk_domain_synch|data_out|q
|
|
Info (332115): 8.620 0.097 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|SPISlaveToAvalonMasterBridge_reset_clk_domain_synch|data_out~la_mlab/laboutt[1]
|
|
Info (332115): 8.962 0.342 RR IC High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MOSIctl|i5|dataf
|
|
Info (332115): 8.999 0.037 RF CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MOSIctl|i5|combout
|
|
Info (332115): 9.001 0.002 FF CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MOSIctl|i5~la_mlab/laboutt[19]
|
|
Info (332115): 9.123 0.122 FF IC High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MISOctl|loadstsinkdata|clrn
|
|
Info (332115): 9.123 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MISOctl|loadstsinkdata
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 6.940 6.940 R clock network delay
|
|
Info (332115): 7.250 0.310 clock uncertainty
|
|
Info (332115): 7.330 0.080 uTh fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MISOctl|loadstsinkdata
|
|
Info (332115): Data Arrival Time : 9.123
|
|
Info (332115): Data Required Time : 7.330
|
|
Info (332115): Slack : 1.793
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 4.837
|
|
Info (20696): -to_clock [get_clocks {filtered_sclk_negedge}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 4.837
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MOSIctl|sync_spi_reset|dreg[0]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MOSIctl|sclkpedgecounter[1]
|
|
Info (332115): Launch Clock : u0|dcp_iopll|dcp_iopll|clk1x
|
|
Info (332115): Latch Clock : filtered_sclk_negedge
|
|
Info (332115): Exception : dcp_bbs.sdc:3063: set_multicycle_path -hold -from [get_keepers {*sync_spi_reset|dreg*}] -to [get_keepers {*SPIPhy_MOSIctl|sclkpedgecounter*}] 1
|
|
Info (332115): Multicycle - Setup Start : 3
|
|
Info (332115): Multicycle - Hold Start : 1
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 245.000 245.000 launch edge time
|
|
Info (332115): 253.309 8.309 R clock network delay
|
|
Info (332115): 253.309 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MOSIctl|sync_spi_reset|dreg[0]
|
|
Info (332115): 253.520 0.211 RR uTco fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MOSIctl|sync_spi_reset|dreg[0]|q
|
|
Info (332115): 253.609 0.089 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MOSIctl|sync_spi_reset|dreg[0]~la_mlab/laboutt[6]
|
|
Info (332115): 255.523 1.914 RR IC High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MOSIctl|sclkpedgecounter[1]|clrn
|
|
Info (332115): 255.523 0.000 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MOSIctl|sclkpedgecounter[1]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 250.000 250.000 latch edge time
|
|
Info (332115): 250.275 0.275 R clock network delay
|
|
Info (332115): 250.575 0.300 clock uncertainty
|
|
Info (332115): 250.686 0.111 uTh fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MOSIctl|sclkpedgecounter[1]
|
|
Info (332115): Data Arrival Time : 255.523
|
|
Info (332115): Data Required Time : 250.686
|
|
Info (332115): Slack : 4.837
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 8.547
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|rx_pma_clk}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 8.547
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|rx_pma_clk
|
|
Info (332115): Exception : dcp_bbs.sdc:3195: set_min_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pma_rxpma_rstb}] -10.000
|
|
Info (332115): Min Delay Exception : -10.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 2.007 2.007 R clock network delay
|
|
Info (332115): 2.007 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): 3.579 1.572 FF uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|rx_pma_rstb2
|
|
Info (332115): 3.579 0.000 FF IC fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_pma_rxpma_rstb
|
|
Info (332115): 3.579 0.000 FF CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): -10.000 -10.000 latch edge time
|
|
Info (332115): -5.088 4.912 R clock network delay
|
|
Info (332115): -4.968 0.120 clock uncertainty
|
|
Info (332115): -4.968 0.000 uTh fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Data Arrival Time : 3.579
|
|
Info (332115): Data Required Time : -4.968
|
|
Info (332115): Slack : 8.547
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 8.547
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|rx_pma_clk}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 8.547
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|rx_pma_clk
|
|
Info (332115): Exception : dcp_bbs.sdc:3195: set_min_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pma_rxpma_rstb}] -10.000
|
|
Info (332115): Min Delay Exception : -10.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 2.007 2.007 R clock network delay
|
|
Info (332115): 2.007 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): 3.579 1.572 FF uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|rx_pma_rstb3
|
|
Info (332115): 3.579 0.000 FF IC fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_pma_rxpma_rstb
|
|
Info (332115): 3.579 0.000 FF CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): -10.000 -10.000 latch edge time
|
|
Info (332115): -5.088 4.912 R clock network delay
|
|
Info (332115): -4.968 0.120 clock uncertainty
|
|
Info (332115): -4.968 0.000 uTh fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Data Arrival Time : 3.579
|
|
Info (332115): Data Required Time : -4.968
|
|
Info (332115): Slack : 8.547
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 8.844
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|rx_pma_clk}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 8.844
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|rx_pma_clk
|
|
Info (332115): Exception : dcp_bbs.sdc:3195: set_min_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pma_rxpma_rstb}] -10.000
|
|
Info (332115): Min Delay Exception : -10.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 2.007 2.007 R clock network delay
|
|
Info (332115): 2.007 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): 3.875 1.868 FF uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|rx_pma_rstb4
|
|
Info (332115): 3.876 0.001 FF IC fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_pma_rxpma_rstb
|
|
Info (332115): 3.876 0.000 FF CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): -10.000 -10.000 latch edge time
|
|
Info (332115): -5.088 4.912 R clock network delay
|
|
Info (332115): -4.968 0.120 clock uncertainty
|
|
Info (332115): -4.968 0.000 uTh fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Data Arrival Time : 3.876
|
|
Info (332115): Data Required Time : -4.968
|
|
Info (332115): Slack : 8.844
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 8.875
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|rx_pma_clk}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 8.875
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|rx_pma_clk
|
|
Info (332115): Exception : dcp_bbs.sdc:3195: set_min_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pma_rxpma_rstb}] -10.000
|
|
Info (332115): Min Delay Exception : -10.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 2.007 2.007 R clock network delay
|
|
Info (332115): 2.007 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): 3.985 1.978 FF uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|rx_pma_rstb5
|
|
Info (332115): 3.985 0.000 FF IC fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_pma_rxpma_rstb
|
|
Info (332115): 3.985 0.000 FF CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): -10.000 -10.000 latch edge time
|
|
Info (332115): -5.010 4.990 R clock network delay
|
|
Info (332115): -4.890 0.120 clock uncertainty
|
|
Info (332115): -4.890 0.000 uTh fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Data Arrival Time : 3.985
|
|
Info (332115): Data Required Time : -4.890
|
|
Info (332115): Slack : 8.875
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 8.896
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|rx_pma_clk}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 8.896
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|rx_pma_clk
|
|
Info (332115): Exception : dcp_bbs.sdc:3195: set_min_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pma_rxpma_rstb}] -10.000
|
|
Info (332115): Min Delay Exception : -10.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 2.007 2.007 R clock network delay
|
|
Info (332115): 2.007 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): 3.836 1.829 FF uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|rx_pma_rstb1
|
|
Info (332115): 3.836 0.000 FF IC fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_pma_rxpma_rstb
|
|
Info (332115): 3.836 0.000 FF CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): -10.000 -10.000 latch edge time
|
|
Info (332115): -5.180 4.820 R clock network delay
|
|
Info (332115): -5.060 0.120 clock uncertainty
|
|
Info (332115): -5.060 0.000 uTh fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Data Arrival Time : 3.836
|
|
Info (332115): Data Required Time : -5.060
|
|
Info (332115): Slack : 8.896
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 8.952
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|rx_pma_clk}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 8.952
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|rx_pma_clk
|
|
Info (332115): Exception : dcp_bbs.sdc:3195: set_min_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pma_rxpma_rstb}] -10.000
|
|
Info (332115): Min Delay Exception : -10.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 2.007 2.007 R clock network delay
|
|
Info (332115): 2.007 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): 4.062 2.055 FF uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|rx_pma_rstb6
|
|
Info (332115): 4.062 0.000 FF IC fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_pma_rxpma_rstb
|
|
Info (332115): 4.062 0.000 FF CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): -10.000 -10.000 latch edge time
|
|
Info (332115): -5.010 4.990 R clock network delay
|
|
Info (332115): -4.890 0.120 clock uncertainty
|
|
Info (332115): -4.890 0.000 uTh fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Data Arrival Time : 4.062
|
|
Info (332115): Data Required Time : -4.890
|
|
Info (332115): Slack : 8.952
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 9.486
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|rx_pma_clk}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 9.486
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|rx_pma_clk
|
|
Info (332115): Exception : dcp_bbs.sdc:3195: set_min_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pma_rxpma_rstb}] -10.000
|
|
Info (332115): Min Delay Exception : -10.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 2.007 2.007 R clock network delay
|
|
Info (332115): 2.007 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): 4.596 2.589 FF uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|rx_pma_rstb7
|
|
Info (332115): 4.596 0.000 FF IC fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_pma_rxpma_rstb
|
|
Info (332115): 4.596 0.000 FF CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): -10.000 -10.000 latch edge time
|
|
Info (332115): -5.010 4.990 R clock network delay
|
|
Info (332115): -4.890 0.120 clock uncertainty
|
|
Info (332115): -4.890 0.000 uTh fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Data Arrival Time : 4.596
|
|
Info (332115): Data Required Time : -4.890
|
|
Info (332115): Slack : 9.486
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 9.513
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_pma_clk}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 9.513
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_pma_clk
|
|
Info (332115): Exception : dcp_bbs.sdc:3195: set_min_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pma_rxpma_rstb}] -10.000
|
|
Info (332115): Min Delay Exception : -10.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 2.007 2.007 R clock network delay
|
|
Info (332115): 2.007 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): 4.119 2.112 FF uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|rx_pma_rstb0
|
|
Info (332115): 4.119 0.000 FF IC fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_pma_rxpma_rstb
|
|
Info (332115): 4.119 0.000 FF CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): -10.000 -10.000 latch edge time
|
|
Info (332115): -5.180 4.820 R clock network delay
|
|
Info (332115): -5.414 -0.234 clock pessimism removed
|
|
Info (332115): -5.394 0.020 clock uncertainty
|
|
Info (332115): -5.394 0.000 uTh fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Data Arrival Time : 4.119
|
|
Info (332115): Data Required Time : -5.394
|
|
Info (332115): Slack : 9.513
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 10.242
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|rx_fref}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 10.242
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|rx_fref
|
|
Info (332115): Exception : dcp_bbs.sdc:3195: set_min_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pma_rxpma_rstb}] -10.000
|
|
Info (332115): Min Delay Exception : -10.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 2.007 2.007 R clock network delay
|
|
Info (332115): 2.007 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): 3.693 1.686 RR uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|rx_pma_rstb3
|
|
Info (332115): 3.693 0.000 RR IC fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_pma_rxpma_rstb
|
|
Info (332115): 3.693 0.000 RR CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): -10.000 -10.000 latch edge time
|
|
Info (332115): -6.390 3.610 R clock network delay
|
|
Info (332115): -6.270 0.120 clock uncertainty
|
|
Info (332115): -6.549 -0.279 uTh fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Data Arrival Time : 3.693
|
|
Info (332115): Data Required Time : -6.549
|
|
Info (332115): Slack : 10.242
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 10.258
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|rx_fref}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 10.258
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|rx_fref
|
|
Info (332115): Exception : dcp_bbs.sdc:3195: set_min_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pma_rxpma_rstb}] -10.000
|
|
Info (332115): Min Delay Exception : -10.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 2.007 2.007 R clock network delay
|
|
Info (332115): 2.007 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): 3.709 1.702 RR uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|rx_pma_rstb2
|
|
Info (332115): 3.709 0.000 RR IC fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_pma_rxpma_rstb
|
|
Info (332115): 3.709 0.000 RR CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): -10.000 -10.000 latch edge time
|
|
Info (332115): -6.390 3.610 R clock network delay
|
|
Info (332115): -6.270 0.120 clock uncertainty
|
|
Info (332115): -6.549 -0.279 uTh fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Data Arrival Time : 3.709
|
|
Info (332115): Data Required Time : -6.549
|
|
Info (332115): Slack : 10.258
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 10.501
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|rx_fref}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 10.501
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|rx_fref
|
|
Info (332115): Exception : dcp_bbs.sdc:3195: set_min_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pma_rxpma_rstb}] -10.000
|
|
Info (332115): Min Delay Exception : -10.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 2.007 2.007 R clock network delay
|
|
Info (332115): 2.007 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): 3.951 1.944 RR uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|rx_pma_rstb4
|
|
Info (332115): 3.952 0.001 RR IC fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_pma_rxpma_rstb
|
|
Info (332115): 3.952 0.000 RR CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): -10.000 -10.000 latch edge time
|
|
Info (332115): -6.390 3.610 R clock network delay
|
|
Info (332115): -6.270 0.120 clock uncertainty
|
|
Info (332115): -6.549 -0.279 uTh fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Data Arrival Time : 3.952
|
|
Info (332115): Data Required Time : -6.549
|
|
Info (332115): Slack : 10.501
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 10.516
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|rx_fref}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 10.516
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|rx_fref
|
|
Info (332115): Exception : dcp_bbs.sdc:3195: set_min_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pma_rxpma_rstb}] -10.000
|
|
Info (332115): Min Delay Exception : -10.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 2.007 2.007 R clock network delay
|
|
Info (332115): 2.007 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): 4.045 2.038 RR uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|rx_pma_rstb5
|
|
Info (332115): 4.045 0.000 RR IC fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_pma_rxpma_rstb
|
|
Info (332115): 4.045 0.000 RR CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): -10.000 -10.000 latch edge time
|
|
Info (332115): -6.312 3.688 R clock network delay
|
|
Info (332115): -6.192 0.120 clock uncertainty
|
|
Info (332115): -6.471 -0.279 uTh fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Data Arrival Time : 4.045
|
|
Info (332115): Data Required Time : -6.471
|
|
Info (332115): Slack : 10.516
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 10.570
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|rx_fref}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 10.570
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|rx_fref
|
|
Info (332115): Exception : dcp_bbs.sdc:3195: set_min_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pma_rxpma_rstb}] -10.000
|
|
Info (332115): Min Delay Exception : -10.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 2.007 2.007 R clock network delay
|
|
Info (332115): 2.007 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): 3.929 1.922 RR uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|rx_pma_rstb1
|
|
Info (332115): 3.929 0.000 RR IC fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_pma_rxpma_rstb
|
|
Info (332115): 3.929 0.000 RR CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): -10.000 -10.000 latch edge time
|
|
Info (332115): -6.482 3.518 R clock network delay
|
|
Info (332115): -6.362 0.120 clock uncertainty
|
|
Info (332115): -6.641 -0.279 uTh fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Data Arrival Time : 3.929
|
|
Info (332115): Data Required Time : -6.641
|
|
Info (332115): Slack : 10.570
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 10.623
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|rx_fref}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 10.623
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|rx_fref
|
|
Info (332115): Exception : dcp_bbs.sdc:3195: set_min_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pma_rxpma_rstb}] -10.000
|
|
Info (332115): Min Delay Exception : -10.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 2.007 2.007 R clock network delay
|
|
Info (332115): 2.007 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): 4.152 2.145 RR uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|rx_pma_rstb6
|
|
Info (332115): 4.152 0.000 RR IC fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_pma_rxpma_rstb
|
|
Info (332115): 4.152 0.000 RR CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): -10.000 -10.000 latch edge time
|
|
Info (332115): -6.312 3.688 R clock network delay
|
|
Info (332115): -6.192 0.120 clock uncertainty
|
|
Info (332115): -6.471 -0.279 uTh fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Data Arrival Time : 4.152
|
|
Info (332115): Data Required Time : -6.471
|
|
Info (332115): Slack : 10.623
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 11.094
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|rx_fref}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 11.094
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|rx_fref
|
|
Info (332115): Exception : dcp_bbs.sdc:3195: set_min_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pma_rxpma_rstb}] -10.000
|
|
Info (332115): Min Delay Exception : -10.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 2.007 2.007 R clock network delay
|
|
Info (332115): 2.007 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): 4.623 2.616 RR uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|rx_pma_rstb7
|
|
Info (332115): 4.623 0.000 RR IC fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_pma_rxpma_rstb
|
|
Info (332115): 4.623 0.000 RR CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): -10.000 -10.000 latch edge time
|
|
Info (332115): -6.312 3.688 R clock network delay
|
|
Info (332115): -6.192 0.120 clock uncertainty
|
|
Info (332115): -6.471 -0.279 uTh fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Data Arrival Time : 4.623
|
|
Info (332115): Data Required Time : -6.471
|
|
Info (332115): Slack : 11.094
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 12.749
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 12.749
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332115): Exception : dcp_bbs.sdc:3195: set_min_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pma_rxpma_rstb}] -10.000
|
|
Info (332115): Min Delay Exception : -10.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 2.007 2.007 R clock network delay
|
|
Info (332115): 2.007 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): 4.223 2.216 RR uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|rx_pma_rstb0
|
|
Info (332115): 4.223 0.000 RR IC fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_pma_rxpma_rstb
|
|
Info (332115): 4.223 0.000 RR CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): -10.000 -10.000 latch edge time
|
|
Info (332115): -6.482 3.518 R clock network delay
|
|
Info (332115): -8.277 -1.795 clock pessimism removed
|
|
Info (332115): -8.247 0.030 clock uncertainty
|
|
Info (332115): -8.526 -0.279 uTh fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Data Arrival Time : 4.223
|
|
Info (332115): Data Required Time : -8.526
|
|
Info (332115): Slack : 12.749
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 51.952
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|tx_coreclkin}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 51.952
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_avmm_csr_enabled.embedded_debug_soft_csr|g_control_reg.r_tx_digitalreset
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_10g_tx_pcs.inst_twentynm_hssi_10g_tx_pcs~pld_10g_krfec_tx_pld_rst_n_fifo.reg
|
|
Info (332115): Launch Clock : SYS_RefClk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|tx_coreclkin
|
|
Info (332115): Exception : dcp_bbs.sdc:3193: set_min_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_10g_krfec_tx_pld_rst_n}] -50.000
|
|
Info (332115): Min Delay Exception : -50.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 4.382 4.382 R clock network delay
|
|
Info (332115): 4.382 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_avmm_csr_enabled.embedded_debug_soft_csr|g_control_reg.r_tx_digitalreset
|
|
Info (332115): 4.617 0.235 FF uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_avmm_csr_enabled.embedded_debug_soft_csr|g_control_reg.r_tx_digitalreset|q
|
|
Info (332115): 4.683 0.066 FF CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_avmm_csr_enabled.embedded_debug_soft_csr|g_control_reg.r_tx_digitalreset~la_mlab/laboutb[17]
|
|
Info (332115): 4.913 0.230 FF IC Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0|datad
|
|
Info (332115): 5.052 0.139 FR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0|combout
|
|
Info (332115): 5.054 0.002 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0~la_mlab/laboutb[18]
|
|
Info (332115): 7.169 2.115 RR IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_tx_pld_pcs_interface.inst_twentynm_hssi_tx_pld_pcs_interface|pld_10g_krfec_tx_pld_rst_n
|
|
Info (332115): 7.169 0.000 RR CELL fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_10g_tx_pcs.inst_twentynm_hssi_10g_tx_pcs~pld_10g_krfec_tx_pld_rst_n_fifo.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): -50.000 -50.000 latch edge time
|
|
Info (332115): -44.833 5.167 R clock network delay
|
|
Info (332115): -44.764 0.069 clock uncertainty
|
|
Info (332115): -44.783 -0.019 uTh fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_10g_tx_pcs.inst_twentynm_hssi_10g_tx_pcs~pld_10g_krfec_tx_pld_rst_n_fifo.reg
|
|
Info (332115): Data Arrival Time : 7.169
|
|
Info (332115): Data Required Time : -44.783
|
|
Info (332115): Slack : 51.952
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 52.441
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|tx_coreclkin}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 52.441
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_avmm_csr_enabled.embedded_debug_soft_csr|g_control_reg.r_tx_digitalreset_override
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_10g_tx_pcs.inst_twentynm_hssi_10g_tx_pcs~pld_10g_krfec_tx_pld_rst_n_fifo.reg
|
|
Info (332115): Launch Clock : SYS_RefClk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|tx_coreclkin
|
|
Info (332115): Exception : dcp_bbs.sdc:3193: set_min_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_10g_krfec_tx_pld_rst_n}] -50.000
|
|
Info (332115): Min Delay Exception : -50.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 4.384 4.384 R clock network delay
|
|
Info (332115): 4.384 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_avmm_csr_enabled.embedded_debug_soft_csr|g_control_reg.r_tx_digitalreset_override
|
|
Info (332115): 4.603 0.219 FF uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_avmm_csr_enabled.embedded_debug_soft_csr|g_control_reg.r_tx_digitalreset_override|q
|
|
Info (332115): 4.603 0.000 FF CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0|datae
|
|
Info (332115): 5.018 0.415 FR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0|combout
|
|
Info (332115): 5.019 0.001 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0~la_lab/laboutb[16]
|
|
Info (332115): 7.506 2.487 RR IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_tx_pld_pcs_interface.inst_twentynm_hssi_tx_pld_pcs_interface|pld_10g_krfec_tx_pld_rst_n
|
|
Info (332115): 7.506 0.000 RR CELL fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_10g_tx_pcs.inst_twentynm_hssi_10g_tx_pcs~pld_10g_krfec_tx_pld_rst_n_fifo.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): -50.000 -50.000 latch edge time
|
|
Info (332115): -44.985 5.015 R clock network delay
|
|
Info (332115): -44.916 0.069 clock uncertainty
|
|
Info (332115): -44.935 -0.019 uTh fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_10g_tx_pcs.inst_twentynm_hssi_10g_tx_pcs~pld_10g_krfec_tx_pld_rst_n_fifo.reg
|
|
Info (332115): Data Arrival Time : 7.506
|
|
Info (332115): Data Required Time : -44.935
|
|
Info (332115): Slack : 52.441
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 52.465
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|tx_coreclkin}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 52.465
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_avmm_csr_enabled.embedded_debug_soft_csr|g_control_reg.r_tx_digitalreset
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_10g_tx_pcs.inst_twentynm_hssi_10g_tx_pcs~pld_10g_krfec_tx_pld_rst_n_fifo.reg
|
|
Info (332115): Launch Clock : SYS_RefClk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|tx_coreclkin
|
|
Info (332115): Exception : dcp_bbs.sdc:3193: set_min_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_10g_krfec_tx_pld_rst_n}] -50.000
|
|
Info (332115): Min Delay Exception : -50.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 4.364 4.364 R clock network delay
|
|
Info (332115): 4.364 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_avmm_csr_enabled.embedded_debug_soft_csr|g_control_reg.r_tx_digitalreset
|
|
Info (332115): 4.559 0.195 FF uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_avmm_csr_enabled.embedded_debug_soft_csr|g_control_reg.r_tx_digitalreset|q
|
|
Info (332115): 4.622 0.063 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_avmm_csr_enabled.embedded_debug_soft_csr|g_control_reg.r_tx_digitalreset~la_lab/laboutt[14]
|
|
Info (332115): 5.002 0.380 FF IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0|datae
|
|
Info (332115): 5.173 0.171 FR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0|combout
|
|
Info (332115): 5.175 0.002 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0~la_mlab/laboutb[18]
|
|
Info (332115): 7.542 2.367 RR IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_tx_pld_pcs_interface.inst_twentynm_hssi_tx_pld_pcs_interface|pld_10g_krfec_tx_pld_rst_n
|
|
Info (332115): 7.542 0.000 RR CELL fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_10g_tx_pcs.inst_twentynm_hssi_10g_tx_pcs~pld_10g_krfec_tx_pld_rst_n_fifo.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): -50.000 -50.000 latch edge time
|
|
Info (332115): -44.973 5.027 R clock network delay
|
|
Info (332115): -44.904 0.069 clock uncertainty
|
|
Info (332115): -44.923 -0.019 uTh fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_10g_tx_pcs.inst_twentynm_hssi_10g_tx_pcs~pld_10g_krfec_tx_pld_rst_n_fifo.reg
|
|
Info (332115): Data Arrival Time : 7.542
|
|
Info (332115): Data Required Time : -44.923
|
|
Info (332115): Slack : 52.465
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 52.500
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|tx_coreclkin}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 52.500
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_avmm_csr_enabled.embedded_debug_soft_csr|g_control_reg.r_tx_digitalreset_override
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_10g_tx_pcs.inst_twentynm_hssi_10g_tx_pcs~pld_10g_krfec_tx_pld_rst_n_fifo.reg
|
|
Info (332115): Launch Clock : SYS_RefClk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|tx_coreclkin
|
|
Info (332115): Exception : dcp_bbs.sdc:3193: set_min_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_10g_krfec_tx_pld_rst_n}] -50.000
|
|
Info (332115): Min Delay Exception : -50.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 4.384 4.384 R clock network delay
|
|
Info (332115): 4.384 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_avmm_csr_enabled.embedded_debug_soft_csr|g_control_reg.r_tx_digitalreset_override
|
|
Info (332115): 4.611 0.227 FF uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_avmm_csr_enabled.embedded_debug_soft_csr|g_control_reg.r_tx_digitalreset_override|q
|
|
Info (332115): 4.611 0.000 FF CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0|datae
|
|
Info (332115): 5.025 0.414 FR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0|combout
|
|
Info (332115): 5.027 0.002 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0~la_lab/laboutt[8]
|
|
Info (332115): 7.606 2.579 RR IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_tx_pld_pcs_interface.inst_twentynm_hssi_tx_pld_pcs_interface|pld_10g_krfec_tx_pld_rst_n
|
|
Info (332115): 7.606 0.000 RR CELL fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_10g_tx_pcs.inst_twentynm_hssi_10g_tx_pcs~pld_10g_krfec_tx_pld_rst_n_fifo.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): -50.000 -50.000 latch edge time
|
|
Info (332115): -44.944 5.056 R clock network delay
|
|
Info (332115): -44.875 0.069 clock uncertainty
|
|
Info (332115): -44.894 -0.019 uTh fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_10g_tx_pcs.inst_twentynm_hssi_10g_tx_pcs~pld_10g_krfec_tx_pld_rst_n_fifo.reg
|
|
Info (332115): Data Arrival Time : 7.606
|
|
Info (332115): Data Required Time : -44.894
|
|
Info (332115): Slack : 52.500
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 53.433
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|tx_pma_clk}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 53.433
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_avmm_csr_enabled.embedded_debug_soft_csr|g_control_reg.r_tx_digitalreset
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_tx_pld_pcs_interface.inst_twentynm_hssi_tx_pld_pcs_interface~pld_pmaif_tx_pld_rst_n_reg.reg
|
|
Info (332115): Launch Clock : SYS_RefClk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|tx_pma_clk
|
|
Info (332115): Exception : dcp_bbs.sdc:3191: set_min_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pmaif_tx_pld_rst_n}] -50.000
|
|
Info (332115): Min Delay Exception : -50.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 4.382 4.382 R clock network delay
|
|
Info (332115): 4.382 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_avmm_csr_enabled.embedded_debug_soft_csr|g_control_reg.r_tx_digitalreset
|
|
Info (332115): 4.617 0.235 FF uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_avmm_csr_enabled.embedded_debug_soft_csr|g_control_reg.r_tx_digitalreset|q
|
|
Info (332115): 4.683 0.066 FF CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_avmm_csr_enabled.embedded_debug_soft_csr|g_control_reg.r_tx_digitalreset~la_mlab/laboutb[17]
|
|
Info (332115): 4.913 0.230 FF IC Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0|datad
|
|
Info (332115): 5.052 0.139 FR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0|combout
|
|
Info (332115): 5.054 0.002 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0~la_mlab/laboutb[18]
|
|
Info (332115): 7.055 2.001 RR IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_tx_pld_pcs_interface.inst_twentynm_hssi_tx_pld_pcs_interface|pld_pmaif_tx_pld_rst_n
|
|
Info (332115): 7.055 0.000 RR CELL fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_tx_pld_pcs_interface.inst_twentynm_hssi_tx_pld_pcs_interface~pld_pmaif_tx_pld_rst_n_reg.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): -50.000 -50.000 latch edge time
|
|
Info (332115): -46.567 3.433 R clock network delay
|
|
Info (332115): -46.497 0.070 clock uncertainty
|
|
Info (332115): -46.378 0.119 uTh fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_tx_pld_pcs_interface.inst_twentynm_hssi_tx_pld_pcs_interface~pld_pmaif_tx_pld_rst_n_reg.reg
|
|
Info (332115): Data Arrival Time : 7.055
|
|
Info (332115): Data Required Time : -46.378
|
|
Info (332115): Slack : 53.433
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 53.678
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|tx_pma_clk}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 53.678
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_avmm_csr_enabled.embedded_debug_soft_csr|g_control_reg.r_tx_digitalreset_override
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs~pld_8g_g3_tx_pld_rst_n_reg.reg
|
|
Info (332115): Launch Clock : SYS_RefClk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|tx_pma_clk
|
|
Info (332115): Exception : dcp_bbs.sdc:3192: set_min_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_8g_g3_tx_pld_rst_n}] -50.000
|
|
Info (332115): Min Delay Exception : -50.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 4.384 4.384 R clock network delay
|
|
Info (332115): 4.384 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_avmm_csr_enabled.embedded_debug_soft_csr|g_control_reg.r_tx_digitalreset_override
|
|
Info (332115): 4.603 0.219 FF uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_avmm_csr_enabled.embedded_debug_soft_csr|g_control_reg.r_tx_digitalreset_override|q
|
|
Info (332115): 4.603 0.000 FF CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0|datae
|
|
Info (332115): 5.018 0.415 FR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0|combout
|
|
Info (332115): 5.019 0.001 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0~la_lab/laboutb[16]
|
|
Info (332115): 7.506 2.487 RR IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_tx_pld_pcs_interface.inst_twentynm_hssi_tx_pld_pcs_interface|pld_8g_g3_tx_pld_rst_n
|
|
Info (332115): 7.506 0.000 RR CELL fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs~pld_8g_g3_tx_pld_rst_n_reg.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): -50.000 -50.000 latch edge time
|
|
Info (332115): -46.567 3.433 R clock network delay
|
|
Info (332115): -46.497 0.070 clock uncertainty
|
|
Info (332115): -46.172 0.325 uTh fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs~pld_8g_g3_tx_pld_rst_n_reg.reg
|
|
Info (332115): Data Arrival Time : 7.506
|
|
Info (332115): Data Required Time : -46.172
|
|
Info (332115): Slack : 53.678
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 53.750
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|tx_pma_clk}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 53.750
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_avmm_csr_enabled.embedded_debug_soft_csr|g_control_reg.r_tx_digitalreset
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs~pld_8g_g3_tx_pld_rst_n_reg.reg
|
|
Info (332115): Launch Clock : SYS_RefClk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|tx_pma_clk
|
|
Info (332115): Exception : dcp_bbs.sdc:3192: set_min_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_8g_g3_tx_pld_rst_n}] -50.000
|
|
Info (332115): Min Delay Exception : -50.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 4.364 4.364 R clock network delay
|
|
Info (332115): 4.364 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_avmm_csr_enabled.embedded_debug_soft_csr|g_control_reg.r_tx_digitalreset
|
|
Info (332115): 4.559 0.195 FF uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_avmm_csr_enabled.embedded_debug_soft_csr|g_control_reg.r_tx_digitalreset|q
|
|
Info (332115): 4.622 0.063 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_avmm_csr_enabled.embedded_debug_soft_csr|g_control_reg.r_tx_digitalreset~la_lab/laboutt[14]
|
|
Info (332115): 5.002 0.380 FF IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0|datae
|
|
Info (332115): 5.173 0.171 FR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0|combout
|
|
Info (332115): 5.175 0.002 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0~la_mlab/laboutb[18]
|
|
Info (332115): 7.542 2.367 RR IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_tx_pld_pcs_interface.inst_twentynm_hssi_tx_pld_pcs_interface|pld_8g_g3_tx_pld_rst_n
|
|
Info (332115): 7.542 0.000 RR CELL fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs~pld_8g_g3_tx_pld_rst_n_reg.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): -50.000 -50.000 latch edge time
|
|
Info (332115): -46.603 3.397 R clock network delay
|
|
Info (332115): -46.533 0.070 clock uncertainty
|
|
Info (332115): -46.208 0.325 uTh fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs~pld_8g_g3_tx_pld_rst_n_reg.reg
|
|
Info (332115): Data Arrival Time : 7.542
|
|
Info (332115): Data Required Time : -46.208
|
|
Info (332115): Slack : 53.750
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 53.808
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|tx_pma_clk}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 53.808
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_avmm_csr_enabled.embedded_debug_soft_csr|g_control_reg.r_tx_digitalreset_override
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs~pld_8g_g3_tx_pld_rst_n_reg.reg
|
|
Info (332115): Launch Clock : SYS_RefClk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|tx_pma_clk
|
|
Info (332115): Exception : dcp_bbs.sdc:3192: set_min_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_8g_g3_tx_pld_rst_n}] -50.000
|
|
Info (332115): Min Delay Exception : -50.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 4.384 4.384 R clock network delay
|
|
Info (332115): 4.384 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_avmm_csr_enabled.embedded_debug_soft_csr|g_control_reg.r_tx_digitalreset_override
|
|
Info (332115): 4.611 0.227 FF uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_avmm_csr_enabled.embedded_debug_soft_csr|g_control_reg.r_tx_digitalreset_override|q
|
|
Info (332115): 4.611 0.000 FF CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0|datae
|
|
Info (332115): 5.025 0.414 FR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0|combout
|
|
Info (332115): 5.027 0.002 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0~la_lab/laboutt[8]
|
|
Info (332115): 7.600 2.573 RR IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_tx_pld_pcs_interface.inst_twentynm_hssi_tx_pld_pcs_interface|pld_8g_g3_tx_pld_rst_n
|
|
Info (332115): 7.600 0.000 RR CELL fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs~pld_8g_g3_tx_pld_rst_n_reg.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): -50.000 -50.000 latch edge time
|
|
Info (332115): -46.603 3.397 R clock network delay
|
|
Info (332115): -46.533 0.070 clock uncertainty
|
|
Info (332115): -46.208 0.325 uTh fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs~pld_8g_g3_tx_pld_rst_n_reg.reg
|
|
Info (332115): Data Arrival Time : 7.600
|
|
Info (332115): Data Required Time : -46.208
|
|
Info (332115): Slack : 53.808
|
|
Info (332115): ===================================================================
|
|
Info: Analyzing Fast 900mV 100C Model
|
|
Info (332146): Worst-case setup slack is 0.162
|
|
Info (332119): Slack End Point TNS Clock
|
|
Info (332119): ========= =================== =====================
|
|
Info (332119): 0.162 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk1
|
|
Info (332119): 0.799 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_bonding_clocks[0]
|
|
Info (332119): 1.057 0.000 mem|ddr4a|ddr4a_core_usr_clk
|
|
Info (332119): 1.077 0.000 mem|ddr4a|ddr4a_phy_clk_l_2
|
|
Info (332119): 1.096 0.000 mem|ddr4a|ddr4a_phy_clk_l_1
|
|
Info (332119): 1.133 0.000 mem|ddr4b|ddr4b_phy_clk_l_1
|
|
Info (332119): 1.223 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|wys~CORE_CLK_OUT
|
|
Info (332119): 1.333 0.000 mem|ddr4b|ddr4b_phy_clk_l_2
|
|
Info (332119): 1.408 0.000 mem|ddr4b|ddr4b_phy_clk_l_0
|
|
Info (332119): 1.480 0.000 u0|dcp_iopll|dcp_iopll|clk1x
|
|
Info (332119): 1.616 0.000 mem|ddr4a|ddr4a_phy_clk_l_0
|
|
Info (332119): 1.621 0.000 u0|dcp_iopll|dcp_iopll|clk100
|
|
Info (332119): 1.651 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|pld_clk
|
|
Info (332119): 2.560 0.000 mem|ddr4a|ddr4a_core_cal_slave_clk
|
|
Info (332119): 2.606 0.000 hssi_pll_r_0_outclk0
|
|
Info (332119): 2.626 0.000 ETH_RefClk
|
|
Info (332119): 2.659 0.000 hssi_pll_t_outclk0
|
|
Info (332119): 2.798 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_clk
|
|
Info (332119): 2.837 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|rx_pma_clk
|
|
Info (332119): 2.944 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|rx_pma_clk
|
|
Info (332119): 2.979 0.000 DDR4_RefClk
|
|
Info (332119): 3.037 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|rx_pma_clk
|
|
Info (332119): 3.249 0.000 hssi_pll_t_outclk1
|
|
Info (332119): 3.274 0.000 hssi_pll_r_0_outclk1
|
|
Info (332119): 3.525 0.000 PCIE_REFCLK
|
|
Info (332119): 3.576 0.000 vl_qph_user_clk_clkpsc_clk1
|
|
Info (332119): 3.915 0.000 SYS_RefClk
|
|
Info (332119): 4.766 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|avmmclk
|
|
Info (332119): 5.019 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|avmmclk
|
|
Info (332119): 5.193 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|avmmclk
|
|
Info (332119): 5.821 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|avmmclk
|
|
Info (332119): 5.850 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|tx_pma_div_clk
|
|
Info (332119): 5.927 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_div_clk
|
|
Info (332119): 6.009 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|avmmclk
|
|
Info (332119): 6.153 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|avmmclk
|
|
Info (332119): 6.232 0.000 fspi_sclk
|
|
Info (332119): 6.365 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|avmmclk
|
|
Info (332119): 6.627 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|avmmclk
|
|
Info (332119): 6.891 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|avmmclk
|
|
Info (332119): 7.098 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|avmmclk
|
|
Info (332119): 7.368 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|avmmclk
|
|
Info (332119): 8.073 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|avmmclk
|
|
Info (332119): 8.121 0.000 vl_qph_user_clk_clkpsc_clk0
|
|
Info (332119): 8.753 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk0
|
|
Info (332119): 11.338 0.000 pr_clk_enable_dclk_reg2_user_clk
|
|
Info (332119): 18.748 0.000 u0|dcp_iopll|dcp_iopll|clk25
|
|
Info (332119): 19.508 0.000 u0|dcp_iopll|dcp_iopll|clk50
|
|
Info (332119): 23.109 0.000 filtered_sclk_negedge
|
|
Info (332119): 42.570 0.000 altera_reserved_tck
|
|
Info (332146): Worst-case hold slack is 0.002
|
|
Info (332119): Slack End Point TNS Clock
|
|
Info (332119): ========= =================== =====================
|
|
Info (332119): 0.002 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk1
|
|
Info (332119): 0.013 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|wys~CORE_CLK_OUT
|
|
Info (332119): 0.014 0.000 SYS_RefClk
|
|
Info (332119): 0.015 0.000 u0|dcp_iopll|dcp_iopll|clk100
|
|
Info (332119): 0.015 0.000 u0|dcp_iopll|dcp_iopll|clk1x
|
|
Info (332119): 0.016 0.000 altera_reserved_tck
|
|
Info (332119): 0.018 0.000 u0|dcp_iopll|dcp_iopll|clk25
|
|
Info (332119): 0.020 0.000 mem|ddr4a|ddr4a_core_cal_slave_clk
|
|
Info (332119): 0.020 0.000 mem|ddr4a|ddr4a_core_usr_clk
|
|
Info (332119): 0.021 0.000 DDR4_RefClk
|
|
Info (332119): 0.021 0.000 PCIE_REFCLK
|
|
Info (332119): 0.021 0.000 filtered_sclk_negedge
|
|
Info (332119): 0.021 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|rx_pma_clk
|
|
Info (332119): 0.021 0.000 hssi_pll_t_outclk1
|
|
Info (332119): 0.023 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk0
|
|
Info (332119): 0.024 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_clk
|
|
Info (332119): 0.024 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_div_clk
|
|
Info (332119): 0.025 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|rx_pma_clk
|
|
Info (332119): 0.026 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|tx_pma_div_clk
|
|
Info (332119): 0.026 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|rx_pma_clk
|
|
Info (332119): 0.026 0.000 hssi_pll_r_0_outclk0
|
|
Info (332119): 0.029 0.000 hssi_pll_r_0_outclk1
|
|
Info (332119): 0.030 0.000 hssi_pll_t_outclk0
|
|
Info (332119): 0.031 0.000 ETH_RefClk
|
|
Info (332119): 0.035 0.000 u0|dcp_iopll|dcp_iopll|clk50
|
|
Info (332119): 0.076 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_bonding_clocks[0]
|
|
Info (332119): 0.108 0.000 fspi_sclk
|
|
Info (332119): 0.192 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|pld_clk
|
|
Info (332119): 0.218 0.000 mem|ddr4a|ddr4a_phy_clk_l_0
|
|
Info (332119): 0.223 0.000 mem|ddr4a|ddr4a_phy_clk_l_2
|
|
Info (332119): 0.227 0.000 mem|ddr4b|ddr4b_phy_clk_l_2
|
|
Info (332119): 0.236 0.000 mem|ddr4b|ddr4b_phy_clk_l_0
|
|
Info (332119): 0.242 0.000 mem|ddr4a|ddr4a_phy_clk_l_1
|
|
Info (332119): 0.266 0.000 mem|ddr4b|ddr4b_phy_clk_l_1
|
|
Info (332119): 0.465 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|avmmclk
|
|
Info (332119): 0.532 0.000 vl_qph_user_clk_clkpsc_clk0
|
|
Info (332119): 0.532 0.000 vl_qph_user_clk_clkpsc_clk1
|
|
Info (332119): 0.608 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|avmmclk
|
|
Info (332119): 0.661 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|avmmclk
|
|
Info (332119): 0.730 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|avmmclk
|
|
Info (332119): 0.810 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|avmmclk
|
|
Info (332119): 0.853 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|avmmclk
|
|
Info (332119): 0.892 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|avmmclk
|
|
Info (332119): 0.981 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|avmmclk
|
|
Info (332119): 0.985 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|avmmclk
|
|
Info (332119): 1.139 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|avmmclk
|
|
Info (332119): 1.280 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|avmmclk
|
|
Info (332119): 1.400 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|avmmclk
|
|
Info (332119): 6.592 0.000 pr_clk_enable_dclk_reg2_user_clk
|
|
Info (332146): Worst-case recovery slack is 1.158
|
|
Info (332119): Slack End Point TNS Clock
|
|
Info (332119): ========= =================== =====================
|
|
Info (332119): 1.158 0.000 mem|ddr4a|ddr4a_core_usr_clk
|
|
Info (332119): 1.668 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|wys~CORE_CLK_OUT
|
|
Info (332119): 1.917 0.000 u0|dcp_iopll|dcp_iopll|clk1x
|
|
Info (332119): 1.987 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk1
|
|
Info (332119): 2.253 0.000 u0|dcp_iopll|dcp_iopll|clk100
|
|
Info (332119): 3.219 0.000 u0|dcp_iopll|dcp_iopll|clk25
|
|
Info (332119): 3.226 0.000 DDR4_RefClk
|
|
Info (332119): 3.231 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|rx_pma_clk
|
|
Info (332119): 3.287 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_clk
|
|
Info (332119): 3.304 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|rx_pma_clk
|
|
Info (332119): 3.309 0.000 mem|ddr4a|ddr4a_core_cal_slave_clk
|
|
Info (332119): 3.353 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|rx_pma_clk
|
|
Info (332119): 4.289 0.000 SYS_RefClk
|
|
Info (332119): 6.098 0.000 fspi_sclk
|
|
Info (332119): 6.144 0.000 filtered_sclk_negedge
|
|
Info (332119): 6.209 0.000 PCIE_REFCLK
|
|
Info (332119): 17.528 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|rx_pma_clk
|
|
Info (332119): 17.562 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|rx_fref
|
|
Info (332119): 17.724 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|rx_pma_clk
|
|
Info (332119): 17.758 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|rx_fref
|
|
Info (332119): 17.784 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|rx_pma_clk
|
|
Info (332119): 17.818 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|rx_fref
|
|
Info (332119): 17.844 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|rx_pma_clk
|
|
Info (332119): 17.878 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|rx_fref
|
|
Info (332119): 17.888 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_pma_clk
|
|
Info (332119): 17.888 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|rx_pma_clk
|
|
Info (332119): 17.922 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|rx_fref
|
|
Info (332119): 17.978 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|rx_pma_clk
|
|
Info (332119): 18.005 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|rx_pma_clk
|
|
Info (332119): 18.012 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|rx_fref
|
|
Info (332119): 18.039 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|rx_fref
|
|
Info (332119): 18.499 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332119): 42.829 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|tx_pma_clk
|
|
Info (332119): 42.951 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|tx_pma_clk
|
|
Info (332119): 43.159 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|tx_pma_clk
|
|
Info (332119): 43.428 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|tx_pma_clk
|
|
Info (332119): 44.220 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|tx_coreclkin
|
|
Info (332119): 44.495 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|tx_coreclkin
|
|
Info (332119): 44.634 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|tx_coreclkin
|
|
Info (332119): 44.774 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|tx_coreclkin
|
|
Info (332119): 97.996 0.000 altera_reserved_tck
|
|
Info (332146): Worst-case removal slack is 0.132
|
|
Info (332119): Slack End Point TNS Clock
|
|
Info (332119): ========= =================== =====================
|
|
Info (332119): 0.132 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk1
|
|
Info (332119): 0.167 0.000 SYS_RefClk
|
|
Info (332119): 0.188 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_clk
|
|
Info (332119): 0.188 0.000 mem|ddr4a|ddr4a_core_usr_clk
|
|
Info (332119): 0.189 0.000 u0|dcp_iopll|dcp_iopll|clk1x
|
|
Info (332119): 0.196 0.000 mem|ddr4a|ddr4a_core_cal_slave_clk
|
|
Info (332119): 0.206 0.000 PCIE_REFCLK
|
|
Info (332119): 0.216 0.000 DDR4_RefClk
|
|
Info (332119): 0.239 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|wys~CORE_CLK_OUT
|
|
Info (332119): 0.245 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|rx_pma_clk
|
|
Info (332119): 0.248 0.000 u0|dcp_iopll|dcp_iopll|clk100
|
|
Info (332119): 0.261 0.000 u0|dcp_iopll|dcp_iopll|clk25
|
|
Info (332119): 0.274 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|rx_pma_clk
|
|
Info (332119): 0.298 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|rx_pma_clk
|
|
Info (332119): 0.662 0.000 altera_reserved_tck
|
|
Info (332119): 1.682 0.000 fspi_sclk
|
|
Info (332119): 1.810 0.000 filtered_sclk_negedge
|
|
Info (332119): 10.011 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|rx_fref
|
|
Info (332119): 10.035 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|rx_fref
|
|
Info (332119): 10.051 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|rx_pma_clk
|
|
Info (332119): 10.067 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|rx_pma_clk
|
|
Info (332119): 10.114 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|rx_fref
|
|
Info (332119): 10.165 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|rx_pma_clk
|
|
Info (332119): 10.174 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|rx_fref
|
|
Info (332119): 10.183 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|rx_fref
|
|
Info (332119): 10.218 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|rx_pma_clk
|
|
Info (332119): 10.237 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|rx_pma_clk
|
|
Info (332119): 10.237 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|rx_fref
|
|
Info (332119): 10.282 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|rx_pma_clk
|
|
Info (332119): 10.409 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|rx_fref
|
|
Info (332119): 10.474 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|rx_pma_clk
|
|
Info (332119): 10.584 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_pma_clk
|
|
Info (332119): 11.116 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332119): 51.562 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|tx_coreclkin
|
|
Info (332119): 51.799 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|tx_coreclkin
|
|
Info (332119): 51.940 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|tx_coreclkin
|
|
Info (332119): 52.044 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|tx_coreclkin
|
|
Info (332119): 52.607 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|tx_pma_clk
|
|
Info (332119): 52.706 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|tx_pma_clk
|
|
Info (332119): 52.887 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|tx_pma_clk
|
|
Info (332119): 52.983 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|tx_pma_clk
|
|
Info (332146): Worst-case minimum pulse width slack is 0.093
|
|
Info (332119): Slack End Point TNS Clock
|
|
Info (332119): ========= =================== =====================
|
|
Info (332119): 0.093 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|atx0|altera_xcvr_atx_pll_ip_inst|mcgb_serial_clk
|
|
Info (332119): 0.125 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|twentynm_atx_pll_inst~O_CLK0_8G
|
|
Info (332119): 0.200 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_serial_clk
|
|
Info (332119): 0.202 0.000 DDR4A_DQS_P[0]_IN
|
|
Info (332119): 0.202 0.000 DDR4A_DQS_P[1]_IN
|
|
Info (332119): 0.202 0.000 DDR4A_DQS_P[3]_IN
|
|
Info (332119): 0.202 0.000 DDR4A_DQS_P[4]_IN
|
|
Info (332119): 0.202 0.000 DDR4A_DQS_P[6]_IN
|
|
Info (332119): 0.202 0.000 DDR4A_DQS_P[7]_IN
|
|
Info (332119): 0.202 0.000 DDR4B_DQS_P[0]_IN
|
|
Info (332119): 0.202 0.000 DDR4B_DQS_P[1]_IN
|
|
Info (332119): 0.202 0.000 DDR4B_DQS_P[3]_IN
|
|
Info (332119): 0.202 0.000 DDR4B_DQS_P[4]_IN
|
|
Info (332119): 0.202 0.000 DDR4B_DQS_P[6]_IN
|
|
Info (332119): 0.202 0.000 DDR4B_DQS_P[7]_IN
|
|
Info (332119): 0.203 0.000 DDR4A_DQS_P[2]_IN
|
|
Info (332119): 0.203 0.000 DDR4A_DQS_P[5]_IN
|
|
Info (332119): 0.203 0.000 DDR4B_DQS_P[2]_IN
|
|
Info (332119): 0.203 0.000 DDR4B_DQS_P[5]_IN
|
|
Info (332119): 0.429 0.000 mem|ddr4a|ddr4a_wf_clk_10
|
|
Info (332119): 0.429 0.000 mem|ddr4a|ddr4a_wf_clk_3
|
|
Info (332119): 0.429 0.000 mem|ddr4a|ddr4a_wf_clk_4
|
|
Info (332119): 0.429 0.000 mem|ddr4a|ddr4a_wf_clk_5
|
|
Info (332119): 0.429 0.000 mem|ddr4a|ddr4a_wf_clk_6
|
|
Info (332119): 0.429 0.000 mem|ddr4a|ddr4a_wf_clk_7
|
|
Info (332119): 0.429 0.000 mem|ddr4a|ddr4a_wf_clk_8
|
|
Info (332119): 0.429 0.000 mem|ddr4a|ddr4a_wf_clk_9
|
|
Info (332119): 0.429 0.000 mem|ddr4b|ddr4b_wf_clk_10
|
|
Info (332119): 0.429 0.000 mem|ddr4b|ddr4b_wf_clk_3
|
|
Info (332119): 0.429 0.000 mem|ddr4b|ddr4b_wf_clk_4
|
|
Info (332119): 0.429 0.000 mem|ddr4b|ddr4b_wf_clk_5
|
|
Info (332119): 0.429 0.000 mem|ddr4b|ddr4b_wf_clk_6
|
|
Info (332119): 0.429 0.000 mem|ddr4b|ddr4b_wf_clk_7
|
|
Info (332119): 0.429 0.000 mem|ddr4b|ddr4b_wf_clk_8
|
|
Info (332119): 0.429 0.000 mem|ddr4b|ddr4b_wf_clk_9
|
|
Info (332119): 0.454 0.000 mem|ddr4a|ddr4a_wf_clk_0
|
|
Info (332119): 0.454 0.000 mem|ddr4b|ddr4b_wf_clk_0
|
|
Info (332119): 0.457 0.000 mem|ddr4a|ddr4a_wf_clk_1
|
|
Info (332119): 0.457 0.000 mem|ddr4a|ddr4a_wf_clk_2
|
|
Info (332119): 0.457 0.000 mem|ddr4b|ddr4b_wf_clk_1
|
|
Info (332119): 0.457 0.000 mem|ddr4b|ddr4b_wf_clk_2
|
|
Info (332119): 0.461 0.000 mem|ddr4a|ddr4a_vco_clk
|
|
Info (332119): 0.466 0.000 mem|ddr4a|ddr4a_vco_clk_1
|
|
Info (332119): 0.466 0.000 mem|ddr4a|ddr4a_vco_clk_2
|
|
Info (332119): 0.466 0.000 mem|ddr4b|ddr4b_vco_clk_0
|
|
Info (332119): 0.466 0.000 mem|ddr4b|ddr4b_vco_clk_1
|
|
Info (332119): 0.466 0.000 mem|ddr4b|ddr4b_vco_clk_2
|
|
Info (332119): 0.816 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_bonding_clocks[0]
|
|
Info (332119): 0.885 0.000 mem|ddr4a|ddr4a_phy_clk_0
|
|
Info (332119): 0.885 0.000 mem|ddr4a|ddr4a_phy_clk_1
|
|
Info (332119): 0.885 0.000 mem|ddr4a|ddr4a_phy_clk_2
|
|
Info (332119): 0.885 0.000 mem|ddr4b|ddr4b_phy_clk_0
|
|
Info (332119): 0.885 0.000 mem|ddr4b|ddr4b_phy_clk_1
|
|
Info (332119): 0.885 0.000 mem|ddr4b|ddr4b_phy_clk_2
|
|
Info (332119): 0.896 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|pll_pcie_clk
|
|
Info (332119): 0.937 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_pma_clk
|
|
Info (332119): 0.937 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|rx_pma_clk
|
|
Info (332119): 0.937 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|rx_pma_clk
|
|
Info (332119): 0.937 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|rx_pma_clk
|
|
Info (332119): 0.937 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|rx_pma_clk
|
|
Info (332119): 0.937 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|rx_pma_clk
|
|
Info (332119): 0.937 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|rx_pma_clk
|
|
Info (332119): 0.937 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|rx_pma_clk
|
|
Info (332119): 0.947 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_pcs_clk_div_by_4[0]
|
|
Info (332119): 0.947 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_pcs_clk_div_by_4[1]
|
|
Info (332119): 0.947 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_pcs_clk_div_by_4[2]
|
|
Info (332119): 0.947 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_pcs_clk_div_by_4[3]
|
|
Info (332119): 0.947 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_pcs_clk_div_by_4[4]
|
|
Info (332119): 0.947 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_pcs_clk_div_by_4[5]
|
|
Info (332119): 0.947 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_pcs_clk_div_by_4[6]
|
|
Info (332119): 0.947 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_pcs_clk_div_by_4[7]
|
|
Info (332119): 0.949 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_clk
|
|
Info (332119): 0.949 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|rx_clk
|
|
Info (332119): 0.949 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|rx_clk
|
|
Info (332119): 0.949 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|rx_clk
|
|
Info (332119): 0.949 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|rx_clk
|
|
Info (332119): 0.949 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|rx_clk
|
|
Info (332119): 0.949 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|rx_clk
|
|
Info (332119): 0.949 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|rx_clk
|
|
Info (332119): 0.949 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|rx_pcs_clk_div_by_4[0]
|
|
Info (332119): 0.949 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|rx_pcs_clk_div_by_4[1]
|
|
Info (332119): 0.949 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|rx_pcs_clk_div_by_4[2]
|
|
Info (332119): 0.949 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|rx_pcs_clk_div_by_4[3]
|
|
Info (332119): 0.949 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|rx_pcs_clk_div_by_4[4]
|
|
Info (332119): 0.949 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|rx_pcs_clk_div_by_4[5]
|
|
Info (332119): 0.949 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|rx_pcs_clk_div_by_4[6]
|
|
Info (332119): 0.949 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|rx_pcs_clk_div_by_4[7]
|
|
Info (332119): 0.970 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|hip_cmn_clk[0]
|
|
Info (332119): 1.384 0.000 ETH_RefClk
|
|
Info (332119): 1.539 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|tx_coreclkin
|
|
Info (332119): 1.539 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|tx_coreclkin
|
|
Info (332119): 1.539 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|tx_coreclkin
|
|
Info (332119): 1.539 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|tx_coreclkin
|
|
Info (332119): 1.546 0.000 hssi_pll_r_0_outclk0
|
|
Info (332119): 1.548 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_coreclkin
|
|
Info (332119): 1.548 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|rx_coreclkin
|
|
Info (332119): 1.548 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|rx_coreclkin
|
|
Info (332119): 1.548 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|rx_coreclkin
|
|
Info (332119): 1.554 0.000 hssi_pll_t_outclk0
|
|
Info (332119): 1.563 0.000 mem|ddr4a|ddr4a_core_usr_clk
|
|
Info (332119): 1.652 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|wys~CORE_CLK_OUT
|
|
Info (332119): 1.769 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|tx_pma_clk
|
|
Info (332119): 1.769 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|tx_pma_clk
|
|
Info (332119): 1.769 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|tx_pma_clk
|
|
Info (332119): 1.769 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|tx_pma_clk
|
|
Info (332119): 1.785 0.000 DDR4_RefClk
|
|
Info (332119): 1.824 0.000 mem|ddr4a|ddr4a_phy_clk_l_0
|
|
Info (332119): 1.824 0.000 mem|ddr4a|ddr4a_phy_clk_l_1
|
|
Info (332119): 1.824 0.000 mem|ddr4a|ddr4a_phy_clk_l_2
|
|
Info (332119): 1.824 0.000 mem|ddr4b|ddr4b_phy_clk_l_0
|
|
Info (332119): 1.824 0.000 mem|ddr4b|ddr4b_phy_clk_l_1
|
|
Info (332119): 1.824 0.000 mem|ddr4b|ddr4b_phy_clk_l_2
|
|
Info (332119): 1.852 0.000 hssi_pll_r_0_outclk1
|
|
Info (332119): 1.867 0.000 hssi_pll_t_outclk1
|
|
Info (332119): 1.876 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_clk
|
|
Info (332119): 1.876 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|rx_pma_clk
|
|
Info (332119): 1.876 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|rx_pma_clk
|
|
Info (332119): 1.876 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|rx_pma_clk
|
|
Info (332119): 1.916 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk1
|
|
Info (332119): 1.939 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|pld_clk
|
|
Info (332119): 1.941 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|pma_hclk_by2
|
|
Info (332119): 1.941 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|pma_hclk_by2
|
|
Info (332119): 1.941 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|pma_hclk_by2
|
|
Info (332119): 1.941 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|pma_hclk_by2
|
|
Info (332119): 1.941 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|pma_hclk_by2
|
|
Info (332119): 1.941 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|pma_hclk_by2
|
|
Info (332119): 1.941 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|pma_hclk_by2
|
|
Info (332119): 1.941 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|pma_hclk_by2
|
|
Info (332119): 2.127 0.000 u0|dcp_iopll|dcp_iopll|clk1x
|
|
Info (332119): 2.235 0.000 vl_qph_user_clk_clkpsc_clk1
|
|
Info (332119): 2.939 0.000 mem|ddr4a|ddr4a_core_cal_slave_clk
|
|
Info (332119): 3.157 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_div_clk
|
|
Info (332119): 3.175 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|tx_pma_div_clk
|
|
Info (332119): 3.937 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_clkout
|
|
Info (332119): 3.955 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|tx_clk
|
|
Info (332119): 3.955 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|tx_clk
|
|
Info (332119): 3.955 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|tx_clk
|
|
Info (332119): 3.955 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|tx_clk
|
|
Info (332119): 3.955 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|tx_clk
|
|
Info (332119): 3.955 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|tx_clk
|
|
Info (332119): 3.955 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|tx_clk
|
|
Info (332119): 3.955 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|tx_clk
|
|
Info (332119): 4.500 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk0
|
|
Info (332119): 4.506 0.000 vl_qph_user_clk_clkpsc_clk0
|
|
Info (332119): 4.638 0.000 u0|dcp_iopll|dcp_iopll|clk100
|
|
Info (332119): 4.658 0.000 SYS_RefClk
|
|
Info (332119): 4.666 0.000 PCIE_REFCLK
|
|
Info (332119): 4.945 0.000 pr_clk_enable_dclk_reg2_user_clk
|
|
Info (332119): 4.950 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332119): 4.951 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|rx_fref
|
|
Info (332119): 4.951 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|rx_fref
|
|
Info (332119): 4.951 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|rx_fref
|
|
Info (332119): 4.951 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|rx_fref
|
|
Info (332119): 4.951 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|rx_fref
|
|
Info (332119): 4.951 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|rx_fref
|
|
Info (332119): 4.951 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|rx_fref
|
|
Info (332119): 4.955 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|avmmclk
|
|
Info (332119): 4.955 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|avmmclk
|
|
Info (332119): 4.955 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|avmmclk
|
|
Info (332119): 4.955 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|avmmclk
|
|
Info (332119): 4.955 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|avmmclk
|
|
Info (332119): 4.955 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|avmmclk
|
|
Info (332119): 4.955 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|avmmclk
|
|
Info (332119): 4.955 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|avmmclk
|
|
Info (332119): 4.955 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|avmmclk
|
|
Info (332119): 4.955 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|avmmclk
|
|
Info (332119): 4.955 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|avmmclk
|
|
Info (332119): 4.955 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|avmmclk
|
|
Info (332119): 4.974 0.000 filtered_sclk_negedge
|
|
Info (332119): 9.949 0.000 u0|dcp_iopll|dcp_iopll|clk50
|
|
Info (332119): 19.643 0.000 u0|dcp_iopll|dcp_iopll|clk25
|
|
Info (332119): 19.875 0.000 flash_oe_clk
|
|
Info (332119): 49.802 0.000 altera_reserved_tck
|
|
Info (332119): 124.796 0.000 fspi_sclk
|
|
Info (332119): 500.000 0.000 altera_ts_clk
|
|
Warning (332182): No path is found satisfying assignment "set_max_skew -from [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|tcm_control_out|pio_0|data_out[0]}] -to [get_pins {fpga_top|inst_green_bs|ddr4*_reset_sync|resync_chains[0].synchronizer_nocut|*|clrn}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 ". This assignment will be ignored.
|
|
Info (332115): Worst-case slack is 2.680 for "set_max_skew -from [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Tx_fifo|C1Tx_fifo.inst_async_C1Tx_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Tx_fifo|C1Tx_fifo.inst_async_C1Tx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 "
|
|
Info (332115): Worst-case slack is 2.758 for "set_max_skew -from [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Tx_fifo|C0Tx_fifo.inst_async_C0Tx_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Tx_fifo|C0Tx_fifo.inst_async_C0Tx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 "
|
|
Info (332115): Worst-case slack is 2.870 for "set_max_skew -from [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_CfgTx_fifo|CfgTx_fifo.inst_async_CfgTx_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_CfgTx_fifo|CfgTx_fifo.inst_async_CfgTx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 "
|
|
Info (332115): Worst-case slack is 2.899 for "set_max_skew -from [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Rx_fifo|C0Rx_fifo.inst_async_C0Rx_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Rx_fifo|C0Rx_fifo.inst_async_C0Rx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 "
|
|
Info (332115): Worst-case slack is 2.928 for "set_max_skew -from [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Rx_fifo|C1Rx_fifo.inst_async_C1Rx_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Rx_fifo|C1Rx_fifo.inst_async_C1Rx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 "
|
|
Info (332115): Worst-case slack is 2.993 for "set_max_skew -from [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_msix_top|msix_brid|msix_dcfifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_msix_top|msix_brid|msix_dcfifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 "
|
|
Info (332115): Worst-case slack is 3.212 for "set_max_skew -from [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 "
|
|
Info (332115): Worst-case slack is 3.215 for "set_max_skew -from [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 "
|
|
Info (332115): Worst-case slack is 3.270 for "set_max_skew -from [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 "
|
|
Info (332115): Worst-case slack is 3.270 for "set_max_skew -from [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Tx_fifo|C0Tx_fifo.inst_async_C0Tx_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Tx_fifo|C0Tx_fifo.inst_async_C0Tx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 "
|
|
Info (332115): Worst-case slack is 3.293 for "set_max_skew -from [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 "
|
|
Info (332115): Worst-case slack is 3.307 for "set_max_skew -from [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 "
|
|
Info (332115): Worst-case slack is 3.345 for "set_max_skew -from [get_keepers {fpga_top|inst_blue_ccip_interface_reg|pck_cp2af_softReset_T0_q}] -to [get_pins {fpga_top|inst_green_bs|ddr4*_reset_sync|resync_chains[0].synchronizer_nocut|*|clrn}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 "
|
|
Info (332115): Worst-case slack is 3.382 for "set_max_skew -from [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 "
|
|
Info (332115): Worst-case slack is 3.490 for "set_max_skew -from [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Rx_fifo|C0Rx_fifo.inst_async_C0Rx_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Rx_fifo|C0Rx_fifo.inst_async_C0Rx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 "
|
|
Info (332115): Worst-case slack is 3.498 for "set_max_skew -from [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 "
|
|
Info (332115): Worst-case slack is 3.504 for "set_max_skew -from [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 "
|
|
Info (332115): Worst-case slack is 3.554 for "set_max_skew -from [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_CfgTx_fifo|CfgTx_fifo.inst_async_CfgTx_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_CfgTx_fifo|CfgTx_fifo.inst_async_CfgTx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 "
|
|
Info (332115): Worst-case slack is 3.555 for "set_max_skew -from [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Tx_fifo|C1Tx_fifo.inst_async_C1Tx_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Tx_fifo|C1Tx_fifo.inst_async_C1Tx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 "
|
|
Info (332115): Worst-case slack is 3.562 for "set_max_skew -from [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 "
|
|
Info (332115): Worst-case slack is 3.608 for "set_max_skew -from [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Rx_fifo|C1Rx_fifo.inst_async_C1Rx_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Rx_fifo|C1Rx_fifo.inst_async_C1Rx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 "
|
|
Info (332115): Worst-case slack is 3.609 for "set_max_skew -from [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 "
|
|
Info (332115): Worst-case slack is 3.613 for "set_max_skew -from [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_msix_top|msix_brid|msix_dcfifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_msix_top|msix_brid|msix_dcfifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 "
|
|
Info (332115): Worst-case slack is 3.656 for "set_max_skew -from [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|ddr_backchannel|mm_clock_crossing_bridge_0|rsp_fifo|out_rd_ptr_gray[*]}] -to [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|ddr_backchannel|mm_clock_crossing_bridge_0|rsp_fifo|read_crosser|sync[*].u|din_s1}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 "
|
|
Info (332115): Worst-case slack is 3.661 for "set_max_skew -from [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|ddr_backchannel|mm_clock_crossing_bridge_0|cmd_fifo|in_wr_ptr_gray[*]}] -to [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|ddr_backchannel|mm_clock_crossing_bridge_0|cmd_fifo|write_crosser|sync[*].u|din_s1}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 "
|
|
Info (332115): Worst-case slack is 7.610 for "set_max_skew -from [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|ddr_backchannel|mm_clock_crossing_bridge_0|cmd_fifo|out_rd_ptr_gray[*]}] -to [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|ddr_backchannel|mm_clock_crossing_bridge_0|cmd_fifo|read_crosser|sync[*].u|din_s1}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 "
|
|
Info (332115): Worst-case slack is 7.637 for "set_max_skew -from [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|ddr_backchannel|mm_clock_crossing_bridge_0|rsp_fifo|in_wr_ptr_gray[*]}] -to [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|ddr_backchannel|mm_clock_crossing_bridge_0|rsp_fifo|write_crosser|sync[*].u|din_s1}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 "
|
|
Info (332115): Worst-case slack is 7.665 for "set_max_skew -from [get_registers {auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|stfabric|t2h0_fifo|in_wr_ptr_gray[*]}] -to [get_registers {auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|stfabric|t2h0_fifo|write_crosser|sync[*].u|din_s1}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 "
|
|
Info (332115): Worst-case slack is 7.701 for "set_max_skew -from [get_registers {auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|stfabric|h2t0_fifo|out_rd_ptr_gray[*]}] -to [get_registers {auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|stfabric|h2t0_fifo|read_crosser|sync[*].u|din_s1}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 "
|
|
Info (332115): Worst-case slack is 7.702 for "set_max_skew -from [get_registers {auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|stfabric|t2h0_fifo|out_rd_ptr_gray[*]}] -to [get_registers {auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|stfabric|t2h0_fifo|read_crosser|sync[*].u|din_s1}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 "
|
|
Info (332115): Worst-case slack is 7.720 for "set_max_skew -from [get_registers {auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|stfabric|h2t0_fifo|in_wr_ptr_gray[*]}] -to [get_registers {auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|stfabric|h2t0_fifo|write_crosser|sync[*].u|din_s1}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 "
|
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Info (332163): Fast 900mV 100C Model Net Delay Summary
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Info (332163): Name Slack Req Actual From To Type
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Info (332163): ============= ====== ====== ====== =============== =============== ====
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Info (332163): set_net_delay 1.747 3.001 1.254 [get_pins -compatibility_mode {*|out_rd_ptr_gray[*]*}]
|
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Info (332163): [get_registers {*|platform_utils_dcfifo_synchronizer_bundle:read_crosser|platform_utils_std_synchronizer_nocut:sync[*].u|din_s1}]
|
|
Info (332163): max
|
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Info (332163): set_net_delay 2.510 3.200 0.690 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Rx_fifo|C1Rx_fifo.inst_async_C1Rx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Rx_fifo|C1Rx_fifo.inst_async_C1Rx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
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Info (332163): set_net_delay 2.523 3.636 1.113 [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 2.536 3.200 0.664 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Tx_fifo|C0Tx_fifo.inst_async_C0Tx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Tx_fifo|C0Tx_fifo.inst_async_C0Tx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
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Info (332163): set_net_delay 2.545 3.200 0.655 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Tx_fifo|C1Tx_fifo.inst_async_C1Tx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}]
|
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Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Tx_fifo|C1Tx_fifo.inst_async_C1Tx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
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Info (332163): set_net_delay 2.587 3.001 0.414 [get_pins -compatibility_mode {*|in_wr_ptr_gray[*]*}]
|
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Info (332163): [get_registers {*|platform_utils_dcfifo_synchronizer_bundle:write_crosser|platform_utils_std_synchronizer_nocut:sync[*].u|din_s1}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 2.648 4.000 1.352 [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser|async_clock_crosser.clock_xer|out_data_toggle_flopped}]
|
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Info (332163): [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser|async_clock_crosser.clock_xer|out_to_in_synchronizer|din_s1}]
|
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Info (332163): max
|
|
Info (332163): set_net_delay 2.712 3.200 0.488 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Rx_fifo|C0Rx_fifo.inst_async_C0Rx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Rx_fifo|C0Rx_fifo.inst_async_C0Rx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 2.715 3.200 0.485 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_CfgTx_fifo|CfgTx_fifo.inst_async_CfgTx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_CfgTx_fifo|CfgTx_fifo.inst_async_CfgTx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 2.751 3.200 0.449 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Tx_fifo|C0Tx_fifo.inst_async_C0Tx_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Tx_fifo|C0Tx_fifo.inst_async_C0Tx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 2.793 3.200 0.407 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Rx_fifo|C0Rx_fifo.inst_async_C0Rx_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Rx_fifo|C0Rx_fifo.inst_async_C0Rx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 2.807 3.200 0.393 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_msix_top|msix_brid|msix_dcfifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_msix_top|msix_brid|msix_dcfifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 2.855 3.200 0.345 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_CfgTx_fifo|CfgTx_fifo.inst_async_CfgTx_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_CfgTx_fifo|CfgTx_fifo.inst_async_CfgTx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 2.856 3.200 0.344 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Tx_fifo|C1Tx_fifo.inst_async_C1Tx_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Tx_fifo|C1Tx_fifo.inst_async_C1Tx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 2.871 3.200 0.329 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Rx_fifo|C1Rx_fifo.inst_async_C1Rx_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Rx_fifo|C1Rx_fifo.inst_async_C1Rx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 2.873 3.636 0.763 [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 2.877 3.200 0.323 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_msix_top|msix_brid|msix_dcfifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_msix_top|msix_brid|msix_dcfifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 2.899 3.636 0.737 [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 2.913 3.636 0.723 [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 2.940 4.000 1.060 [get_registers {*altera_avalon_st_clock_crosser:*|in_data_buffer*}]
|
|
Info (332163): [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_005|async_clock_crosser.clock_xer|out_data_buffer*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 2.948 4.000 1.052 [get_registers {*altera_avalon_st_clock_crosser:*|in_data_buffer*}]
|
|
Info (332163): [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_004|async_clock_crosser.clock_xer|out_data_buffer*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 2.985 3.636 0.651 [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 3.107 4.000 0.893 [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_003|async_clock_crosser.clock_xer|out_data_toggle_flopped}]
|
|
Info (332163): [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_003|async_clock_crosser.clock_xer|out_to_in_synchronizer|din_s1}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 3.119 3.636 0.517 [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|delayed_wrptr_g*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 3.142 4.000 0.858 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Tx_fifo|C1Tx_fifo.inst_async_C1Tx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Tx_fifo|C1Tx_fifo.inst_async_C1Tx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 3.189 4.000 0.811 [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_004|async_clock_crosser.clock_xer|in_data_toggle}]
|
|
Info (332163): [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_004|async_clock_crosser.clock_xer|in_to_out_synchronizer|din_s1}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 3.218 4.000 0.782 [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 3.222 4.000 0.778 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Rx_fifo|C0Rx_fifo.inst_async_C0Rx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Rx_fifo|C0Rx_fifo.inst_async_C0Rx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 3.225 3.636 0.411 [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|*rdptr_g*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 3.244 4.000 0.756 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Tx_fifo|C0Tx_fifo.inst_async_C0Tx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Tx_fifo|C0Tx_fifo.inst_async_C0Tx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 3.251 4.000 0.749 [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_001|async_clock_crosser.clock_xer|out_data_toggle_flopped}]
|
|
Info (332163): [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_001|async_clock_crosser.clock_xer|out_to_in_synchronizer|din_s1}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 3.267 3.636 0.369 [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|delayed_wrptr_g*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 3.273 3.636 0.363 [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|*rdptr_g*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 3.285 4.000 0.715 [get_registers {*altera_avalon_st_clock_crosser:*|in_data_buffer*}]
|
|
Info (332163): [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_006|async_clock_crosser.clock_xer|out_data_buffer*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 3.308 3.636 0.328 [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|*rdptr_g*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 3.337 4.000 0.663 [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 3.417 4.000 0.583 [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 3.444 4.000 0.556 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Rx_fifo|C1Rx_fifo.inst_async_C1Rx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Rx_fifo|C1Rx_fifo.inst_async_C1Rx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 3.450 4.000 0.550 [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 3.452 4.000 0.548 [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 3.461 4.000 0.539 [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|delayed_wrptr_g*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 3.517 4.000 0.483 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_CfgTx_fifo|CfgTx_fifo.inst_async_CfgTx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_CfgTx_fifo|CfgTx_fifo.inst_async_CfgTx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 3.542 4.000 0.458 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Tx_fifo|C1Tx_fifo.inst_async_C1Tx_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Tx_fifo|C1Tx_fifo.inst_async_C1Tx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 3.544 4.000 0.456 [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_002|async_clock_crosser.clock_xer|out_data_toggle_flopped}]
|
|
Info (332163): [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_002|async_clock_crosser.clock_xer|out_to_in_synchronizer|din_s1}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 3.569 4.000 0.431 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_msix_top|msix_brid|msix_dcfifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_msix_top|msix_brid|msix_dcfifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 3.570 4.000 0.430 [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|*rdptr_g*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 3.585 4.000 0.415 [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_005|async_clock_crosser.clock_xer|in_data_toggle}]
|
|
Info (332163): [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_005|async_clock_crosser.clock_xer|in_to_out_synchronizer|din_s1}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 3.615 4.000 0.385 [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|*rdptr_g*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 3.619 4.000 0.381 [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_007|async_clock_crosser.clock_xer|in_data_toggle}]
|
|
Info (332163): [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_007|async_clock_crosser.clock_xer|in_to_out_synchronizer|din_s1}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 3.630 4.000 0.370 [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|delayed_wrptr_g*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 3.646 4.000 0.354 [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_006|async_clock_crosser.clock_xer|in_data_toggle}]
|
|
Info (332163): [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_006|async_clock_crosser.clock_xer|in_to_out_synchronizer|din_s1}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 3.647 4.000 0.353 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_CfgTx_fifo|CfgTx_fifo.inst_async_CfgTx_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_CfgTx_fifo|CfgTx_fifo.inst_async_CfgTx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 3.662 4.000 0.338 [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|delayed_wrptr_g*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 3.670 4.000 0.330 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Rx_fifo|C0Rx_fifo.inst_async_C0Rx_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Rx_fifo|C0Rx_fifo.inst_async_C0Rx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 3.700 4.000 0.300 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Tx_fifo|C0Tx_fifo.inst_async_C0Tx_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Tx_fifo|C0Tx_fifo.inst_async_C0Tx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 3.709 4.000 0.291 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_msix_top|msix_brid|msix_dcfifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_msix_top|msix_brid|msix_dcfifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 3.718 4.000 0.282 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Rx_fifo|C1Rx_fifo.inst_async_C1Rx_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Rx_fifo|C1Rx_fifo.inst_async_C1Rx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 3.755 4.000 0.245 [get_pins -compatibility_mode {*|out_rd_ptr_gray[*]*}]
|
|
Info (332163): [get_registers {*|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer_nocut:sync[*].u|din_s1}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 3.797 4.000 0.203 [get_pins -compatibility_mode {*|in_wr_ptr_gray[*]*}]
|
|
Info (332163): [get_registers {*|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer_nocut:sync[*].u|din_s1}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 6.064 8.000 1.936 [get_registers {*altera_avalon_st_clock_crosser:*|in_data_buffer*}]
|
|
Info (332163): [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_003|async_clock_crosser.clock_xer|out_data_buffer*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 6.339 8.000 1.661 [get_registers {*altera_avalon_st_clock_crosser:*|in_data_buffer*}]
|
|
Info (332163): [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_002|async_clock_crosser.clock_xer|out_data_buffer*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 6.862 8.000 1.138 [get_registers {auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|host_link_jtag|jtag|normal.jtag_dc_streaming|sink_crosser|out_data_toggle_flopped}]
|
|
Info (332163): [get_registers {auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|host_link_jtag|jtag|normal.jtag_dc_streaming|sink_crosser|out_to_in_synchronizer|din_s1}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 7.333 8.000 0.667 [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_002|async_clock_crosser.clock_xer|in_data_toggle}]
|
|
Info (332163): [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_002|async_clock_crosser.clock_xer|in_to_out_synchronizer|din_s1}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 7.402 8.000 0.598 [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_006|async_clock_crosser.clock_xer|out_data_toggle_flopped}]
|
|
Info (332163): [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_006|async_clock_crosser.clock_xer|out_to_in_synchronizer|din_s1}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 7.587 8.000 0.413 [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_003|async_clock_crosser.clock_xer|in_data_toggle}]
|
|
Info (332163): [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_003|async_clock_crosser.clock_xer|in_to_out_synchronizer|din_s1}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 7.670 8.000 0.330 [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_007|async_clock_crosser.clock_xer|out_data_toggle_flopped}]
|
|
Info (332163): [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_007|async_clock_crosser.clock_xer|out_to_in_synchronizer|din_s1}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 30.849 32.000 1.151 [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser|async_clock_crosser.clock_xer|in_data_toggle}]
|
|
Info (332163): [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser|async_clock_crosser.clock_xer|in_to_out_synchronizer|din_s1}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 30.916 32.000 1.084 [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_005|async_clock_crosser.clock_xer|out_data_toggle_flopped}]
|
|
Info (332163): [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_005|async_clock_crosser.clock_xer|out_to_in_synchronizer|din_s1}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 31.123 32.000 0.877 [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_004|async_clock_crosser.clock_xer|out_data_toggle_flopped}]
|
|
Info (332163): [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_004|async_clock_crosser.clock_xer|out_to_in_synchronizer|din_s1}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 31.154 32.000 0.846 [get_registers {*altera_avalon_st_clock_crosser:*|in_data_buffer*}]
|
|
Info (332163): [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_001|async_clock_crosser.clock_xer|out_data_buffer*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 31.305 32.000 0.695 [get_registers {*altera_avalon_st_clock_crosser:*|in_data_buffer*}]
|
|
Info (332163): [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser|async_clock_crosser.clock_xer|out_data_buffer*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 31.541 32.000 0.459 [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_001|async_clock_crosser.clock_xer|in_data_toggle}]
|
|
Info (332163): [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_001|async_clock_crosser.clock_xer|in_to_out_synchronizer|din_s1}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 75.573 80.000 4.427 [get_registers {auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|host_link_jtag|jtag|normal.jtag_dc_streaming|sink_crosser|in_data_toggle}]
|
|
Info (332163): [get_registers {auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|host_link_jtag|jtag|normal.jtag_dc_streaming|sink_crosser|in_to_out_synchronizer|din_s1}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 79.226 80.000 0.774 [get_registers {*altera_avalon_st_clock_crosser:*|in_data_buffer*}]
|
|
Info (332163): [get_registers {auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|host_link_jtag|jtag|normal.jtag_dc_streaming|sink_crosser|out_data_buffer*}]
|
|
Info (332163): max
|
|
Info (332114): Report Metastability: Found 403 synchronizer chains.
|
|
Info (332114): Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds.
|
|
Info (332114): Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.
|
|
|
|
Info (332114): Number of Synchronizer Chains Found: 403
|
|
Info (332114): Shortest Synchronizer Chain: 2 Registers
|
|
Info (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 0.258
|
|
Info (332114): Worst Case Available Settling Time: 3.591 ns
|
|
Info (332114): Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions.
|
|
Info (332114): - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 288.8
|
|
Info (332114): Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions.
|
|
Info (332114): - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 4590.3
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 0.162
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk1}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 0.162
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|mem_unit|icache|[0].bank|core_rsp_req|shift_reg[0][28]
|
|
Info (332115): To Node : fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|issue|ibuffer|q_data_out[2][8]
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk1
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk1
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 4.196 4.196 R clock network delay
|
|
Info (332115): 4.196 0.000 fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|mem_unit|icache|[0].bank|core_rsp_req|shift_reg[0][28]
|
|
Info (332115): 4.316 0.120 FF uTco fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|mem_unit|icache|[0].bank|core_rsp_req|shift_reg[0][28]|q
|
|
Info (332115): 4.360 0.044 FF CELL High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|mem_unit|icache|[0].bank|core_rsp_req|shift_reg[0][28]~la_lab/laboutt[17]
|
|
Info (332115): 4.924 0.564 FF IC High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|mem_unit|icache|[0].bank|core_rsp_req|data_out[28]~14|datad
|
|
Info (332115): 4.997 0.073 FF CELL High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|mem_unit|icache|[0].bank|core_rsp_req|data_out[28]~14|combout
|
|
Info (332115): 5.002 0.005 FF CELL High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|mem_unit|icache|[0].bank|core_rsp_req|data_out[28]~14~la_lab/laboutb[11]
|
|
Info (332115): 6.134 1.132 FF IC High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|decode|reduce_or_12~0|datab
|
|
Info (332115): 6.255 0.121 FR CELL High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|decode|reduce_or_12~0|combout
|
|
Info (332115): 6.260 0.005 RR CELL High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|decode|reduce_or_12~0~la_lab/laboutt[11]
|
|
Info (332115): 6.379 0.119 RR IC High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|decode|Select_52~3|dataf
|
|
Info (332115): 6.405 0.026 RR CELL High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|decode|Select_52~3|combout
|
|
Info (332115): 6.409 0.004 RR CELL High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|decode|Select_52~3~la_lab/laboutb[4]
|
|
Info (332115): 6.553 0.144 RR IC High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|decode|shift_left_0~20|dataf
|
|
Info (332115): 6.580 0.027 RF CELL High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|decode|shift_left_0~20|combout
|
|
Info (332115): 6.584 0.004 FF CELL High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|decode|shift_left_0~20~la_lab/laboutt[8]
|
|
Info (332115): 7.544 0.960 FF IC High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|decode|i571~1|dataf
|
|
Info (332115): 7.573 0.029 FF CELL High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|decode|i571~1|combout
|
|
Info (332115): 7.578 0.005 FF CELL High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|decode|i571~1~la_mlab/laboutb[12]
|
|
Info (332115): 7.718 0.140 FF IC High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|decode|i571~0|dataf
|
|
Info (332115): 7.744 0.026 FF CELL High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|decode|i571~0|combout
|
|
Info (332115): 7.749 0.005 FF CELL High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|decode|i571~0~la_mlab/laboutt[10]
|
|
Info (332115): 8.668 0.919 FF IC High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|issue|ibuffer|q_data_out[2][8]|asdata
|
|
Info (332115): 8.668 0.000 FF CELL High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|issue|ibuffer|q_data_out[2][8]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 4.545 4.545 latch edge time
|
|
Info (332115): 8.117 3.572 R clock network delay
|
|
Info (332115): 8.756 0.639 clock pessimism removed
|
|
Info (332115): 8.726 -0.030 clock uncertainty
|
|
Info (332115): 8.830 0.104 uTsu fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|issue|ibuffer|q_data_out[2][8]
|
|
Info (332115): Data Arrival Time : 8.668
|
|
Info (332115): Data Required Time : 8.830
|
|
Info (332115): Slack : 0.162
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 0.799
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_bonding_clocks[0]}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 0.799
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|sta_rx_clk2_by4_1
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs~byte_deserializer_pcs_clk_div_by_4_txclk_reg.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|rx_clk (INVERTED)
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_bonding_clocks[0]
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 1.000 1.000 launch edge time
|
|
Info (332115): 3.594 2.594 F clock network delay
|
|
Info (332115): 3.594 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|sta_rx_clk2_by4_1
|
|
Info (332115): 3.594 0.000 FF CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs~byte_deserializer_pcs_clk_div_by_4_txclk_reg.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 2.000 2.000 latch edge time
|
|
Info (332115): 3.592 1.592 R clock network delay
|
|
Info (332115): 4.362 0.770 clock pessimism removed
|
|
Info (332115): 4.393 0.031 uTsu fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs~byte_deserializer_pcs_clk_div_by_4_txclk_reg.reg
|
|
Info (332115): Data Arrival Time : 3.594
|
|
Info (332115): Data Required Time : 4.393
|
|
Info (332115): Slack : 0.799
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 1.057
|
|
Info (20696): -to_clock [get_clocks {mem|ddr4a|ddr4a_core_usr_clk}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 1.057
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_green_bs|ddr4a_avmm_bridge|ddr_avmm_bridge|rsp_readdata[450]
|
|
Info (332115): To Node : fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_avalon_mem_if|c.mm_async[0].mem_async_shim|avmm_cross|rsp_fifo|mem_rtl_0|auto_generated|ram_block1a450~reg0
|
|
Info (332115): Launch Clock : mem|ddr4a|ddr4a_core_usr_clk
|
|
Info (332115): Latch Clock : mem|ddr4a|ddr4a_core_usr_clk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.117 0.117 launch edge time
|
|
Info (332115): 1.961 1.844 R clock network delay
|
|
Info (332115): 1.961 0.000 fpga_top|inst_green_bs|ddr4a_avmm_bridge|ddr_avmm_bridge|rsp_readdata[450]
|
|
Info (332115): 2.297 0.336 FF uTco fpga_top|inst_green_bs|ddr4a_avmm_bridge|ddr_avmm_bridge|rsp_readdata[450]|q
|
|
Info (332115): 2.346 0.049 FF CELL High Speed fpga_top|inst_green_bs|ddr4a_avmm_bridge|ddr_avmm_bridge|rsp_readdata[450]~la_lab/laboutb[1]
|
|
Info (332115): 4.593 2.247 FF IC High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_avalon_mem_if|c.mm_async[0].mem_async_shim|avmm_cross|rsp_fifo|mem_rtl_0|auto_generated|ram_block1a450|portadatain[0]
|
|
Info (332115): 4.593 0.000 FF CELL High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_avalon_mem_if|c.mm_async[0].mem_async_shim|avmm_cross|rsp_fifo|mem_rtl_0|auto_generated|ram_block1a450~reg0
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 3.869 3.869 latch edge time
|
|
Info (332115): 5.161 1.292 R clock network delay
|
|
Info (332115): 5.554 0.393 clock pessimism removed
|
|
Info (332115): 5.524 -0.030 clock uncertainty
|
|
Info (332115): 5.650 0.126 uTsu fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_avalon_mem_if|c.mm_async[0].mem_async_shim|avmm_cross|rsp_fifo|mem_rtl_0|auto_generated|ram_block1a450~reg0
|
|
Info (332115): Data Arrival Time : 4.593
|
|
Info (332115): Data Required Time : 5.650
|
|
Info (332115): Slack : 1.057
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 1.077
|
|
Info (20696): -to_clock [get_clocks {mem|ddr4a|ddr4a_phy_clk_l_2}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 1.077
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : mem|ddr4a_avmm_chkr|clearing
|
|
Info (332115): To Node : mem|ddr4a|ddr4a|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[0].lane_gen[2].lane_inst~phy_reg1
|
|
Info (332115): Launch Clock : mem|ddr4a|ddr4a_core_usr_clk
|
|
Info (332115): Latch Clock : mem|ddr4a|ddr4a_phy_clk_l_2
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.117 0.117 launch edge time
|
|
Info (332115): 1.933 1.816 R clock network delay
|
|
Info (332115): 1.933 0.000 mem|ddr4a_avmm_chkr|clearing
|
|
Info (332115): 2.054 0.121 RR uTco mem|ddr4a_avmm_chkr|clearing|q
|
|
Info (332115): 2.124 0.070 RR CELL High Speed mem|ddr4a_avmm_chkr|clearing~la_mlab/laboutt[13]
|
|
Info (332115): 3.039 0.915 RR IC High Speed mem|ddr4a_avmm_chkr|avm_writedata[23]~184|dataf
|
|
Info (332115): 3.068 0.029 RF CELL High Speed mem|ddr4a_avmm_chkr|avm_writedata[23]~184|combout
|
|
Info (332115): 3.072 0.004 FF CELL High Speed mem|ddr4a_avmm_chkr|avm_writedata[23]~184~la_lab/laboutb[2]
|
|
Info (332115): 4.018 0.946 FF IC High Speed mem|ddr4a|ddr4a|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[0].lane_gen[2].lane_inst|data_from_core[0]
|
|
Info (332115): 4.018 0.000 FF CELL mem|ddr4a|ddr4a|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[0].lane_gen[2].lane_inst~phy_reg1
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 3.869 3.869 latch edge time
|
|
Info (332115): 5.162 1.293 R clock network delay
|
|
Info (332115): 5.247 0.085 clock pessimism removed
|
|
Info (332115): 4.958 -0.289 clock uncertainty
|
|
Info (332115): 5.095 0.137 uTsu mem|ddr4a|ddr4a|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[0].lane_gen[2].lane_inst~phy_reg1
|
|
Info (332115): Data Arrival Time : 4.018
|
|
Info (332115): Data Required Time : 5.095
|
|
Info (332115): Slack : 1.077
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 1.096
|
|
Info (20696): -to_clock [get_clocks {mem|ddr4a|ddr4a_phy_clk_l_1}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 1.096
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : mem|ddr4a_avmm_chkr|clearing
|
|
Info (332115): To Node : mem|ddr4a|ddr4a|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[1].lane_gen[3].lane_inst~phy_reg1
|
|
Info (332115): Launch Clock : mem|ddr4a|ddr4a_core_usr_clk
|
|
Info (332115): Latch Clock : mem|ddr4a|ddr4a_phy_clk_l_1
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.117 0.117 launch edge time
|
|
Info (332115): 1.933 1.816 R clock network delay
|
|
Info (332115): 1.933 0.000 mem|ddr4a_avmm_chkr|clearing
|
|
Info (332115): 2.054 0.121 RR uTco mem|ddr4a_avmm_chkr|clearing|q
|
|
Info (332115): 2.124 0.070 RR CELL High Speed mem|ddr4a_avmm_chkr|clearing~la_mlab/laboutt[13]
|
|
Info (332115): 3.041 0.917 RR IC High Speed mem|ddr4a_avmm_chkr|avm_writedata[416]~262|dataf
|
|
Info (332115): 3.068 0.027 RF CELL High Speed mem|ddr4a_avmm_chkr|avm_writedata[416]~262|combout
|
|
Info (332115): 3.073 0.005 FF CELL High Speed mem|ddr4a_avmm_chkr|avm_writedata[416]~262~la_lab/laboutb[9]
|
|
Info (332115): 4.014 0.941 FF IC High Speed mem|ddr4a|ddr4a|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[1].lane_gen[3].lane_inst|data_from_core[78]
|
|
Info (332115): 4.014 0.000 FF CELL mem|ddr4a|ddr4a|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[1].lane_gen[3].lane_inst~phy_reg1
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 3.869 3.869 latch edge time
|
|
Info (332115): 5.167 1.298 R clock network delay
|
|
Info (332115): 5.252 0.085 clock pessimism removed
|
|
Info (332115): 4.963 -0.289 clock uncertainty
|
|
Info (332115): 5.110 0.147 uTsu mem|ddr4a|ddr4a|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[1].lane_gen[3].lane_inst~phy_reg1
|
|
Info (332115): Data Arrival Time : 4.014
|
|
Info (332115): Data Required Time : 5.110
|
|
Info (332115): Slack : 1.096
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 1.133
|
|
Info (20696): -to_clock [get_clocks {mem|ddr4b|ddr4b_phy_clk_l_1}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 1.133
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : mem|ddr4b_avmm_chkr|clearing
|
|
Info (332115): To Node : mem|ddr4b|ddr4b|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[1].lane_gen[3].lane_inst~phy_reg1
|
|
Info (332115): Launch Clock : mem|ddr4a|ddr4a_core_usr_clk
|
|
Info (332115): Latch Clock : mem|ddr4b|ddr4b_phy_clk_l_1
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.117 0.117 launch edge time
|
|
Info (332115): 1.835 1.718 R clock network delay
|
|
Info (332115): 1.835 0.000 mem|ddr4b_avmm_chkr|clearing
|
|
Info (332115): 1.956 0.121 RR uTco mem|ddr4b_avmm_chkr|clearing|q
|
|
Info (332115): 2.024 0.068 RR CELL High Speed mem|ddr4b_avmm_chkr|clearing~la_lab/laboutb[17]
|
|
Info (332115): 3.012 0.988 RR IC High Speed mem|ddr4b_avmm_chkr|avm_writedata[0]~260|dataf
|
|
Info (332115): 3.039 0.027 RF CELL High Speed mem|ddr4b_avmm_chkr|avm_writedata[0]~260|combout
|
|
Info (332115): 3.044 0.005 FF CELL High Speed mem|ddr4b_avmm_chkr|avm_writedata[0]~260~la_lab/laboutb[5]
|
|
Info (332115): 3.905 0.861 FF IC High Speed mem|ddr4b|ddr4b|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[1].lane_gen[3].lane_inst|data_from_core[76]
|
|
Info (332115): 3.905 0.000 FF CELL mem|ddr4b|ddr4b|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[1].lane_gen[3].lane_inst~phy_reg1
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 3.869 3.869 latch edge time
|
|
Info (332115): 5.134 1.265 R clock network delay
|
|
Info (332115): 5.181 0.047 clock pessimism removed
|
|
Info (332115): 4.892 -0.289 clock uncertainty
|
|
Info (332115): 5.038 0.146 uTsu mem|ddr4b|ddr4b|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[1].lane_gen[3].lane_inst~phy_reg1
|
|
Info (332115): Data Arrival Time : 3.905
|
|
Info (332115): Data Required Time : 5.038
|
|
Info (332115): Slack : 1.133
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 1.223
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|wys~CORE_CLK_OUT}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 1.223
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|avl_cci_bridge|b2c_rx_data[49]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Rx_fifo|C0Rx_fifo.inst_async_C0Rx_fifo|fifo_0|dcfifo_component|auto_generated|fifo_ram|ram_block1a83~reg0
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|wys~CORE_CLK_OUT
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|wys~CORE_CLK_OUT
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 5.816 5.816 R clock network delay
|
|
Info (332115): 5.816 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|avl_cci_bridge|b2c_rx_data[49]
|
|
Info (332115): 5.957 0.141 FF uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|avl_cci_bridge|b2c_rx_data[49]|q
|
|
Info (332115): 6.028 0.071 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|avl_cci_bridge|b2c_rx_data[49]~la_mlab/laboutt[4]
|
|
Info (332115): 8.620 2.592 FF IC Mixed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Rx_fifo|C0Rx_fifo.inst_async_C0Rx_fifo|fifo_0|dcfifo_component|auto_generated|fifo_ram|ram_block1a83|portadatain[0]
|
|
Info (332115): 8.620 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Rx_fifo|C0Rx_fifo.inst_async_C0Rx_fifo|fifo_0|dcfifo_component|auto_generated|fifo_ram|ram_block1a83~reg0
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 4.000 4.000 latch edge time
|
|
Info (332115): 8.888 4.888 R clock network delay
|
|
Info (332115): 9.718 0.830 clock pessimism removed
|
|
Info (332115): 9.843 0.125 uTsu fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Rx_fifo|C0Rx_fifo.inst_async_C0Rx_fifo|fifo_0|dcfifo_component|auto_generated|fifo_ram|ram_block1a83~reg0
|
|
Info (332115): Data Arrival Time : 8.620
|
|
Info (332115): Data Required Time : 9.843
|
|
Info (332115): Slack : 1.223
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 1.333
|
|
Info (20696): -to_clock [get_clocks {mem|ddr4b|ddr4b_phy_clk_l_2}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 1.333
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : mem|ddr4b_avmm_chkr|clearing
|
|
Info (332115): To Node : mem|ddr4b|ddr4b|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[0].lane_gen[1].lane_inst~phy_reg1
|
|
Info (332115): Launch Clock : mem|ddr4a|ddr4a_core_usr_clk
|
|
Info (332115): Latch Clock : mem|ddr4b|ddr4b_phy_clk_l_2
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.117 0.117 launch edge time
|
|
Info (332115): 1.835 1.718 R clock network delay
|
|
Info (332115): 1.835 0.000 mem|ddr4b_avmm_chkr|clearing
|
|
Info (332115): 1.956 0.121 RR uTco mem|ddr4b_avmm_chkr|clearing|q
|
|
Info (332115): 2.024 0.068 RR CELL High Speed mem|ddr4b_avmm_chkr|clearing~la_lab/laboutb[17]
|
|
Info (332115): 2.875 0.851 RR IC High Speed mem|ddr4b_avmm_chkr|avm_writedata[0]~111|datae
|
|
Info (332115): 2.953 0.078 RF CELL High Speed mem|ddr4b_avmm_chkr|avm_writedata[0]~111|combout
|
|
Info (332115): 2.959 0.006 FF CELL High Speed mem|ddr4b_avmm_chkr|avm_writedata[0]~111~la_mlab/laboutb[16]
|
|
Info (332115): 3.709 0.750 FF IC High Speed mem|ddr4b|ddr4b|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[0].lane_gen[1].lane_inst|data_from_core[7]
|
|
Info (332115): 3.709 0.000 FF CELL mem|ddr4b|ddr4b|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[0].lane_gen[1].lane_inst~phy_reg1
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 3.869 3.869 latch edge time
|
|
Info (332115): 5.132 1.263 R clock network delay
|
|
Info (332115): 5.179 0.047 clock pessimism removed
|
|
Info (332115): 4.890 -0.289 clock uncertainty
|
|
Info (332115): 5.042 0.152 uTsu mem|ddr4b|ddr4b|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[0].lane_gen[1].lane_inst~phy_reg1
|
|
Info (332115): Data Arrival Time : 3.709
|
|
Info (332115): Data Required Time : 5.042
|
|
Info (332115): Slack : 1.333
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 1.408
|
|
Info (20696): -to_clock [get_clocks {mem|ddr4b|ddr4b_phy_clk_l_0}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 1.408
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : mem|ddr4b_bridge|ddr_avmm_bridge|cmd_burstcount[6]
|
|
Info (332115): To Node : mem|ddr4b|ddr4b|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[1].tile_ctrl_inst~hmc_reg1
|
|
Info (332115): Launch Clock : mem|ddr4a|ddr4a_core_usr_clk
|
|
Info (332115): Latch Clock : mem|ddr4b|ddr4b_phy_clk_l_0
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.117 0.117 launch edge time
|
|
Info (332115): 1.838 1.721 R clock network delay
|
|
Info (332115): 1.838 0.000 mem|ddr4b_bridge|ddr_avmm_bridge|cmd_burstcount[6]
|
|
Info (332115): 1.960 0.122 RR uTco mem|ddr4b_bridge|ddr_avmm_bridge|cmd_burstcount[6]|q
|
|
Info (332115): 2.030 0.070 RR CELL High Speed mem|ddr4b_bridge|ddr_avmm_bridge|cmd_burstcount[6]~la_mlab/laboutb[5]
|
|
Info (332115): 2.358 0.328 RR IC High Speed mem|ddr4b_avmm_chkr|LessThan_0~0|datab
|
|
Info (332115): 2.471 0.113 RF CELL High Speed mem|ddr4b_avmm_chkr|LessThan_0~0|combout
|
|
Info (332115): 2.477 0.006 FF CELL High Speed mem|ddr4b_avmm_chkr|LessThan_0~0~la_mlab/laboutt[17]
|
|
Info (332115): 2.724 0.247 FF IC High Speed mem|ddr4b_avmm_chkr|start_error|datad
|
|
Info (332115): 2.807 0.083 FR CELL High Speed mem|ddr4b_avmm_chkr|start_error|combout
|
|
Info (332115): 2.811 0.004 RR CELL High Speed mem|ddr4b_avmm_chkr|start_error~la_lab/laboutt[0]
|
|
Info (332115): 3.056 0.245 RR IC High Speed mem|ddr4b_emif_read_mux~0|datad
|
|
Info (332115): 3.128 0.072 RR CELL High Speed mem|ddr4b_emif_read_mux~0|combout
|
|
Info (332115): 3.133 0.005 RR CELL High Speed mem|ddr4b_emif_read_mux~0~la_lab/laboutt[7]
|
|
Info (332115): 3.570 0.437 RR IC High Speed mem|ddr4b|ddr4b|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[1].tile_ctrl_inst|core2ctl_avl0[0]
|
|
Info (332115): 3.570 0.000 RR CELL mem|ddr4b|ddr4b|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[1].tile_ctrl_inst~hmc_reg1
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 3.869 3.869 latch edge time
|
|
Info (332115): 5.151 1.282 R clock network delay
|
|
Info (332115): 5.198 0.047 clock pessimism removed
|
|
Info (332115): 4.909 -0.289 clock uncertainty
|
|
Info (332115): 4.978 0.069 uTsu mem|ddr4b|ddr4b|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[1].tile_ctrl_inst~hmc_reg1
|
|
Info (332115): Data Arrival Time : 3.570
|
|
Info (332115): Data Required Time : 4.978
|
|
Info (332115): Slack : 1.408
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 1.480
|
|
Info (20696): -to_clock [get_clocks {u0|dcp_iopll|dcp_iopll|clk1x}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 1.480
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|wrptr_g[2]
|
|
Info (332115): To Node : fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|fifo_ram|ram_block7a264~reg0
|
|
Info (332115): Launch Clock : u0|dcp_iopll|dcp_iopll|clk1x
|
|
Info (332115): Latch Clock : u0|dcp_iopll|dcp_iopll|clk1x
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 6.179 6.179 R clock network delay
|
|
Info (332115): 6.179 0.000 fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|wrptr_g[2]
|
|
Info (332115): 6.303 0.124 FF uTco fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|wrptr_g[2]|q
|
|
Info (332115): 6.347 0.044 FF CELL High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|wrptr_g[2]~la_mlab/laboutt[10]
|
|
Info (332115): 9.545 3.198 FF IC High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|fifo_ram|ram_block7a264|portaaddr[2]
|
|
Info (332115): 9.545 0.000 FF CELL High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|fifo_ram|ram_block7a264~reg0
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 5.000 5.000 latch edge time
|
|
Info (332115): 10.343 5.343 R clock network delay
|
|
Info (332115): 11.034 0.691 clock pessimism removed
|
|
Info (332115): 10.884 -0.150 clock uncertainty
|
|
Info (332115): 11.025 0.141 uTsu fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|fifo_ram|ram_block7a264~reg0
|
|
Info (332115): Data Arrival Time : 9.545
|
|
Info (332115): Data Required Time : 11.025
|
|
Info (332115): Slack : 1.480
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 1.616
|
|
Info (20696): -to_clock [get_clocks {mem|ddr4a|ddr4a_phy_clk_l_0}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 1.616
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : mem|ddr4a_avmm_chkr|clearing
|
|
Info (332115): To Node : mem|ddr4a|ddr4a|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[1].tile_ctrl_inst~hmc_reg1
|
|
Info (332115): Launch Clock : mem|ddr4a|ddr4a_core_usr_clk
|
|
Info (332115): Latch Clock : mem|ddr4a|ddr4a_phy_clk_l_0
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.117 0.117 launch edge time
|
|
Info (332115): 1.933 1.816 R clock network delay
|
|
Info (332115): 1.933 0.000 mem|ddr4a_avmm_chkr|clearing
|
|
Info (332115): 2.054 0.121 RR uTco mem|ddr4a_avmm_chkr|clearing|q
|
|
Info (332115): 2.124 0.070 RR CELL High Speed mem|ddr4a_avmm_chkr|clearing~la_mlab/laboutt[13]
|
|
Info (332115): 2.650 0.526 RR IC High Speed mem|ddr4a_avmm_chkr|avm_address[10]~10|datab
|
|
Info (332115): 2.761 0.111 RF CELL High Speed mem|ddr4a_avmm_chkr|avm_address[10]~10|combout
|
|
Info (332115): 2.766 0.005 FF CELL High Speed mem|ddr4a_avmm_chkr|avm_address[10]~10~la_mlab/laboutb[12]
|
|
Info (332115): 3.834 1.068 FF IC High Speed mem|ddr4a|ddr4a|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[1].tile_ctrl_inst|core2ctl_avl0[12]
|
|
Info (332115): 3.834 0.000 FF CELL mem|ddr4a|ddr4a|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[1].tile_ctrl_inst~hmc_reg1
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 3.869 3.869 latch edge time
|
|
Info (332115): 5.184 1.315 R clock network delay
|
|
Info (332115): 5.453 0.269 clock pessimism removed
|
|
Info (332115): 5.261 -0.192 clock uncertainty
|
|
Info (332115): 5.450 0.189 uTsu mem|ddr4a|ddr4a|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[1].tile_ctrl_inst~hmc_reg1
|
|
Info (332115): Data Arrival Time : 3.834
|
|
Info (332115): Data Required Time : 5.450
|
|
Info (332115): Slack : 1.616
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 1.621
|
|
Info (20696): -to_clock [get_clocks {u0|dcp_iopll|dcp_iopll|clk100}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 1.621
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_bitstream_host|alt_pr_bitstream_controller_v2|pr_data_reg[3]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_bitstream_host|alt_pr_bitstream_controller_v2|pr_data_reg2[3]
|
|
Info (332115): Launch Clock : u0|dcp_iopll|dcp_iopll|clk100
|
|
Info (332115): Latch Clock : u0|dcp_iopll|dcp_iopll|clk100 (INVERTED)
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 6.257 6.257 R clock network delay
|
|
Info (332115): 6.257 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_bitstream_host|alt_pr_bitstream_controller_v2|pr_data_reg[3]
|
|
Info (332115): 6.380 0.123 RR uTco fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_bitstream_host|alt_pr_bitstream_controller_v2|pr_data_reg[3]|q
|
|
Info (332115): 6.444 0.064 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_bitstream_host|alt_pr_bitstream_controller_v2|pr_data_reg[3]~la_lab/laboutb[2]
|
|
Info (332115): 9.466 3.022 RR IC Mixed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_bitstream_host|alt_pr_bitstream_controller_v2|pr_data_reg2[3]|d
|
|
Info (332115): 9.466 0.000 RR CELL Low Power fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_bitstream_host|alt_pr_bitstream_controller_v2|pr_data_reg2[3]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 5.000 5.000 latch edge time
|
|
Info (332115): 10.410 5.410 F clock network delay
|
|
Info (332115): 11.109 0.699 clock pessimism removed
|
|
Info (332115): 10.939 -0.170 clock uncertainty
|
|
Info (332115): 11.087 0.148 uTsu fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_bitstream_host|alt_pr_bitstream_controller_v2|pr_data_reg2[3]
|
|
Info (332115): Data Arrival Time : 9.466
|
|
Info (332115): Data Required Time : 11.087
|
|
Info (332115): Slack : 1.621
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 1.651
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|pld_clk}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 1.651
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_sriov_2.sriov2.sriov_bridge|altpcie_pcie_sriov2_top_inst|altpcie_sriov2_tx_data_bridge_inst|TxStData_hip_o[209]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~pld_clk.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|wys~CORE_CLK_OUT
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|pld_clk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 5.774 5.774 R clock network delay
|
|
Info (332115): 5.774 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_sriov_2.sriov2.sriov_bridge|altpcie_pcie_sriov2_top_inst|altpcie_sriov2_tx_data_bridge_inst|TxStData_hip_o[209]
|
|
Info (332115): 5.908 0.134 FF uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_sriov_2.sriov2.sriov_bridge|altpcie_pcie_sriov2_top_inst|altpcie_sriov2_tx_data_bridge_inst|TxStData_hip_o[209]|q
|
|
Info (332115): 5.962 0.054 FF CELL Low Power fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_sriov_2.sriov2.sriov_bridge|altpcie_pcie_sriov2_top_inst|altpcie_sriov2_tx_data_bridge_inst|TxStData_hip_o[209]~la_mlab/laboutt[18]
|
|
Info (332115): 8.396 2.434 FF IC Mixed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|tx_st_data[209]
|
|
Info (332115): 8.396 0.000 FF CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~pld_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 4.000 4.000 latch edge time
|
|
Info (332115): 9.063 5.063 R clock network delay
|
|
Info (332115): 9.832 0.769 clock pessimism removed
|
|
Info (332115): 9.813 -0.019 clock uncertainty
|
|
Info (332115): 10.047 0.234 uTsu fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~pld_clk.reg
|
|
Info (332115): Data Arrival Time : 8.396
|
|
Info (332115): Data Required Time : 10.047
|
|
Info (332115): Slack : 1.651
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 2.560
|
|
Info (20696): -to_clock [get_clocks {mem|ddr4a|ddr4a_core_cal_slave_clk}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 2.560
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : mem|ddr4b|ddr4b|arch|arch_inst|io_aux_inst|io_aux~soft_ram_reg
|
|
Info (332115): To Node : mem|ddr4b|ddr4b|cal_slave_component|ioaux_master_bridge|cmd_writedata[1]
|
|
Info (332115): Launch Clock : mem|ddr4a|ddr4a_core_cal_slave_clk
|
|
Info (332115): Latch Clock : mem|ddr4a|ddr4a_core_cal_slave_clk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 4.264 4.264 R clock network delay
|
|
Info (332115): 4.264 0.000 mem|ddr4b|ddr4b|arch|arch_inst|io_aux_inst|io_aux~soft_ram_reg
|
|
Info (332115): 4.696 0.432 FF uTco mem|ddr4b|ddr4b|arch|arch_inst|io_aux_inst|io_aux|soft_ram_write_data[1]
|
|
Info (332115): 8.030 3.334 FF IC High Speed mem|ddr4b|ddr4b|cal_slave_component|ioaux_master_bridge|cmd_writedata[1]|asdata
|
|
Info (332115): 8.030 0.000 FF CELL High Speed mem|ddr4b|ddr4b|cal_slave_component|ioaux_master_bridge|cmd_writedata[1]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 6.566 6.566 latch edge time
|
|
Info (332115): 10.118 3.552 R clock network delay
|
|
Info (332115): 10.556 0.438 clock pessimism removed
|
|
Info (332115): 10.506 -0.050 clock uncertainty
|
|
Info (332115): 10.590 0.084 uTsu mem|ddr4b|ddr4b|cal_slave_component|ioaux_master_bridge|cmd_writedata[1]
|
|
Info (332115): Data Arrival Time : 8.030
|
|
Info (332115): Data Required Time : 10.590
|
|
Info (332115): Slack : 2.560
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 2.606
|
|
Info (20696): -to_clock [get_clocks {hssi_pll_r_0_outclk0}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 2.606
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[2].ct0|dout_r[4]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[2].ct0|dout_r[5]
|
|
Info (332115): Launch Clock : hssi_pll_r_0_outclk0
|
|
Info (332115): Latch Clock : hssi_pll_r_0_outclk0
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 3.197 3.197 R clock network delay
|
|
Info (332115): 3.197 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[2].ct0|dout_r[4]
|
|
Info (332115): 3.386 0.189 RR uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[2].ct0|dout_r[4]|q
|
|
Info (332115): 3.476 0.090 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[2].ct0|dout_r[4]~la_lab/laboutt[12]
|
|
Info (332115): 3.826 0.350 RR IC Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[2].ct0|t5|dout|dataf
|
|
Info (332115): 3.853 0.027 RF CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[2].ct0|t5|dout|combout
|
|
Info (332115): 3.853 0.000 FF CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[2].ct0|dout_r[5]|d
|
|
Info (332115): 3.853 0.000 FF CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[2].ct0|dout_r[5]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 3.200 3.200 latch edge time
|
|
Info (332115): 6.075 2.875 R clock network delay
|
|
Info (332115): 6.397 0.322 clock pessimism removed
|
|
Info (332115): 6.287 -0.110 clock uncertainty
|
|
Info (332115): 6.459 0.172 uTsu fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[2].ct0|dout_r[5]
|
|
Info (332115): Data Arrival Time : 3.853
|
|
Info (332115): Data Required Time : 6.459
|
|
Info (332115): Slack : 2.606
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 2.626
|
|
Info (20696): -to_clock [get_clocks {ETH_RefClk}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 2.626
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[6].ct0|dout_r[5]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[6].sn0|ff_launch[0]
|
|
Info (332115): Launch Clock : ETH_RefClk
|
|
Info (332115): Latch Clock : ETH_RefClk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 3.788 3.788 R clock network delay
|
|
Info (332115): 3.788 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[6].ct0|dout_r[5]
|
|
Info (332115): 3.958 0.170 RR uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[6].ct0|dout_r[5]|q
|
|
Info (332115): 4.025 0.067 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[6].ct0|dout_r[5]~la_lab/laboutb[5]
|
|
Info (332115): 4.223 0.198 RR IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[6].sn0|ff_launch[0]|d
|
|
Info (332115): 4.223 0.000 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[6].sn0|ff_launch[0]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 3.103 3.103 latch edge time
|
|
Info (332115): 6.485 3.382 R clock network delay
|
|
Info (332115): 6.862 0.377 clock pessimism removed
|
|
Info (332115): 6.822 -0.040 clock uncertainty
|
|
Info (332115): 6.849 0.027 uTsu fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[6].sn0|ff_launch[0]
|
|
Info (332115): Data Arrival Time : 4.223
|
|
Info (332115): Data Required Time : 6.849
|
|
Info (332115): Slack : 2.626
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 2.659
|
|
Info (20696): -to_clock [get_clocks {hssi_pll_t_outclk0}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 2.659
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[3].ct0|dout_r[5]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[3].sn0|ff_launch[0]
|
|
Info (332115): Launch Clock : hssi_pll_t_outclk0
|
|
Info (332115): Latch Clock : hssi_pll_t_outclk0
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 2.998 2.998 R clock network delay
|
|
Info (332115): 2.998 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[3].ct0|dout_r[5]
|
|
Info (332115): 3.171 0.173 RR uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[3].ct0|dout_r[5]|q
|
|
Info (332115): 3.261 0.090 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[3].ct0|dout_r[5]~la_lab/laboutt[8]
|
|
Info (332115): 3.518 0.257 RR IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[3].sn0|ff_launch[0]|asdata
|
|
Info (332115): 3.518 0.000 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[3].sn0|ff_launch[0]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 3.200 3.200 latch edge time
|
|
Info (332115): 5.900 2.700 R clock network delay
|
|
Info (332115): 6.171 0.271 clock pessimism removed
|
|
Info (332115): 6.061 -0.110 clock uncertainty
|
|
Info (332115): 6.177 0.116 uTsu fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[3].sn0|ff_launch[0]
|
|
Info (332115): Data Arrival Time : 3.518
|
|
Info (332115): Data Required Time : 6.177
|
|
Info (332115): Slack : 2.659
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 2.798
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_clk}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 2.798
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_prbs_done_sync|resync_chains[0].sync_r[1]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_snapshot[1]
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_clk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_clk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 3.070 3.070 R clock network delay
|
|
Info (332115): 3.070 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_prbs_done_sync|resync_chains[0].sync_r[1]
|
|
Info (332115): 3.192 0.122 RR uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_prbs_done_sync|resync_chains[0].sync_r[1]|q
|
|
Info (332115): 3.281 0.089 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_prbs_done_sync|resync_chains[0].sync_r[1]~la_lab/laboutb[3]
|
|
Info (332115): 3.725 0.444 RR IC High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_snapshot[1]~0|datac
|
|
Info (332115): 3.804 0.079 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_snapshot[1]~0|combout
|
|
Info (332115): 3.809 0.005 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_snapshot[1]~0~la_lab/laboutt[7]
|
|
Info (332115): 4.120 0.311 RR IC High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_snapshot[1]|ena
|
|
Info (332115): 4.120 0.000 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_snapshot[1]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 3.878 3.878 latch edge time
|
|
Info (332115): 5.973 2.095 R clock network delay
|
|
Info (332115): 6.918 0.945 clock pessimism removed
|
|
Info (332115): 6.888 -0.030 clock uncertainty
|
|
Info (332115): 6.918 0.030 uTsu fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_snapshot[1]
|
|
Info (332115): Data Arrival Time : 4.120
|
|
Info (332115): Data Required Time : 6.918
|
|
Info (332115): Slack : 2.798
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 2.837
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|rx_pma_clk}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 2.837
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_prbs_reset_sync|resync_chains[0].sync_r[2]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_snapshot[6]
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|rx_pma_clk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|rx_pma_clk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 3.007 3.007 R clock network delay
|
|
Info (332115): 3.007 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_prbs_reset_sync|resync_chains[0].sync_r[2]
|
|
Info (332115): 3.128 0.121 RR uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_prbs_reset_sync|resync_chains[0].sync_r[2]|q
|
|
Info (332115): 3.189 0.061 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_prbs_reset_sync|resync_chains[0].sync_r[2]~la_lab/laboutt[14]
|
|
Info (332115): 3.551 0.362 RR IC High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_snapshot[0]~0|dataa
|
|
Info (332115): 3.669 0.118 RF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_snapshot[0]~0|combout
|
|
Info (332115): 3.673 0.004 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_snapshot[0]~0~la_lab/laboutt[8]
|
|
Info (332115): 4.036 0.363 FF IC High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_snapshot[6]|ena
|
|
Info (332115): 4.036 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_snapshot[6]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 3.878 3.878 latch edge time
|
|
Info (332115): 5.912 2.034 R clock network delay
|
|
Info (332115): 6.874 0.962 clock pessimism removed
|
|
Info (332115): 6.844 -0.030 clock uncertainty
|
|
Info (332115): 6.873 0.029 uTsu fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_snapshot[6]
|
|
Info (332115): Data Arrival Time : 4.036
|
|
Info (332115): Data Required Time : 6.873
|
|
Info (332115): Slack : 2.837
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 2.944
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|rx_pma_clk}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 2.944
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_prbs_reset_sync|resync_chains[0].sync_r[2]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_snapshot[1]
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|rx_pma_clk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|rx_pma_clk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 2.923 2.923 R clock network delay
|
|
Info (332115): 2.923 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_prbs_reset_sync|resync_chains[0].sync_r[2]
|
|
Info (332115): 3.051 0.128 RR uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_prbs_reset_sync|resync_chains[0].sync_r[2]|q
|
|
Info (332115): 3.144 0.093 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_prbs_reset_sync|resync_chains[0].sync_r[2]~la_mlab/laboutb[12]
|
|
Info (332115): 3.632 0.488 RR IC High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_snapshot[5]~0|datad
|
|
Info (332115): 3.706 0.074 RF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_snapshot[5]~0|combout
|
|
Info (332115): 3.710 0.004 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_snapshot[5]~0~la_lab/laboutb[0]
|
|
Info (332115): 3.826 0.116 FF IC High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_snapshot[1]|ena
|
|
Info (332115): 3.826 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_snapshot[1]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 3.878 3.878 latch edge time
|
|
Info (332115): 5.806 1.928 R clock network delay
|
|
Info (332115): 6.771 0.965 clock pessimism removed
|
|
Info (332115): 6.741 -0.030 clock uncertainty
|
|
Info (332115): 6.770 0.029 uTsu fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_snapshot[1]
|
|
Info (332115): Data Arrival Time : 3.826
|
|
Info (332115): Data Required Time : 6.770
|
|
Info (332115): Slack : 2.944
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 2.979
|
|
Info (20696): -to_clock [get_clocks {DDR4_RefClk}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 2.979
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|use_counter_lock.counter_lock_gen_master.cpa_count_to_lock[1]
|
|
Info (332115): To Node : mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|use_counter_lock.counter_lock_gen_master.cpa_count_to_lock[16]~LRTM_3
|
|
Info (332115): Launch Clock : DDR4_RefClk
|
|
Info (332115): Latch Clock : DDR4_RefClk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 2.849 2.849 R clock network delay
|
|
Info (332115): 2.849 0.000 mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|use_counter_lock.counter_lock_gen_master.cpa_count_to_lock[1]
|
|
Info (332115): 2.971 0.122 RR uTco mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|use_counter_lock.counter_lock_gen_master.cpa_count_to_lock[1]|q
|
|
Info (332115): 3.034 0.063 RR CELL High Speed mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|use_counter_lock.counter_lock_gen_master.cpa_count_to_lock[1]~la_lab/laboutt[1]
|
|
Info (332115): 3.153 0.119 RR IC High Speed mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|add_0~61|datac
|
|
Info (332115): 3.466 0.313 RR CELL High Speed mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|add_0~21|cin
|
|
Info (332115): 3.482 0.016 RF CELL High Speed mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|add_0~17|cout
|
|
Info (332115): 3.482 0.000 FF CELL High Speed mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|add_0~13|cin
|
|
Info (332115): 3.499 0.017 FR CELL High Speed mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|add_0~9|cout
|
|
Info (332115): 3.499 0.000 RR CELL High Speed mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|add_0~5|cin
|
|
Info (332115): 3.605 0.106 RR CELL High Speed mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|add_0~1|sumout
|
|
Info (332115): 3.609 0.004 RR CELL High Speed mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|add_0~1~la_lab/laboutb[10]
|
|
Info (332115): 3.715 0.106 RR IC High Speed mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|use_counter_lock.counter_lock_gen_master.cpa_count_to_lock[16]~LRTM_3|d
|
|
Info (332115): 3.715 0.000 RR CELL High Speed mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|use_counter_lock.counter_lock_gen_master.cpa_count_to_lock[16]~LRTM_3
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 3.752 3.752 latch edge time
|
|
Info (332115): 6.388 2.636 R clock network delay
|
|
Info (332115): 6.588 0.200 clock pessimism removed
|
|
Info (332115): 6.558 -0.030 clock uncertainty
|
|
Info (332115): 6.694 0.136 uTsu mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|use_counter_lock.counter_lock_gen_master.cpa_count_to_lock[16]~LRTM_3
|
|
Info (332115): Data Arrival Time : 3.715
|
|
Info (332115): Data Required Time : 6.694
|
|
Info (332115): Slack : 2.979
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 3.037
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|rx_pma_clk}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 3.037
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_prbs_err_sync|resync_chains[0].sync_r[1]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_count[0]
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|rx_pma_clk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|rx_pma_clk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 3.050 3.050 R clock network delay
|
|
Info (332115): 3.050 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_prbs_err_sync|resync_chains[0].sync_r[1]
|
|
Info (332115): 3.171 0.121 RR uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_prbs_err_sync|resync_chains[0].sync_r[1]|q
|
|
Info (332115): 3.231 0.060 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_prbs_err_sync|resync_chains[0].sync_r[1]~la_mlab/laboutt[14]
|
|
Info (332115): 3.517 0.286 RR IC High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|add_2~1|datab
|
|
Info (332115): 3.767 0.250 RF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|add_2~1|sumout
|
|
Info (332115): 3.772 0.005 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|add_2~1~la_lab/laboutb[1]
|
|
Info (332115): 3.937 0.165 FF IC High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|i58~0|datad
|
|
Info (332115): 4.029 0.092 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|i58~0|combout
|
|
Info (332115): 4.029 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_count[0]|d
|
|
Info (332115): 4.029 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_count[0]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 3.878 3.878 latch edge time
|
|
Info (332115): 5.950 2.072 R clock network delay
|
|
Info (332115): 6.928 0.978 clock pessimism removed
|
|
Info (332115): 6.898 -0.030 clock uncertainty
|
|
Info (332115): 7.066 0.168 uTsu fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_count[0]
|
|
Info (332115): Data Arrival Time : 4.029
|
|
Info (332115): Data Required Time : 7.066
|
|
Info (332115): Slack : 3.037
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 3.249
|
|
Info (20696): -to_clock [get_clocks {hssi_pll_t_outclk1}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 3.249
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[1].ct0|dout_r[1]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[1].ct0|dout_r[3]
|
|
Info (332115): Launch Clock : hssi_pll_t_outclk1
|
|
Info (332115): Latch Clock : hssi_pll_t_outclk1
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 2.975 2.975 R clock network delay
|
|
Info (332115): 2.975 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[1].ct0|dout_r[1]
|
|
Info (332115): 3.127 0.152 RR uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[1].ct0|dout_r[1]|q
|
|
Info (332115): 3.212 0.085 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[1].ct0|dout_r[1]~la_mlab/laboutt[8]
|
|
Info (332115): 3.500 0.288 RR IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[1].ct0|t3|dout|dataf
|
|
Info (332115): 3.528 0.028 RF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[1].ct0|t3|dout|combout
|
|
Info (332115): 3.528 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[1].ct0|dout_r[3]|d
|
|
Info (332115): 3.528 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[1].ct0|dout_r[3]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 3.800 3.800 latch edge time
|
|
Info (332115): 6.493 2.693 R clock network delay
|
|
Info (332115): 6.775 0.282 clock pessimism removed
|
|
Info (332115): 6.665 -0.110 clock uncertainty
|
|
Info (332115): 6.777 0.112 uTsu fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[1].ct0|dout_r[3]
|
|
Info (332115): Data Arrival Time : 3.528
|
|
Info (332115): Data Required Time : 6.777
|
|
Info (332115): Slack : 3.249
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 3.274
|
|
Info (20696): -to_clock [get_clocks {hssi_pll_r_0_outclk1}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 3.274
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[0].ct0|dout_r[5]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[0].sn0|ff_launch[0]
|
|
Info (332115): Launch Clock : hssi_pll_r_0_outclk1
|
|
Info (332115): Latch Clock : hssi_pll_r_0_outclk1
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 3.190 3.190 R clock network delay
|
|
Info (332115): 3.190 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[0].ct0|dout_r[5]
|
|
Info (332115): 3.352 0.162 RR uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[0].ct0|dout_r[5]|q
|
|
Info (332115): 3.442 0.090 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[0].ct0|dout_r[5]~la_lab/laboutt[0]
|
|
Info (332115): 3.716 0.274 RR IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[0].sn0|ff_launch[0]|asdata
|
|
Info (332115): 3.716 0.000 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[0].sn0|ff_launch[0]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 3.800 3.800 latch edge time
|
|
Info (332115): 6.667 2.867 R clock network delay
|
|
Info (332115): 6.990 0.323 clock pessimism removed
|
|
Info (332115): 6.880 -0.110 clock uncertainty
|
|
Info (332115): 6.990 0.110 uTsu fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[0].sn0|ff_launch[0]
|
|
Info (332115): Data Arrival Time : 3.716
|
|
Info (332115): Data Required Time : 6.990
|
|
Info (332115): Slack : 3.274
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 3.525
|
|
Info (20696): -to_clock [get_clocks {PCIE_REFCLK}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 3.525
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|sm_state.SM_POWERUP
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|timer_counter[20]
|
|
Info (332115): Launch Clock : PCIE_REFCLK
|
|
Info (332115): Latch Clock : PCIE_REFCLK
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 3.832 3.832 R clock network delay
|
|
Info (332115): 3.832 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|sm_state.SM_POWERUP
|
|
Info (332115): 3.955 0.123 FF uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|sm_state.SM_POWERUP|q
|
|
Info (332115): 3.998 0.043 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|sm_state.SM_POWERUP~la_mlab/laboutt[13]
|
|
Info (332115): 7.446 3.448 FF IC Mixed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|reduce_or_14|datac
|
|
Info (332115): 7.533 0.087 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|reduce_or_14|combout
|
|
Info (332115): 7.539 0.006 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|reduce_or_14~la_mlab/laboutb[16]
|
|
Info (332115): 10.210 2.671 FF IC Mixed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|timer_counter[20]|ena
|
|
Info (332115): 10.210 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|timer_counter[20]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 10.000 10.000 latch edge time
|
|
Info (332115): 13.475 3.475 R clock network delay
|
|
Info (332115): 13.747 0.272 clock pessimism removed
|
|
Info (332115): 13.707 -0.040 clock uncertainty
|
|
Info (332115): 13.735 0.028 uTsu fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|timer_counter[20]
|
|
Info (332115): Data Arrival Time : 10.210
|
|
Info (332115): Data Required Time : 13.735
|
|
Info (332115): Slack : 3.525
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 3.576
|
|
Info (20696): -to_clock [get_clocks {vl_qph_user_clk_clkpsc_clk1}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 3.576
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[0]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[1]
|
|
Info (332115): Launch Clock : vl_qph_user_clk_clkpsc_clk1
|
|
Info (332115): Latch Clock : vl_qph_user_clk_clkpsc_clk1
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 4.574 4.574 R clock network delay
|
|
Info (332115): 4.574 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[0]
|
|
Info (332115): 4.703 0.129 RR uTco fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[0]|q
|
|
Info (332115): 4.765 0.062 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[0]~la_mlab/laboutb[9]
|
|
Info (332115): 5.530 0.765 RR IC Mixed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[1]~2|dataa
|
|
Info (332115): 5.655 0.125 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[1]~2|combout
|
|
Info (332115): 5.655 0.000 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[1]|d
|
|
Info (332115): 5.655 0.000 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[1]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 4.545 4.545 latch edge time
|
|
Info (332115): 8.406 3.861 R clock network delay
|
|
Info (332115): 9.115 0.709 clock pessimism removed
|
|
Info (332115): 9.085 -0.030 clock uncertainty
|
|
Info (332115): 9.231 0.146 uTsu fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[1]
|
|
Info (332115): Data Arrival Time : 5.655
|
|
Info (332115): Data Required Time : 9.231
|
|
Info (332115): Slack : 3.576
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 3.915
|
|
Info (20696): -to_clock [get_clocks {SYS_RefClk}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 3.915
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_cb_host|alt_pr_cb_controller_v2|freeze_reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi.f2a_prmgmt_freeze
|
|
Info (332115): Launch Clock : u0|dcp_iopll|dcp_iopll|clk100
|
|
Info (332115): Latch Clock : SYS_RefClk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 6.218 6.218 R clock network delay
|
|
Info (332115): 6.218 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_cb_host|alt_pr_cb_controller_v2|freeze_reg
|
|
Info (332115): 6.342 0.124 RR uTco fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_cb_host|alt_pr_cb_controller_v2|freeze_reg|q
|
|
Info (332115): 6.427 0.085 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_cb_host|alt_pr_cb_controller_v2|freeze_reg~la_lab/laboutt[8]
|
|
Info (332115): 8.762 2.335 RR IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|i617~0|datae
|
|
Info (332115): 8.829 0.067 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|i617~0|combout
|
|
Info (332115): 8.829 0.000 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi.f2a_prmgmt_freeze|d
|
|
Info (332115): 8.829 0.000 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi.f2a_prmgmt_freeze
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 10.000 10.000 latch edge time
|
|
Info (332115): 12.737 2.737 R clock network delay
|
|
Info (332115): 12.884 0.147 clock pessimism removed
|
|
Info (332115): 12.574 -0.310 clock uncertainty
|
|
Info (332115): 12.744 0.170 uTsu fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi.f2a_prmgmt_freeze
|
|
Info (332115): Data Arrival Time : 8.829
|
|
Info (332115): Data Required Time : 12.744
|
|
Info (332115): Slack : 3.915
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 4.766
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|avmmclk}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 4.766
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|reconfig_read
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Launch Clock : SYS_RefClk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|avmmclk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 2.981 2.981 R clock network delay
|
|
Info (332115): 2.981 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|reconfig_read
|
|
Info (332115): 3.115 0.134 RR uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|reconfig_read|q
|
|
Info (332115): 3.204 0.089 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|reconfig_read~la_mlab/laboutb[4]
|
|
Info (332115): 4.461 1.257 RR IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|avmm_read[1]~1|dataa
|
|
Info (332115): 4.590 0.129 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|avmm_read[1]~1|combout
|
|
Info (332115): 4.595 0.005 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|avmm_read[1]~1~la_lab/laboutt[7]
|
|
Info (332115): 8.325 3.730 RR IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst|avmmread
|
|
Info (332115): 8.325 0.000 RR CELL fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 10.000 10.000 latch edge time
|
|
Info (332115): 12.870 2.870 R clock network delay
|
|
Info (332115): 13.017 0.147 clock pessimism removed
|
|
Info (332115): 12.987 -0.030 clock uncertainty
|
|
Info (332115): 13.091 0.104 uTsu fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Arrival Time : 8.325
|
|
Info (332115): Data Required Time : 13.091
|
|
Info (332115): Slack : 4.766
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 5.019
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|avmmclk}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 5.019
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|reconfig_write
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Launch Clock : SYS_RefClk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|avmmclk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 2.981 2.981 R clock network delay
|
|
Info (332115): 2.981 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|reconfig_write
|
|
Info (332115): 3.122 0.141 FF uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|reconfig_write|q
|
|
Info (332115): 3.169 0.047 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|reconfig_write~la_mlab/laboutt[10]
|
|
Info (332115): 4.445 1.276 FF IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|avmm_write[2]~2|datac
|
|
Info (332115): 4.530 0.085 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|avmm_write[2]~2|combout
|
|
Info (332115): 4.534 0.004 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|avmm_write[2]~2~la_lab/laboutb[4]
|
|
Info (332115): 8.015 3.481 FF IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst|avmmwrite
|
|
Info (332115): 8.015 0.000 FF CELL fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 10.000 10.000 latch edge time
|
|
Info (332115): 12.869 2.869 R clock network delay
|
|
Info (332115): 13.016 0.147 clock pessimism removed
|
|
Info (332115): 12.986 -0.030 clock uncertainty
|
|
Info (332115): 13.034 0.048 uTsu fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Arrival Time : 8.015
|
|
Info (332115): Data Required Time : 13.034
|
|
Info (332115): Slack : 5.019
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 5.193
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|avmmclk}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 5.193
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|reconfig_read
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Launch Clock : SYS_RefClk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|avmmclk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 2.981 2.981 R clock network delay
|
|
Info (332115): 2.981 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|reconfig_read
|
|
Info (332115): 3.115 0.134 RR uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|reconfig_read|q
|
|
Info (332115): 3.204 0.089 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|reconfig_read~la_mlab/laboutb[4]
|
|
Info (332115): 4.461 1.257 RR IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|avmm_read[0]~0|dataa
|
|
Info (332115): 4.594 0.133 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|avmm_read[0]~0|combout
|
|
Info (332115): 4.598 0.004 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|avmm_read[0]~0~la_lab/laboutt[4]
|
|
Info (332115): 7.901 3.303 RR IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst|avmmread
|
|
Info (332115): 7.901 0.000 RR CELL fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 10.000 10.000 latch edge time
|
|
Info (332115): 12.873 2.873 R clock network delay
|
|
Info (332115): 13.020 0.147 clock pessimism removed
|
|
Info (332115): 12.990 -0.030 clock uncertainty
|
|
Info (332115): 13.094 0.104 uTsu fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Arrival Time : 7.901
|
|
Info (332115): Data Required Time : 13.094
|
|
Info (332115): Slack : 5.193
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 5.821
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|avmmclk}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 5.821
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|reconfig_read
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Launch Clock : SYS_RefClk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|avmmclk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 2.981 2.981 R clock network delay
|
|
Info (332115): 2.981 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|reconfig_read
|
|
Info (332115): 3.115 0.134 RR uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|reconfig_read|q
|
|
Info (332115): 3.204 0.089 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|reconfig_read~la_mlab/laboutb[4]
|
|
Info (332115): 4.381 1.177 RR IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|avmm_read[3]~3|datab
|
|
Info (332115): 4.507 0.126 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|avmm_read[3]~3|combout
|
|
Info (332115): 4.512 0.005 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|avmm_read[3]~3~la_mlab/laboutt[2]
|
|
Info (332115): 7.347 2.835 RR IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst|avmmread
|
|
Info (332115): 7.347 0.000 RR CELL fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 10.000 10.000 latch edge time
|
|
Info (332115): 12.947 2.947 R clock network delay
|
|
Info (332115): 13.094 0.147 clock pessimism removed
|
|
Info (332115): 13.064 -0.030 clock uncertainty
|
|
Info (332115): 13.168 0.104 uTsu fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Arrival Time : 7.347
|
|
Info (332115): Data Required Time : 13.168
|
|
Info (332115): Slack : 5.821
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 5.850
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|tx_pma_div_clk}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 5.850
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[5].ct0|dout_r[5]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[5].ct0|dout_r[5]
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|tx_pma_div_clk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|tx_pma_div_clk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 5.917 5.917 R clock network delay
|
|
Info (332115): 5.917 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[5].ct0|dout_r[5]
|
|
Info (332115): 6.039 0.122 RR uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[5].ct0|dout_r[5]|q
|
|
Info (332115): 6.124 0.085 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[5].ct0|dout_r[5]~la_lab/laboutb[8]
|
|
Info (332115): 6.486 0.362 RR IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[5].ct0|t5|dout|datae
|
|
Info (332115): 6.559 0.073 RF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[5].ct0|t5|dout|combout
|
|
Info (332115): 6.559 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[5].ct0|dout_r[5]|d
|
|
Info (332115): 6.559 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[5].ct0|dout_r[5]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 6.399 6.399 latch edge time
|
|
Info (332115): 11.046 4.647 R clock network delay
|
|
Info (332115): 12.315 1.269 clock pessimism removed
|
|
Info (332115): 12.295 -0.020 clock uncertainty
|
|
Info (332115): 12.409 0.114 uTsu fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[5].ct0|dout_r[5]
|
|
Info (332115): Data Arrival Time : 6.559
|
|
Info (332115): Data Required Time : 12.409
|
|
Info (332115): Slack : 5.850
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 5.927
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_div_clk}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 5.927
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[4].ct0|dout_r[4]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[4].ct0|dout_r[5]
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_div_clk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_div_clk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 6.354 6.354 R clock network delay
|
|
Info (332115): 6.354 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[4].ct0|dout_r[4]
|
|
Info (332115): 6.493 0.139 RR uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[4].ct0|dout_r[4]|q
|
|
Info (332115): 6.556 0.063 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[4].ct0|dout_r[4]~la_lab/laboutb[9]
|
|
Info (332115): 6.882 0.326 RR IC High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[4].ct0|t5|dout|dataf
|
|
Info (332115): 6.909 0.027 RF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[4].ct0|t5|dout|combout
|
|
Info (332115): 6.909 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[4].ct0|dout_r[5]|d
|
|
Info (332115): 6.909 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[4].ct0|dout_r[5]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 6.399 6.399 latch edge time
|
|
Info (332115): 11.420 5.021 R clock network delay
|
|
Info (332115): 12.753 1.333 clock pessimism removed
|
|
Info (332115): 12.723 -0.030 clock uncertainty
|
|
Info (332115): 12.836 0.113 uTsu fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[4].ct0|dout_r[5]
|
|
Info (332115): Data Arrival Time : 6.909
|
|
Info (332115): Data Required Time : 12.836
|
|
Info (332115): Slack : 5.927
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 6.009
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|avmmclk}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 6.009
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_address[3]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Launch Clock : PCIE_REFCLK
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|avmmclk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 3.847 3.847 R clock network delay
|
|
Info (332115): 3.847 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_address[3]
|
|
Info (332115): 3.974 0.127 RR uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_address[3]|q
|
|
Info (332115): 4.075 0.101 RR CELL Low Power fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_address[3]~la_lab/laboutt[19]
|
|
Info (332115): 4.966 0.891 RR IC Mixed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i1697|dataf
|
|
Info (332115): 4.992 0.026 RR CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i1697|combout
|
|
Info (332115): 4.996 0.004 RR CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i1697~la_lab/laboutb[0]
|
|
Info (332115): 7.829 2.833 RR IC Mixed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst|avmmaddress[3]
|
|
Info (332115): 7.829 0.000 RR CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 10.000 10.000 latch edge time
|
|
Info (332115): 13.531 3.531 R clock network delay
|
|
Info (332115): 13.863 0.332 clock pessimism removed
|
|
Info (332115): 13.823 -0.040 clock uncertainty
|
|
Info (332115): 13.838 0.015 uTsu fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Arrival Time : 7.829
|
|
Info (332115): Data Required Time : 13.838
|
|
Info (332115): Slack : 6.009
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 6.153
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|avmmclk}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 6.153
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_writedata[4]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Launch Clock : PCIE_REFCLK
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|avmmclk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 3.835 3.835 R clock network delay
|
|
Info (332115): 3.835 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_writedata[4]
|
|
Info (332115): 3.963 0.128 FF uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_writedata[4]|q
|
|
Info (332115): 4.012 0.049 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_writedata[4]~la_lab/laboutt[5]
|
|
Info (332115): 4.863 0.851 FF IC Mixed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i1496~4|datac
|
|
Info (332115): 4.960 0.097 FF CELL Low Power fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i1496~4|combout
|
|
Info (332115): 4.965 0.005 FF CELL Low Power fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i1496~4~la_mlab/laboutt[14]
|
|
Info (332115): 7.688 2.723 FF IC Mixed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst|avmmwritedata[4]
|
|
Info (332115): 7.688 0.000 FF CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 10.000 10.000 latch edge time
|
|
Info (332115): 13.541 3.541 R clock network delay
|
|
Info (332115): 13.873 0.332 clock pessimism removed
|
|
Info (332115): 13.833 -0.040 clock uncertainty
|
|
Info (332115): 13.841 0.008 uTsu fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Arrival Time : 7.688
|
|
Info (332115): Data Required Time : 13.841
|
|
Info (332115): Slack : 6.153
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 6.232
|
|
Info (20696): -to_clock [get_clocks {fspi_sclk}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 6.232
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_altera_avalon_st_packets_to_bytes_inst_for_spichain|the_altera_avalon_st_packets_to_bytes|out_data[6]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MISOctl|rdshiftreg[0]
|
|
Info (332115): Launch Clock : u0|dcp_iopll|dcp_iopll|clk1x
|
|
Info (332115): Latch Clock : fspi_sclk
|
|
Info (332115): Exception : dcp_bbs.sdc:3006: set_multicycle_path -setup -to [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MISOctl|rdshiftreg*}] 2
|
|
Info (332115): Multicycle - Setup Start : 2
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 240.000 240.000 launch edge time
|
|
Info (332115): 246.222 6.222 R clock network delay
|
|
Info (332115): 246.222 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_altera_avalon_st_packets_to_bytes_inst_for_spichain|the_altera_avalon_st_packets_to_bytes|out_data[6]
|
|
Info (332115): 246.344 0.122 RR uTco fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_altera_avalon_st_packets_to_bytes_inst_for_spichain|the_altera_avalon_st_packets_to_bytes|out_data[6]|q
|
|
Info (332115): 246.429 0.085 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_altera_avalon_st_packets_to_bytes_inst_for_spichain|the_altera_avalon_st_packets_to_bytes|out_data[6]~la_lab/laboutb[8]
|
|
Info (332115): 246.621 0.192 RR IC High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_altera_avalon_st_idle_inserter|i15~1|datab
|
|
Info (332115): 246.754 0.133 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_altera_avalon_st_idle_inserter|i15~1|combout
|
|
Info (332115): 246.759 0.005 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_altera_avalon_st_idle_inserter|i15~1~la_lab/laboutb[5]
|
|
Info (332115): 246.883 0.124 RR IC High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MISOctl|i36~7|dataa
|
|
Info (332115): 247.016 0.133 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MISOctl|i36~7|combout
|
|
Info (332115): 247.016 0.000 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MISOctl|rdshiftreg[0]|d
|
|
Info (332115): 247.016 0.000 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MISOctl|rdshiftreg[0]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 250.000 250.000 latch edge time
|
|
Info (332115): 253.397 3.397 R clock network delay
|
|
Info (332115): 253.087 -0.310 clock uncertainty
|
|
Info (332115): 253.248 0.161 uTsu fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MISOctl|rdshiftreg[0]
|
|
Info (332115): Data Arrival Time : 247.016
|
|
Info (332115): Data Required Time : 253.248
|
|
Info (332115): Slack : 6.232
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 6.365
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|avmmclk}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 6.365
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|g_arb[5].arbiter_inst|grant[0]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Launch Clock : PCIE_REFCLK
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|avmmclk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 3.839 3.839 R clock network delay
|
|
Info (332115): 3.839 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|g_arb[5].arbiter_inst|grant[0]
|
|
Info (332115): 3.974 0.135 FF uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|g_arb[5].arbiter_inst|grant[0]|q
|
|
Info (332115): 4.047 0.073 FF CELL Low Power fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|g_arb[5].arbiter_inst|grant[0]~la_mlab/laboutb[11]
|
|
Info (332115): 4.694 0.647 FF IC Low Power fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i1215|dataf
|
|
Info (332115): 4.721 0.027 FF CELL Low Power fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i1215|combout
|
|
Info (332115): 4.725 0.004 FF CELL Low Power fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i1215~la_lab/laboutt[2]
|
|
Info (332115): 7.451 2.726 FF IC Mixed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst|avmmaddress[1]
|
|
Info (332115): 7.451 0.000 FF CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 10.000 10.000 latch edge time
|
|
Info (332115): 13.516 3.516 R clock network delay
|
|
Info (332115): 13.848 0.332 clock pessimism removed
|
|
Info (332115): 13.808 -0.040 clock uncertainty
|
|
Info (332115): 13.816 0.008 uTsu fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Arrival Time : 7.451
|
|
Info (332115): Data Required Time : 13.816
|
|
Info (332115): Slack : 6.365
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 6.627
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|avmmclk}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 6.627
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_address[2]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Launch Clock : PCIE_REFCLK
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|avmmclk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 3.847 3.847 R clock network delay
|
|
Info (332115): 3.847 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_address[2]
|
|
Info (332115): 3.975 0.128 FF uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_address[2]|q
|
|
Info (332115): 4.027 0.052 FF CELL Low Power fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_address[2]~la_lab/laboutb[13]
|
|
Info (332115): 4.953 0.926 FF IC Mixed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i984|datac
|
|
Info (332115): 5.039 0.086 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i984|combout
|
|
Info (332115): 5.045 0.006 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i984~la_mlab/laboutt[0]
|
|
Info (332115): 7.241 2.196 FF IC Mixed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst|avmmaddress[2]
|
|
Info (332115): 7.241 0.000 FF CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 10.000 10.000 latch edge time
|
|
Info (332115): 13.531 3.531 R clock network delay
|
|
Info (332115): 13.863 0.332 clock pessimism removed
|
|
Info (332115): 13.823 -0.040 clock uncertainty
|
|
Info (332115): 13.868 0.045 uTsu fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Arrival Time : 7.241
|
|
Info (332115): Data Required Time : 13.868
|
|
Info (332115): Slack : 6.627
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 6.891
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|avmmclk}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 6.891
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_address[5]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Launch Clock : PCIE_REFCLK
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|avmmclk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 3.847 3.847 R clock network delay
|
|
Info (332115): 3.847 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_address[5]
|
|
Info (332115): 3.976 0.129 FF uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_address[5]|q
|
|
Info (332115): 4.049 0.073 FF CELL Low Power fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_address[5]~la_lab/laboutb[7]
|
|
Info (332115): 4.860 0.811 FF IC Mixed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i763|dataf
|
|
Info (332115): 4.886 0.026 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i763|combout
|
|
Info (332115): 4.891 0.005 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i763~la_lab/laboutt[3]
|
|
Info (332115): 6.946 2.055 FF IC High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst|avmmaddress[5]
|
|
Info (332115): 6.946 0.000 FF CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 10.000 10.000 latch edge time
|
|
Info (332115): 13.547 3.547 R clock network delay
|
|
Info (332115): 13.879 0.332 clock pessimism removed
|
|
Info (332115): 13.839 -0.040 clock uncertainty
|
|
Info (332115): 13.837 -0.002 uTsu fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Arrival Time : 6.946
|
|
Info (332115): Data Required Time : 13.837
|
|
Info (332115): Slack : 6.891
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 7.098
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|avmmclk}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 7.098
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_write
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Launch Clock : PCIE_REFCLK
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|avmmclk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 3.835 3.835 R clock network delay
|
|
Info (332115): 3.835 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_write
|
|
Info (332115): 4.018 0.183 FF uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_write|q
|
|
Info (332115): 4.086 0.068 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_write~la_lab/laboutb[0]
|
|
Info (332115): 4.897 0.811 FF IC High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i480~0|datad
|
|
Info (332115): 4.976 0.079 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i480~0|combout
|
|
Info (332115): 4.982 0.006 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i480~0~la_mlab/laboutb[15]
|
|
Info (332115): 6.781 1.799 FF IC High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst|avmmwrite
|
|
Info (332115): 6.781 0.000 FF CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 10.000 10.000 latch edge time
|
|
Info (332115): 13.539 3.539 R clock network delay
|
|
Info (332115): 13.871 0.332 clock pessimism removed
|
|
Info (332115): 13.831 -0.040 clock uncertainty
|
|
Info (332115): 13.879 0.048 uTsu fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Arrival Time : 6.781
|
|
Info (332115): Data Required Time : 13.879
|
|
Info (332115): Slack : 7.098
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 7.368
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|avmmclk}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 7.368
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_address[2]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Launch Clock : PCIE_REFCLK
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|avmmclk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 3.847 3.847 R clock network delay
|
|
Info (332115): 3.847 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_address[2]
|
|
Info (332115): 3.975 0.128 FF uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_address[2]|q
|
|
Info (332115): 4.027 0.052 FF CELL Low Power fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_address[2]~la_lab/laboutb[13]
|
|
Info (332115): 4.499 0.472 FF IC Mixed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i276|datac
|
|
Info (332115): 4.585 0.086 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i276|combout
|
|
Info (332115): 4.591 0.006 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i276~la_mlab/laboutb[9]
|
|
Info (332115): 6.599 2.008 FF IC Mixed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst|avmmaddress[2]
|
|
Info (332115): 6.599 0.000 FF CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 10.000 10.000 latch edge time
|
|
Info (332115): 13.611 3.611 R clock network delay
|
|
Info (332115): 13.962 0.351 clock pessimism removed
|
|
Info (332115): 13.922 -0.040 clock uncertainty
|
|
Info (332115): 13.967 0.045 uTsu fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Arrival Time : 6.599
|
|
Info (332115): Data Required Time : 13.967
|
|
Info (332115): Slack : 7.368
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 8.073
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|avmmclk}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 8.073
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_writedata[3]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Launch Clock : PCIE_REFCLK
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|avmmclk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 3.835 3.835 R clock network delay
|
|
Info (332115): 3.835 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_writedata[3]
|
|
Info (332115): 4.023 0.188 FF uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_writedata[3]|q
|
|
Info (332115): 4.067 0.044 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_writedata[3]~la_lab/laboutt[17]
|
|
Info (332115): 4.857 0.790 FF IC Mixed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i80~3|datae
|
|
Info (332115): 4.915 0.058 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i80~3|combout
|
|
Info (332115): 4.920 0.005 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i80~3~la_mlab/laboutb[8]
|
|
Info (332115): 5.921 1.001 FF IC High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst|avmmwritedata[3]
|
|
Info (332115): 5.921 0.000 FF CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 10.000 10.000 latch edge time
|
|
Info (332115): 13.604 3.604 R clock network delay
|
|
Info (332115): 13.955 0.351 clock pessimism removed
|
|
Info (332115): 13.915 -0.040 clock uncertainty
|
|
Info (332115): 13.994 0.079 uTsu fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Arrival Time : 5.921
|
|
Info (332115): Data Required Time : 13.994
|
|
Info (332115): Slack : 8.073
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 8.121
|
|
Info (20696): -to_clock [get_clocks {vl_qph_user_clk_clkpsc_clk0}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 8.121
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[0]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[1]
|
|
Info (332115): Launch Clock : vl_qph_user_clk_clkpsc_clk0
|
|
Info (332115): Latch Clock : vl_qph_user_clk_clkpsc_clk0
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 4.495 4.495 R clock network delay
|
|
Info (332115): 4.495 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[0]
|
|
Info (332115): 4.624 0.129 RR uTco fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[0]|q
|
|
Info (332115): 4.686 0.062 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[0]~la_mlab/laboutb[9]
|
|
Info (332115): 5.451 0.765 RR IC Mixed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[1]~2|dataa
|
|
Info (332115): 5.576 0.125 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[1]~2|combout
|
|
Info (332115): 5.576 0.000 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[1]|d
|
|
Info (332115): 5.576 0.000 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[1]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 9.090 9.090 latch edge time
|
|
Info (332115): 12.885 3.795 R clock network delay
|
|
Info (332115): 13.581 0.696 clock pessimism removed
|
|
Info (332115): 13.551 -0.030 clock uncertainty
|
|
Info (332115): 13.697 0.146 uTsu fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[1]
|
|
Info (332115): Data Arrival Time : 5.576
|
|
Info (332115): Data Required Time : 13.697
|
|
Info (332115): Slack : 8.121
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 8.753
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk0}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 8.753
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_green_bs|uClk_usrDiv2_q2
|
|
Info (332115): To Node : fpga_top|inst_green_bs|uClk_usrDiv2_q1
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk0
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk0
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 4.229 4.229 R clock network delay
|
|
Info (332115): 4.229 0.000 fpga_top|inst_green_bs|uClk_usrDiv2_q2
|
|
Info (332115): 4.352 0.123 RR uTco fpga_top|inst_green_bs|uClk_usrDiv2_q2|q
|
|
Info (332115): 4.414 0.062 RR CELL High Speed fpga_top|inst_green_bs|uClk_usrDiv2_q2~la_mlab/laboutb[13]
|
|
Info (332115): 4.628 0.214 RR IC High Speed fpga_top|inst_green_bs|uClk_usrDiv2_q1|asdata
|
|
Info (332115): 4.628 0.000 RR CELL High Speed fpga_top|inst_green_bs|uClk_usrDiv2_q1
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 9.090 9.090 latch edge time
|
|
Info (332115): 12.653 3.563 R clock network delay
|
|
Info (332115): 13.318 0.665 clock pessimism removed
|
|
Info (332115): 13.288 -0.030 clock uncertainty
|
|
Info (332115): 13.381 0.093 uTsu fpga_top|inst_green_bs|uClk_usrDiv2_q1
|
|
Info (332115): Data Arrival Time : 4.628
|
|
Info (332115): Data Required Time : 13.381
|
|
Info (332115): Slack : 8.753
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 11.338
|
|
Info (20696): -to_clock [get_clocks {pr_clk_enable_dclk_reg2_user_clk}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 11.338
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_cb_host|alt_pr_cb_controller_v2|pr_request_reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_cb_host|alt_pr_cb_controller_v2|alt_pr_cb_interface|m_prblock~cs_css/pr_clk_core.reg
|
|
Info (332115): Launch Clock : u0|dcp_iopll|dcp_iopll|clk100
|
|
Info (332115): Latch Clock : pr_clk_enable_dclk_reg2_user_clk
|
|
Info (332115): Exception : dcp_bbs.sdc:3118: set_multicycle_path -setup -from [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_cb_host|alt_pr_cb_controller_v2|pr_request_reg}] -to [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_cb_host|alt_pr_cb_controller_v2|alt_pr_cb_interface|m_prblock~cs_css/pr_clk_core.reg}] 2
|
|
Info (332115): Multicycle - Setup Start : 2
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 6.218 6.218 R clock network delay
|
|
Info (332115): 6.218 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_cb_host|alt_pr_cb_controller_v2|pr_request_reg
|
|
Info (332115): 6.404 0.186 FF uTco fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_cb_host|alt_pr_cb_controller_v2|pr_request_reg|q
|
|
Info (332115): 6.472 0.068 FF CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_cb_host|alt_pr_cb_controller_v2|pr_request_reg~la_lab/laboutt[0]
|
|
Info (332115): 10.651 4.179 FF IC High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_cb_host|alt_pr_cb_controller_v2|alt_pr_cb_interface|m_prblock|prrequest
|
|
Info (332115): 10.651 0.000 FF CELL fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_cb_host|alt_pr_cb_controller_v2|alt_pr_cb_interface|m_prblock~cs_css/pr_clk_core.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 15.000 15.000 latch edge time
|
|
Info (332115): 21.152 6.152 R clock network delay
|
|
Info (332115): 21.851 0.699 clock pessimism removed
|
|
Info (332115): 21.681 -0.170 clock uncertainty
|
|
Info (332115): 21.989 0.308 uTsu fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_cb_host|alt_pr_cb_controller_v2|alt_pr_cb_interface|m_prblock~cs_css/pr_clk_core.reg
|
|
Info (332115): Data Arrival Time : 10.651
|
|
Info (332115): Data Required Time : 21.989
|
|
Info (332115): Slack : 11.338
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 18.748
|
|
Info (20696): -to_clock [get_clocks {u0|dcp_iopll|dcp_iopll|clk25}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 18.748
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|generic_quad_spi_controller2_0|generic_quad_spi_controller2_0|asmi2_inst_qspi_ctrl|asmi2_cmd_generator_0|state.ST_SEND_ADDR
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|generic_quad_spi_controller2_0|generic_quad_spi_controller2_0|asmi2_inst_qspi_ctrl|asmi2_qspi_interface_0|dataout_reg[0]~RTM_7
|
|
Info (332115): Launch Clock : u0|dcp_iopll|dcp_iopll|clk25
|
|
Info (332115): Latch Clock : u0|dcp_iopll|dcp_iopll|clk25 (INVERTED)
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 6.352 6.352 R clock network delay
|
|
Info (332115): 6.352 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|generic_quad_spi_controller2_0|generic_quad_spi_controller2_0|asmi2_inst_qspi_ctrl|asmi2_cmd_generator_0|state.ST_SEND_ADDR
|
|
Info (332115): 6.479 0.127 RR uTco fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|generic_quad_spi_controller2_0|generic_quad_spi_controller2_0|asmi2_inst_qspi_ctrl|asmi2_cmd_generator_0|state.ST_SEND_ADDR|q
|
|
Info (332115): 6.542 0.063 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|generic_quad_spi_controller2_0|generic_quad_spi_controller2_0|asmi2_inst_qspi_ctrl|asmi2_cmd_generator_0|state.ST_SEND_ADDR~la_lab/laboutb[13]
|
|
Info (332115): 6.957 0.415 RR IC High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|generic_quad_spi_controller2_0|generic_quad_spi_controller2_0|asmi2_inst_qspi_ctrl|asmi2_cmd_generator_0|Select_8~0|datac
|
|
Info (332115): 7.039 0.082 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|generic_quad_spi_controller2_0|generic_quad_spi_controller2_0|asmi2_inst_qspi_ctrl|asmi2_cmd_generator_0|Select_8~0|combout
|
|
Info (332115): 7.043 0.004 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|generic_quad_spi_controller2_0|generic_quad_spi_controller2_0|asmi2_inst_qspi_ctrl|asmi2_cmd_generator_0|Select_8~0~la_lab/laboutt[4]
|
|
Info (332115): 7.189 0.146 RR IC High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|generic_quad_spi_controller2_0|generic_quad_spi_controller2_0|asmi2_inst_qspi_ctrl|asmi2_qspi_interface_0|dataout_reg[1]~0|dataf
|
|
Info (332115): 7.215 0.026 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|generic_quad_spi_controller2_0|generic_quad_spi_controller2_0|asmi2_inst_qspi_ctrl|asmi2_qspi_interface_0|dataout_reg[1]~0|combout
|
|
Info (332115): 7.219 0.004 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|generic_quad_spi_controller2_0|generic_quad_spi_controller2_0|asmi2_inst_qspi_ctrl|asmi2_qspi_interface_0|dataout_reg[1]~0~la_lab/laboutb[18]
|
|
Info (332115): 7.450 0.231 RR IC High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|generic_quad_spi_controller2_0|generic_quad_spi_controller2_0|asmi2_inst_qspi_ctrl|asmi2_qspi_interface_0|dataout_reg[0]~RTM_7|d
|
|
Info (332115): 7.450 0.000 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|generic_quad_spi_controller2_0|generic_quad_spi_controller2_0|asmi2_inst_qspi_ctrl|asmi2_qspi_interface_0|dataout_reg[0]~RTM_7
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 20.000 20.000 latch edge time
|
|
Info (332115): 25.474 5.474 F clock network delay
|
|
Info (332115): 26.277 0.803 clock pessimism removed
|
|
Info (332115): 26.057 -0.220 clock uncertainty
|
|
Info (332115): 26.198 0.141 uTsu fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|generic_quad_spi_controller2_0|generic_quad_spi_controller2_0|asmi2_inst_qspi_ctrl|asmi2_qspi_interface_0|dataout_reg[0]~RTM_7
|
|
Info (332115): Data Arrival Time : 7.450
|
|
Info (332115): Data Required Time : 26.198
|
|
Info (332115): Slack : 18.748
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 19.508
|
|
Info (20696): -to_clock [get_clocks {u0|dcp_iopll|dcp_iopll|clk50}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 19.508
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_green_bs|pClkDiv4_q2
|
|
Info (332115): To Node : fpga_top|inst_green_bs|pClkDiv4_q1
|
|
Info (332115): Launch Clock : u0|dcp_iopll|dcp_iopll|clk50
|
|
Info (332115): Latch Clock : u0|dcp_iopll|dcp_iopll|clk50
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 6.318 6.318 R clock network delay
|
|
Info (332115): 6.318 0.000 fpga_top|inst_green_bs|pClkDiv4_q2
|
|
Info (332115): 6.440 0.122 RR uTco fpga_top|inst_green_bs|pClkDiv4_q2|q
|
|
Info (332115): 6.502 0.062 RR CELL High Speed fpga_top|inst_green_bs|pClkDiv4_q2~la_mlab/laboutb[17]
|
|
Info (332115): 6.706 0.204 RR IC High Speed fpga_top|inst_green_bs|pClkDiv4_q1|asdata
|
|
Info (332115): 6.706 0.000 RR CELL High Speed fpga_top|inst_green_bs|pClkDiv4_q1
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 20.000 20.000 latch edge time
|
|
Info (332115): 25.495 5.495 R clock network delay
|
|
Info (332115): 26.318 0.823 clock pessimism removed
|
|
Info (332115): 26.128 -0.190 clock uncertainty
|
|
Info (332115): 26.214 0.086 uTsu fpga_top|inst_green_bs|pClkDiv4_q1
|
|
Info (332115): Data Arrival Time : 6.706
|
|
Info (332115): Data Required Time : 26.214
|
|
Info (332115): Slack : 19.508
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 23.109
|
|
Info (20696): -to_clock [get_clocks {filtered_sclk_negedge}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 23.109
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MOSIctl|filtered_mosi_out
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MOSIctl|wrshiftreg[0]
|
|
Info (332115): Launch Clock : u0|dcp_iopll|dcp_iopll|clk1x
|
|
Info (332115): Latch Clock : filtered_sclk_negedge
|
|
Info (332115): Exception : dcp_bbs.sdc:3138: set_max_delay -from [get_keepers {*filtered_mosi*}] 30.000
|
|
Info (332115): Max Delay Exception : 30.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 6.224 6.224 R clock network delay
|
|
Info (332115): 6.224 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MOSIctl|filtered_mosi_out
|
|
Info (332115): 6.407 0.183 FF uTco fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MOSIctl|filtered_mosi_out|q
|
|
Info (332115): 6.451 0.044 FF CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MOSIctl|filtered_mosi_out~la_lab/laboutb[5]
|
|
Info (332115): 6.823 0.372 FF IC High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MOSIctl|wrshiftreg[0]|asdata
|
|
Info (332115): 6.823 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MOSIctl|wrshiftreg[0]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 30.000 30.000 latch edge time
|
|
Info (332115): 30.141 0.141 R clock network delay
|
|
Info (332115): 29.841 -0.300 clock uncertainty
|
|
Info (332115): 29.932 0.091 uTsu fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MOSIctl|wrshiftreg[0]
|
|
Info (332115): Data Arrival Time : 6.823
|
|
Info (332115): Data Required Time : 29.932
|
|
Info (332115): Slack : 23.109
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 42.570
|
|
Info (20696): -to_clock [get_clocks {altera_reserved_tck}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 42.570
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|nios2_gen2_0|nios2_gen2_0|cpu|the_tcm_nios2_gen2_0_altera_nios2_gen2_unit_191_dbuc52a_nios2_oci|the_tcm_nios2_gen2_0_altera_nios2_gen2_unit_191_dbuc52a_debug_slave_wrapper|the_tcm_nios2_gen2_0_altera_nios2_gen2_unit_191_dbuc52a_debug_slave_tck|sr[0]
|
|
Info (332115): To Node : auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|jtagpins|int_tdo_reg~LRTM_5
|
|
Info (332115): Launch Clock : altera_reserved_tck
|
|
Info (332115): Latch Clock : altera_reserved_tck (INVERTED)
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 4.015 4.015 R clock network delay
|
|
Info (332115): 4.015 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|nios2_gen2_0|nios2_gen2_0|cpu|the_tcm_nios2_gen2_0_altera_nios2_gen2_unit_191_dbuc52a_nios2_oci|the_tcm_nios2_gen2_0_altera_nios2_gen2_unit_191_dbuc52a_debug_slave_wrapper|the_tcm_nios2_gen2_0_altera_nios2_gen2_unit_191_dbuc52a_debug_slave_tck|sr[0]
|
|
Info (332115): 4.142 0.127 FF uTco fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|nios2_gen2_0|nios2_gen2_0|cpu|the_tcm_nios2_gen2_0_altera_nios2_gen2_unit_191_dbuc52a_nios2_oci|the_tcm_nios2_gen2_0_altera_nios2_gen2_unit_191_dbuc52a_debug_slave_wrapper|the_tcm_nios2_gen2_0_altera_nios2_gen2_unit_191_dbuc52a_debug_slave_tck|sr[0]|q
|
|
Info (332115): 4.186 0.044 FF CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|nios2_gen2_0|nios2_gen2_0|cpu|the_tcm_nios2_gen2_0_altera_nios2_gen2_unit_191_dbuc52a_nios2_oci|the_tcm_nios2_gen2_0_altera_nios2_gen2_unit_191_dbuc52a_debug_slave_wrapper|the_tcm_nios2_gen2_0_altera_nios2_gen2_unit_191_dbuc52a_debug_slave_tck|sr[0]~la_lab/laboutb[9]
|
|
Info (332115): 4.186 0.000 FF IC auto_fab_0|auto_export_alt_sld_fab_0_alt_sld_fab_0_splitter_send_2[0]|input
|
|
Info (332115): 4.186 0.000 FF CELL auto_fab_0|auto_export_alt_sld_fab_0_alt_sld_fab_0_splitter_send_2[0]
|
|
Info (332115): 9.971 5.785 FF IC High Speed auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|sldfabric|\jtag_hub_gen:real_sld_jtag_hub|i705~4|datab
|
|
Info (332115): 10.072 0.101 FF CELL High Speed auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|sldfabric|\jtag_hub_gen:real_sld_jtag_hub|i705~4|combout
|
|
Info (332115): 10.072 0.000 FF CELL High Speed auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|jtagpins|int_tdo_reg~LRTM_5|d
|
|
Info (332115): 10.072 0.000 FF CELL High Speed auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|jtagpins|int_tdo_reg~LRTM_5
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 50.000 50.000 latch edge time
|
|
Info (332115): 52.177 2.177 F clock network delay
|
|
Info (332115): 52.493 0.316 clock pessimism removed
|
|
Info (332115): 52.463 -0.030 clock uncertainty
|
|
Info (332115): 52.642 0.179 uTsu auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|jtagpins|int_tdo_reg~LRTM_5
|
|
Info (332115): Data Arrival Time : 10.072
|
|
Info (332115): Data Required Time : 52.642
|
|
Info (332115): Slack : 42.570
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.002
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk1}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.002
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[3].core|pipeline|issue|instr_demux|gpu_buffer|shift_reg[1][170]
|
|
Info (332115): To Node : fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[3].core|pipeline|execute|gpu_unit|pipe_reg|value_d[5]
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk1
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk1
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 3.614 3.614 R clock network delay
|
|
Info (332115): 3.614 0.000 fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[3].core|pipeline|issue|instr_demux|gpu_buffer|shift_reg[1][170]
|
|
Info (332115): 3.717 0.103 FF uTco fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[3].core|pipeline|issue|instr_demux|gpu_buffer|shift_reg[1][170]|q
|
|
Info (332115): 3.876 0.159 FF CELL High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[3].core|pipeline|execute|gpu_unit|pipe_reg|value_d[5]|d
|
|
Info (332115): 3.876 0.000 FF CELL High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[3].core|pipeline|execute|gpu_unit|pipe_reg|value_d[5]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 4.287 4.287 R clock network delay
|
|
Info (332115): 3.614 -0.673 clock pessimism removed
|
|
Info (332115): 3.614 0.000 clock uncertainty
|
|
Info (332115): 3.874 0.260 uTh fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[0].cluster|[3].core|pipeline|execute|gpu_unit|pipe_reg|value_d[5]
|
|
Info (332115): Data Arrival Time : 3.876
|
|
Info (332115): Data Required Time : 3.874
|
|
Info (332115): Slack : 0.002
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.013
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|wys~CORE_CLK_OUT}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.013
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_sriov_2.sriov2.sriov_bridge|altpcie_pcie_sriov2_top_inst|altpcie_sriov2_cfg_dataflow_inst|gen_vf_regset_pf0.altpcie_sriov2_cfg_vf_regset_pf0_inst|vf_pci_status_reg_mod|altpcie_sriov2_cfg_vf_bar_check_error_status_fifo|read_ptr[0]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_sriov_2.sriov2.sriov_bridge|altpcie_pcie_sriov2_top_inst|altpcie_sriov2_cfg_dataflow_inst|gen_vf_regset_pf0.altpcie_sriov2_cfg_vf_regset_pf0_inst|vf_pci_status_reg_mod|altpcie_sriov2_cfg_vf_bar_check_error_status_fifo|reg_array_rtl_0|auto_generated|rdaddr_reg[0]
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|wys~CORE_CLK_OUT
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|wys~CORE_CLK_OUT
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 4.956 4.956 R clock network delay
|
|
Info (332115): 4.956 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_sriov_2.sriov2.sriov_bridge|altpcie_pcie_sriov2_top_inst|altpcie_sriov2_cfg_dataflow_inst|gen_vf_regset_pf0.altpcie_sriov2_cfg_vf_regset_pf0_inst|vf_pci_status_reg_mod|altpcie_sriov2_cfg_vf_bar_check_error_status_fifo|read_ptr[0]
|
|
Info (332115): 5.072 0.116 FF uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_sriov_2.sriov2.sriov_bridge|altpcie_pcie_sriov2_top_inst|altpcie_sriov2_cfg_dataflow_inst|gen_vf_regset_pf0.altpcie_sriov2_cfg_vf_regset_pf0_inst|vf_pci_status_reg_mod|altpcie_sriov2_cfg_vf_bar_check_error_status_fifo|read_ptr[0]|q
|
|
Info (332115): 5.072 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_sriov_2.sriov2.sriov_bridge|altpcie_pcie_sriov2_top_inst|altpcie_sriov2_cfg_dataflow_inst|gen_vf_regset_pf0.altpcie_sriov2_cfg_vf_regset_pf0_inst|vf_pci_status_reg_mod|altpcie_sriov2_cfg_vf_bar_check_error_status_fifo|i26~0|datad
|
|
Info (332115): 5.230 0.158 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_sriov_2.sriov2.sriov_bridge|altpcie_pcie_sriov2_top_inst|altpcie_sriov2_cfg_dataflow_inst|gen_vf_regset_pf0.altpcie_sriov2_cfg_vf_regset_pf0_inst|vf_pci_status_reg_mod|altpcie_sriov2_cfg_vf_bar_check_error_status_fifo|i26~0|combout
|
|
Info (332115): 5.230 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_sriov_2.sriov2.sriov_bridge|altpcie_pcie_sriov2_top_inst|altpcie_sriov2_cfg_dataflow_inst|gen_vf_regset_pf0.altpcie_sriov2_cfg_vf_regset_pf0_inst|vf_pci_status_reg_mod|altpcie_sriov2_cfg_vf_bar_check_error_status_fifo|reg_array_rtl_0|auto_generated|rdaddr_reg[0]|d
|
|
Info (332115): 5.230 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_sriov_2.sriov2.sriov_bridge|altpcie_pcie_sriov2_top_inst|altpcie_sriov2_cfg_dataflow_inst|gen_vf_regset_pf0.altpcie_sriov2_cfg_vf_regset_pf0_inst|vf_pci_status_reg_mod|altpcie_sriov2_cfg_vf_bar_check_error_status_fifo|reg_array_rtl_0|auto_generated|rdaddr_reg[0]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 5.835 5.835 R clock network delay
|
|
Info (332115): 4.956 -0.879 clock pessimism removed
|
|
Info (332115): 5.217 0.261 uTh fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_sriov_2.sriov2.sriov_bridge|altpcie_pcie_sriov2_top_inst|altpcie_sriov2_cfg_dataflow_inst|gen_vf_regset_pf0.altpcie_sriov2_cfg_vf_regset_pf0_inst|vf_pci_status_reg_mod|altpcie_sriov2_cfg_vf_bar_check_error_status_fifo|reg_array_rtl_0|auto_generated|rdaddr_reg[0]
|
|
Info (332115): Data Arrival Time : 5.230
|
|
Info (332115): Data Required Time : 5.217
|
|
Info (332115): Slack : 0.013
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.014
|
|
Info (20696): -to_clock [get_clocks {SYS_RefClk}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.014
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|aux_rdata[10]~RTM
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|nct|aux_rdata[10]
|
|
Info (332115): Launch Clock : SYS_RefClk
|
|
Info (332115): Latch Clock : SYS_RefClk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 2.736 2.736 R clock network delay
|
|
Info (332115): 2.736 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|aux_rdata[10]~RTM
|
|
Info (332115): 2.852 0.116 FF uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|aux_rdata[10]~RTM|q
|
|
Info (332115): 2.852 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|Select_21~4|datae
|
|
Info (332115): 3.011 0.159 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|Select_21~4|combout
|
|
Info (332115): 3.011 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|nct|aux_rdata[10]|d
|
|
Info (332115): 3.011 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|nct|aux_rdata[10]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 2.990 2.990 R clock network delay
|
|
Info (332115): 2.736 -0.254 clock pessimism removed
|
|
Info (332115): 2.736 0.000 clock uncertainty
|
|
Info (332115): 2.997 0.261 uTh fpga_top|inst_fiu_top|inst_hssi_ctrl|nct|aux_rdata[10]
|
|
Info (332115): Data Arrival Time : 3.011
|
|
Info (332115): Data Required Time : 2.997
|
|
Info (332115): Slack : 0.014
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.015
|
|
Info (20696): -to_clock [get_clocks {u0|dcp_iopll|dcp_iopll|clk100}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.015
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_ap_mach_C0|e_FSM_ap.vTRIGGER
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_ap_mach_C0|e_FSM_ap.vTRIGGER
|
|
Info (332115): Launch Clock : u0|dcp_iopll|dcp_iopll|clk100
|
|
Info (332115): Latch Clock : u0|dcp_iopll|dcp_iopll|clk100
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 5.466 5.466 R clock network delay
|
|
Info (332115): 5.466 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_ap_mach_C0|e_FSM_ap.vTRIGGER
|
|
Info (332115): 5.582 0.116 FF uTco fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_ap_mach_C0|e_FSM_ap.vTRIGGER|q
|
|
Info (332115): 5.582 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_ap_mach_C0|i66~0|datae
|
|
Info (332115): 5.740 0.158 FF CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_ap_mach_C0|i66~0|combout
|
|
Info (332115): 5.740 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_ap_mach_C0|e_FSM_ap.vTRIGGER|d
|
|
Info (332115): 5.740 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_ap_mach_C0|e_FSM_ap.vTRIGGER
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 6.281 6.281 R clock network delay
|
|
Info (332115): 5.466 -0.815 clock pessimism removed
|
|
Info (332115): 5.466 0.000 clock uncertainty
|
|
Info (332115): 5.725 0.259 uTh fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_ap_mach_C0|e_FSM_ap.vTRIGGER
|
|
Info (332115): Data Arrival Time : 5.740
|
|
Info (332115): Data Required Time : 5.725
|
|
Info (332115): Slack : 0.015
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.015
|
|
Info (20696): -to_clock [get_clocks {u0|dcp_iopll|dcp_iopll|clk1x}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.015
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_perf_mon_fab|inst_ss_fab_ctr|preamble_sent
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_perf_mon_fab|inst_ss_fab_ctr|preamble_sent
|
|
Info (332115): Launch Clock : u0|dcp_iopll|dcp_iopll|clk1x
|
|
Info (332115): Latch Clock : u0|dcp_iopll|dcp_iopll|clk1x
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 5.419 5.419 R clock network delay
|
|
Info (332115): 5.419 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_perf_mon_fab|inst_ss_fab_ctr|preamble_sent
|
|
Info (332115): 5.535 0.116 FF uTco fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_perf_mon_fab|inst_ss_fab_ctr|preamble_sent|q
|
|
Info (332115): 5.535 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_perf_mon_fab|inst_ss_fab_ctr|i13~0|datad
|
|
Info (332115): 5.692 0.157 FF CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_perf_mon_fab|inst_ss_fab_ctr|i13~0|combout
|
|
Info (332115): 5.692 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_perf_mon_fab|inst_ss_fab_ctr|preamble_sent|d
|
|
Info (332115): 5.692 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_perf_mon_fab|inst_ss_fab_ctr|preamble_sent
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 6.221 6.221 R clock network delay
|
|
Info (332115): 5.419 -0.802 clock pessimism removed
|
|
Info (332115): 5.419 0.000 clock uncertainty
|
|
Info (332115): 5.677 0.258 uTh fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_perf_mon_fab|inst_ss_fab_ctr|preamble_sent
|
|
Info (332115): Data Arrival Time : 5.692
|
|
Info (332115): Data Required Time : 5.677
|
|
Info (332115): Slack : 0.015
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.016
|
|
Info (20696): -to_clock [get_clocks {altera_reserved_tck}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.016
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|sldfabric|\jtag_hub_gen:real_sld_jtag_hub|jtag_ir_reg[8]
|
|
Info (332115): To Node : auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|sldfabric|\jtag_hub_gen:real_sld_jtag_hub|jtag_ir_reg[7]
|
|
Info (332115): Launch Clock : altera_reserved_tck
|
|
Info (332115): Latch Clock : altera_reserved_tck
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 2.000 2.000 R clock network delay
|
|
Info (332115): 2.000 0.000 auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|sldfabric|\jtag_hub_gen:real_sld_jtag_hub|jtag_ir_reg[8]
|
|
Info (332115): 2.109 0.109 FF uTco auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|sldfabric|\jtag_hub_gen:real_sld_jtag_hub|jtag_ir_reg[8]|q
|
|
Info (332115): 2.270 0.161 FF CELL High Speed auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|sldfabric|\jtag_hub_gen:real_sld_jtag_hub|jtag_ir_reg[7]|d
|
|
Info (332115): 2.270 0.000 FF CELL High Speed auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|sldfabric|\jtag_hub_gen:real_sld_jtag_hub|jtag_ir_reg[7]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 2.527 2.527 R clock network delay
|
|
Info (332115): 2.004 -0.523 clock pessimism removed
|
|
Info (332115): 2.004 0.000 clock uncertainty
|
|
Info (332115): 2.254 0.250 uTh auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|sldfabric|\jtag_hub_gen:real_sld_jtag_hub|jtag_ir_reg[7]
|
|
Info (332115): Data Arrival Time : 2.270
|
|
Info (332115): Data Required Time : 2.254
|
|
Info (332115): Slack : 0.016
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.018
|
|
Info (20696): -to_clock [get_clocks {u0|dcp_iopll|dcp_iopll|clk25}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.018
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|generic_quad_spi_controller2_0|generic_quad_spi_controller2_0|asmi2_inst_qspi_ctrl|asmi2_qspi_interface_0|datain_reg[5]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|generic_quad_spi_controller2_0|generic_quad_spi_controller2_0|asmi2_inst_qspi_ctrl|asmi2_qspi_interface_0|datain_reg[6]
|
|
Info (332115): Launch Clock : u0|dcp_iopll|dcp_iopll|clk25 (INVERTED)
|
|
Info (332115): Latch Clock : u0|dcp_iopll|dcp_iopll|clk25 (INVERTED)
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 20.000 20.000 launch edge time
|
|
Info (332115): 25.478 5.478 F clock network delay
|
|
Info (332115): 25.478 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|generic_quad_spi_controller2_0|generic_quad_spi_controller2_0|asmi2_inst_qspi_ctrl|asmi2_qspi_interface_0|datain_reg[5]
|
|
Info (332115): 25.589 0.111 FF uTco fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|generic_quad_spi_controller2_0|generic_quad_spi_controller2_0|asmi2_inst_qspi_ctrl|asmi2_qspi_interface_0|datain_reg[5]|q
|
|
Info (332115): 25.759 0.170 FF CELL Low Power fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|generic_quad_spi_controller2_0|generic_quad_spi_controller2_0|asmi2_inst_qspi_ctrl|asmi2_qspi_interface_0|datain_reg[6]|d
|
|
Info (332115): 25.759 0.000 FF CELL Low Power fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|generic_quad_spi_controller2_0|generic_quad_spi_controller2_0|asmi2_inst_qspi_ctrl|asmi2_qspi_interface_0|datain_reg[6]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 20.000 20.000 latch edge time
|
|
Info (332115): 26.312 6.312 F clock network delay
|
|
Info (332115): 25.478 -0.834 clock pessimism removed
|
|
Info (332115): 25.478 0.000 clock uncertainty
|
|
Info (332115): 25.741 0.263 uTh fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|generic_quad_spi_controller2_0|generic_quad_spi_controller2_0|asmi2_inst_qspi_ctrl|asmi2_qspi_interface_0|datain_reg[6]
|
|
Info (332115): Data Arrival Time : 25.759
|
|
Info (332115): Data Required Time : 25.741
|
|
Info (332115): Slack : 0.018
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.020
|
|
Info (20696): -to_clock [get_clocks {mem|ddr4a|ddr4a_core_cal_slave_clk}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.020
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : mem|ddr4b|ddr4b|arch|arch_inst|non_hps.core_clks_rsts_inst|per_if_cal_slave_reset_sync[8]
|
|
Info (332115): To Node : mem|ddr4b|ddr4b|arch|arch_inst|non_hps.core_clks_rsts_inst|per_if_cal_slave_reset_sync[9]
|
|
Info (332115): Launch Clock : mem|ddr4a|ddr4a_core_cal_slave_clk
|
|
Info (332115): Latch Clock : mem|ddr4a|ddr4a_core_cal_slave_clk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 3.543 3.543 R clock network delay
|
|
Info (332115): 3.543 0.000 mem|ddr4b|ddr4b|arch|arch_inst|non_hps.core_clks_rsts_inst|per_if_cal_slave_reset_sync[8]
|
|
Info (332115): 3.643 0.100 FF uTco mem|ddr4b|ddr4b|arch|arch_inst|non_hps.core_clks_rsts_inst|per_if_cal_slave_reset_sync[8]|q
|
|
Info (332115): 3.805 0.162 FF CELL High Speed mem|ddr4b|ddr4b|arch|arch_inst|non_hps.core_clks_rsts_inst|per_if_cal_slave_reset_sync[9]|d
|
|
Info (332115): 3.805 0.000 FF CELL High Speed mem|ddr4b|ddr4b|arch|arch_inst|non_hps.core_clks_rsts_inst|per_if_cal_slave_reset_sync[9]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 4.097 4.097 R clock network delay
|
|
Info (332115): 3.543 -0.554 clock pessimism removed
|
|
Info (332115): 3.543 0.000 clock uncertainty
|
|
Info (332115): 3.785 0.242 uTh mem|ddr4b|ddr4b|arch|arch_inst|non_hps.core_clks_rsts_inst|per_if_cal_slave_reset_sync[9]
|
|
Info (332115): Data Arrival Time : 3.805
|
|
Info (332115): Data Required Time : 3.785
|
|
Info (332115): Slack : 0.020
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.020
|
|
Info (20696): -to_clock [get_clocks {mem|ddr4a|ddr4a_core_usr_clk}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.020
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_green_bs|ddr4a_avmm_bridge|ddr_avmm_bridge|wr_reg_writedata[286]
|
|
Info (332115): To Node : fpga_top|inst_green_bs|ddr4a_avmm_bridge|ddr_avmm_bridge|cmd_writedata[286]
|
|
Info (332115): Launch Clock : mem|ddr4a|ddr4a_core_usr_clk
|
|
Info (332115): Latch Clock : mem|ddr4a|ddr4a_core_usr_clk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.117 0.117 launch edge time
|
|
Info (332115): 1.395 1.278 R clock network delay
|
|
Info (332115): 1.395 0.000 fpga_top|inst_green_bs|ddr4a_avmm_bridge|ddr_avmm_bridge|wr_reg_writedata[286]
|
|
Info (332115): 1.496 0.101 FF uTco fpga_top|inst_green_bs|ddr4a_avmm_bridge|ddr_avmm_bridge|wr_reg_writedata[286]|q
|
|
Info (332115): 1.658 0.162 FF CELL High Speed fpga_top|inst_green_bs|ddr4a_avmm_bridge|ddr_avmm_bridge|cmd_writedata[286]|d
|
|
Info (332115): 1.658 0.000 FF CELL High Speed fpga_top|inst_green_bs|ddr4a_avmm_bridge|ddr_avmm_bridge|cmd_writedata[286]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.117 0.117 latch edge time
|
|
Info (332115): 1.897 1.780 R clock network delay
|
|
Info (332115): 1.396 -0.501 clock pessimism removed
|
|
Info (332115): 1.396 0.000 clock uncertainty
|
|
Info (332115): 1.638 0.242 uTh fpga_top|inst_green_bs|ddr4a_avmm_bridge|ddr_avmm_bridge|cmd_writedata[286]
|
|
Info (332115): Data Arrival Time : 1.658
|
|
Info (332115): Data Required Time : 1.638
|
|
Info (332115): Slack : 0.020
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.021
|
|
Info (20696): -to_clock [get_clocks {DDR4_RefClk}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.021
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|use_counter_lock.counter_lock_gen_master.pll_ref_clk_reset_n_sync_rr
|
|
Info (332115): To Node : mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|use_counter_lock.counter_lock_gen_master.pll_ref_clk_reset_n_sync_rrr
|
|
Info (332115): Launch Clock : DDR4_RefClk
|
|
Info (332115): Latch Clock : DDR4_RefClk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 2.636 2.636 R clock network delay
|
|
Info (332115): 2.636 0.000 mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|use_counter_lock.counter_lock_gen_master.pll_ref_clk_reset_n_sync_rr
|
|
Info (332115): 2.737 0.101 FF uTco mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|use_counter_lock.counter_lock_gen_master.pll_ref_clk_reset_n_sync_rr|q
|
|
Info (332115): 2.899 0.162 FF CELL High Speed mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|use_counter_lock.counter_lock_gen_master.pll_ref_clk_reset_n_sync_rrr|d
|
|
Info (332115): 2.899 0.000 FF CELL High Speed mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|use_counter_lock.counter_lock_gen_master.pll_ref_clk_reset_n_sync_rrr
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 2.850 2.850 R clock network delay
|
|
Info (332115): 2.636 -0.214 clock pessimism removed
|
|
Info (332115): 2.636 0.000 clock uncertainty
|
|
Info (332115): 2.878 0.242 uTh mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|use_counter_lock.counter_lock_gen_master.pll_ref_clk_reset_n_sync_rrr
|
|
Info (332115): Data Arrival Time : 2.899
|
|
Info (332115): Data Required Time : 2.878
|
|
Info (332115): Slack : 0.021
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.021
|
|
Info (20696): -to_clock [get_clocks {PCIE_REFCLK}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.021
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|ltssm_state_sync_inst|resync_chains[2].sync_r[0]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|ltssm_state_sync_inst|resync_chains[2].sync_r[1]
|
|
Info (332115): Launch Clock : PCIE_REFCLK
|
|
Info (332115): Latch Clock : PCIE_REFCLK
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 3.435 3.435 R clock network delay
|
|
Info (332115): 3.435 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|ltssm_state_sync_inst|resync_chains[2].sync_r[0]
|
|
Info (332115): 3.535 0.100 FF uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|ltssm_state_sync_inst|resync_chains[2].sync_r[0]|q
|
|
Info (332115): 3.697 0.162 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|ltssm_state_sync_inst|resync_chains[2].sync_r[1]|d
|
|
Info (332115): 3.697 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|ltssm_state_sync_inst|resync_chains[2].sync_r[1]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 3.820 3.820 R clock network delay
|
|
Info (332115): 3.435 -0.385 clock pessimism removed
|
|
Info (332115): 3.435 0.000 clock uncertainty
|
|
Info (332115): 3.676 0.241 uTh fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|ltssm_state_sync_inst|resync_chains[2].sync_r[1]
|
|
Info (332115): Data Arrival Time : 3.697
|
|
Info (332115): Data Required Time : 3.676
|
|
Info (332115): Slack : 0.021
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.021
|
|
Info (20696): -to_clock [get_clocks {filtered_sclk_negedge}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.021
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MOSIctl|wrshiftreg[0]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MOSIctl|wrshiftreg[1]
|
|
Info (332115): Launch Clock : filtered_sclk_negedge
|
|
Info (332115): Latch Clock : filtered_sclk_negedge
|
|
Info (332115): Exception : dcp_bbs.sdc:3040: set_multicycle_path -hold -to [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MOSIctl|wrshiftreg[1]}] 1
|
|
Info (332115): Multicycle - Setup Start : 2
|
|
Info (332115): Multicycle - Hold Start : 1
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 0.141 0.141 R clock network delay
|
|
Info (332115): 0.141 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MOSIctl|wrshiftreg[0]
|
|
Info (332115): 0.247 0.106 FF uTco fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MOSIctl|wrshiftreg[0]|q
|
|
Info (332115): 0.415 0.168 FF CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MOSIctl|wrshiftreg[1]|d
|
|
Info (332115): 0.415 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MOSIctl|wrshiftreg[1]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 0.167 0.167 R clock network delay
|
|
Info (332115): 0.144 -0.023 clock pessimism removed
|
|
Info (332115): 0.394 0.250 uTh fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MOSIctl|wrshiftreg[1]
|
|
Info (332115): Data Arrival Time : 0.415
|
|
Info (332115): Data Required Time : 0.394
|
|
Info (332115): Slack : 0.021
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.021
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|rx_pma_clk}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.021
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_prbs_err_sync|resync_chains[0].sync_r[0]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_prbs_err_sync|resync_chains[0].sync_r[1]
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|rx_pma_clk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|rx_pma_clk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 1.927 1.927 R clock network delay
|
|
Info (332115): 1.927 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_prbs_err_sync|resync_chains[0].sync_r[0]
|
|
Info (332115): 2.027 0.100 FF uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_prbs_err_sync|resync_chains[0].sync_r[0]|q
|
|
Info (332115): 2.189 0.162 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_prbs_err_sync|resync_chains[0].sync_r[1]|d
|
|
Info (332115): 2.189 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_prbs_err_sync|resync_chains[0].sync_r[1]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 2.922 2.922 R clock network delay
|
|
Info (332115): 1.926 -0.996 clock pessimism removed
|
|
Info (332115): 1.926 0.000 clock uncertainty
|
|
Info (332115): 2.168 0.242 uTh fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_prbs_err_sync|resync_chains[0].sync_r[1]
|
|
Info (332115): Data Arrival Time : 2.189
|
|
Info (332115): Data Required Time : 2.168
|
|
Info (332115): Slack : 0.021
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.021
|
|
Info (20696): -to_clock [get_clocks {hssi_pll_t_outclk1}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.021
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[1].ct0|dout_r[1]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[1].ct0|dout_r[1]
|
|
Info (332115): Launch Clock : hssi_pll_t_outclk1
|
|
Info (332115): Latch Clock : hssi_pll_t_outclk1
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 2.693 2.693 R clock network delay
|
|
Info (332115): 2.693 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[1].ct0|dout_r[1]
|
|
Info (332115): 2.798 0.105 FF uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[1].ct0|dout_r[1]|q
|
|
Info (332115): 2.798 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[1].ct0|t1|dout|datae
|
|
Info (332115): 2.956 0.158 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[1].ct0|t1|dout|combout
|
|
Info (332115): 2.956 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[1].ct0|dout_r[1]|d
|
|
Info (332115): 2.956 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[1].ct0|dout_r[1]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 2.975 2.975 R clock network delay
|
|
Info (332115): 2.693 -0.282 clock pessimism removed
|
|
Info (332115): 2.693 0.000 clock uncertainty
|
|
Info (332115): 2.935 0.242 uTh fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[1].ct0|dout_r[1]
|
|
Info (332115): Data Arrival Time : 2.956
|
|
Info (332115): Data Required Time : 2.935
|
|
Info (332115): Slack : 0.021
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.023
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk0}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.023
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_green_bs|uClk_usrDiv2_q1
|
|
Info (332115): To Node : fpga_top|inst_green_bs|uClk_usrDiv2_q2
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk0
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk0
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 3.563 3.563 R clock network delay
|
|
Info (332115): 3.563 0.000 fpga_top|inst_green_bs|uClk_usrDiv2_q1
|
|
Info (332115): 3.666 0.103 FF uTco fpga_top|inst_green_bs|uClk_usrDiv2_q1|q
|
|
Info (332115): 3.666 0.000 FF CELL High Speed fpga_top|inst_green_bs|uClk_usrDiv2_q2~0|datae
|
|
Info (332115): 3.827 0.161 FR CELL High Speed fpga_top|inst_green_bs|uClk_usrDiv2_q2~0|combout
|
|
Info (332115): 3.827 0.000 RR CELL High Speed fpga_top|inst_green_bs|uClk_usrDiv2_q2|d
|
|
Info (332115): 3.827 0.000 RR CELL High Speed fpga_top|inst_green_bs|uClk_usrDiv2_q2
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 4.229 4.229 R clock network delay
|
|
Info (332115): 3.564 -0.665 clock pessimism removed
|
|
Info (332115): 3.564 0.000 clock uncertainty
|
|
Info (332115): 3.804 0.240 uTh fpga_top|inst_green_bs|uClk_usrDiv2_q2
|
|
Info (332115): Data Arrival Time : 3.827
|
|
Info (332115): Data Required Time : 3.804
|
|
Info (332115): Slack : 0.023
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.024
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_clk}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.024
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[7].ct0|dout_r[1]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[7].ct0|dout_r[1]
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_clk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_clk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 2.091 2.091 R clock network delay
|
|
Info (332115): 2.091 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[7].ct0|dout_r[1]
|
|
Info (332115): 2.192 0.101 FF uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[7].ct0|dout_r[1]|q
|
|
Info (332115): 2.192 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[7].ct0|t1|dout|datae
|
|
Info (332115): 2.353 0.161 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[7].ct0|t1|dout|combout
|
|
Info (332115): 2.353 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[7].ct0|dout_r[1]|d
|
|
Info (332115): 2.353 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[7].ct0|dout_r[1]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 3.065 3.065 R clock network delay
|
|
Info (332115): 2.091 -0.974 clock pessimism removed
|
|
Info (332115): 2.091 0.000 clock uncertainty
|
|
Info (332115): 2.329 0.238 uTh fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[7].ct0|dout_r[1]
|
|
Info (332115): Data Arrival Time : 2.353
|
|
Info (332115): Data Required Time : 2.329
|
|
Info (332115): Slack : 0.024
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.024
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_div_clk}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.024
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[4].ct0|dout_r[5]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[4].ct0|dout_r[5]
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_div_clk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_div_clk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 5.021 5.021 R clock network delay
|
|
Info (332115): 5.021 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[4].ct0|dout_r[5]
|
|
Info (332115): 5.121 0.100 FF uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[4].ct0|dout_r[5]|q
|
|
Info (332115): 5.121 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[4].ct0|t5|dout|datae
|
|
Info (332115): 5.282 0.161 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[4].ct0|t5|dout|combout
|
|
Info (332115): 5.282 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[4].ct0|dout_r[5]|d
|
|
Info (332115): 5.282 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[4].ct0|dout_r[5]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 6.354 6.354 R clock network delay
|
|
Info (332115): 5.021 -1.333 clock pessimism removed
|
|
Info (332115): 5.021 0.000 clock uncertainty
|
|
Info (332115): 5.258 0.237 uTh fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[4].ct0|dout_r[5]
|
|
Info (332115): Data Arrival Time : 5.282
|
|
Info (332115): Data Required Time : 5.258
|
|
Info (332115): Slack : 0.024
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.025
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|rx_pma_clk}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.025
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_consecutive_error[0]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_consecutive_error[0]
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|rx_pma_clk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|rx_pma_clk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 2.034 2.034 R clock network delay
|
|
Info (332115): 2.034 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_consecutive_error[0]
|
|
Info (332115): 2.133 0.099 FF uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_consecutive_error[0]|q
|
|
Info (332115): 2.133 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|i41~1|datae
|
|
Info (332115): 2.293 0.160 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|i41~1|combout
|
|
Info (332115): 2.293 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_consecutive_error[0]|d
|
|
Info (332115): 2.293 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_consecutive_error[0]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 3.026 3.026 R clock network delay
|
|
Info (332115): 2.035 -0.991 clock pessimism removed
|
|
Info (332115): 2.035 0.000 clock uncertainty
|
|
Info (332115): 2.268 0.233 uTh fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_consecutive_error[0]
|
|
Info (332115): Data Arrival Time : 2.293
|
|
Info (332115): Data Required Time : 2.268
|
|
Info (332115): Slack : 0.025
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.026
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|tx_pma_div_clk}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.026
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[5].ct0|dout_r[3]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[5].ct0|dout_r[3]
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|tx_pma_div_clk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|tx_pma_div_clk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 4.647 4.647 R clock network delay
|
|
Info (332115): 4.647 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[5].ct0|dout_r[3]
|
|
Info (332115): 4.747 0.100 FF uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[5].ct0|dout_r[3]|q
|
|
Info (332115): 4.747 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[5].ct0|t3|dout|datae
|
|
Info (332115): 4.908 0.161 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[5].ct0|t3|dout|combout
|
|
Info (332115): 4.908 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[5].ct0|dout_r[3]|d
|
|
Info (332115): 4.908 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[5].ct0|dout_r[3]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 5.917 5.917 R clock network delay
|
|
Info (332115): 4.648 -1.269 clock pessimism removed
|
|
Info (332115): 4.648 0.000 clock uncertainty
|
|
Info (332115): 4.882 0.234 uTh fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[5].ct0|dout_r[3]
|
|
Info (332115): Data Arrival Time : 4.908
|
|
Info (332115): Data Required Time : 4.882
|
|
Info (332115): Slack : 0.026
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.026
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|rx_pma_clk}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.026
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_consecutive_error[0]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_consecutive_error[0]
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|rx_pma_clk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|rx_pma_clk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 2.074 2.074 R clock network delay
|
|
Info (332115): 2.074 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_consecutive_error[0]
|
|
Info (332115): 2.174 0.100 FF uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_consecutive_error[0]|q
|
|
Info (332115): 2.174 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|i41~1|datae
|
|
Info (332115): 2.335 0.161 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|i41~1|combout
|
|
Info (332115): 2.335 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_consecutive_error[0]|d
|
|
Info (332115): 2.335 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_consecutive_error[0]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 3.052 3.052 R clock network delay
|
|
Info (332115): 2.074 -0.978 clock pessimism removed
|
|
Info (332115): 2.074 0.000 clock uncertainty
|
|
Info (332115): 2.309 0.235 uTh fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_consecutive_error[0]
|
|
Info (332115): Data Arrival Time : 2.335
|
|
Info (332115): Data Required Time : 2.309
|
|
Info (332115): Slack : 0.026
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.026
|
|
Info (20696): -to_clock [get_clocks {hssi_pll_r_0_outclk0}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.026
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[2].ct0|dout_r[0]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[2].ct0|dout_r[0]
|
|
Info (332115): Launch Clock : hssi_pll_r_0_outclk0
|
|
Info (332115): Latch Clock : hssi_pll_r_0_outclk0
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 2.875 2.875 R clock network delay
|
|
Info (332115): 2.875 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[2].ct0|dout_r[0]
|
|
Info (332115): 2.981 0.106 FF uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[2].ct0|dout_r[0]|q
|
|
Info (332115): 2.981 0.000 FF CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[2].ct0|t0|dout|datad
|
|
Info (332115): 3.152 0.171 FR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[2].ct0|t0|dout|combout
|
|
Info (332115): 3.152 0.000 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[2].ct0|dout_r[0]|d
|
|
Info (332115): 3.152 0.000 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[2].ct0|dout_r[0]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 3.197 3.197 R clock network delay
|
|
Info (332115): 2.875 -0.322 clock pessimism removed
|
|
Info (332115): 2.875 0.000 clock uncertainty
|
|
Info (332115): 3.126 0.251 uTh fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[2].ct0|dout_r[0]
|
|
Info (332115): Data Arrival Time : 3.152
|
|
Info (332115): Data Required Time : 3.126
|
|
Info (332115): Slack : 0.026
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.029
|
|
Info (20696): -to_clock [get_clocks {hssi_pll_r_0_outclk1}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.029
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[0].ct0|dout_r[0]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[0].ct0|dout_r[0]
|
|
Info (332115): Launch Clock : hssi_pll_r_0_outclk1
|
|
Info (332115): Latch Clock : hssi_pll_r_0_outclk1
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 2.867 2.867 R clock network delay
|
|
Info (332115): 2.867 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[0].ct0|dout_r[0]
|
|
Info (332115): 2.972 0.105 FF uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[0].ct0|dout_r[0]|q
|
|
Info (332115): 2.972 0.000 FF CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[0].ct0|t0|dout|datad
|
|
Info (332115): 3.143 0.171 FR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[0].ct0|t0|dout|combout
|
|
Info (332115): 3.143 0.000 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[0].ct0|dout_r[0]|d
|
|
Info (332115): 3.143 0.000 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[0].ct0|dout_r[0]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 3.190 3.190 R clock network delay
|
|
Info (332115): 2.867 -0.323 clock pessimism removed
|
|
Info (332115): 2.867 0.000 clock uncertainty
|
|
Info (332115): 3.114 0.247 uTh fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[0].ct0|dout_r[0]
|
|
Info (332115): Data Arrival Time : 3.143
|
|
Info (332115): Data Required Time : 3.114
|
|
Info (332115): Slack : 0.029
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.030
|
|
Info (20696): -to_clock [get_clocks {hssi_pll_t_outclk0}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.030
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[3].ct0|dout_r[1]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[3].ct0|dout_r[1]
|
|
Info (332115): Launch Clock : hssi_pll_t_outclk0
|
|
Info (332115): Latch Clock : hssi_pll_t_outclk0
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 2.711 2.711 R clock network delay
|
|
Info (332115): 2.711 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[3].ct0|dout_r[1]
|
|
Info (332115): 2.815 0.104 FF uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[3].ct0|dout_r[1]|q
|
|
Info (332115): 2.815 0.000 FF CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[3].ct0|t1|dout|datae
|
|
Info (332115): 2.984 0.169 FF CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[3].ct0|t1|dout|combout
|
|
Info (332115): 2.984 0.000 FF CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[3].ct0|dout_r[1]|d
|
|
Info (332115): 2.984 0.000 FF CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[3].ct0|dout_r[1]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 2.998 2.998 R clock network delay
|
|
Info (332115): 2.711 -0.287 clock pessimism removed
|
|
Info (332115): 2.711 0.000 clock uncertainty
|
|
Info (332115): 2.954 0.243 uTh fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[3].ct0|dout_r[1]
|
|
Info (332115): Data Arrival Time : 2.984
|
|
Info (332115): Data Required Time : 2.954
|
|
Info (332115): Slack : 0.030
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.031
|
|
Info (20696): -to_clock [get_clocks {ETH_RefClk}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.031
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[6].ct0|dout_r[1]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[6].ct0|dout_r[1]
|
|
Info (332115): Launch Clock : ETH_RefClk
|
|
Info (332115): Latch Clock : ETH_RefClk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 3.395 3.395 R clock network delay
|
|
Info (332115): 3.395 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[6].ct0|dout_r[1]
|
|
Info (332115): 3.501 0.106 FF uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[6].ct0|dout_r[1]|q
|
|
Info (332115): 3.501 0.000 FF CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[6].ct0|t1|dout|datae
|
|
Info (332115): 3.673 0.172 FF CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[6].ct0|t1|dout|combout
|
|
Info (332115): 3.673 0.000 FF CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[6].ct0|dout_r[1]|d
|
|
Info (332115): 3.673 0.000 FF CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[6].ct0|dout_r[1]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 3.788 3.788 R clock network delay
|
|
Info (332115): 3.395 -0.393 clock pessimism removed
|
|
Info (332115): 3.395 0.000 clock uncertainty
|
|
Info (332115): 3.642 0.247 uTh fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[6].ct0|dout_r[1]
|
|
Info (332115): Data Arrival Time : 3.673
|
|
Info (332115): Data Required Time : 3.642
|
|
Info (332115): Slack : 0.031
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.035
|
|
Info (20696): -to_clock [get_clocks {u0|dcp_iopll|dcp_iopll|clk50}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.035
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_green_bs|pClkDiv4_q1
|
|
Info (332115): To Node : fpga_top|inst_green_bs|pClkDiv4_q2
|
|
Info (332115): Launch Clock : u0|dcp_iopll|dcp_iopll|clk50
|
|
Info (332115): Latch Clock : u0|dcp_iopll|dcp_iopll|clk50
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 5.495 5.495 R clock network delay
|
|
Info (332115): 5.495 0.000 fpga_top|inst_green_bs|pClkDiv4_q1
|
|
Info (332115): 5.603 0.108 FF uTco fpga_top|inst_green_bs|pClkDiv4_q1|q
|
|
Info (332115): 5.603 0.000 FF CELL High Speed fpga_top|inst_green_bs|pClkDiv4_q2~0|datae
|
|
Info (332115): 5.766 0.163 FR CELL High Speed fpga_top|inst_green_bs|pClkDiv4_q2~0|combout
|
|
Info (332115): 5.766 0.000 RR CELL High Speed fpga_top|inst_green_bs|pClkDiv4_q2|d
|
|
Info (332115): 5.766 0.000 RR CELL High Speed fpga_top|inst_green_bs|pClkDiv4_q2
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 6.318 6.318 R clock network delay
|
|
Info (332115): 5.495 -0.823 clock pessimism removed
|
|
Info (332115): 5.495 0.000 clock uncertainty
|
|
Info (332115): 5.731 0.236 uTh fpga_top|inst_green_bs|pClkDiv4_q2
|
|
Info (332115): Data Arrival Time : 5.766
|
|
Info (332115): Data Required Time : 5.731
|
|
Info (332115): Slack : 0.035
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.076
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_bonding_clocks[0]}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.076
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|sta_rx_clk2_by4_1
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs~byte_deserializer_pcs_clk_div_by_4_txclk_reg.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|rx_clk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_bonding_clocks[0]
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 1.776 1.776 R clock network delay
|
|
Info (332115): 1.776 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|sta_rx_clk2_by4_1
|
|
Info (332115): 1.776 0.000 RR CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs~byte_deserializer_pcs_clk_div_by_4_txclk_reg.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 2.362 2.362 R clock network delay
|
|
Info (332115): 1.592 -0.770 clock pessimism removed
|
|
Info (332115): 1.700 0.108 uTh fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs~byte_deserializer_pcs_clk_div_by_4_txclk_reg.reg
|
|
Info (332115): Data Arrival Time : 1.776
|
|
Info (332115): Data Required Time : 1.700
|
|
Info (332115): Slack : 0.076
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.108
|
|
Info (20696): -to_clock [get_clocks {fspi_sclk}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.108
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MISOctl|rdshiftreg[4]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MISOctl|rdshiftreg[5]
|
|
Info (332115): Launch Clock : fspi_sclk
|
|
Info (332115): Latch Clock : fspi_sclk
|
|
Info (332115): Exception : dcp_bbs.sdc:3007: set_multicycle_path -hold -to [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MISOctl|rdshiftreg*}] 1
|
|
Info (332115): Multicycle - Setup Start : 2
|
|
Info (332115): Multicycle - Hold Start : 1
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 3.397 3.397 R clock network delay
|
|
Info (332115): 3.397 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MISOctl|rdshiftreg[4]
|
|
Info (332115): 3.498 0.101 FF uTco fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MISOctl|rdshiftreg[4]|q
|
|
Info (332115): 3.531 0.033 FF CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MISOctl|rdshiftreg[4]~la_lab/laboutt[10]
|
|
Info (332115): 3.657 0.126 FF IC High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MISOctl|i36~2|datab
|
|
Info (332115): 3.740 0.083 FF CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MISOctl|i36~2|combout
|
|
Info (332115): 3.740 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MISOctl|rdshiftreg[5]|d
|
|
Info (332115): 3.740 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MISOctl|rdshiftreg[5]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 3.930 3.930 R clock network delay
|
|
Info (332115): 3.397 -0.533 clock pessimism removed
|
|
Info (332115): 3.397 0.000 clock uncertainty
|
|
Info (332115): 3.632 0.235 uTh fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MISOctl|rdshiftreg[5]
|
|
Info (332115): Data Arrival Time : 3.740
|
|
Info (332115): Data Required Time : 3.632
|
|
Info (332115): Slack : 0.108
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.192
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|pld_clk}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.192
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_sriov_2.sriov2.sriov_bridge|altpcie_pcie_sriov2_top_inst|altpcie_sriov2_cfg_dataflow_inst|device_control_reg_max_payload_size_o[0]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~pld_clk.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|wys~CORE_CLK_OUT
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|pld_clk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 4.962 4.962 R clock network delay
|
|
Info (332115): 4.962 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_sriov_2.sriov2.sriov_bridge|altpcie_pcie_sriov2_top_inst|altpcie_sriov2_cfg_dataflow_inst|device_control_reg_max_payload_size_o[0]
|
|
Info (332115): 5.065 0.103 FF uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_sriov_2.sriov2.sriov_bridge|altpcie_pcie_sriov2_top_inst|altpcie_sriov2_cfg_dataflow_inst|device_control_reg_max_payload_size_o[0]|q
|
|
Info (332115): 5.117 0.052 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_sriov_2.sriov2.sriov_bridge|altpcie_pcie_sriov2_top_inst|altpcie_sriov2_cfg_dataflow_inst|device_control_reg_max_payload_size_o[0]~la_mlab/laboutb[8]
|
|
Info (332115): 5.565 0.448 FF IC High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|app_msi_num[0]
|
|
Info (332115): 5.565 0.000 FF CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~pld_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 6.001 6.001 R clock network delay
|
|
Info (332115): 5.153 -0.848 clock pessimism removed
|
|
Info (332115): 5.220 0.067 clock uncertainty
|
|
Info (332115): 5.373 0.153 uTh fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~pld_clk.reg
|
|
Info (332115): Data Arrival Time : 5.565
|
|
Info (332115): Data Required Time : 5.373
|
|
Info (332115): Slack : 0.192
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.218
|
|
Info (20696): -to_clock [get_clocks {mem|ddr4a|ddr4a_phy_clk_l_0}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.218
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : mem|ddr4a_bridge|ddr_avmm_bridge|cmd_address[14]
|
|
Info (332115): To Node : mem|ddr4a|ddr4a|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[1].tile_ctrl_inst~hmc_reg1
|
|
Info (332115): Launch Clock : mem|ddr4a|ddr4a_core_usr_clk
|
|
Info (332115): Latch Clock : mem|ddr4a|ddr4a_phy_clk_l_0
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.117 0.117 launch edge time
|
|
Info (332115): 1.430 1.313 R clock network delay
|
|
Info (332115): 1.430 0.000 mem|ddr4a_bridge|ddr_avmm_bridge|cmd_address[14]
|
|
Info (332115): 1.531 0.101 FF uTco mem|ddr4a_bridge|ddr_avmm_bridge|cmd_address[14]|q
|
|
Info (332115): 1.564 0.033 FF CELL High Speed mem|ddr4a_bridge|ddr_avmm_bridge|cmd_address[14]~la_lab/laboutt[1]
|
|
Info (332115): 1.644 0.080 FF IC High Speed mem|ddr4a_avmm_chkr|avm_address[14]~14|datac
|
|
Info (332115): 1.707 0.063 FF CELL High Speed mem|ddr4a_avmm_chkr|avm_address[14]~14|combout
|
|
Info (332115): 1.709 0.002 FF CELL High Speed mem|ddr4a_avmm_chkr|avm_address[14]~14~la_lab/laboutt[3]
|
|
Info (332115): 2.215 0.506 FF IC High Speed mem|ddr4a|ddr4a|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[1].tile_ctrl_inst|core2ctl_avl0[16]
|
|
Info (332115): 2.215 0.000 FF CELL mem|ddr4a|ddr4a|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[1].tile_ctrl_inst~hmc_reg1
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.117 0.117 latch edge time
|
|
Info (332115): 1.790 1.673 R clock network delay
|
|
Info (332115): 1.521 -0.269 clock pessimism removed
|
|
Info (332115): 1.744 0.223 clock uncertainty
|
|
Info (332115): 1.997 0.253 uTh mem|ddr4a|ddr4a|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[1].tile_ctrl_inst~hmc_reg1
|
|
Info (332115): Data Arrival Time : 2.215
|
|
Info (332115): Data Required Time : 1.997
|
|
Info (332115): Slack : 0.218
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.223
|
|
Info (20696): -to_clock [get_clocks {mem|ddr4a|ddr4a_phy_clk_l_2}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.223
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : mem|ddr4a_bridge|ddr_avmm_bridge|cmd_writedata[20]
|
|
Info (332115): To Node : mem|ddr4a|ddr4a|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[0].lane_gen[2].lane_inst~phy_reg1
|
|
Info (332115): Launch Clock : mem|ddr4a|ddr4a_core_usr_clk
|
|
Info (332115): Latch Clock : mem|ddr4a|ddr4a_phy_clk_l_2
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.117 0.117 launch edge time
|
|
Info (332115): 1.425 1.308 R clock network delay
|
|
Info (332115): 1.425 0.000 mem|ddr4a_bridge|ddr_avmm_bridge|cmd_writedata[20]
|
|
Info (332115): 1.526 0.101 FF uTco mem|ddr4a_bridge|ddr_avmm_bridge|cmd_writedata[20]|q
|
|
Info (332115): 1.559 0.033 FF CELL High Speed mem|ddr4a_bridge|ddr_avmm_bridge|cmd_writedata[20]~la_lab/laboutt[6]
|
|
Info (332115): 1.655 0.096 FF IC High Speed mem|ddr4a_avmm_chkr|avm_writedata[20]~160|datab
|
|
Info (332115): 1.739 0.084 FF CELL High Speed mem|ddr4a_avmm_chkr|avm_writedata[20]~160|combout
|
|
Info (332115): 1.741 0.002 FF CELL High Speed mem|ddr4a_avmm_chkr|avm_writedata[20]~160~la_lab/laboutb[17]
|
|
Info (332115): 2.457 0.716 FF IC High Speed mem|ddr4a|ddr4a|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[0].lane_gen[2].lane_inst|data_from_core[48]
|
|
Info (332115): 2.457 0.000 FF CELL mem|ddr4a|ddr4a|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[0].lane_gen[2].lane_inst~phy_reg1
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.117 0.117 latch edge time
|
|
Info (332115): 1.785 1.668 R clock network delay
|
|
Info (332115): 1.700 -0.085 clock pessimism removed
|
|
Info (332115): 2.020 0.320 clock uncertainty
|
|
Info (332115): 2.234 0.214 uTh mem|ddr4a|ddr4a|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[0].lane_gen[2].lane_inst~phy_reg1
|
|
Info (332115): Data Arrival Time : 2.457
|
|
Info (332115): Data Required Time : 2.234
|
|
Info (332115): Slack : 0.223
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.227
|
|
Info (20696): -to_clock [get_clocks {mem|ddr4b|ddr4b_phy_clk_l_2}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.227
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : mem|ddr4b_bridge|ddr_avmm_bridge|cmd_writedata[141]
|
|
Info (332115): To Node : mem|ddr4b|ddr4b|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[0].lane_gen[1].lane_inst~phy_reg1
|
|
Info (332115): Launch Clock : mem|ddr4a|ddr4a_core_usr_clk
|
|
Info (332115): Latch Clock : mem|ddr4b|ddr4b_phy_clk_l_2
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.117 0.117 launch edge time
|
|
Info (332115): 1.372 1.255 R clock network delay
|
|
Info (332115): 1.372 0.000 mem|ddr4b_bridge|ddr_avmm_bridge|cmd_writedata[141]
|
|
Info (332115): 1.473 0.101 FF uTco mem|ddr4b_bridge|ddr_avmm_bridge|cmd_writedata[141]|q
|
|
Info (332115): 1.506 0.033 FF CELL High Speed mem|ddr4b_bridge|ddr_avmm_bridge|cmd_writedata[141]~la_mlab/laboutb[1]
|
|
Info (332115): 1.904 0.398 FF IC High Speed mem|ddr4b_avmm_chkr|avm_writedata[0]~106|datab
|
|
Info (332115): 1.987 0.083 FF CELL High Speed mem|ddr4b_avmm_chkr|avm_writedata[0]~106|combout
|
|
Info (332115): 1.990 0.003 FF CELL High Speed mem|ddr4b_avmm_chkr|avm_writedata[0]~106~la_mlab/laboutb[8]
|
|
Info (332115): 2.446 0.456 FF IC High Speed mem|ddr4b|ddr4b|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[0].lane_gen[1].lane_inst|data_from_core[2]
|
|
Info (332115): 2.446 0.000 FF CELL mem|ddr4b|ddr4b|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[0].lane_gen[1].lane_inst~phy_reg1
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.117 0.117 latch edge time
|
|
Info (332115): 1.745 1.628 R clock network delay
|
|
Info (332115): 1.698 -0.047 clock pessimism removed
|
|
Info (332115): 2.018 0.320 clock uncertainty
|
|
Info (332115): 2.219 0.201 uTh mem|ddr4b|ddr4b|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[0].lane_gen[1].lane_inst~phy_reg1
|
|
Info (332115): Data Arrival Time : 2.446
|
|
Info (332115): Data Required Time : 2.219
|
|
Info (332115): Slack : 0.227
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.236
|
|
Info (20696): -to_clock [get_clocks {mem|ddr4b|ddr4b_phy_clk_l_0}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.236
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : mem|ddr4b_bridge|ddr_avmm_bridge|cmd_address[23]
|
|
Info (332115): To Node : mem|ddr4b|ddr4b|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[1].tile_ctrl_inst~hmc_reg1
|
|
Info (332115): Launch Clock : mem|ddr4a|ddr4a_core_usr_clk
|
|
Info (332115): Latch Clock : mem|ddr4b|ddr4b_phy_clk_l_0
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.117 0.117 launch edge time
|
|
Info (332115): 1.341 1.224 R clock network delay
|
|
Info (332115): 1.341 0.000 mem|ddr4b_bridge|ddr_avmm_bridge|cmd_address[23]
|
|
Info (332115): 1.441 0.100 FF uTco mem|ddr4b_bridge|ddr_avmm_bridge|cmd_address[23]|q
|
|
Info (332115): 1.474 0.033 FF CELL High Speed mem|ddr4b_bridge|ddr_avmm_bridge|cmd_address[23]~la_mlab/laboutb[13]
|
|
Info (332115): 1.817 0.343 FF IC High Speed mem|ddr4b_emif_address_mux[23]~23|datab
|
|
Info (332115): 1.901 0.084 FF CELL High Speed mem|ddr4b_emif_address_mux[23]~23|combout
|
|
Info (332115): 1.904 0.003 FF CELL High Speed mem|ddr4b_emif_address_mux[23]~23~la_mlab/laboutt[12]
|
|
Info (332115): 2.511 0.607 FF IC High Speed mem|ddr4b|ddr4b|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[1].tile_ctrl_inst|core2ctl_avl0[25]
|
|
Info (332115): 2.511 0.000 FF CELL mem|ddr4b|ddr4b|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[1].tile_ctrl_inst~hmc_reg1
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.117 0.117 latch edge time
|
|
Info (332115): 1.748 1.631 R clock network delay
|
|
Info (332115): 1.701 -0.047 clock pessimism removed
|
|
Info (332115): 2.021 0.320 clock uncertainty
|
|
Info (332115): 2.275 0.254 uTh mem|ddr4b|ddr4b|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[1].tile_ctrl_inst~hmc_reg1
|
|
Info (332115): Data Arrival Time : 2.511
|
|
Info (332115): Data Required Time : 2.275
|
|
Info (332115): Slack : 0.236
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.242
|
|
Info (20696): -to_clock [get_clocks {mem|ddr4a|ddr4a_phy_clk_l_1}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.242
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : mem|ddr4a_bridge|ddr_avmm_bridge|cmd_writedata[189]
|
|
Info (332115): To Node : mem|ddr4a|ddr4a|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[2].lane_gen[2].lane_inst~phy_reg1
|
|
Info (332115): Launch Clock : mem|ddr4a|ddr4a_core_usr_clk
|
|
Info (332115): Latch Clock : mem|ddr4a|ddr4a_phy_clk_l_1
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.117 0.117 launch edge time
|
|
Info (332115): 1.431 1.314 R clock network delay
|
|
Info (332115): 1.431 0.000 mem|ddr4a_bridge|ddr_avmm_bridge|cmd_writedata[189]
|
|
Info (332115): 1.535 0.104 FF uTco mem|ddr4a_bridge|ddr_avmm_bridge|cmd_writedata[189]|q
|
|
Info (332115): 1.587 0.052 FF CELL High Speed mem|ddr4a_bridge|ddr_avmm_bridge|cmd_writedata[189]~la_mlab/laboutt[16]
|
|
Info (332115): 1.782 0.195 FF IC High Speed mem|ddr4a_avmm_chkr|avm_writedata[189]~490|dataa
|
|
Info (332115): 1.862 0.080 FF CELL High Speed mem|ddr4a_avmm_chkr|avm_writedata[189]~490|combout
|
|
Info (332115): 1.864 0.002 FF CELL High Speed mem|ddr4a_avmm_chkr|avm_writedata[189]~490~la_mlab/laboutt[15]
|
|
Info (332115): 2.483 0.619 FF IC High Speed mem|ddr4a|ddr4a|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[2].lane_gen[2].lane_inst|data_from_core[26]
|
|
Info (332115): 2.483 0.000 FF CELL mem|ddr4a|ddr4a|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[2].lane_gen[2].lane_inst~phy_reg1
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.117 0.117 latch edge time
|
|
Info (332115): 1.797 1.680 R clock network delay
|
|
Info (332115): 1.712 -0.085 clock pessimism removed
|
|
Info (332115): 2.032 0.320 clock uncertainty
|
|
Info (332115): 2.241 0.209 uTh mem|ddr4a|ddr4a|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[2].lane_gen[2].lane_inst~phy_reg1
|
|
Info (332115): Data Arrival Time : 2.483
|
|
Info (332115): Data Required Time : 2.241
|
|
Info (332115): Slack : 0.242
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.266
|
|
Info (20696): -to_clock [get_clocks {mem|ddr4b|ddr4b_phy_clk_l_1}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.266
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : mem|ddr4b_bridge|ddr_avmm_bridge|cmd_writedata[501]
|
|
Info (332115): To Node : mem|ddr4b|ddr4b|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[2].lane_gen[1].lane_inst~phy_reg1
|
|
Info (332115): Launch Clock : mem|ddr4a|ddr4a_core_usr_clk
|
|
Info (332115): Latch Clock : mem|ddr4b|ddr4b_phy_clk_l_1
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.117 0.117 launch edge time
|
|
Info (332115): 1.349 1.232 R clock network delay
|
|
Info (332115): 1.349 0.000 mem|ddr4b_bridge|ddr_avmm_bridge|cmd_writedata[501]
|
|
Info (332115): 1.449 0.100 FF uTco mem|ddr4b_bridge|ddr_avmm_bridge|cmd_writedata[501]|q
|
|
Info (332115): 1.482 0.033 FF CELL High Speed mem|ddr4b_bridge|ddr_avmm_bridge|cmd_writedata[501]~la_mlab/laboutb[13]
|
|
Info (332115): 1.885 0.403 FF IC High Speed mem|ddr4b_avmm_chkr|avm_writedata[0]~431|dataa
|
|
Info (332115): 1.968 0.083 FF CELL High Speed mem|ddr4b_avmm_chkr|avm_writedata[0]~431|combout
|
|
Info (332115): 1.970 0.002 FF CELL High Speed mem|ddr4b_avmm_chkr|avm_writedata[0]~431~la_mlab/laboutt[10]
|
|
Info (332115): 2.489 0.519 FF IC High Speed mem|ddr4b|ddr4b|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[2].lane_gen[1].lane_inst|data_from_core[15]
|
|
Info (332115): 2.489 0.000 FF CELL mem|ddr4b|ddr4b|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[2].lane_gen[1].lane_inst~phy_reg1
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.117 0.117 latch edge time
|
|
Info (332115): 1.745 1.628 R clock network delay
|
|
Info (332115): 1.698 -0.047 clock pessimism removed
|
|
Info (332115): 2.018 0.320 clock uncertainty
|
|
Info (332115): 2.223 0.205 uTh mem|ddr4b|ddr4b|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[2].lane_gen[1].lane_inst~phy_reg1
|
|
Info (332115): Data Arrival Time : 2.489
|
|
Info (332115): Data Required Time : 2.223
|
|
Info (332115): Slack : 0.266
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.465
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|avmmclk}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.465
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|channel_count[2]~RTMDUPLICATE
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Launch Clock : PCIE_REFCLK
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|avmmclk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 3.435 3.435 R clock network delay
|
|
Info (332115): 3.435 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|channel_count[2]~RTMDUPLICATE
|
|
Info (332115): 3.535 0.100 RR uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|channel_count[2]~RTMDUPLICATE|q
|
|
Info (332115): 3.581 0.046 RR CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|channel_count[2]~RTMDUPLICATE~la_mlab/laboutt[2]
|
|
Info (332115): 3.701 0.120 RR IC High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i8~0|datab
|
|
Info (332115): 3.788 0.087 RF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i8~0|combout
|
|
Info (332115): 3.790 0.002 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i8~0~la_mlab/laboutb[15]
|
|
Info (332115): 4.375 0.585 FF IC Mixed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst|avmmwrite
|
|
Info (332115): 4.375 0.000 FF CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 4.072 4.072 R clock network delay
|
|
Info (332115): 3.721 -0.351 clock pessimism removed
|
|
Info (332115): 3.761 0.040 clock uncertainty
|
|
Info (332115): 3.910 0.149 uTh fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Arrival Time : 4.375
|
|
Info (332115): Data Required Time : 3.910
|
|
Info (332115): Slack : 0.465
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.532
|
|
Info (20696): -to_clock [get_clocks {vl_qph_user_clk_clkpsc_clk0}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.532
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[3]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[3]
|
|
Info (332115): Launch Clock : vl_qph_user_clk_clkpsc_clk0
|
|
Info (332115): Latch Clock : vl_qph_user_clk_clkpsc_clk0
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 3.795 3.795 R clock network delay
|
|
Info (332115): 3.795 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[3]
|
|
Info (332115): 3.901 0.106 FF uTco fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[3]|q
|
|
Info (332115): 3.934 0.033 FF CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[3]~la_mlab/laboutb[6]
|
|
Info (332115): 4.493 0.559 FF IC High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[3]~0|datac
|
|
Info (332115): 4.570 0.077 FR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[3]~0|combout
|
|
Info (332115): 4.570 0.000 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[3]|d
|
|
Info (332115): 4.570 0.000 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[3]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 4.495 4.495 R clock network delay
|
|
Info (332115): 3.795 -0.700 clock pessimism removed
|
|
Info (332115): 3.795 0.000 clock uncertainty
|
|
Info (332115): 4.038 0.243 uTh fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[3]
|
|
Info (332115): Data Arrival Time : 4.570
|
|
Info (332115): Data Required Time : 4.038
|
|
Info (332115): Slack : 0.532
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.532
|
|
Info (20696): -to_clock [get_clocks {vl_qph_user_clk_clkpsc_clk1}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.532
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[3]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[3]
|
|
Info (332115): Launch Clock : vl_qph_user_clk_clkpsc_clk1
|
|
Info (332115): Latch Clock : vl_qph_user_clk_clkpsc_clk1
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 3.861 3.861 R clock network delay
|
|
Info (332115): 3.861 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[3]
|
|
Info (332115): 3.967 0.106 FF uTco fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[3]|q
|
|
Info (332115): 4.000 0.033 FF CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[3]~la_mlab/laboutb[6]
|
|
Info (332115): 4.559 0.559 FF IC High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[3]~0|datac
|
|
Info (332115): 4.636 0.077 FR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[3]~0|combout
|
|
Info (332115): 4.636 0.000 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[3]|d
|
|
Info (332115): 4.636 0.000 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[3]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 4.574 4.574 R clock network delay
|
|
Info (332115): 3.861 -0.713 clock pessimism removed
|
|
Info (332115): 3.861 0.000 clock uncertainty
|
|
Info (332115): 4.104 0.243 uTh fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[3]
|
|
Info (332115): Data Arrival Time : 4.636
|
|
Info (332115): Data Required Time : 4.104
|
|
Info (332115): Slack : 0.532
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.608
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|avmmclk}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.608
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|reconfig_address[8]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Launch Clock : SYS_RefClk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|avmmclk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 2.708 2.708 R clock network delay
|
|
Info (332115): 2.708 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|reconfig_address[8]
|
|
Info (332115): 2.812 0.104 FF uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|reconfig_address[8]|q
|
|
Info (332115): 2.867 0.055 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|reconfig_address[8]~la_mlab/laboutt[19]
|
|
Info (332115): 3.872 1.005 FF IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst|avmmaddress[8]
|
|
Info (332115): 3.872 0.000 FF CELL fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 3.184 3.184 R clock network delay
|
|
Info (332115): 3.037 -0.147 clock pessimism removed
|
|
Info (332115): 3.067 0.030 clock uncertainty
|
|
Info (332115): 3.264 0.197 uTh fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Arrival Time : 3.872
|
|
Info (332115): Data Required Time : 3.264
|
|
Info (332115): Slack : 0.608
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.661
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|avmmclk}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.661
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|channel_count[2]~RTMDUPLICATE
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Launch Clock : PCIE_REFCLK
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|avmmclk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 3.435 3.435 R clock network delay
|
|
Info (332115): 3.435 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|channel_count[2]~RTMDUPLICATE
|
|
Info (332115): 3.535 0.100 RR uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|channel_count[2]~RTMDUPLICATE|q
|
|
Info (332115): 3.581 0.046 RR CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|channel_count[2]~RTMDUPLICATE~la_mlab/laboutt[2]
|
|
Info (332115): 3.701 0.120 RR IC High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i244~0|datab
|
|
Info (332115): 3.786 0.085 RF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i244~0|combout
|
|
Info (332115): 3.789 0.003 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i244~0~la_mlab/laboutb[13]
|
|
Info (332115): 4.579 0.790 FF IC High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst|avmmwrite
|
|
Info (332115): 4.579 0.000 FF CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 4.080 4.080 R clock network delay
|
|
Info (332115): 3.729 -0.351 clock pessimism removed
|
|
Info (332115): 3.769 0.040 clock uncertainty
|
|
Info (332115): 3.918 0.149 uTh fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Arrival Time : 4.579
|
|
Info (332115): Data Required Time : 3.918
|
|
Info (332115): Slack : 0.661
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.730
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|avmmclk}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.730
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|reconfig_address[8]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Launch Clock : SYS_RefClk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|avmmclk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 2.708 2.708 R clock network delay
|
|
Info (332115): 2.708 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|reconfig_address[8]
|
|
Info (332115): 2.812 0.104 FF uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|reconfig_address[8]|q
|
|
Info (332115): 2.867 0.055 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|reconfig_address[8]~la_mlab/laboutt[19]
|
|
Info (332115): 3.994 1.127 FF IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst|avmmaddress[8]
|
|
Info (332115): 3.994 0.000 FF CELL fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 3.184 3.184 R clock network delay
|
|
Info (332115): 3.037 -0.147 clock pessimism removed
|
|
Info (332115): 3.067 0.030 clock uncertainty
|
|
Info (332115): 3.264 0.197 uTh fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Arrival Time : 3.994
|
|
Info (332115): Data Required Time : 3.264
|
|
Info (332115): Slack : 0.730
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.810
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|avmmclk}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.810
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_address[4]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Launch Clock : PCIE_REFCLK
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|avmmclk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 3.460 3.460 R clock network delay
|
|
Info (332115): 3.460 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_address[4]
|
|
Info (332115): 3.566 0.106 RR uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_address[4]|q
|
|
Info (332115): 3.619 0.053 RR CELL Low Power fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_address[4]~la_lab/laboutb[1]
|
|
Info (332115): 4.042 0.423 RR IC Mixed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i522|dataf
|
|
Info (332115): 4.063 0.021 RR CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i522|combout
|
|
Info (332115): 4.065 0.002 RR CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i522~la_lab/laboutt[16]
|
|
Info (332115): 4.700 0.635 RR IC High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst|avmmaddress[4]
|
|
Info (332115): 4.700 0.000 RR CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 4.003 4.003 R clock network delay
|
|
Info (332115): 3.671 -0.332 clock pessimism removed
|
|
Info (332115): 3.711 0.040 clock uncertainty
|
|
Info (332115): 3.890 0.179 uTh fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Arrival Time : 4.700
|
|
Info (332115): Data Required Time : 3.890
|
|
Info (332115): Slack : 0.810
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.853
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|avmmclk}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.853
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|g_arb[3].arbiter_inst|grant[0]~DUPLICATE
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Launch Clock : PCIE_REFCLK
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|avmmclk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 3.443 3.443 R clock network delay
|
|
Info (332115): 3.443 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|g_arb[3].arbiter_inst|grant[0]~DUPLICATE
|
|
Info (332115): 3.544 0.101 FF uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|g_arb[3].arbiter_inst|grant[0]~DUPLICATE|q
|
|
Info (332115): 3.577 0.033 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|g_arb[3].arbiter_inst|grant[0]~DUPLICATE~la_mlab/laboutb[6]
|
|
Info (332115): 3.926 0.349 FF IC Mixed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i768|datac
|
|
Info (332115): 4.005 0.079 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i768|combout
|
|
Info (332115): 4.007 0.002 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i768~la_mlab/laboutt[14]
|
|
Info (332115): 4.784 0.777 FF IC High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst|avmmaddress[6]
|
|
Info (332115): 4.784 0.000 FF CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 4.013 4.013 R clock network delay
|
|
Info (332115): 3.681 -0.332 clock pessimism removed
|
|
Info (332115): 3.721 0.040 clock uncertainty
|
|
Info (332115): 3.931 0.210 uTh fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Arrival Time : 4.784
|
|
Info (332115): Data Required Time : 3.931
|
|
Info (332115): Slack : 0.853
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.892
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|avmmclk}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.892
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|reconfig_address[8]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Launch Clock : SYS_RefClk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|avmmclk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 2.708 2.708 R clock network delay
|
|
Info (332115): 2.708 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|reconfig_address[8]
|
|
Info (332115): 2.812 0.104 FF uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|reconfig_address[8]|q
|
|
Info (332115): 2.867 0.055 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|reconfig_address[8]~la_mlab/laboutt[19]
|
|
Info (332115): 4.159 1.292 FF IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst|avmmaddress[8]
|
|
Info (332115): 4.159 0.000 FF CELL fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 3.187 3.187 R clock network delay
|
|
Info (332115): 3.040 -0.147 clock pessimism removed
|
|
Info (332115): 3.070 0.030 clock uncertainty
|
|
Info (332115): 3.267 0.197 uTh fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Arrival Time : 4.159
|
|
Info (332115): Data Required Time : 3.267
|
|
Info (332115): Slack : 0.892
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.981
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|avmmclk}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.981
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|channel_count[2]~RTM_1
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Launch Clock : PCIE_REFCLK
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|avmmclk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 3.440 3.440 R clock network delay
|
|
Info (332115): 3.440 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|channel_count[2]~RTM_1
|
|
Info (332115): 3.540 0.100 FF uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|channel_count[2]~RTM_1|q
|
|
Info (332115): 3.573 0.033 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|channel_count[2]~RTM_1~la_lab/laboutb[14]
|
|
Info (332115): 3.972 0.399 FF IC Mixed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i1188~0|dataf
|
|
Info (332115): 3.993 0.021 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i1188~0|combout
|
|
Info (332115): 3.995 0.002 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i1188~0~la_mlab/laboutt[14]
|
|
Info (332115): 4.816 0.821 FF IC Mixed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst|avmmwrite
|
|
Info (332115): 4.816 0.000 FF CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 3.978 3.978 R clock network delay
|
|
Info (332115): 3.646 -0.332 clock pessimism removed
|
|
Info (332115): 3.686 0.040 clock uncertainty
|
|
Info (332115): 3.835 0.149 uTh fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Arrival Time : 4.816
|
|
Info (332115): Data Required Time : 3.835
|
|
Info (332115): Slack : 0.981
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.985
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|avmmclk}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.985
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_writedata[3]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Launch Clock : PCIE_REFCLK
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|avmmclk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 3.450 3.450 R clock network delay
|
|
Info (332115): 3.450 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_writedata[3]
|
|
Info (332115): 3.553 0.103 FF uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_writedata[3]|q
|
|
Info (332115): 3.586 0.033 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_writedata[3]~la_lab/laboutt[17]
|
|
Info (332115): 4.151 0.565 FF IC Mixed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i1024~3|dataf
|
|
Info (332115): 4.171 0.020 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i1024~3|combout
|
|
Info (332115): 4.173 0.002 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i1024~3~la_mlab/laboutb[19]
|
|
Info (332115): 4.912 0.739 FF IC High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst|avmmwritedata[3]
|
|
Info (332115): 4.912 0.000 FF CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 3.996 3.996 R clock network delay
|
|
Info (332115): 3.664 -0.332 clock pessimism removed
|
|
Info (332115): 3.704 0.040 clock uncertainty
|
|
Info (332115): 3.927 0.223 uTh fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Arrival Time : 4.912
|
|
Info (332115): Data Required Time : 3.927
|
|
Info (332115): Slack : 0.985
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 1.139
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|avmmclk}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 1.139
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_writedata[3]~DUPLICATE
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Launch Clock : PCIE_REFCLK
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|avmmclk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 3.450 3.450 R clock network delay
|
|
Info (332115): 3.450 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_writedata[3]~DUPLICATE
|
|
Info (332115): 3.552 0.102 FF uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_writedata[3]~DUPLICATE|q
|
|
Info (332115): 3.604 0.052 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_writedata[3]~DUPLICATE~la_lab/laboutt[16]
|
|
Info (332115): 3.779 0.175 FF IC High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i1732~3|datac
|
|
Info (332115): 3.843 0.064 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i1732~3|combout
|
|
Info (332115): 3.844 0.001 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i1732~3~la_lab/laboutt[2]
|
|
Info (332115): 5.064 1.220 FF IC Mixed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst|avmmwritedata[3]
|
|
Info (332115): 5.064 0.000 FF CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 3.994 3.994 R clock network delay
|
|
Info (332115): 3.662 -0.332 clock pessimism removed
|
|
Info (332115): 3.702 0.040 clock uncertainty
|
|
Info (332115): 3.925 0.223 uTh fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Arrival Time : 5.064
|
|
Info (332115): Data Required Time : 3.925
|
|
Info (332115): Slack : 1.139
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 1.280
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|avmmclk}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 1.280
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|reconfig_address[0]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Launch Clock : SYS_RefClk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|avmmclk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 2.708 2.708 R clock network delay
|
|
Info (332115): 2.708 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|reconfig_address[0]
|
|
Info (332115): 2.815 0.107 FF uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|reconfig_address[0]|q
|
|
Info (332115): 2.870 0.055 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|reconfig_address[0]~la_mlab/laboutb[19]
|
|
Info (332115): 4.659 1.789 FF IC High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst|avmmaddress[0]
|
|
Info (332115): 4.659 0.000 FF CELL fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 3.286 3.286 R clock network delay
|
|
Info (332115): 3.139 -0.147 clock pessimism removed
|
|
Info (332115): 3.169 0.030 clock uncertainty
|
|
Info (332115): 3.379 0.210 uTh fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Arrival Time : 4.659
|
|
Info (332115): Data Required Time : 3.379
|
|
Info (332115): Slack : 1.280
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 1.400
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|avmmclk}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 1.400
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|g_arb[6].arbiter_inst|grant[0]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Launch Clock : PCIE_REFCLK
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|avmmclk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 3.453 3.453 R clock network delay
|
|
Info (332115): 3.453 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|g_arb[6].arbiter_inst|grant[0]
|
|
Info (332115): 3.558 0.105 FF uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|g_arb[6].arbiter_inst|grant[0]|q
|
|
Info (332115): 3.593 0.035 FF CELL Low Power fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|g_arb[6].arbiter_inst|grant[0]~la_mlab/laboutt[9]
|
|
Info (332115): 3.957 0.364 FF IC Low Power fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i1496~7|dataa
|
|
Info (332115): 4.053 0.096 FF CELL Low Power fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i1496~7|combout
|
|
Info (332115): 4.055 0.002 FF CELL Low Power fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i1496~7~la_mlab/laboutt[6]
|
|
Info (332115): 5.285 1.230 FF IC Mixed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst|avmmwritedata[7]
|
|
Info (332115): 5.285 0.000 FF CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 4.006 4.006 R clock network delay
|
|
Info (332115): 3.674 -0.332 clock pessimism removed
|
|
Info (332115): 3.714 0.040 clock uncertainty
|
|
Info (332115): 3.885 0.171 uTh fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Arrival Time : 5.285
|
|
Info (332115): Data Required Time : 3.885
|
|
Info (332115): Slack : 1.400
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 6.592
|
|
Info (20696): -to_clock [get_clocks {pr_clk_enable_dclk_reg2_user_clk}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 6.592
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_cb_host|alt_pr_cb_controller_v2|pr_request_reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_cb_host|alt_pr_cb_controller_v2|alt_pr_cb_interface|m_prblock~cs_css/pr_clk_core.reg
|
|
Info (332115): Launch Clock : u0|dcp_iopll|dcp_iopll|clk100
|
|
Info (332115): Latch Clock : pr_clk_enable_dclk_reg2_user_clk
|
|
Info (332115): Exception : dcp_bbs.sdc:3119: set_multicycle_path -hold -from [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_cb_host|alt_pr_cb_controller_v2|pr_request_reg}] -to [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_cb_host|alt_pr_cb_controller_v2|alt_pr_cb_interface|m_prblock~cs_css/pr_clk_core.reg}] 1
|
|
Info (332115): Multicycle - Setup Start : 2
|
|
Info (332115): Multicycle - Hold Start : 1
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 10.000 10.000 launch edge time
|
|
Info (332115): 15.408 5.408 R clock network delay
|
|
Info (332115): 15.408 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_cb_host|alt_pr_cb_controller_v2|pr_request_reg
|
|
Info (332115): 15.511 0.103 RR uTco fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_cb_host|alt_pr_cb_controller_v2|pr_request_reg|q
|
|
Info (332115): 15.576 0.065 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_cb_host|alt_pr_cb_controller_v2|pr_request_reg~la_lab/laboutt[0]
|
|
Info (332115): 18.792 3.216 RR IC High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_cb_host|alt_pr_cb_controller_v2|alt_pr_cb_interface|m_prblock|prrequest
|
|
Info (332115): 18.792 0.000 RR CELL fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_cb_host|alt_pr_cb_controller_v2|alt_pr_cb_interface|m_prblock~cs_css/pr_clk_core.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 5.000 5.000 latch edge time
|
|
Info (332115): 12.188 7.188 R clock network delay
|
|
Info (332115): 11.489 -0.699 clock pessimism removed
|
|
Info (332115): 11.659 0.170 clock uncertainty
|
|
Info (332115): 12.200 0.541 uTh fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_cb_host|alt_pr_cb_controller_v2|alt_pr_cb_interface|m_prblock~cs_css/pr_clk_core.reg
|
|
Info (332115): Data Arrival Time : 18.792
|
|
Info (332115): Data Required Time : 12.200
|
|
Info (332115): Slack : 6.592
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 1.158
|
|
Info (20696): -to_clock [get_clocks {mem|ddr4a|ddr4a_core_usr_clk}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 1.158
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_green_bs|ddr4a_reset_sync|resync_chains[0].synchronizer_nocut|dreg[0]
|
|
Info (332115): To Node : fpga_top|inst_green_bs|ddr4a_avmm_bridge|ddr_avmm_bridge|rsp_readdata[450]
|
|
Info (332115): Launch Clock : mem|ddr4a|ddr4a_core_usr_clk
|
|
Info (332115): Latch Clock : mem|ddr4a|ddr4a_core_usr_clk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.117 0.117 launch edge time
|
|
Info (332115): 1.903 1.786 R clock network delay
|
|
Info (332115): 1.903 0.000 fpga_top|inst_green_bs|ddr4a_reset_sync|resync_chains[0].synchronizer_nocut|dreg[0]
|
|
Info (332115): 2.079 0.176 RR uTco fpga_top|inst_green_bs|ddr4a_reset_sync|resync_chains[0].synchronizer_nocut|dreg[0]|q
|
|
Info (332115): 2.146 0.067 RR CELL High Speed fpga_top|inst_green_bs|ddr4a_reset_sync|resync_chains[0].synchronizer_nocut|dreg[0]~la_lab/laboutb[6]
|
|
Info (332115): 4.341 2.195 RR IC High Speed fpga_top|inst_green_bs|ddr4a_avmm_bridge|ddr_avmm_bridge|rsp_readdata[450]|clrn
|
|
Info (332115): 4.341 0.000 RR CELL High Speed fpga_top|inst_green_bs|ddr4a_avmm_bridge|ddr_avmm_bridge|rsp_readdata[450]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 3.869 3.869 latch edge time
|
|
Info (332115): 5.210 1.341 R clock network delay
|
|
Info (332115): 5.603 0.393 clock pessimism removed
|
|
Info (332115): 5.573 -0.030 clock uncertainty
|
|
Info (332115): 5.499 -0.074 uTsu fpga_top|inst_green_bs|ddr4a_avmm_bridge|ddr_avmm_bridge|rsp_readdata[450]
|
|
Info (332115): Data Arrival Time : 4.341
|
|
Info (332115): Data Required Time : 5.499
|
|
Info (332115): Slack : 1.158
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 1.668
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|wys~CORE_CLK_OUT}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 1.668
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_sriov_2.sriov2.sriov_bridge|rs_hip|npor_sync_pld_clk
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_sriov_2.sriov2.sriov_bridge|rs_hip|recovery_cnt[0]
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|wys~CORE_CLK_OUT
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|wys~CORE_CLK_OUT
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 5.838 5.838 R clock network delay
|
|
Info (332115): 5.838 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_sriov_2.sriov2.sriov_bridge|rs_hip|npor_sync_pld_clk
|
|
Info (332115): 5.967 0.129 RR uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_sriov_2.sriov2.sriov_bridge|rs_hip|npor_sync_pld_clk|q
|
|
Info (332115): 6.064 0.097 RR CELL Low Power fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_sriov_2.sriov2.sriov_bridge|rs_hip|npor_sync_pld_clk~la_lab/laboutb[8]
|
|
Info (332115): 8.032 1.968 RR IC Mixed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_sriov_2.sriov2.sriov_bridge|rs_hip|recovery_cnt[0]|clrn
|
|
Info (332115): 8.032 0.000 RR CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_sriov_2.sriov2.sriov_bridge|rs_hip|recovery_cnt[0]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 4.000 4.000 latch edge time
|
|
Info (332115): 8.990 4.990 R clock network delay
|
|
Info (332115): 9.759 0.769 clock pessimism removed
|
|
Info (332115): 9.700 -0.059 uTsu fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_sriov_2.sriov2.sriov_bridge|rs_hip|recovery_cnt[0]
|
|
Info (332115): Data Arrival Time : 8.032
|
|
Info (332115): Data Required Time : 9.700
|
|
Info (332115): Slack : 1.668
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 1.917
|
|
Info (20696): -to_clock [get_clocks {u0|dcp_iopll|dcp_iopll|clk1x}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 1.917
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|c32ui_SystemReset_n
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|tcm_to_bmc_mm_bridge_s0_agent_rdata_fifo|infer_mem_rtl_0|auto_generated|ram_block1a7~reg0
|
|
Info (332115): Launch Clock : u0|dcp_iopll|dcp_iopll|clk1x
|
|
Info (332115): Latch Clock : u0|dcp_iopll|dcp_iopll|clk1x
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 6.244 6.244 R clock network delay
|
|
Info (332115): 6.244 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|c32ui_SystemReset_n
|
|
Info (332115): 6.365 0.121 RR uTco fpga_top|inst_fiu_top|inst_ccip_fabric_top|c32ui_SystemReset_n|q
|
|
Info (332115): 6.426 0.061 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|c32ui_SystemReset_n~la_lab/laboutb[18]
|
|
Info (332115): 7.755 1.329 RR IC Mixed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|tcm_master_reset~0|dataf
|
|
Info (332115): 7.782 0.027 RF CELL Low Power fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|tcm_master_reset~0|combout
|
|
Info (332115): 7.787 0.005 FF CELL Low Power fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|tcm_master_reset~0~la_mlab/laboutb[10]
|
|
Info (332115): 8.800 1.013 FF IC Mixed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|tcm_to_bmc_mm_bridge_s0_agent_rdata_fifo|infer_mem_rtl_0|auto_generated|ram_block1a7|clr0
|
|
Info (332115): 8.800 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|tcm_to_bmc_mm_bridge_s0_agent_rdata_fifo|infer_mem_rtl_0|auto_generated|ram_block1a7~reg0
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 5.000 5.000 latch edge time
|
|
Info (332115): 10.429 5.429 R clock network delay
|
|
Info (332115): 11.183 0.754 clock pessimism removed
|
|
Info (332115): 11.033 -0.150 clock uncertainty
|
|
Info (332115): 10.717 -0.316 uTsu fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|tcm_to_bmc_mm_bridge_s0_agent_rdata_fifo|infer_mem_rtl_0|auto_generated|ram_block1a7~reg0
|
|
Info (332115): Data Arrival Time : 8.800
|
|
Info (332115): Data Required Time : 10.717
|
|
Info (332115): Slack : 1.917
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 1.987
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk1}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 1.987
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[3].core|pipeline|execute|fpu_unit|fpu_fpga|fp_div|[3].reset_relay|reset_r[0]
|
|
Info (332115): To Node : fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[3].core|pipeline|execute|fpu_unit|fpu_fpga|fp_div|[3].fdiv|memoryC1_uid115_invTables_lutmem_dmem|auto_generated|altsyncram1|ram_block2a20~reg0
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk1
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk1
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 4.219 4.219 R clock network delay
|
|
Info (332115): 4.219 0.000 fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[3].core|pipeline|execute|fpu_unit|fpu_fpga|fp_div|[3].reset_relay|reset_r[0]
|
|
Info (332115): 4.343 0.124 FF uTco fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[3].core|pipeline|execute|fpu_unit|fpu_fpga|fp_div|[3].reset_relay|reset_r[0]|q
|
|
Info (332115): 4.419 0.076 FF CELL High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[3].core|pipeline|execute|fpu_unit|fpu_fpga|fp_div|[3].reset_relay|reset_r[0]~la_mlab/laboutb[15]
|
|
Info (332115): 6.276 1.857 FF IC Mixed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[3].core|pipeline|execute|fpu_unit|fpu_fpga|fp_div|[3].fdiv|memoryC1_uid115_invTables_lutmem_dmem|auto_generated|altsyncram1|ram_block2a20|clr0
|
|
Info (332115): 6.276 0.000 FF CELL High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[3].core|pipeline|execute|fpu_unit|fpu_fpga|fp_div|[3].fdiv|memoryC1_uid115_invTables_lutmem_dmem|auto_generated|altsyncram1|ram_block2a20~reg0
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 4.545 4.545 latch edge time
|
|
Info (332115): 8.050 3.505 R clock network delay
|
|
Info (332115): 8.610 0.560 clock pessimism removed
|
|
Info (332115): 8.580 -0.030 clock uncertainty
|
|
Info (332115): 8.263 -0.317 uTsu fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[3].core|pipeline|execute|fpu_unit|fpu_fpga|fp_div|[3].fdiv|memoryC1_uid115_invTables_lutmem_dmem|auto_generated|altsyncram1|ram_block2a20~reg0
|
|
Info (332115): Data Arrival Time : 6.276
|
|
Info (332115): Data Required Time : 8.263
|
|
Info (332115): Slack : 1.987
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 2.253
|
|
Info (20696): -to_clock [get_clocks {u0|dcp_iopll|dcp_iopll|clk100}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 2.253
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|c32ui_SystemReset_n
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|ddr_backchannel|mm_clock_crossing_bridge_0|cmd_fifo|mem_rtl_0|auto_generated|ram_block1a26~reg1
|
|
Info (332115): Launch Clock : u0|dcp_iopll|dcp_iopll|clk1x
|
|
Info (332115): Latch Clock : u0|dcp_iopll|dcp_iopll|clk100
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 5.000 5.000 launch edge time
|
|
Info (332115): 11.244 6.244 R clock network delay
|
|
Info (332115): 11.244 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|c32ui_SystemReset_n
|
|
Info (332115): 11.365 0.121 RR uTco fpga_top|inst_fiu_top|inst_ccip_fabric_top|c32ui_SystemReset_n|q
|
|
Info (332115): 11.426 0.061 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|c32ui_SystemReset_n~la_lab/laboutb[18]
|
|
Info (332115): 12.755 1.329 RR IC Mixed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|tcm_master_reset~0|dataf
|
|
Info (332115): 12.782 0.027 RF CELL Low Power fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|tcm_master_reset~0|combout
|
|
Info (332115): 12.787 0.005 FF CELL Low Power fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|tcm_master_reset~0~la_mlab/laboutb[10]
|
|
Info (332115): 13.267 0.480 FF IC Mixed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|ddr_backchannel|mm_clock_crossing_bridge_0|cmd_fifo|mem_rtl_0|auto_generated|ram_block1a26|clr0
|
|
Info (332115): 13.267 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|ddr_backchannel|mm_clock_crossing_bridge_0|cmd_fifo|mem_rtl_0|auto_generated|ram_block1a26~reg1
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 10.000 10.000 latch edge time
|
|
Info (332115): 15.475 5.475 R clock network delay
|
|
Info (332115): 15.997 0.522 clock pessimism removed
|
|
Info (332115): 15.837 -0.160 clock uncertainty
|
|
Info (332115): 15.520 -0.317 uTsu fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|ddr_backchannel|mm_clock_crossing_bridge_0|cmd_fifo|mem_rtl_0|auto_generated|ram_block1a26~reg1
|
|
Info (332115): Data Arrival Time : 13.267
|
|
Info (332115): Data Required Time : 15.520
|
|
Info (332115): Slack : 2.253
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 3.219
|
|
Info (20696): -to_clock [get_clocks {u0|dcp_iopll|dcp_iopll|clk25}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 3.219
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|c32ui_SystemReset_n
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|tcm_flash_reset_sync_reg[3]
|
|
Info (332115): Launch Clock : u0|dcp_iopll|dcp_iopll|clk1x
|
|
Info (332115): Latch Clock : u0|dcp_iopll|dcp_iopll|clk25
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 35.000 35.000 launch edge time
|
|
Info (332115): 41.244 6.244 R clock network delay
|
|
Info (332115): 41.244 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|c32ui_SystemReset_n
|
|
Info (332115): 41.365 0.121 RR uTco fpga_top|inst_fiu_top|inst_ccip_fabric_top|c32ui_SystemReset_n|q
|
|
Info (332115): 41.426 0.061 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|c32ui_SystemReset_n~la_lab/laboutb[18]
|
|
Info (332115): 42.555 1.129 RR IC Mixed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|tcm_flash_reset_sync_reg[3]|clrn
|
|
Info (332115): 42.555 0.000 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|tcm_flash_reset_sync_reg[3]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 40.000 40.000 latch edge time
|
|
Info (332115): 45.491 5.491 R clock network delay
|
|
Info (332115): 46.013 0.522 clock pessimism removed
|
|
Info (332115): 45.833 -0.180 clock uncertainty
|
|
Info (332115): 45.774 -0.059 uTsu fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|tcm_flash_reset_sync_reg[3]
|
|
Info (332115): Data Arrival Time : 42.555
|
|
Info (332115): Data Required Time : 45.774
|
|
Info (332115): Slack : 3.219
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 3.226
|
|
Info (20696): -to_clock [get_clocks {DDR4_RefClk}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 3.226
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|use_counter_lock.counter_lock_gen_master.pll_ref_clk_reset_n_sync_rrr
|
|
Info (332115): To Node : mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|use_counter_lock.counter_lock_gen_master.cpa_count_to_lock[3]
|
|
Info (332115): Launch Clock : DDR4_RefClk
|
|
Info (332115): Latch Clock : DDR4_RefClk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 2.850 2.850 R clock network delay
|
|
Info (332115): 2.850 0.000 mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|use_counter_lock.counter_lock_gen_master.pll_ref_clk_reset_n_sync_rrr
|
|
Info (332115): 2.978 0.128 RR uTco mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|use_counter_lock.counter_lock_gen_master.pll_ref_clk_reset_n_sync_rrr|q
|
|
Info (332115): 3.063 0.085 RR CELL High Speed mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|use_counter_lock.counter_lock_gen_master.pll_ref_clk_reset_n_sync_rrr~la_mlab/laboutb[4]
|
|
Info (332115): 3.253 0.190 RR IC High Speed mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|use_counter_lock.counter_lock_gen_master.cpa_count_to_lock[3]|clrn
|
|
Info (332115): 3.253 0.000 RR CELL High Speed mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|use_counter_lock.counter_lock_gen_master.cpa_count_to_lock[3]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 3.752 3.752 latch edge time
|
|
Info (332115): 6.387 2.635 R clock network delay
|
|
Info (332115): 6.587 0.200 clock pessimism removed
|
|
Info (332115): 6.557 -0.030 clock uncertainty
|
|
Info (332115): 6.479 -0.078 uTsu mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|use_counter_lock.counter_lock_gen_master.cpa_count_to_lock[3]
|
|
Info (332115): Data Arrival Time : 3.253
|
|
Info (332115): Data Required Time : 6.479
|
|
Info (332115): Slack : 3.226
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 3.231
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|rx_pma_clk}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 3.231
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_reset_sync|resync_chains[0].sync_r[2]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_consecutive_error[3]
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|rx_pma_clk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|rx_pma_clk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 3.022 3.022 R clock network delay
|
|
Info (332115): 3.022 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_reset_sync|resync_chains[0].sync_r[2]
|
|
Info (332115): 3.145 0.123 RR uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_reset_sync|resync_chains[0].sync_r[2]|q
|
|
Info (332115): 3.215 0.070 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_reset_sync|resync_chains[0].sync_r[2]~la_mlab/laboutb[5]
|
|
Info (332115): 3.554 0.339 RR IC High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_consecutive_error[3]|clrn
|
|
Info (332115): 3.554 0.000 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_consecutive_error[3]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 3.878 3.878 latch edge time
|
|
Info (332115): 5.912 2.034 R clock network delay
|
|
Info (332115): 6.874 0.962 clock pessimism removed
|
|
Info (332115): 6.844 -0.030 clock uncertainty
|
|
Info (332115): 6.785 -0.059 uTsu fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_consecutive_error[3]
|
|
Info (332115): Data Arrival Time : 3.554
|
|
Info (332115): Data Required Time : 6.785
|
|
Info (332115): Slack : 3.231
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 3.287
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_clk}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 3.287
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_reset_sync|resync_chains[0].sync_r[2]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_consecutive_error[1]
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_clk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_clk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 3.069 3.069 R clock network delay
|
|
Info (332115): 3.069 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_reset_sync|resync_chains[0].sync_r[2]
|
|
Info (332115): 3.189 0.120 RR uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_reset_sync|resync_chains[0].sync_r[2]|q
|
|
Info (332115): 3.250 0.061 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_reset_sync|resync_chains[0].sync_r[2]~la_lab/laboutb[18]
|
|
Info (332115): 3.542 0.292 RR IC High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_consecutive_error[1]|clrn
|
|
Info (332115): 3.542 0.000 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_consecutive_error[1]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 3.878 3.878 latch edge time
|
|
Info (332115): 5.973 2.095 R clock network delay
|
|
Info (332115): 6.918 0.945 clock pessimism removed
|
|
Info (332115): 6.888 -0.030 clock uncertainty
|
|
Info (332115): 6.829 -0.059 uTsu fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_consecutive_error[1]
|
|
Info (332115): Data Arrival Time : 3.542
|
|
Info (332115): Data Required Time : 6.829
|
|
Info (332115): Slack : 3.287
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 3.304
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|rx_pma_clk}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 3.304
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_reset_sync|resync_chains[0].sync_r[2]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_count[5]
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|rx_pma_clk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|rx_pma_clk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 2.923 2.923 R clock network delay
|
|
Info (332115): 2.923 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_reset_sync|resync_chains[0].sync_r[2]
|
|
Info (332115): 3.045 0.122 RR uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_reset_sync|resync_chains[0].sync_r[2]|q
|
|
Info (332115): 3.105 0.060 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_reset_sync|resync_chains[0].sync_r[2]~la_mlab/laboutb[2]
|
|
Info (332115): 3.377 0.272 RR IC High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_count[5]|clrn
|
|
Info (332115): 3.377 0.000 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_count[5]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 3.878 3.878 latch edge time
|
|
Info (332115): 5.805 1.927 R clock network delay
|
|
Info (332115): 6.770 0.965 clock pessimism removed
|
|
Info (332115): 6.740 -0.030 clock uncertainty
|
|
Info (332115): 6.681 -0.059 uTsu fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_count[5]
|
|
Info (332115): Data Arrival Time : 3.377
|
|
Info (332115): Data Required Time : 6.681
|
|
Info (332115): Slack : 3.304
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 3.309
|
|
Info (20696): -to_clock [get_clocks {mem|ddr4a|ddr4a_core_cal_slave_clk}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 3.309
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : mem|ddr4b|ddr4b|arch|arch_inst|non_hps.core_clks_rsts_inst|per_if_cal_slave_reset_sync[9]
|
|
Info (332115): To Node : mem|ddr4b|ddr4b|arch|arch_inst|io_aux_inst|io_aux~soft_ram_reg
|
|
Info (332115): Launch Clock : mem|ddr4a|ddr4a_core_cal_slave_clk
|
|
Info (332115): Latch Clock : mem|ddr4a|ddr4a_core_cal_slave_clk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 4.097 4.097 R clock network delay
|
|
Info (332115): 4.097 0.000 mem|ddr4b|ddr4b|arch|arch_inst|non_hps.core_clks_rsts_inst|per_if_cal_slave_reset_sync[9]
|
|
Info (332115): 4.225 0.128 RR uTco mem|ddr4b|ddr4b|arch|arch_inst|non_hps.core_clks_rsts_inst|per_if_cal_slave_reset_sync[9]|q
|
|
Info (332115): 4.310 0.085 RR CELL High Speed mem|ddr4b|ddr4b|arch|arch_inst|non_hps.core_clks_rsts_inst|per_if_cal_slave_reset_sync[9]~la_mlab/laboutb[8]
|
|
Info (332115): 7.280 2.970 RR IC Mixed mem|ddr4b|ddr4b|arch|arch_inst|io_aux_inst|io_aux|soft_ram_reset_n
|
|
Info (332115): 7.280 0.000 RR CELL mem|ddr4b|ddr4b|arch|arch_inst|io_aux_inst|io_aux~soft_ram_reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 6.566 6.566 latch edge time
|
|
Info (332115): 10.217 3.651 R clock network delay
|
|
Info (332115): 10.655 0.438 clock pessimism removed
|
|
Info (332115): 10.605 -0.050 clock uncertainty
|
|
Info (332115): 10.589 -0.016 uTsu mem|ddr4b|ddr4b|arch|arch_inst|io_aux_inst|io_aux~soft_ram_reg
|
|
Info (332115): Data Arrival Time : 7.280
|
|
Info (332115): Data Required Time : 10.589
|
|
Info (332115): Slack : 3.309
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 3.353
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|rx_pma_clk}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 3.353
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_reset_sync|resync_chains[0].sync_r[2]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_count[2]
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|rx_pma_clk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|rx_pma_clk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 3.051 3.051 R clock network delay
|
|
Info (332115): 3.051 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_reset_sync|resync_chains[0].sync_r[2]
|
|
Info (332115): 3.171 0.120 RR uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_reset_sync|resync_chains[0].sync_r[2]|q
|
|
Info (332115): 3.232 0.061 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_reset_sync|resync_chains[0].sync_r[2]~la_lab/laboutb[18]
|
|
Info (332115): 3.471 0.239 RR IC High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_count[2]|clrn
|
|
Info (332115): 3.471 0.000 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_count[2]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 3.878 3.878 latch edge time
|
|
Info (332115): 5.950 2.072 R clock network delay
|
|
Info (332115): 6.913 0.963 clock pessimism removed
|
|
Info (332115): 6.883 -0.030 clock uncertainty
|
|
Info (332115): 6.824 -0.059 uTsu fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_count[2]
|
|
Info (332115): Data Arrival Time : 3.471
|
|
Info (332115): Data Required Time : 6.824
|
|
Info (332115): Slack : 3.353
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 4.289
|
|
Info (20696): -to_clock [get_clocks {SYS_RefClk}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 4.289
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_cb_host|alt_pr_cb_controller_v2|freeze_reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|pr_freeze_rsync
|
|
Info (332115): Launch Clock : u0|dcp_iopll|dcp_iopll|clk100
|
|
Info (332115): Latch Clock : SYS_RefClk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 6.218 6.218 R clock network delay
|
|
Info (332115): 6.218 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_cb_host|alt_pr_cb_controller_v2|freeze_reg
|
|
Info (332115): 6.342 0.124 FF uTco fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_cb_host|alt_pr_cb_controller_v2|freeze_reg|q
|
|
Info (332115): 6.410 0.068 FF CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_cb_host|alt_pr_cb_controller_v2|freeze_reg~la_lab/laboutt[8]
|
|
Info (332115): 8.201 1.791 FF IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|pr_freeze_rsync|clrn
|
|
Info (332115): 8.201 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|pr_freeze_rsync
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 10.000 10.000 latch edge time
|
|
Info (332115): 12.717 2.717 R clock network delay
|
|
Info (332115): 12.864 0.147 clock pessimism removed
|
|
Info (332115): 12.554 -0.310 clock uncertainty
|
|
Info (332115): 12.490 -0.064 uTsu fpga_top|inst_fiu_top|inst_hssi_ctrl|pr_freeze_rsync
|
|
Info (332115): Data Arrival Time : 8.201
|
|
Info (332115): Data Required Time : 12.490
|
|
Info (332115): Slack : 4.289
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 6.098
|
|
Info (20696): -to_clock [get_clocks {fspi_sclk}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 6.098
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|SPISlaveToAvalonMasterBridge_reset_clk_domain_synch|data_out
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MISOctl|rdshiftreg[5]
|
|
Info (332115): Launch Clock : u0|dcp_iopll|dcp_iopll|clk1x
|
|
Info (332115): Latch Clock : fspi_sclk
|
|
Info (332115): Exception : dcp_bbs.sdc:3056: set_multicycle_path -setup -from [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|SPISlaveToAvalonMasterBridge_reset_clk_domain_synch|data_out}] -to [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MISOctl|*}] 2
|
|
Info (332115): Multicycle - Setup Start : 2
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 240.000 240.000 launch edge time
|
|
Info (332115): 246.226 6.226 R clock network delay
|
|
Info (332115): 246.226 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|SPISlaveToAvalonMasterBridge_reset_clk_domain_synch|data_out
|
|
Info (332115): 246.368 0.142 RR uTco fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|SPISlaveToAvalonMasterBridge_reset_clk_domain_synch|data_out|q
|
|
Info (332115): 246.438 0.070 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|SPISlaveToAvalonMasterBridge_reset_clk_domain_synch|data_out~la_mlab/laboutt[1]
|
|
Info (332115): 246.760 0.322 RR IC High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MOSIctl|i5|dataf
|
|
Info (332115): 246.786 0.026 RF CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MOSIctl|i5|combout
|
|
Info (332115): 246.792 0.006 FF CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MOSIctl|i5~la_mlab/laboutt[18]
|
|
Info (332115): 246.901 0.109 FF IC High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MISOctl|rdshiftreg[5]|clrn
|
|
Info (332115): 246.901 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MISOctl|rdshiftreg[5]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 250.000 250.000 latch edge time
|
|
Info (332115): 253.397 3.397 R clock network delay
|
|
Info (332115): 253.087 -0.310 clock uncertainty
|
|
Info (332115): 252.999 -0.088 uTsu fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MISOctl|rdshiftreg[5]
|
|
Info (332115): Data Arrival Time : 246.901
|
|
Info (332115): Data Required Time : 252.999
|
|
Info (332115): Slack : 6.098
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 6.144
|
|
Info (20696): -to_clock [get_clocks {filtered_sclk_negedge}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 6.144
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|SPISlaveToAvalonMasterBridge_reset_clk_domain_synch|data_out
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MOSIctl|stsourcedata[4]
|
|
Info (332115): Launch Clock : u0|dcp_iopll|dcp_iopll|clk1x
|
|
Info (332115): Latch Clock : filtered_sclk_negedge
|
|
Info (332115): Exception : dcp_bbs.sdc:3060: set_multicycle_path -setup -from [get_keepers {*SPISlaveToAvalonMasterBridge_reset_clk_domain_synch|data_out}] -to [get_keepers {*SPIPhy_MOSIctl|stsourcedata*}] 3
|
|
Info (332115): Multicycle - Setup Start : 3
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 235.000 235.000 launch edge time
|
|
Info (332115): 241.226 6.226 R clock network delay
|
|
Info (332115): 241.226 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|SPISlaveToAvalonMasterBridge_reset_clk_domain_synch|data_out
|
|
Info (332115): 241.368 0.142 RR uTco fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|SPISlaveToAvalonMasterBridge_reset_clk_domain_synch|data_out|q
|
|
Info (332115): 241.438 0.070 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|SPISlaveToAvalonMasterBridge_reset_clk_domain_synch|data_out~la_mlab/laboutt[1]
|
|
Info (332115): 243.627 2.189 RR IC Mixed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MOSIctl|stsourcedata[4]|clrn
|
|
Info (332115): 243.627 0.000 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MOSIctl|stsourcedata[4]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 250.000 250.000 latch edge time
|
|
Info (332115): 250.141 0.141 R clock network delay
|
|
Info (332115): 249.841 -0.300 clock uncertainty
|
|
Info (332115): 249.771 -0.070 uTsu fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MOSIctl|stsourcedata[4]
|
|
Info (332115): Data Arrival Time : 243.627
|
|
Info (332115): Data Required Time : 249.771
|
|
Info (332115): Slack : 6.144
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 6.209
|
|
Info (20696): -to_clock [get_clocks {PCIE_REFCLK}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 6.209
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|reset_pulse_inst|resync_chains[0].sync_r[2]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|cpu_memory[69][16]
|
|
Info (332115): Launch Clock : PCIE_REFCLK
|
|
Info (332115): Latch Clock : PCIE_REFCLK
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 3.845 3.845 R clock network delay
|
|
Info (332115): 3.845 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|reset_pulse_inst|resync_chains[0].sync_r[2]
|
|
Info (332115): 3.974 0.129 RR uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|reset_pulse_inst|resync_chains[0].sync_r[2]|q
|
|
Info (332115): 4.040 0.066 RR CELL Low Power fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|reset_pulse_inst|resync_chains[0].sync_r[2]~la_mlab/laboutb[13]
|
|
Info (332115): 7.412 3.372 RR IC Mixed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|cpu_memory[69][16]|clrn
|
|
Info (332115): 7.412 0.000 RR CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|cpu_memory[69][16]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 10.000 10.000 latch edge time
|
|
Info (332115): 13.469 3.469 R clock network delay
|
|
Info (332115): 13.741 0.272 clock pessimism removed
|
|
Info (332115): 13.701 -0.040 clock uncertainty
|
|
Info (332115): 13.621 -0.080 uTsu fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|cpu_memory[69][16]
|
|
Info (332115): Data Arrival Time : 7.412
|
|
Info (332115): Data Required Time : 13.621
|
|
Info (332115): Slack : 6.209
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 17.528
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|rx_pma_clk}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 17.528
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|rx_pma_clk
|
|
Info (332115): Exception : dcp_bbs.sdc:3148: set_max_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pma_rxpma_rstb}] 20.000
|
|
Info (332115): Max Delay Exception : 20.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 1.902 1.902 R clock network delay
|
|
Info (332115): 1.902 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): 3.118 1.216 RR uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|rx_pma_rstb7
|
|
Info (332115): 3.118 0.000 RR IC fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_pma_rxpma_rstb
|
|
Info (332115): 3.118 0.000 RR CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 20.000 20.000 latch edge time
|
|
Info (332115): 20.766 0.766 R clock network delay
|
|
Info (332115): 20.646 -0.120 clock uncertainty
|
|
Info (332115): 20.646 0.000 uTsu fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Data Arrival Time : 3.118
|
|
Info (332115): Data Required Time : 20.646
|
|
Info (332115): Slack : 17.528
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 17.562
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|rx_fref}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 17.562
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|rx_fref
|
|
Info (332115): Exception : dcp_bbs.sdc:3148: set_max_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pma_rxpma_rstb}] 20.000
|
|
Info (332115): Max Delay Exception : 20.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 1.902 1.902 R clock network delay
|
|
Info (332115): 1.902 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): 3.118 1.216 RR uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|rx_pma_rstb7
|
|
Info (332115): 3.118 0.000 RR IC fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_pma_rxpma_rstb
|
|
Info (332115): 3.118 0.000 RR CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 20.000 20.000 latch edge time
|
|
Info (332115): 21.006 1.006 R clock network delay
|
|
Info (332115): 20.886 -0.120 clock uncertainty
|
|
Info (332115): 20.680 -0.206 uTsu fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Data Arrival Time : 3.118
|
|
Info (332115): Data Required Time : 20.680
|
|
Info (332115): Slack : 17.562
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 17.724
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|rx_pma_clk}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 17.724
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|rx_pma_clk
|
|
Info (332115): Exception : dcp_bbs.sdc:3148: set_max_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pma_rxpma_rstb}] 20.000
|
|
Info (332115): Max Delay Exception : 20.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 1.902 1.902 R clock network delay
|
|
Info (332115): 1.902 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): 2.922 1.020 RR uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|rx_pma_rstb6
|
|
Info (332115): 2.922 0.000 RR IC fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_pma_rxpma_rstb
|
|
Info (332115): 2.922 0.000 RR CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 20.000 20.000 latch edge time
|
|
Info (332115): 20.766 0.766 R clock network delay
|
|
Info (332115): 20.646 -0.120 clock uncertainty
|
|
Info (332115): 20.646 0.000 uTsu fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Data Arrival Time : 2.922
|
|
Info (332115): Data Required Time : 20.646
|
|
Info (332115): Slack : 17.724
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 17.758
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|rx_fref}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 17.758
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|rx_fref
|
|
Info (332115): Exception : dcp_bbs.sdc:3148: set_max_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pma_rxpma_rstb}] 20.000
|
|
Info (332115): Max Delay Exception : 20.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 1.902 1.902 R clock network delay
|
|
Info (332115): 1.902 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): 2.922 1.020 RR uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|rx_pma_rstb6
|
|
Info (332115): 2.922 0.000 RR IC fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_pma_rxpma_rstb
|
|
Info (332115): 2.922 0.000 RR CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 20.000 20.000 latch edge time
|
|
Info (332115): 21.006 1.006 R clock network delay
|
|
Info (332115): 20.886 -0.120 clock uncertainty
|
|
Info (332115): 20.680 -0.206 uTsu fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Data Arrival Time : 2.922
|
|
Info (332115): Data Required Time : 20.680
|
|
Info (332115): Slack : 17.758
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 17.784
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|rx_pma_clk}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 17.784
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|rx_pma_clk
|
|
Info (332115): Exception : dcp_bbs.sdc:3148: set_max_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pma_rxpma_rstb}] 20.000
|
|
Info (332115): Max Delay Exception : 20.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 1.902 1.902 R clock network delay
|
|
Info (332115): 1.902 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): 2.862 0.960 RR uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|rx_pma_rstb5
|
|
Info (332115): 2.862 0.000 RR IC fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_pma_rxpma_rstb
|
|
Info (332115): 2.862 0.000 RR CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 20.000 20.000 latch edge time
|
|
Info (332115): 20.766 0.766 R clock network delay
|
|
Info (332115): 20.646 -0.120 clock uncertainty
|
|
Info (332115): 20.646 0.000 uTsu fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Data Arrival Time : 2.862
|
|
Info (332115): Data Required Time : 20.646
|
|
Info (332115): Slack : 17.784
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 17.818
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|rx_fref}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 17.818
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|rx_fref
|
|
Info (332115): Exception : dcp_bbs.sdc:3148: set_max_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pma_rxpma_rstb}] 20.000
|
|
Info (332115): Max Delay Exception : 20.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 1.902 1.902 R clock network delay
|
|
Info (332115): 1.902 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): 2.862 0.960 RR uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|rx_pma_rstb5
|
|
Info (332115): 2.862 0.000 RR IC fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_pma_rxpma_rstb
|
|
Info (332115): 2.862 0.000 RR CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 20.000 20.000 latch edge time
|
|
Info (332115): 21.006 1.006 R clock network delay
|
|
Info (332115): 20.886 -0.120 clock uncertainty
|
|
Info (332115): 20.680 -0.206 uTsu fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Data Arrival Time : 2.862
|
|
Info (332115): Data Required Time : 20.680
|
|
Info (332115): Slack : 17.818
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 17.844
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|rx_pma_clk}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 17.844
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|rx_pma_clk
|
|
Info (332115): Exception : dcp_bbs.sdc:3148: set_max_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pma_rxpma_rstb}] 20.000
|
|
Info (332115): Max Delay Exception : 20.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 1.902 1.902 R clock network delay
|
|
Info (332115): 1.902 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): 2.785 0.883 RR uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|rx_pma_rstb1
|
|
Info (332115): 2.785 0.000 RR IC fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_pma_rxpma_rstb
|
|
Info (332115): 2.785 0.000 RR CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 20.000 20.000 latch edge time
|
|
Info (332115): 20.749 0.749 R clock network delay
|
|
Info (332115): 20.629 -0.120 clock uncertainty
|
|
Info (332115): 20.629 0.000 uTsu fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Data Arrival Time : 2.785
|
|
Info (332115): Data Required Time : 20.629
|
|
Info (332115): Slack : 17.844
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 17.878
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|rx_fref}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 17.878
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|rx_fref
|
|
Info (332115): Exception : dcp_bbs.sdc:3148: set_max_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pma_rxpma_rstb}] 20.000
|
|
Info (332115): Max Delay Exception : 20.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 1.902 1.902 R clock network delay
|
|
Info (332115): 1.902 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): 2.785 0.883 RR uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|rx_pma_rstb1
|
|
Info (332115): 2.785 0.000 RR IC fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_pma_rxpma_rstb
|
|
Info (332115): 2.785 0.000 RR CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 20.000 20.000 latch edge time
|
|
Info (332115): 20.989 0.989 R clock network delay
|
|
Info (332115): 20.869 -0.120 clock uncertainty
|
|
Info (332115): 20.663 -0.206 uTsu fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Data Arrival Time : 2.785
|
|
Info (332115): Data Required Time : 20.663
|
|
Info (332115): Slack : 17.878
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 17.888
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_pma_clk}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 17.888
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_pma_clk
|
|
Info (332115): Exception : dcp_bbs.sdc:3148: set_max_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pma_rxpma_rstb}] 20.000
|
|
Info (332115): Max Delay Exception : 20.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 1.902 1.902 R clock network delay
|
|
Info (332115): 1.902 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): 2.955 1.053 RR uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|rx_pma_rstb0
|
|
Info (332115): 2.956 0.001 RR IC fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_pma_rxpma_rstb
|
|
Info (332115): 2.956 0.000 RR CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 20.000 20.000 latch edge time
|
|
Info (332115): 20.749 0.749 R clock network delay
|
|
Info (332115): 20.864 0.115 clock pessimism removed
|
|
Info (332115): 20.844 -0.020 clock uncertainty
|
|
Info (332115): 20.844 0.000 uTsu fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Data Arrival Time : 2.956
|
|
Info (332115): Data Required Time : 20.844
|
|
Info (332115): Slack : 17.888
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 17.888
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|rx_pma_clk}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 17.888
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|rx_pma_clk
|
|
Info (332115): Exception : dcp_bbs.sdc:3148: set_max_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pma_rxpma_rstb}] 20.000
|
|
Info (332115): Max Delay Exception : 20.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 1.902 1.902 R clock network delay
|
|
Info (332115): 1.902 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): 2.771 0.869 RR uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|rx_pma_rstb4
|
|
Info (332115): 2.772 0.001 RR IC fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_pma_rxpma_rstb
|
|
Info (332115): 2.772 0.000 RR CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 20.000 20.000 latch edge time
|
|
Info (332115): 20.780 0.780 R clock network delay
|
|
Info (332115): 20.660 -0.120 clock uncertainty
|
|
Info (332115): 20.660 0.000 uTsu fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Data Arrival Time : 2.772
|
|
Info (332115): Data Required Time : 20.660
|
|
Info (332115): Slack : 17.888
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 17.922
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|rx_fref}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 17.922
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|rx_fref
|
|
Info (332115): Exception : dcp_bbs.sdc:3148: set_max_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pma_rxpma_rstb}] 20.000
|
|
Info (332115): Max Delay Exception : 20.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 1.902 1.902 R clock network delay
|
|
Info (332115): 1.902 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): 2.771 0.869 RR uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|rx_pma_rstb4
|
|
Info (332115): 2.772 0.001 RR IC fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_pma_rxpma_rstb
|
|
Info (332115): 2.772 0.000 RR CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 20.000 20.000 latch edge time
|
|
Info (332115): 21.020 1.020 R clock network delay
|
|
Info (332115): 20.900 -0.120 clock uncertainty
|
|
Info (332115): 20.694 -0.206 uTsu fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Data Arrival Time : 2.772
|
|
Info (332115): Data Required Time : 20.694
|
|
Info (332115): Slack : 17.922
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 17.978
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|rx_pma_clk}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 17.978
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|rx_pma_clk
|
|
Info (332115): Exception : dcp_bbs.sdc:3148: set_max_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pma_rxpma_rstb}] 20.000
|
|
Info (332115): Max Delay Exception : 20.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 1.902 1.902 R clock network delay
|
|
Info (332115): 1.902 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): 2.682 0.780 RR uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|rx_pma_rstb2
|
|
Info (332115): 2.682 0.000 RR IC fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_pma_rxpma_rstb
|
|
Info (332115): 2.682 0.000 RR CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 20.000 20.000 latch edge time
|
|
Info (332115): 20.780 0.780 R clock network delay
|
|
Info (332115): 20.660 -0.120 clock uncertainty
|
|
Info (332115): 20.660 0.000 uTsu fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Data Arrival Time : 2.682
|
|
Info (332115): Data Required Time : 20.660
|
|
Info (332115): Slack : 17.978
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 18.005
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|rx_pma_clk}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 18.005
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|rx_pma_clk
|
|
Info (332115): Exception : dcp_bbs.sdc:3148: set_max_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pma_rxpma_rstb}] 20.000
|
|
Info (332115): Max Delay Exception : 20.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 1.902 1.902 R clock network delay
|
|
Info (332115): 1.902 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): 2.655 0.753 RR uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|rx_pma_rstb3
|
|
Info (332115): 2.655 0.000 RR IC fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_pma_rxpma_rstb
|
|
Info (332115): 2.655 0.000 RR CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 20.000 20.000 latch edge time
|
|
Info (332115): 20.780 0.780 R clock network delay
|
|
Info (332115): 20.660 -0.120 clock uncertainty
|
|
Info (332115): 20.660 0.000 uTsu fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Data Arrival Time : 2.655
|
|
Info (332115): Data Required Time : 20.660
|
|
Info (332115): Slack : 18.005
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 18.012
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|rx_fref}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 18.012
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|rx_fref
|
|
Info (332115): Exception : dcp_bbs.sdc:3148: set_max_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pma_rxpma_rstb}] 20.000
|
|
Info (332115): Max Delay Exception : 20.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 1.902 1.902 R clock network delay
|
|
Info (332115): 1.902 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): 2.682 0.780 RR uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|rx_pma_rstb2
|
|
Info (332115): 2.682 0.000 RR IC fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_pma_rxpma_rstb
|
|
Info (332115): 2.682 0.000 RR CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 20.000 20.000 latch edge time
|
|
Info (332115): 21.020 1.020 R clock network delay
|
|
Info (332115): 20.900 -0.120 clock uncertainty
|
|
Info (332115): 20.694 -0.206 uTsu fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Data Arrival Time : 2.682
|
|
Info (332115): Data Required Time : 20.694
|
|
Info (332115): Slack : 18.012
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 18.039
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|rx_fref}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 18.039
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|rx_fref
|
|
Info (332115): Exception : dcp_bbs.sdc:3148: set_max_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pma_rxpma_rstb}] 20.000
|
|
Info (332115): Max Delay Exception : 20.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 1.902 1.902 R clock network delay
|
|
Info (332115): 1.902 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): 2.655 0.753 RR uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|rx_pma_rstb3
|
|
Info (332115): 2.655 0.000 RR IC fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_pma_rxpma_rstb
|
|
Info (332115): 2.655 0.000 RR CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 20.000 20.000 latch edge time
|
|
Info (332115): 21.020 1.020 R clock network delay
|
|
Info (332115): 20.900 -0.120 clock uncertainty
|
|
Info (332115): 20.694 -0.206 uTsu fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Data Arrival Time : 2.655
|
|
Info (332115): Data Required Time : 20.694
|
|
Info (332115): Slack : 18.039
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 18.499
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 18.499
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332115): Exception : dcp_bbs.sdc:3148: set_max_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pma_rxpma_rstb}] 20.000
|
|
Info (332115): Max Delay Exception : 20.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 1.902 1.902 R clock network delay
|
|
Info (332115): 1.902 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): 2.955 1.053 RR uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|rx_pma_rstb0
|
|
Info (332115): 2.956 0.001 RR IC fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_pma_rxpma_rstb
|
|
Info (332115): 2.956 0.000 RR CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 20.000 20.000 latch edge time
|
|
Info (332115): 20.989 0.989 R clock network delay
|
|
Info (332115): 21.691 0.702 clock pessimism removed
|
|
Info (332115): 21.661 -0.030 clock uncertainty
|
|
Info (332115): 21.455 -0.206 uTsu fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Data Arrival Time : 2.956
|
|
Info (332115): Data Required Time : 21.455
|
|
Info (332115): Slack : 18.499
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 42.829
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|tx_pma_clk}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 42.829
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi_txdig_ena
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_tx_pld_pcs_interface.inst_twentynm_hssi_tx_pld_pcs_interface~pld_pmaif_tx_pld_rst_n_reg.reg
|
|
Info (332115): Launch Clock : SYS_RefClk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|tx_pma_clk
|
|
Info (332115): Exception : dcp_bbs.sdc:3144: set_max_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pmaif_tx_pld_rst_n}] 50.000
|
|
Info (332115): Max Delay Exception : 50.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 3.011 3.011 R clock network delay
|
|
Info (332115): 3.011 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi_txdig_ena
|
|
Info (332115): 3.191 0.180 RR uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi_txdig_ena|q
|
|
Info (332115): 3.253 0.062 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi_txdig_ena~la_mlab/laboutb[17]
|
|
Info (332115): 5.402 2.149 RR IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0|datac
|
|
Info (332115): 5.498 0.096 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0|combout
|
|
Info (332115): 5.504 0.006 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0~la_mlab/laboutb[18]
|
|
Info (332115): 8.412 2.908 RR IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_tx_pld_pcs_interface.inst_twentynm_hssi_tx_pld_pcs_interface|pld_pmaif_tx_pld_rst_n
|
|
Info (332115): 8.412 0.000 RR CELL fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_tx_pld_pcs_interface.inst_twentynm_hssi_tx_pld_pcs_interface~pld_pmaif_tx_pld_rst_n_reg.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 50.000 50.000 latch edge time
|
|
Info (332115): 51.444 1.444 R clock network delay
|
|
Info (332115): 51.374 -0.070 clock uncertainty
|
|
Info (332115): 51.241 -0.133 uTsu fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_tx_pld_pcs_interface.inst_twentynm_hssi_tx_pld_pcs_interface~pld_pmaif_tx_pld_rst_n_reg.reg
|
|
Info (332115): Data Arrival Time : 8.412
|
|
Info (332115): Data Required Time : 51.241
|
|
Info (332115): Slack : 42.829
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 42.951
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|tx_pma_clk}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 42.951
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi_txdig_ena
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_tx_pld_pcs_interface.inst_twentynm_hssi_tx_pld_pcs_interface~pld_pmaif_tx_pld_rst_n_reg.reg
|
|
Info (332115): Launch Clock : SYS_RefClk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|tx_pma_clk
|
|
Info (332115): Exception : dcp_bbs.sdc:3144: set_max_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pmaif_tx_pld_rst_n}] 50.000
|
|
Info (332115): Max Delay Exception : 50.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 3.011 3.011 R clock network delay
|
|
Info (332115): 3.011 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi_txdig_ena
|
|
Info (332115): 3.191 0.180 RR uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi_txdig_ena|q
|
|
Info (332115): 3.253 0.062 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi_txdig_ena~la_mlab/laboutb[17]
|
|
Info (332115): 5.224 1.971 RR IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0|datac
|
|
Info (332115): 5.311 0.087 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0|combout
|
|
Info (332115): 5.315 0.004 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0~la_lab/laboutt[8]
|
|
Info (332115): 8.290 2.975 RR IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_tx_pld_pcs_interface.inst_twentynm_hssi_tx_pld_pcs_interface|pld_pmaif_tx_pld_rst_n
|
|
Info (332115): 8.290 0.000 RR CELL fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_tx_pld_pcs_interface.inst_twentynm_hssi_tx_pld_pcs_interface~pld_pmaif_tx_pld_rst_n_reg.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 50.000 50.000 latch edge time
|
|
Info (332115): 51.444 1.444 R clock network delay
|
|
Info (332115): 51.374 -0.070 clock uncertainty
|
|
Info (332115): 51.241 -0.133 uTsu fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_tx_pld_pcs_interface.inst_twentynm_hssi_tx_pld_pcs_interface~pld_pmaif_tx_pld_rst_n_reg.reg
|
|
Info (332115): Data Arrival Time : 8.290
|
|
Info (332115): Data Required Time : 51.241
|
|
Info (332115): Slack : 42.951
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 43.159
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|tx_pma_clk}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 43.159
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi_txdig_ena
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs~pld_8g_g3_tx_pld_rst_n_reg.reg
|
|
Info (332115): Launch Clock : SYS_RefClk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|tx_pma_clk
|
|
Info (332115): Exception : dcp_bbs.sdc:3145: set_max_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_8g_g3_tx_pld_rst_n}] 50.000
|
|
Info (332115): Max Delay Exception : 50.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 3.011 3.011 R clock network delay
|
|
Info (332115): 3.011 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi_txdig_ena
|
|
Info (332115): 3.191 0.180 RR uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi_txdig_ena|q
|
|
Info (332115): 3.253 0.062 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi_txdig_ena~la_mlab/laboutb[17]
|
|
Info (332115): 5.284 2.031 RR IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0|datac
|
|
Info (332115): 5.380 0.096 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0|combout
|
|
Info (332115): 5.386 0.006 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0~la_mlab/laboutb[18]
|
|
Info (332115): 8.175 2.789 RR IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_tx_pld_pcs_interface.inst_twentynm_hssi_tx_pld_pcs_interface|pld_8g_g3_tx_pld_rst_n
|
|
Info (332115): 8.175 0.000 RR CELL fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs~pld_8g_g3_tx_pld_rst_n_reg.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 50.000 50.000 latch edge time
|
|
Info (332115): 51.463 1.463 R clock network delay
|
|
Info (332115): 51.393 -0.070 clock uncertainty
|
|
Info (332115): 51.334 -0.059 uTsu fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs~pld_8g_g3_tx_pld_rst_n_reg.reg
|
|
Info (332115): Data Arrival Time : 8.175
|
|
Info (332115): Data Required Time : 51.334
|
|
Info (332115): Slack : 43.159
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 43.428
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|tx_pma_clk}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 43.428
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi_txdig_ena
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs~pld_8g_g3_tx_pld_rst_n_reg.reg
|
|
Info (332115): Launch Clock : SYS_RefClk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|tx_pma_clk
|
|
Info (332115): Exception : dcp_bbs.sdc:3145: set_max_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_8g_g3_tx_pld_rst_n}] 50.000
|
|
Info (332115): Max Delay Exception : 50.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 3.011 3.011 R clock network delay
|
|
Info (332115): 3.011 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi_txdig_ena
|
|
Info (332115): 3.191 0.180 RR uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi_txdig_ena|q
|
|
Info (332115): 3.253 0.062 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi_txdig_ena~la_mlab/laboutb[17]
|
|
Info (332115): 5.202 1.949 RR IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0|dataa
|
|
Info (332115): 5.342 0.140 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0|combout
|
|
Info (332115): 5.346 0.004 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0~la_lab/laboutb[16]
|
|
Info (332115): 7.906 2.560 RR IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_tx_pld_pcs_interface.inst_twentynm_hssi_tx_pld_pcs_interface|pld_8g_g3_tx_pld_rst_n
|
|
Info (332115): 7.906 0.000 RR CELL fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs~pld_8g_g3_tx_pld_rst_n_reg.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 50.000 50.000 latch edge time
|
|
Info (332115): 51.463 1.463 R clock network delay
|
|
Info (332115): 51.393 -0.070 clock uncertainty
|
|
Info (332115): 51.334 -0.059 uTsu fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs~pld_8g_g3_tx_pld_rst_n_reg.reg
|
|
Info (332115): Data Arrival Time : 7.906
|
|
Info (332115): Data Required Time : 51.334
|
|
Info (332115): Slack : 43.428
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 44.220
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|tx_coreclkin}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 44.220
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi_txdig_ena
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_10g_tx_pcs.inst_twentynm_hssi_10g_tx_pcs~pld_10g_krfec_tx_pld_rst_n_fifo.reg
|
|
Info (332115): Launch Clock : SYS_RefClk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|tx_coreclkin
|
|
Info (332115): Exception : dcp_bbs.sdc:3146: set_max_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_10g_krfec_tx_pld_rst_n}] 50.000
|
|
Info (332115): Max Delay Exception : 50.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 3.011 3.011 R clock network delay
|
|
Info (332115): 3.011 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi_txdig_ena
|
|
Info (332115): 3.191 0.180 RR uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi_txdig_ena|q
|
|
Info (332115): 3.253 0.062 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi_txdig_ena~la_mlab/laboutb[17]
|
|
Info (332115): 5.402 2.149 RR IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0|datac
|
|
Info (332115): 5.498 0.096 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0|combout
|
|
Info (332115): 5.504 0.006 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0~la_mlab/laboutb[18]
|
|
Info (332115): 8.469 2.965 RR IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_tx_pld_pcs_interface.inst_twentynm_hssi_tx_pld_pcs_interface|pld_10g_krfec_tx_pld_rst_n
|
|
Info (332115): 8.469 0.000 RR CELL fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_10g_tx_pcs.inst_twentynm_hssi_10g_tx_pcs~pld_10g_krfec_tx_pld_rst_n_fifo.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 50.000 50.000 latch edge time
|
|
Info (332115): 52.790 2.790 R clock network delay
|
|
Info (332115): 52.750 -0.040 clock uncertainty
|
|
Info (332115): 52.689 -0.061 uTsu fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_10g_tx_pcs.inst_twentynm_hssi_10g_tx_pcs~pld_10g_krfec_tx_pld_rst_n_fifo.reg
|
|
Info (332115): Data Arrival Time : 8.469
|
|
Info (332115): Data Required Time : 52.689
|
|
Info (332115): Slack : 44.220
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 44.495
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|tx_coreclkin}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 44.495
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi_txdig_ena
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_10g_tx_pcs.inst_twentynm_hssi_10g_tx_pcs~pld_10g_krfec_tx_pld_rst_n_fifo.reg
|
|
Info (332115): Launch Clock : SYS_RefClk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|tx_coreclkin
|
|
Info (332115): Exception : dcp_bbs.sdc:3146: set_max_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_10g_krfec_tx_pld_rst_n}] 50.000
|
|
Info (332115): Max Delay Exception : 50.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 3.011 3.011 R clock network delay
|
|
Info (332115): 3.011 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi_txdig_ena
|
|
Info (332115): 3.191 0.180 RR uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi_txdig_ena|q
|
|
Info (332115): 3.253 0.062 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi_txdig_ena~la_mlab/laboutb[17]
|
|
Info (332115): 5.224 1.971 RR IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0|datac
|
|
Info (332115): 5.311 0.087 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0|combout
|
|
Info (332115): 5.315 0.004 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0~la_lab/laboutt[8]
|
|
Info (332115): 8.197 2.882 RR IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_tx_pld_pcs_interface.inst_twentynm_hssi_tx_pld_pcs_interface|pld_10g_krfec_tx_pld_rst_n
|
|
Info (332115): 8.197 0.000 RR CELL fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_10g_tx_pcs.inst_twentynm_hssi_10g_tx_pcs~pld_10g_krfec_tx_pld_rst_n_fifo.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 50.000 50.000 latch edge time
|
|
Info (332115): 52.793 2.793 R clock network delay
|
|
Info (332115): 52.753 -0.040 clock uncertainty
|
|
Info (332115): 52.692 -0.061 uTsu fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_10g_tx_pcs.inst_twentynm_hssi_10g_tx_pcs~pld_10g_krfec_tx_pld_rst_n_fifo.reg
|
|
Info (332115): Data Arrival Time : 8.197
|
|
Info (332115): Data Required Time : 52.692
|
|
Info (332115): Slack : 44.495
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 44.634
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|tx_coreclkin}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 44.634
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi_txdig_ena
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_10g_tx_pcs.inst_twentynm_hssi_10g_tx_pcs~pld_10g_krfec_tx_pld_rst_n_fifo.reg
|
|
Info (332115): Launch Clock : SYS_RefClk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|tx_coreclkin
|
|
Info (332115): Exception : dcp_bbs.sdc:3146: set_max_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_10g_krfec_tx_pld_rst_n}] 50.000
|
|
Info (332115): Max Delay Exception : 50.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 3.011 3.011 R clock network delay
|
|
Info (332115): 3.011 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi_txdig_ena
|
|
Info (332115): 3.191 0.180 RR uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi_txdig_ena|q
|
|
Info (332115): 3.253 0.062 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi_txdig_ena~la_mlab/laboutb[17]
|
|
Info (332115): 5.284 2.031 RR IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0|datac
|
|
Info (332115): 5.380 0.096 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0|combout
|
|
Info (332115): 5.386 0.006 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0~la_mlab/laboutb[18]
|
|
Info (332115): 8.118 2.732 RR IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_tx_pld_pcs_interface.inst_twentynm_hssi_tx_pld_pcs_interface|pld_10g_krfec_tx_pld_rst_n
|
|
Info (332115): 8.118 0.000 RR CELL fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_10g_tx_pcs.inst_twentynm_hssi_10g_tx_pcs~pld_10g_krfec_tx_pld_rst_n_fifo.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 50.000 50.000 latch edge time
|
|
Info (332115): 52.853 2.853 R clock network delay
|
|
Info (332115): 52.813 -0.040 clock uncertainty
|
|
Info (332115): 52.752 -0.061 uTsu fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_10g_tx_pcs.inst_twentynm_hssi_10g_tx_pcs~pld_10g_krfec_tx_pld_rst_n_fifo.reg
|
|
Info (332115): Data Arrival Time : 8.118
|
|
Info (332115): Data Required Time : 52.752
|
|
Info (332115): Slack : 44.634
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 44.774
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|tx_coreclkin}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 44.774
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi_txdig_ena
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_10g_tx_pcs.inst_twentynm_hssi_10g_tx_pcs~pld_10g_krfec_tx_pld_rst_n_fifo.reg
|
|
Info (332115): Launch Clock : SYS_RefClk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|tx_coreclkin
|
|
Info (332115): Exception : dcp_bbs.sdc:3146: set_max_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_10g_krfec_tx_pld_rst_n}] 50.000
|
|
Info (332115): Max Delay Exception : 50.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 3.011 3.011 R clock network delay
|
|
Info (332115): 3.011 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi_txdig_ena
|
|
Info (332115): 3.191 0.180 RR uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi_txdig_ena|q
|
|
Info (332115): 3.253 0.062 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi_txdig_ena~la_mlab/laboutb[17]
|
|
Info (332115): 5.202 1.949 RR IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0|dataa
|
|
Info (332115): 5.342 0.140 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0|combout
|
|
Info (332115): 5.346 0.004 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0~la_lab/laboutb[16]
|
|
Info (332115): 7.906 2.560 RR IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_tx_pld_pcs_interface.inst_twentynm_hssi_tx_pld_pcs_interface|pld_10g_krfec_tx_pld_rst_n
|
|
Info (332115): 7.906 0.000 RR CELL fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_10g_tx_pcs.inst_twentynm_hssi_10g_tx_pcs~pld_10g_krfec_tx_pld_rst_n_fifo.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 50.000 50.000 latch edge time
|
|
Info (332115): 52.781 2.781 R clock network delay
|
|
Info (332115): 52.741 -0.040 clock uncertainty
|
|
Info (332115): 52.680 -0.061 uTsu fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_10g_tx_pcs.inst_twentynm_hssi_10g_tx_pcs~pld_10g_krfec_tx_pld_rst_n_fifo.reg
|
|
Info (332115): Data Arrival Time : 7.906
|
|
Info (332115): Data Required Time : 52.680
|
|
Info (332115): Slack : 44.774
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 97.996
|
|
Info (20696): -to_clock [get_clocks {altera_reserved_tck}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 97.996
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|host_link_jtag|jtag|normal.jtag_dc_streaming|synchronizer|dreg[1]
|
|
Info (332115): To Node : auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|host_link_jtag|jtag|normal.jtag_dc_streaming|jtag_streaming|idle_inserter|received_esc
|
|
Info (332115): Launch Clock : altera_reserved_tck
|
|
Info (332115): Latch Clock : altera_reserved_tck
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 2.757 2.757 R clock network delay
|
|
Info (332115): 2.757 0.000 auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|host_link_jtag|jtag|normal.jtag_dc_streaming|synchronizer|dreg[1]
|
|
Info (332115): 2.886 0.129 RR uTco auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|host_link_jtag|jtag|normal.jtag_dc_streaming|synchronizer|dreg[1]|q
|
|
Info (332115): 2.977 0.091 RR CELL High Speed auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|host_link_jtag|jtag|normal.jtag_dc_streaming|synchronizer|dreg[1]~la_lab/laboutt[0]
|
|
Info (332115): 4.118 1.141 RR IC High Speed auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|host_link_jtag|jtag|normal.jtag_dc_streaming|jtag_streaming|idle_inserter|received_esc|clrn
|
|
Info (332115): 4.118 0.000 RR CELL High Speed auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|host_link_jtag|jtag|normal.jtag_dc_streaming|jtag_streaming|idle_inserter|received_esc
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 100.000 100.000 latch edge time
|
|
Info (332115): 102.061 2.061 R clock network delay
|
|
Info (332115): 102.213 0.152 clock pessimism removed
|
|
Info (332115): 102.183 -0.030 clock uncertainty
|
|
Info (332115): 102.114 -0.069 uTsu auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|host_link_jtag|jtag|normal.jtag_dc_streaming|jtag_streaming|idle_inserter|received_esc
|
|
Info (332115): Data Arrival Time : 4.118
|
|
Info (332115): Data Required Time : 102.114
|
|
Info (332115): Slack : 97.996
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 0.132
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk1}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 0.132
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|execute|fpu_unit|fpu_fpga|fp_div|[3].reset_relay|reset_r[0]
|
|
Info (332115): To Node : fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|execute|fpu_unit|fpu_fpga|fp_div|[3].fdiv|redist8_yAddr_uid51_fpDivTest_b_3|delays[0][3]
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk1
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk1
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 3.539 3.539 R clock network delay
|
|
Info (332115): 3.539 0.000 fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|execute|fpu_unit|fpu_fpga|fp_div|[3].reset_relay|reset_r[0]
|
|
Info (332115): 3.639 0.100 FF uTco fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|execute|fpu_unit|fpu_fpga|fp_div|[3].reset_relay|reset_r[0]|q
|
|
Info (332115): 3.674 0.035 FF CELL High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|execute|fpu_unit|fpu_fpga|fp_div|[3].reset_relay|reset_r[0]~la_mlab/laboutb[10]
|
|
Info (332115): 3.833 0.159 FF IC High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|execute|fpu_unit|fpu_fpga|fp_div|[3].fdiv|redist8_yAddr_uid51_fpDivTest_b_3|delays[0][3]|clrn
|
|
Info (332115): 3.833 0.000 FF CELL High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|execute|fpu_unit|fpu_fpga|fp_div|[3].fdiv|redist8_yAddr_uid51_fpDivTest_b_3|delays[0][3]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 4.206 4.206 R clock network delay
|
|
Info (332115): 3.646 -0.560 clock pessimism removed
|
|
Info (332115): 3.646 0.000 clock uncertainty
|
|
Info (332115): 3.701 0.055 uTh fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|execute|fpu_unit|fpu_fpga|fp_div|[3].fdiv|redist8_yAddr_uid51_fpDivTest_b_3|delays[0][3]
|
|
Info (332115): Data Arrival Time : 3.833
|
|
Info (332115): Data Required Time : 3.701
|
|
Info (332115): Slack : 0.132
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 0.167
|
|
Info (20696): -to_clock [get_clocks {SYS_RefClk}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 0.167
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].avmm_reset_sync_inst|resync_chains[0].sync_r[1]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_read_cycles_cnt[2]
|
|
Info (332115): Launch Clock : SYS_RefClk
|
|
Info (332115): Latch Clock : SYS_RefClk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 2.743 2.743 R clock network delay
|
|
Info (332115): 2.743 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].avmm_reset_sync_inst|resync_chains[0].sync_r[1]
|
|
Info (332115): 2.843 0.100 RR uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].avmm_reset_sync_inst|resync_chains[0].sync_r[1]|q
|
|
Info (332115): 2.891 0.048 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].avmm_reset_sync_inst|resync_chains[0].sync_r[1]~la_lab/laboutb[14]
|
|
Info (332115): 2.986 0.095 RR IC High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_read_cycles_cnt[2]|clrn
|
|
Info (332115): 2.986 0.000 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_read_cycles_cnt[2]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 2.999 2.999 R clock network delay
|
|
Info (332115): 2.759 -0.240 clock pessimism removed
|
|
Info (332115): 2.759 0.000 clock uncertainty
|
|
Info (332115): 2.819 0.060 uTh fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_read_cycles_cnt[2]
|
|
Info (332115): Data Arrival Time : 2.986
|
|
Info (332115): Data Required Time : 2.819
|
|
Info (332115): Slack : 0.167
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 0.188
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_clk}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 0.188
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_reset_sync|resync_chains[0].sync_r[2]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_snapshot[6]
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_clk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_clk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 2.095 2.095 R clock network delay
|
|
Info (332115): 2.095 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_reset_sync|resync_chains[0].sync_r[2]
|
|
Info (332115): 2.194 0.099 RR uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_reset_sync|resync_chains[0].sync_r[2]|q
|
|
Info (332115): 2.240 0.046 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_reset_sync|resync_chains[0].sync_r[2]~la_lab/laboutb[18]
|
|
Info (332115): 2.362 0.122 RR IC High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_snapshot[6]|clrn
|
|
Info (332115): 2.362 0.000 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_snapshot[6]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 3.069 3.069 R clock network delay
|
|
Info (332115): 2.109 -0.960 clock pessimism removed
|
|
Info (332115): 2.109 0.000 clock uncertainty
|
|
Info (332115): 2.174 0.065 uTh fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_snapshot[6]
|
|
Info (332115): Data Arrival Time : 2.362
|
|
Info (332115): Data Required Time : 2.174
|
|
Info (332115): Slack : 0.188
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 0.188
|
|
Info (20696): -to_clock [get_clocks {mem|ddr4a|ddr4a_core_usr_clk}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 0.188
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|reset_sync_pri_sdc_anchor
|
|
Info (332115): To Node : mem|ddr4a|ddr4a|arch|arch_inst|seq_if_inst|afi_cal_fail_sync_inst|dreg[0]
|
|
Info (332115): Launch Clock : mem|ddr4a|ddr4a_core_usr_clk
|
|
Info (332115): Latch Clock : mem|ddr4a|ddr4a_core_usr_clk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.117 0.117 launch edge time
|
|
Info (332115): 1.430 1.313 R clock network delay
|
|
Info (332115): 1.430 0.000 mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|reset_sync_pri_sdc_anchor
|
|
Info (332115): 1.530 0.100 RR uTco mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|reset_sync_pri_sdc_anchor|q
|
|
Info (332115): 1.579 0.049 RR CELL High Speed mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|reset_sync_pri_sdc_anchor~la_mlab/laboutb[13]
|
|
Info (332115): 1.696 0.117 RR IC High Speed mem|ddr4a|ddr4a|arch|arch_inst|seq_if_inst|afi_cal_fail_sync_inst|dreg[0]|clrn
|
|
Info (332115): 1.696 0.000 RR CELL High Speed mem|ddr4a|ddr4a|arch|arch_inst|seq_if_inst|afi_cal_fail_sync_inst|dreg[0]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.117 0.117 latch edge time
|
|
Info (332115): 1.933 1.816 R clock network delay
|
|
Info (332115): 1.443 -0.490 clock pessimism removed
|
|
Info (332115): 1.443 0.000 clock uncertainty
|
|
Info (332115): 1.508 0.065 uTh mem|ddr4a|ddr4a|arch|arch_inst|seq_if_inst|afi_cal_fail_sync_inst|dreg[0]
|
|
Info (332115): Data Arrival Time : 1.696
|
|
Info (332115): Data Required Time : 1.508
|
|
Info (332115): Slack : 0.188
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 0.189
|
|
Info (20696): -to_clock [get_clocks {u0|dcp_iopll|dcp_iopll|clk1x}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 0.189
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|rdaclr|dffe7a[0]
|
|
Info (332115): To Node : fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|fifo_ram|ram_block7a561~reg1
|
|
Info (332115): Launch Clock : u0|dcp_iopll|dcp_iopll|clk1x
|
|
Info (332115): Latch Clock : u0|dcp_iopll|dcp_iopll|clk1x
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 5.412 5.412 R clock network delay
|
|
Info (332115): 5.412 0.000 fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|rdaclr|dffe7a[0]
|
|
Info (332115): 5.517 0.105 RR uTco fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|rdaclr|dffe7a[0]|q
|
|
Info (332115): 5.566 0.049 RR CELL High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|rdaclr|dffe7a[0]~la_lab/laboutt[5]
|
|
Info (332115): 5.699 0.133 RR IC High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|fifo_ram|ram_block7a561|clr1
|
|
Info (332115): 5.699 0.000 RR CELL High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|fifo_ram|ram_block7a561~reg1
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 6.201 6.201 R clock network delay
|
|
Info (332115): 5.412 -0.789 clock pessimism removed
|
|
Info (332115): 5.412 0.000 clock uncertainty
|
|
Info (332115): 5.510 0.098 uTh fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|fifo_ram|ram_block7a561~reg1
|
|
Info (332115): Data Arrival Time : 5.699
|
|
Info (332115): Data Required Time : 5.510
|
|
Info (332115): Slack : 0.189
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 0.196
|
|
Info (20696): -to_clock [get_clocks {mem|ddr4a|ddr4a_core_cal_slave_clk}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 0.196
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : mem|ddr4b|ddr4b|cal_slave_component|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out
|
|
Info (332115): To Node : mem|ddr4b|ddr4b|cal_slave_component|ioaux_master_bridge|wr_reg_write
|
|
Info (332115): Launch Clock : mem|ddr4a|ddr4a_core_cal_slave_clk
|
|
Info (332115): Latch Clock : mem|ddr4a|ddr4a_core_cal_slave_clk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 3.551 3.551 R clock network delay
|
|
Info (332115): 3.551 0.000 mem|ddr4b|ddr4b|cal_slave_component|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out
|
|
Info (332115): 3.657 0.106 RR uTco mem|ddr4b|ddr4b|cal_slave_component|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out|q
|
|
Info (332115): 3.725 0.068 RR CELL High Speed mem|ddr4b|ddr4b|cal_slave_component|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~la_mlab/laboutb[11]
|
|
Info (332115): 3.823 0.098 RR IC High Speed mem|ddr4b|ddr4b|cal_slave_component|ioaux_master_bridge|wr_reg_write|clrn
|
|
Info (332115): 3.823 0.000 RR CELL High Speed mem|ddr4b|ddr4b|cal_slave_component|ioaux_master_bridge|wr_reg_write
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 4.104 4.104 R clock network delay
|
|
Info (332115): 3.551 -0.553 clock pessimism removed
|
|
Info (332115): 3.551 0.000 clock uncertainty
|
|
Info (332115): 3.627 0.076 uTh mem|ddr4b|ddr4b|cal_slave_component|ioaux_master_bridge|wr_reg_write
|
|
Info (332115): Data Arrival Time : 3.823
|
|
Info (332115): Data Required Time : 3.627
|
|
Info (332115): Slack : 0.196
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 0.206
|
|
Info (20696): -to_clock [get_clocks {PCIE_REFCLK}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 0.206
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|reset_pulse_inst|resync_chains[0].sync_r[2]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|cpu_memory[0][5]
|
|
Info (332115): Launch Clock : PCIE_REFCLK
|
|
Info (332115): Latch Clock : PCIE_REFCLK
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 3.458 3.458 R clock network delay
|
|
Info (332115): 3.458 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|reset_pulse_inst|resync_chains[0].sync_r[2]
|
|
Info (332115): 3.564 0.106 RR uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|reset_pulse_inst|resync_chains[0].sync_r[2]|q
|
|
Info (332115): 3.615 0.051 RR CELL Low Power fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|reset_pulse_inst|resync_chains[0].sync_r[2]~la_mlab/laboutb[13]
|
|
Info (332115): 3.725 0.110 RR IC Low Power fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|cpu_memory[0][5]|clrn
|
|
Info (332115): 3.725 0.000 RR CELL Low Power fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|cpu_memory[0][5]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 3.845 3.845 R clock network delay
|
|
Info (332115): 3.459 -0.386 clock pessimism removed
|
|
Info (332115): 3.459 0.000 clock uncertainty
|
|
Info (332115): 3.519 0.060 uTh fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|cpu_memory[0][5]
|
|
Info (332115): Data Arrival Time : 3.725
|
|
Info (332115): Data Required Time : 3.519
|
|
Info (332115): Slack : 0.206
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 0.216
|
|
Info (20696): -to_clock [get_clocks {DDR4_RefClk}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 0.216
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|use_counter_lock.counter_lock_gen_master.pll_ref_clk_reset_n_sync_rrr
|
|
Info (332115): To Node : mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|use_counter_lock.counter_lock_gen_master.cpa_count_to_lock[16]~LRTM_3
|
|
Info (332115): Launch Clock : DDR4_RefClk
|
|
Info (332115): Latch Clock : DDR4_RefClk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 2.636 2.636 R clock network delay
|
|
Info (332115): 2.636 0.000 mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|use_counter_lock.counter_lock_gen_master.pll_ref_clk_reset_n_sync_rrr
|
|
Info (332115): 2.742 0.106 RR uTco mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|use_counter_lock.counter_lock_gen_master.pll_ref_clk_reset_n_sync_rrr|q
|
|
Info (332115): 2.807 0.065 RR CELL High Speed mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|use_counter_lock.counter_lock_gen_master.pll_ref_clk_reset_n_sync_rrr~la_mlab/laboutb[4]
|
|
Info (332115): 2.909 0.102 RR IC High Speed mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|use_counter_lock.counter_lock_gen_master.cpa_count_to_lock[16]~LRTM_3|clrn
|
|
Info (332115): 2.909 0.000 RR CELL High Speed mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|use_counter_lock.counter_lock_gen_master.cpa_count_to_lock[16]~LRTM_3
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 2.850 2.850 R clock network delay
|
|
Info (332115): 2.636 -0.214 clock pessimism removed
|
|
Info (332115): 2.636 0.000 clock uncertainty
|
|
Info (332115): 2.693 0.057 uTh mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|use_counter_lock.counter_lock_gen_master.cpa_count_to_lock[16]~LRTM_3
|
|
Info (332115): Data Arrival Time : 2.909
|
|
Info (332115): Data Required Time : 2.693
|
|
Info (332115): Slack : 0.216
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 0.239
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|wys~CORE_CLK_OUT}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 0.239
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_rst_sync.syncrstn_avmm_sriov.app_rstn_altpcie_reset_delay_sync_altpcie_a10_hip_hwtcl|sync_rst[1]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_sriov_2.sriov2.lmi_burst_intf|hip_lmi_addr_o[4]
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|wys~CORE_CLK_OUT
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|wys~CORE_CLK_OUT
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 4.971 4.971 R clock network delay
|
|
Info (332115): 4.971 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_rst_sync.syncrstn_avmm_sriov.app_rstn_altpcie_reset_delay_sync_altpcie_a10_hip_hwtcl|sync_rst[1]
|
|
Info (332115): 5.071 0.100 RR uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_rst_sync.syncrstn_avmm_sriov.app_rstn_altpcie_reset_delay_sync_altpcie_a10_hip_hwtcl|sync_rst[1]|q
|
|
Info (332115): 5.119 0.048 RR CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_rst_sync.syncrstn_avmm_sriov.app_rstn_altpcie_reset_delay_sync_altpcie_a10_hip_hwtcl|sync_rst[1]~la_mlab/laboutt[9]
|
|
Info (332115): 5.293 0.174 RR IC High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_sriov_2.sriov2.lmi_burst_intf|hip_lmi_addr_o[4]|clrn
|
|
Info (332115): 5.293 0.000 RR CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_sriov_2.sriov2.lmi_burst_intf|hip_lmi_addr_o[4]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 5.853 5.853 R clock network delay
|
|
Info (332115): 4.986 -0.867 clock pessimism removed
|
|
Info (332115): 5.054 0.068 uTh fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_sriov_2.sriov2.lmi_burst_intf|hip_lmi_addr_o[4]
|
|
Info (332115): Data Arrival Time : 5.293
|
|
Info (332115): Data Required Time : 5.054
|
|
Info (332115): Slack : 0.239
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 0.245
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|rx_pma_clk}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 0.245
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_reset_sync|resync_chains[0].sync_r[2]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_error_high
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|rx_pma_clk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|rx_pma_clk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 2.073 2.073 R clock network delay
|
|
Info (332115): 2.073 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_reset_sync|resync_chains[0].sync_r[2]
|
|
Info (332115): 2.171 0.098 RR uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_reset_sync|resync_chains[0].sync_r[2]|q
|
|
Info (332115): 2.217 0.046 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_reset_sync|resync_chains[0].sync_r[2]~la_lab/laboutb[18]
|
|
Info (332115): 2.398 0.181 RR IC High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_error_high|clrn
|
|
Info (332115): 2.398 0.000 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_error_high
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 3.052 3.052 R clock network delay
|
|
Info (332115): 2.089 -0.963 clock pessimism removed
|
|
Info (332115): 2.089 0.000 clock uncertainty
|
|
Info (332115): 2.153 0.064 uTh fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_error_high
|
|
Info (332115): Data Arrival Time : 2.398
|
|
Info (332115): Data Required Time : 2.153
|
|
Info (332115): Slack : 0.245
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 0.248
|
|
Info (20696): -to_clock [get_clocks {u0|dcp_iopll|dcp_iopll|clk100}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 0.248
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|gen_ccip_ports[0].inst_remote_green_stp|inst_stp_ep|inst_SLD_HUB_cont_sys|sld_hub_controller_system_without_sldep_0|sld_hub_controller_system_without_sldep_0|link|mm_mgmt|debug_reset
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|gen_ccip_ports[0].inst_remote_green_stp|inst_stp_ep|inst_SLD_HUB_cont_sys|sld_hub_controller_system_without_sldep_0|sld_hub_controller_system_without_sldep_0|fabric|mgmt_demux|outpipe1|out_payload[0]
|
|
Info (332115): Launch Clock : u0|dcp_iopll|dcp_iopll|clk100
|
|
Info (332115): Latch Clock : u0|dcp_iopll|dcp_iopll|clk100
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 5.468 5.468 R clock network delay
|
|
Info (332115): 5.468 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|gen_ccip_ports[0].inst_remote_green_stp|inst_stp_ep|inst_SLD_HUB_cont_sys|sld_hub_controller_system_without_sldep_0|sld_hub_controller_system_without_sldep_0|link|mm_mgmt|debug_reset
|
|
Info (332115): 5.569 0.101 RR uTco fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|gen_ccip_ports[0].inst_remote_green_stp|inst_stp_ep|inst_SLD_HUB_cont_sys|sld_hub_controller_system_without_sldep_0|sld_hub_controller_system_without_sldep_0|link|mm_mgmt|debug_reset|q
|
|
Info (332115): 5.617 0.048 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|gen_ccip_ports[0].inst_remote_green_stp|inst_stp_ep|inst_SLD_HUB_cont_sys|sld_hub_controller_system_without_sldep_0|sld_hub_controller_system_without_sldep_0|link|mm_mgmt|debug_reset~la_lab/laboutt[1]
|
|
Info (332115): 5.777 0.160 RR IC High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|gen_ccip_ports[0].inst_remote_green_stp|inst_stp_ep|inst_SLD_HUB_cont_sys|sld_hub_controller_system_without_sldep_0|sld_hub_controller_system_without_sldep_0|fabric|mgmt_demux|outpipe1|out_payload[0]|clrn
|
|
Info (332115): 5.777 0.000 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|gen_ccip_ports[0].inst_remote_green_stp|inst_stp_ep|inst_SLD_HUB_cont_sys|sld_hub_controller_system_without_sldep_0|sld_hub_controller_system_without_sldep_0|fabric|mgmt_demux|outpipe1|out_payload[0]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 6.283 6.283 R clock network delay
|
|
Info (332115): 5.469 -0.814 clock pessimism removed
|
|
Info (332115): 5.469 0.000 clock uncertainty
|
|
Info (332115): 5.529 0.060 uTh fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|gen_ccip_ports[0].inst_remote_green_stp|inst_stp_ep|inst_SLD_HUB_cont_sys|sld_hub_controller_system_without_sldep_0|sld_hub_controller_system_without_sldep_0|fabric|mgmt_demux|outpipe1|out_payload[0]
|
|
Info (332115): Data Arrival Time : 5.777
|
|
Info (332115): Data Required Time : 5.529
|
|
Info (332115): Slack : 0.248
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 0.261
|
|
Info (20696): -to_clock [get_clocks {u0|dcp_iopll|dcp_iopll|clk25}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 0.261
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|generic_quad_spi_controller2_0|generic_quad_spi_controller2_0|asmi2_inst_qspi_ctrl|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|generic_quad_spi_controller2_0|generic_quad_spi_controller2_0|asmi2_inst_qspi_ctrl|asmi2_qspi_interface_0|read_cnt_q[1]
|
|
Info (332115): Launch Clock : u0|dcp_iopll|dcp_iopll|clk25
|
|
Info (332115): Latch Clock : u0|dcp_iopll|dcp_iopll|clk25
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 5.520 5.520 R clock network delay
|
|
Info (332115): 5.520 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|generic_quad_spi_controller2_0|generic_quad_spi_controller2_0|asmi2_inst_qspi_ctrl|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out
|
|
Info (332115): 5.631 0.111 RR uTco fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|generic_quad_spi_controller2_0|generic_quad_spi_controller2_0|asmi2_inst_qspi_ctrl|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out|q
|
|
Info (332115): 5.680 0.049 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|generic_quad_spi_controller2_0|generic_quad_spi_controller2_0|asmi2_inst_qspi_ctrl|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~la_mlab/laboutb[5]
|
|
Info (332115): 5.840 0.160 RR IC High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|generic_quad_spi_controller2_0|generic_quad_spi_controller2_0|asmi2_inst_qspi_ctrl|asmi2_qspi_interface_0|read_cnt_q[1]|clrn
|
|
Info (332115): 5.840 0.000 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|generic_quad_spi_controller2_0|generic_quad_spi_controller2_0|asmi2_inst_qspi_ctrl|asmi2_qspi_interface_0|read_cnt_q[1]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 6.360 6.360 R clock network delay
|
|
Info (332115): 5.519 -0.841 clock pessimism removed
|
|
Info (332115): 5.519 0.000 clock uncertainty
|
|
Info (332115): 5.579 0.060 uTh fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|generic_quad_spi_controller2_0|generic_quad_spi_controller2_0|asmi2_inst_qspi_ctrl|asmi2_qspi_interface_0|read_cnt_q[1]
|
|
Info (332115): Data Arrival Time : 5.840
|
|
Info (332115): Data Required Time : 5.579
|
|
Info (332115): Slack : 0.261
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 0.274
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|rx_pma_clk}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 0.274
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_reset_sync|resync_chains[0].sync_r[2]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_bit_count[1]
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|rx_pma_clk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|rx_pma_clk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 1.927 1.927 R clock network delay
|
|
Info (332115): 1.927 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_reset_sync|resync_chains[0].sync_r[2]
|
|
Info (332115): 2.028 0.101 RR uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_reset_sync|resync_chains[0].sync_r[2]|q
|
|
Info (332115): 2.074 0.046 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_reset_sync|resync_chains[0].sync_r[2]~la_mlab/laboutb[2]
|
|
Info (332115): 2.298 0.224 RR IC High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_bit_count[1]|clrn
|
|
Info (332115): 2.298 0.000 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_bit_count[1]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 2.923 2.923 R clock network delay
|
|
Info (332115): 1.958 -0.965 clock pessimism removed
|
|
Info (332115): 1.958 0.000 clock uncertainty
|
|
Info (332115): 2.024 0.066 uTh fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_bit_count[1]
|
|
Info (332115): Data Arrival Time : 2.298
|
|
Info (332115): Data Required Time : 2.024
|
|
Info (332115): Slack : 0.274
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 0.298
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|rx_pma_clk}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 0.298
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_reset_sync|resync_chains[0].sync_r[2]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_bit_count[1]
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|rx_pma_clk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|rx_pma_clk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 2.031 2.031 R clock network delay
|
|
Info (332115): 2.031 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_reset_sync|resync_chains[0].sync_r[2]
|
|
Info (332115): 2.132 0.101 RR uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_reset_sync|resync_chains[0].sync_r[2]|q
|
|
Info (332115): 2.181 0.049 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_reset_sync|resync_chains[0].sync_r[2]~la_mlab/laboutb[5]
|
|
Info (332115): 2.412 0.231 RR IC High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_bit_count[1]|clrn
|
|
Info (332115): 2.412 0.000 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_bit_count[1]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 3.008 3.008 R clock network delay
|
|
Info (332115): 2.046 -0.962 clock pessimism removed
|
|
Info (332115): 2.046 0.000 clock uncertainty
|
|
Info (332115): 2.114 0.068 uTh fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_bit_count[1]
|
|
Info (332115): Data Arrival Time : 2.412
|
|
Info (332115): Data Required Time : 2.114
|
|
Info (332115): Slack : 0.298
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 0.662
|
|
Info (20696): -to_clock [get_clocks {altera_reserved_tck}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 0.662
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|host_link_jtag|jtag|normal.jtag_dc_streaming|synchronizer|dreg[1]
|
|
Info (332115): To Node : auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|host_link_jtag|jtag|normal.jtag_dc_streaming|sink_crosser|in_to_out_synchronizer|dreg[1]
|
|
Info (332115): Launch Clock : altera_reserved_tck
|
|
Info (332115): Latch Clock : altera_reserved_tck
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 2.186 2.186 R clock network delay
|
|
Info (332115): 2.186 0.000 auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|host_link_jtag|jtag|normal.jtag_dc_streaming|synchronizer|dreg[1]
|
|
Info (332115): 2.292 0.106 RR uTco auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|host_link_jtag|jtag|normal.jtag_dc_streaming|synchronizer|dreg[1]|q
|
|
Info (332115): 2.359 0.067 RR CELL High Speed auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|host_link_jtag|jtag|normal.jtag_dc_streaming|synchronizer|dreg[1]~la_lab/laboutt[0]
|
|
Info (332115): 2.923 0.564 RR IC High Speed auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|host_link_jtag|jtag|normal.jtag_dc_streaming|sink_crosser|in_to_out_synchronizer|dreg[1]|clrn
|
|
Info (332115): 2.923 0.000 RR CELL High Speed auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|host_link_jtag|jtag|normal.jtag_dc_streaming|sink_crosser|in_to_out_synchronizer|dreg[1]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 2.757 2.757 R clock network delay
|
|
Info (332115): 2.189 -0.568 clock pessimism removed
|
|
Info (332115): 2.189 0.000 clock uncertainty
|
|
Info (332115): 2.261 0.072 uTh auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|host_link_jtag|jtag|normal.jtag_dc_streaming|sink_crosser|in_to_out_synchronizer|dreg[1]
|
|
Info (332115): Data Arrival Time : 2.923
|
|
Info (332115): Data Required Time : 2.261
|
|
Info (332115): Slack : 0.662
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 1.682
|
|
Info (20696): -to_clock [get_clocks {fspi_sclk}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 1.682
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|SPISlaveToAvalonMasterBridge_reset_clk_domain_synch|data_out
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MISOctl|loadstsinkdata
|
|
Info (332115): Launch Clock : u0|dcp_iopll|dcp_iopll|clk1x
|
|
Info (332115): Latch Clock : fspi_sclk
|
|
Info (332115): Exception : dcp_bbs.sdc:3057: set_multicycle_path -hold -from [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|SPISlaveToAvalonMasterBridge_reset_clk_domain_synch|data_out}] -to [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MISOctl|*}] 1
|
|
Info (332115): Multicycle - Setup Start : 2
|
|
Info (332115): Multicycle - Hold Start : 1
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 5.424 5.424 R clock network delay
|
|
Info (332115): 5.424 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|SPISlaveToAvalonMasterBridge_reset_clk_domain_synch|data_out
|
|
Info (332115): 5.541 0.117 RR uTco fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|SPISlaveToAvalonMasterBridge_reset_clk_domain_synch|data_out|q
|
|
Info (332115): 5.591 0.050 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|SPISlaveToAvalonMasterBridge_reset_clk_domain_synch|data_out~la_mlab/laboutt[1]
|
|
Info (332115): 5.871 0.280 RR IC High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MOSIctl|i5|dataf
|
|
Info (332115): 5.892 0.021 RF CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MOSIctl|i5|combout
|
|
Info (332115): 5.894 0.002 FF CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MOSIctl|i5~la_mlab/laboutt[19]
|
|
Info (332115): 5.983 0.089 FF IC High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MISOctl|loadstsinkdata|clrn
|
|
Info (332115): 5.983 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MISOctl|loadstsinkdata
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 3.932 3.932 R clock network delay
|
|
Info (332115): 4.242 0.310 clock uncertainty
|
|
Info (332115): 4.301 0.059 uTh fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MISOctl|loadstsinkdata
|
|
Info (332115): Data Arrival Time : 5.983
|
|
Info (332115): Data Required Time : 4.301
|
|
Info (332115): Slack : 1.682
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 1.810
|
|
Info (20696): -to_clock [get_clocks {filtered_sclk_negedge}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 1.810
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|SPISlaveToAvalonMasterBridge_reset_clk_domain_synch|data_out
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MOSIctl|stsourcedata[4]
|
|
Info (332115): Launch Clock : u0|dcp_iopll|dcp_iopll|clk1x
|
|
Info (332115): Latch Clock : filtered_sclk_negedge
|
|
Info (332115): Exception : dcp_bbs.sdc:3061: set_multicycle_path -hold -from [get_keepers {*SPISlaveToAvalonMasterBridge_reset_clk_domain_synch|data_out}] -to [get_keepers {*SPIPhy_MOSIctl|stsourcedata*}] 1
|
|
Info (332115): Multicycle - Setup Start : 3
|
|
Info (332115): Multicycle - Hold Start : 1
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 245.000 245.000 launch edge time
|
|
Info (332115): 250.424 5.424 R clock network delay
|
|
Info (332115): 250.424 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|SPISlaveToAvalonMasterBridge_reset_clk_domain_synch|data_out
|
|
Info (332115): 250.541 0.117 RR uTco fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|SPISlaveToAvalonMasterBridge_reset_clk_domain_synch|data_out|q
|
|
Info (332115): 250.591 0.050 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|SPISlaveToAvalonMasterBridge_reset_clk_domain_synch|data_out~la_mlab/laboutt[1]
|
|
Info (332115): 252.343 1.752 RR IC Mixed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MOSIctl|stsourcedata[4]|clrn
|
|
Info (332115): 252.343 0.000 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MOSIctl|stsourcedata[4]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 250.000 250.000 latch edge time
|
|
Info (332115): 250.167 0.167 R clock network delay
|
|
Info (332115): 250.467 0.300 clock uncertainty
|
|
Info (332115): 250.533 0.066 uTh fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MOSIctl|stsourcedata[4]
|
|
Info (332115): Data Arrival Time : 252.343
|
|
Info (332115): Data Required Time : 250.533
|
|
Info (332115): Slack : 1.810
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 10.011
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|rx_fref}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 10.011
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|rx_fref
|
|
Info (332115): Exception : dcp_bbs.sdc:3195: set_min_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pma_rxpma_rstb}] -10.000
|
|
Info (332115): Min Delay Exception : -10.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 1.135 1.135 R clock network delay
|
|
Info (332115): 1.135 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): 1.777 0.642 RR uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|rx_pma_rstb3
|
|
Info (332115): 1.777 0.000 RR IC fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_pma_rxpma_rstb
|
|
Info (332115): 1.777 0.000 RR CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): -10.000 -10.000 latch edge time
|
|
Info (332115): -8.261 1.739 R clock network delay
|
|
Info (332115): -8.141 0.120 clock uncertainty
|
|
Info (332115): -8.234 -0.093 uTh fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Data Arrival Time : 1.777
|
|
Info (332115): Data Required Time : -8.234
|
|
Info (332115): Slack : 10.011
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 10.035
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|rx_fref}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 10.035
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|rx_fref
|
|
Info (332115): Exception : dcp_bbs.sdc:3195: set_min_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pma_rxpma_rstb}] -10.000
|
|
Info (332115): Min Delay Exception : -10.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 1.135 1.135 R clock network delay
|
|
Info (332115): 1.135 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): 1.801 0.666 RR uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|rx_pma_rstb2
|
|
Info (332115): 1.801 0.000 RR IC fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_pma_rxpma_rstb
|
|
Info (332115): 1.801 0.000 RR CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): -10.000 -10.000 latch edge time
|
|
Info (332115): -8.261 1.739 R clock network delay
|
|
Info (332115): -8.141 0.120 clock uncertainty
|
|
Info (332115): -8.234 -0.093 uTh fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Data Arrival Time : 1.801
|
|
Info (332115): Data Required Time : -8.234
|
|
Info (332115): Slack : 10.035
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 10.051
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|rx_pma_clk}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 10.051
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|rx_pma_clk
|
|
Info (332115): Exception : dcp_bbs.sdc:3195: set_min_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pma_rxpma_rstb}] -10.000
|
|
Info (332115): Min Delay Exception : -10.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 1.135 1.135 R clock network delay
|
|
Info (332115): 1.135 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): 1.745 0.610 FF uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|rx_pma_rstb3
|
|
Info (332115): 1.745 0.000 FF IC fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_pma_rxpma_rstb
|
|
Info (332115): 1.745 0.000 FF CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): -10.000 -10.000 latch edge time
|
|
Info (332115): -8.426 1.574 R clock network delay
|
|
Info (332115): -8.306 0.120 clock uncertainty
|
|
Info (332115): -8.306 0.000 uTh fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Data Arrival Time : 1.745
|
|
Info (332115): Data Required Time : -8.306
|
|
Info (332115): Slack : 10.051
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 10.067
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|rx_pma_clk}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 10.067
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|rx_pma_clk
|
|
Info (332115): Exception : dcp_bbs.sdc:3195: set_min_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pma_rxpma_rstb}] -10.000
|
|
Info (332115): Min Delay Exception : -10.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 1.135 1.135 R clock network delay
|
|
Info (332115): 1.135 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): 1.761 0.626 FF uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|rx_pma_rstb2
|
|
Info (332115): 1.761 0.000 FF IC fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_pma_rxpma_rstb
|
|
Info (332115): 1.761 0.000 FF CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): -10.000 -10.000 latch edge time
|
|
Info (332115): -8.426 1.574 R clock network delay
|
|
Info (332115): -8.306 0.120 clock uncertainty
|
|
Info (332115): -8.306 0.000 uTh fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Data Arrival Time : 1.761
|
|
Info (332115): Data Required Time : -8.306
|
|
Info (332115): Slack : 10.067
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 10.114
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|rx_fref}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 10.114
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|rx_fref
|
|
Info (332115): Exception : dcp_bbs.sdc:3195: set_min_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pma_rxpma_rstb}] -10.000
|
|
Info (332115): Min Delay Exception : -10.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 1.135 1.135 R clock network delay
|
|
Info (332115): 1.135 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): 1.879 0.744 RR uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|rx_pma_rstb4
|
|
Info (332115): 1.880 0.001 RR IC fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_pma_rxpma_rstb
|
|
Info (332115): 1.880 0.000 RR CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): -10.000 -10.000 latch edge time
|
|
Info (332115): -8.261 1.739 R clock network delay
|
|
Info (332115): -8.141 0.120 clock uncertainty
|
|
Info (332115): -8.234 -0.093 uTh fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Data Arrival Time : 1.880
|
|
Info (332115): Data Required Time : -8.234
|
|
Info (332115): Slack : 10.114
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 10.165
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|rx_pma_clk}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 10.165
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|rx_pma_clk
|
|
Info (332115): Exception : dcp_bbs.sdc:3195: set_min_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pma_rxpma_rstb}] -10.000
|
|
Info (332115): Min Delay Exception : -10.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 1.135 1.135 R clock network delay
|
|
Info (332115): 1.135 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): 1.858 0.723 FF uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|rx_pma_rstb4
|
|
Info (332115): 1.859 0.001 FF IC fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_pma_rxpma_rstb
|
|
Info (332115): 1.859 0.000 FF CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): -10.000 -10.000 latch edge time
|
|
Info (332115): -8.426 1.574 R clock network delay
|
|
Info (332115): -8.306 0.120 clock uncertainty
|
|
Info (332115): -8.306 0.000 uTh fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Data Arrival Time : 1.859
|
|
Info (332115): Data Required Time : -8.306
|
|
Info (332115): Slack : 10.165
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 10.174
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|rx_fref}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 10.174
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|rx_fref
|
|
Info (332115): Exception : dcp_bbs.sdc:3195: set_min_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pma_rxpma_rstb}] -10.000
|
|
Info (332115): Min Delay Exception : -10.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 1.135 1.135 R clock network delay
|
|
Info (332115): 1.135 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): 1.892 0.757 RR uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|rx_pma_rstb1
|
|
Info (332115): 1.892 0.000 RR IC fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_pma_rxpma_rstb
|
|
Info (332115): 1.892 0.000 RR CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): -10.000 -10.000 latch edge time
|
|
Info (332115): -8.309 1.691 R clock network delay
|
|
Info (332115): -8.189 0.120 clock uncertainty
|
|
Info (332115): -8.282 -0.093 uTh fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Data Arrival Time : 1.892
|
|
Info (332115): Data Required Time : -8.282
|
|
Info (332115): Slack : 10.174
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 10.183
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|rx_fref}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 10.183
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|rx_fref
|
|
Info (332115): Exception : dcp_bbs.sdc:3195: set_min_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pma_rxpma_rstb}] -10.000
|
|
Info (332115): Min Delay Exception : -10.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 1.135 1.135 R clock network delay
|
|
Info (332115): 1.135 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): 1.958 0.823 RR uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|rx_pma_rstb5
|
|
Info (332115): 1.958 0.000 RR IC fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_pma_rxpma_rstb
|
|
Info (332115): 1.958 0.000 RR CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): -10.000 -10.000 latch edge time
|
|
Info (332115): -8.252 1.748 R clock network delay
|
|
Info (332115): -8.132 0.120 clock uncertainty
|
|
Info (332115): -8.225 -0.093 uTh fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Data Arrival Time : 1.958
|
|
Info (332115): Data Required Time : -8.225
|
|
Info (332115): Slack : 10.183
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 10.218
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|rx_pma_clk}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 10.218
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|rx_pma_clk
|
|
Info (332115): Exception : dcp_bbs.sdc:3195: set_min_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pma_rxpma_rstb}] -10.000
|
|
Info (332115): Min Delay Exception : -10.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 1.135 1.135 R clock network delay
|
|
Info (332115): 1.135 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): 1.864 0.729 FF uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|rx_pma_rstb1
|
|
Info (332115): 1.864 0.000 FF IC fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_pma_rxpma_rstb
|
|
Info (332115): 1.864 0.000 FF CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): -10.000 -10.000 latch edge time
|
|
Info (332115): -8.474 1.526 R clock network delay
|
|
Info (332115): -8.354 0.120 clock uncertainty
|
|
Info (332115): -8.354 0.000 uTh fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Data Arrival Time : 1.864
|
|
Info (332115): Data Required Time : -8.354
|
|
Info (332115): Slack : 10.218
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 10.237
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|rx_pma_clk}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 10.237
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|rx_pma_clk
|
|
Info (332115): Exception : dcp_bbs.sdc:3195: set_min_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pma_rxpma_rstb}] -10.000
|
|
Info (332115): Min Delay Exception : -10.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 1.135 1.135 R clock network delay
|
|
Info (332115): 1.135 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): 1.940 0.805 FF uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|rx_pma_rstb5
|
|
Info (332115): 1.940 0.000 FF IC fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_pma_rxpma_rstb
|
|
Info (332115): 1.940 0.000 FF CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): -10.000 -10.000 latch edge time
|
|
Info (332115): -8.417 1.583 R clock network delay
|
|
Info (332115): -8.297 0.120 clock uncertainty
|
|
Info (332115): -8.297 0.000 uTh fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Data Arrival Time : 1.940
|
|
Info (332115): Data Required Time : -8.297
|
|
Info (332115): Slack : 10.237
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 10.237
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|rx_fref}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 10.237
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|rx_fref
|
|
Info (332115): Exception : dcp_bbs.sdc:3195: set_min_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pma_rxpma_rstb}] -10.000
|
|
Info (332115): Min Delay Exception : -10.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 1.135 1.135 R clock network delay
|
|
Info (332115): 1.135 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): 2.012 0.877 RR uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|rx_pma_rstb6
|
|
Info (332115): 2.012 0.000 RR IC fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_pma_rxpma_rstb
|
|
Info (332115): 2.012 0.000 RR CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): -10.000 -10.000 latch edge time
|
|
Info (332115): -8.252 1.748 R clock network delay
|
|
Info (332115): -8.132 0.120 clock uncertainty
|
|
Info (332115): -8.225 -0.093 uTh fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Data Arrival Time : 2.012
|
|
Info (332115): Data Required Time : -8.225
|
|
Info (332115): Slack : 10.237
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 10.282
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|rx_pma_clk}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 10.282
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|rx_pma_clk
|
|
Info (332115): Exception : dcp_bbs.sdc:3195: set_min_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pma_rxpma_rstb}] -10.000
|
|
Info (332115): Min Delay Exception : -10.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 1.135 1.135 R clock network delay
|
|
Info (332115): 1.135 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): 1.985 0.850 FF uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|rx_pma_rstb6
|
|
Info (332115): 1.985 0.000 FF IC fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_pma_rxpma_rstb
|
|
Info (332115): 1.985 0.000 FF CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): -10.000 -10.000 latch edge time
|
|
Info (332115): -8.417 1.583 R clock network delay
|
|
Info (332115): -8.297 0.120 clock uncertainty
|
|
Info (332115): -8.297 0.000 uTh fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Data Arrival Time : 1.985
|
|
Info (332115): Data Required Time : -8.297
|
|
Info (332115): Slack : 10.282
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 10.409
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|rx_fref}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 10.409
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|rx_fref
|
|
Info (332115): Exception : dcp_bbs.sdc:3195: set_min_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pma_rxpma_rstb}] -10.000
|
|
Info (332115): Min Delay Exception : -10.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 1.135 1.135 R clock network delay
|
|
Info (332115): 1.135 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): 2.184 1.049 RR uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|rx_pma_rstb7
|
|
Info (332115): 2.184 0.000 RR IC fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_pma_rxpma_rstb
|
|
Info (332115): 2.184 0.000 RR CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): -10.000 -10.000 latch edge time
|
|
Info (332115): -8.252 1.748 R clock network delay
|
|
Info (332115): -8.132 0.120 clock uncertainty
|
|
Info (332115): -8.225 -0.093 uTh fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Data Arrival Time : 2.184
|
|
Info (332115): Data Required Time : -8.225
|
|
Info (332115): Slack : 10.409
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 10.474
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|rx_pma_clk}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 10.474
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|rx_pma_clk
|
|
Info (332115): Exception : dcp_bbs.sdc:3195: set_min_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pma_rxpma_rstb}] -10.000
|
|
Info (332115): Min Delay Exception : -10.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 1.135 1.135 R clock network delay
|
|
Info (332115): 1.135 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): 2.177 1.042 FF uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|rx_pma_rstb7
|
|
Info (332115): 2.177 0.000 FF IC fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_pma_rxpma_rstb
|
|
Info (332115): 2.177 0.000 FF CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): -10.000 -10.000 latch edge time
|
|
Info (332115): -8.417 1.583 R clock network delay
|
|
Info (332115): -8.297 0.120 clock uncertainty
|
|
Info (332115): -8.297 0.000 uTh fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Data Arrival Time : 2.177
|
|
Info (332115): Data Required Time : -8.297
|
|
Info (332115): Slack : 10.474
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 10.584
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_pma_clk}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 10.584
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_pma_clk
|
|
Info (332115): Exception : dcp_bbs.sdc:3195: set_min_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pma_rxpma_rstb}] -10.000
|
|
Info (332115): Min Delay Exception : -10.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 1.135 1.135 R clock network delay
|
|
Info (332115): 1.135 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): 2.014 0.879 FF uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|rx_pma_rstb0
|
|
Info (332115): 2.015 0.001 FF IC fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_pma_rxpma_rstb
|
|
Info (332115): 2.015 0.000 FF CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): -10.000 -10.000 latch edge time
|
|
Info (332115): -8.474 1.526 R clock network delay
|
|
Info (332115): -8.589 -0.115 clock pessimism removed
|
|
Info (332115): -8.569 0.020 clock uncertainty
|
|
Info (332115): -8.569 0.000 uTh fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Data Arrival Time : 2.015
|
|
Info (332115): Data Required Time : -8.569
|
|
Info (332115): Slack : 10.584
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 11.116
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 11.116
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332115): Exception : dcp_bbs.sdc:3195: set_min_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pma_rxpma_rstb}] -10.000
|
|
Info (332115): Min Delay Exception : -10.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 1.135 1.135 R clock network delay
|
|
Info (332115): 1.135 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): 2.041 0.906 RR uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|rx_pma_rstb0
|
|
Info (332115): 2.042 0.001 RR IC fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_pma_rxpma_rstb
|
|
Info (332115): 2.042 0.000 RR CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): -10.000 -10.000 latch edge time
|
|
Info (332115): -8.309 1.691 R clock network delay
|
|
Info (332115): -9.011 -0.702 clock pessimism removed
|
|
Info (332115): -8.981 0.030 clock uncertainty
|
|
Info (332115): -9.074 -0.093 uTh fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Data Arrival Time : 2.042
|
|
Info (332115): Data Required Time : -9.074
|
|
Info (332115): Slack : 11.116
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 51.562
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|tx_coreclkin}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 51.562
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_avmm_csr_enabled.embedded_debug_soft_csr|g_control_reg.r_tx_digitalreset_override
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_10g_tx_pcs.inst_twentynm_hssi_10g_tx_pcs~pld_10g_krfec_tx_pld_rst_n_fifo.reg
|
|
Info (332115): Launch Clock : SYS_RefClk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|tx_coreclkin
|
|
Info (332115): Exception : dcp_bbs.sdc:3193: set_min_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_10g_krfec_tx_pld_rst_n}] -50.000
|
|
Info (332115): Min Delay Exception : -50.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 2.757 2.757 R clock network delay
|
|
Info (332115): 2.757 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_avmm_csr_enabled.embedded_debug_soft_csr|g_control_reg.r_tx_digitalreset_override
|
|
Info (332115): 2.872 0.115 FF uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_avmm_csr_enabled.embedded_debug_soft_csr|g_control_reg.r_tx_digitalreset_override|q
|
|
Info (332115): 2.929 0.057 FF CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_avmm_csr_enabled.embedded_debug_soft_csr|g_control_reg.r_tx_digitalreset_override~la_mlab/laboutb[16]
|
|
Info (332115): 3.035 0.106 FF IC Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0|datab
|
|
Info (332115): 3.139 0.104 FR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0|combout
|
|
Info (332115): 3.141 0.002 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0~la_mlab/laboutb[18]
|
|
Info (332115): 4.871 1.730 RR IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_tx_pld_pcs_interface.inst_twentynm_hssi_tx_pld_pcs_interface|pld_10g_krfec_tx_pld_rst_n
|
|
Info (332115): 4.871 0.000 RR CELL fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_10g_tx_pcs.inst_twentynm_hssi_10g_tx_pcs~pld_10g_krfec_tx_pld_rst_n_fifo.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): -50.000 -50.000 latch edge time
|
|
Info (332115): -46.782 3.218 R clock network delay
|
|
Info (332115): -46.713 0.069 clock uncertainty
|
|
Info (332115): -46.691 0.022 uTh fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_10g_tx_pcs.inst_twentynm_hssi_10g_tx_pcs~pld_10g_krfec_tx_pld_rst_n_fifo.reg
|
|
Info (332115): Data Arrival Time : 4.871
|
|
Info (332115): Data Required Time : -46.691
|
|
Info (332115): Slack : 51.562
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 51.799
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|tx_coreclkin}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 51.799
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_avmm_csr_enabled.embedded_debug_soft_csr|g_control_reg.r_tx_digitalreset_override
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_10g_tx_pcs.inst_twentynm_hssi_10g_tx_pcs~pld_10g_krfec_tx_pld_rst_n_fifo.reg
|
|
Info (332115): Launch Clock : SYS_RefClk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|tx_coreclkin
|
|
Info (332115): Exception : dcp_bbs.sdc:3193: set_min_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_10g_krfec_tx_pld_rst_n}] -50.000
|
|
Info (332115): Min Delay Exception : -50.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 2.758 2.758 R clock network delay
|
|
Info (332115): 2.758 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_avmm_csr_enabled.embedded_debug_soft_csr|g_control_reg.r_tx_digitalreset_override
|
|
Info (332115): 2.863 0.105 FF uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_avmm_csr_enabled.embedded_debug_soft_csr|g_control_reg.r_tx_digitalreset_override|q
|
|
Info (332115): 2.863 0.000 FF CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0|datae
|
|
Info (332115): 3.042 0.179 FR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0|combout
|
|
Info (332115): 3.044 0.002 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0~la_lab/laboutb[16]
|
|
Info (332115): 5.012 1.968 RR IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_tx_pld_pcs_interface.inst_twentynm_hssi_tx_pld_pcs_interface|pld_10g_krfec_tx_pld_rst_n
|
|
Info (332115): 5.012 0.000 RR CELL fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_10g_tx_pcs.inst_twentynm_hssi_10g_tx_pcs~pld_10g_krfec_tx_pld_rst_n_fifo.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): -50.000 -50.000 latch edge time
|
|
Info (332115): -46.878 3.122 R clock network delay
|
|
Info (332115): -46.809 0.069 clock uncertainty
|
|
Info (332115): -46.787 0.022 uTh fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_10g_tx_pcs.inst_twentynm_hssi_10g_tx_pcs~pld_10g_krfec_tx_pld_rst_n_fifo.reg
|
|
Info (332115): Data Arrival Time : 5.012
|
|
Info (332115): Data Required Time : -46.787
|
|
Info (332115): Slack : 51.799
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 51.940
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|tx_coreclkin}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 51.940
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_avmm_csr_enabled.embedded_debug_soft_csr|g_control_reg.r_tx_digitalreset_override
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_10g_tx_pcs.inst_twentynm_hssi_10g_tx_pcs~pld_10g_krfec_tx_pld_rst_n_fifo.reg
|
|
Info (332115): Launch Clock : SYS_RefClk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|tx_coreclkin
|
|
Info (332115): Exception : dcp_bbs.sdc:3193: set_min_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_10g_krfec_tx_pld_rst_n}] -50.000
|
|
Info (332115): Min Delay Exception : -50.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 2.758 2.758 R clock network delay
|
|
Info (332115): 2.758 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_avmm_csr_enabled.embedded_debug_soft_csr|g_control_reg.r_tx_digitalreset_override
|
|
Info (332115): 2.868 0.110 FF uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_avmm_csr_enabled.embedded_debug_soft_csr|g_control_reg.r_tx_digitalreset_override|q
|
|
Info (332115): 2.868 0.000 FF CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0|datae
|
|
Info (332115): 3.047 0.179 FR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0|combout
|
|
Info (332115): 3.049 0.002 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0~la_lab/laboutt[8]
|
|
Info (332115): 5.166 2.117 RR IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_tx_pld_pcs_interface.inst_twentynm_hssi_tx_pld_pcs_interface|pld_10g_krfec_tx_pld_rst_n
|
|
Info (332115): 5.166 0.000 RR CELL fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_10g_tx_pcs.inst_twentynm_hssi_10g_tx_pcs~pld_10g_krfec_tx_pld_rst_n_fifo.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): -50.000 -50.000 latch edge time
|
|
Info (332115): -46.865 3.135 R clock network delay
|
|
Info (332115): -46.796 0.069 clock uncertainty
|
|
Info (332115): -46.774 0.022 uTh fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_10g_tx_pcs.inst_twentynm_hssi_10g_tx_pcs~pld_10g_krfec_tx_pld_rst_n_fifo.reg
|
|
Info (332115): Data Arrival Time : 5.166
|
|
Info (332115): Data Required Time : -46.774
|
|
Info (332115): Slack : 51.940
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 52.044
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|tx_coreclkin}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 52.044
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_avmm_csr_enabled.embedded_debug_soft_csr|g_control_reg.r_tx_digitalreset_override
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_10g_tx_pcs.inst_twentynm_hssi_10g_tx_pcs~pld_10g_krfec_tx_pld_rst_n_fifo.reg
|
|
Info (332115): Launch Clock : SYS_RefClk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|tx_coreclkin
|
|
Info (332115): Exception : dcp_bbs.sdc:3193: set_min_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_10g_krfec_tx_pld_rst_n}] -50.000
|
|
Info (332115): Min Delay Exception : -50.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 2.743 2.743 R clock network delay
|
|
Info (332115): 2.743 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_avmm_csr_enabled.embedded_debug_soft_csr|g_control_reg.r_tx_digitalreset_override
|
|
Info (332115): 2.847 0.104 FF uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_avmm_csr_enabled.embedded_debug_soft_csr|g_control_reg.r_tx_digitalreset_override|q
|
|
Info (332115): 2.882 0.035 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_avmm_csr_enabled.embedded_debug_soft_csr|g_control_reg.r_tx_digitalreset_override~la_lab/laboutt[13]
|
|
Info (332115): 3.157 0.275 FF IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0|dataa
|
|
Info (332115): 3.262 0.105 FR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0|combout
|
|
Info (332115): 3.264 0.002 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0~la_mlab/laboutb[18]
|
|
Info (332115): 5.267 2.003 RR IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_tx_pld_pcs_interface.inst_twentynm_hssi_tx_pld_pcs_interface|pld_10g_krfec_tx_pld_rst_n
|
|
Info (332115): 5.267 0.000 RR CELL fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_10g_tx_pcs.inst_twentynm_hssi_10g_tx_pcs~pld_10g_krfec_tx_pld_rst_n_fifo.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): -50.000 -50.000 latch edge time
|
|
Info (332115): -46.868 3.132 R clock network delay
|
|
Info (332115): -46.799 0.069 clock uncertainty
|
|
Info (332115): -46.777 0.022 uTh fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_10g_tx_pcs.inst_twentynm_hssi_10g_tx_pcs~pld_10g_krfec_tx_pld_rst_n_fifo.reg
|
|
Info (332115): Data Arrival Time : 5.267
|
|
Info (332115): Data Required Time : -46.777
|
|
Info (332115): Slack : 52.044
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 52.607
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|tx_pma_clk}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 52.607
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_avmm_csr_enabled.embedded_debug_soft_csr|g_control_reg.r_tx_digitalreset_override
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_10g_tx_pcs.inst_twentynm_hssi_10g_tx_pcs~pld_10g_krfec_tx_pld_rst_n_reg.reg
|
|
Info (332115): Launch Clock : SYS_RefClk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|tx_pma_clk
|
|
Info (332115): Exception : dcp_bbs.sdc:3193: set_min_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_10g_krfec_tx_pld_rst_n}] -50.000
|
|
Info (332115): Min Delay Exception : -50.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 2.757 2.757 R clock network delay
|
|
Info (332115): 2.757 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_avmm_csr_enabled.embedded_debug_soft_csr|g_control_reg.r_tx_digitalreset_override
|
|
Info (332115): 2.872 0.115 FF uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_avmm_csr_enabled.embedded_debug_soft_csr|g_control_reg.r_tx_digitalreset_override|q
|
|
Info (332115): 2.929 0.057 FF CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_avmm_csr_enabled.embedded_debug_soft_csr|g_control_reg.r_tx_digitalreset_override~la_mlab/laboutb[16]
|
|
Info (332115): 3.035 0.106 FF IC Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0|datab
|
|
Info (332115): 3.139 0.104 FR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0|combout
|
|
Info (332115): 3.141 0.002 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0~la_mlab/laboutb[18]
|
|
Info (332115): 4.871 1.730 RR IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_tx_pld_pcs_interface.inst_twentynm_hssi_tx_pld_pcs_interface|pld_10g_krfec_tx_pld_rst_n
|
|
Info (332115): 4.871 0.000 RR CELL fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_10g_tx_pcs.inst_twentynm_hssi_10g_tx_pcs~pld_10g_krfec_tx_pld_rst_n_reg.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): -50.000 -50.000 latch edge time
|
|
Info (332115): -47.938 2.062 R clock network delay
|
|
Info (332115): -47.868 0.070 clock uncertainty
|
|
Info (332115): -47.736 0.132 uTh fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_10g_tx_pcs.inst_twentynm_hssi_10g_tx_pcs~pld_10g_krfec_tx_pld_rst_n_reg.reg
|
|
Info (332115): Data Arrival Time : 4.871
|
|
Info (332115): Data Required Time : -47.736
|
|
Info (332115): Slack : 52.607
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 52.706
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|tx_pma_clk}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 52.706
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_avmm_csr_enabled.embedded_debug_soft_csr|g_control_reg.r_tx_digitalreset_override
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs~pld_8g_g3_tx_pld_rst_n_reg.reg
|
|
Info (332115): Launch Clock : SYS_RefClk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|tx_pma_clk
|
|
Info (332115): Exception : dcp_bbs.sdc:3192: set_min_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_8g_g3_tx_pld_rst_n}] -50.000
|
|
Info (332115): Min Delay Exception : -50.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 2.758 2.758 R clock network delay
|
|
Info (332115): 2.758 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_avmm_csr_enabled.embedded_debug_soft_csr|g_control_reg.r_tx_digitalreset_override
|
|
Info (332115): 2.863 0.105 FF uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_avmm_csr_enabled.embedded_debug_soft_csr|g_control_reg.r_tx_digitalreset_override|q
|
|
Info (332115): 2.863 0.000 FF CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0|datae
|
|
Info (332115): 3.042 0.179 FR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0|combout
|
|
Info (332115): 3.044 0.002 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0~la_lab/laboutb[16]
|
|
Info (332115): 5.012 1.968 RR IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_tx_pld_pcs_interface.inst_twentynm_hssi_tx_pld_pcs_interface|pld_8g_g3_tx_pld_rst_n
|
|
Info (332115): 5.012 0.000 RR CELL fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs~pld_8g_g3_tx_pld_rst_n_reg.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): -50.000 -50.000 latch edge time
|
|
Info (332115): -47.938 2.062 R clock network delay
|
|
Info (332115): -47.868 0.070 clock uncertainty
|
|
Info (332115): -47.694 0.174 uTh fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs~pld_8g_g3_tx_pld_rst_n_reg.reg
|
|
Info (332115): Data Arrival Time : 5.012
|
|
Info (332115): Data Required Time : -47.694
|
|
Info (332115): Slack : 52.706
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 52.887
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|tx_pma_clk}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 52.887
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_avmm_csr_enabled.embedded_debug_soft_csr|g_control_reg.r_tx_digitalreset_override
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs~pld_8g_g3_tx_pld_rst_n_reg.reg
|
|
Info (332115): Launch Clock : SYS_RefClk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|tx_pma_clk
|
|
Info (332115): Exception : dcp_bbs.sdc:3192: set_min_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_8g_g3_tx_pld_rst_n}] -50.000
|
|
Info (332115): Min Delay Exception : -50.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 2.758 2.758 R clock network delay
|
|
Info (332115): 2.758 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_avmm_csr_enabled.embedded_debug_soft_csr|g_control_reg.r_tx_digitalreset_override
|
|
Info (332115): 2.868 0.110 FF uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_avmm_csr_enabled.embedded_debug_soft_csr|g_control_reg.r_tx_digitalreset_override|q
|
|
Info (332115): 2.868 0.000 FF CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0|datae
|
|
Info (332115): 3.047 0.179 FR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0|combout
|
|
Info (332115): 3.049 0.002 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0~la_lab/laboutt[8]
|
|
Info (332115): 5.171 2.122 RR IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_tx_pld_pcs_interface.inst_twentynm_hssi_tx_pld_pcs_interface|pld_8g_g3_tx_pld_rst_n
|
|
Info (332115): 5.171 0.000 RR CELL fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs~pld_8g_g3_tx_pld_rst_n_reg.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): -50.000 -50.000 latch edge time
|
|
Info (332115): -47.960 2.040 R clock network delay
|
|
Info (332115): -47.890 0.070 clock uncertainty
|
|
Info (332115): -47.716 0.174 uTh fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs~pld_8g_g3_tx_pld_rst_n_reg.reg
|
|
Info (332115): Data Arrival Time : 5.171
|
|
Info (332115): Data Required Time : -47.716
|
|
Info (332115): Slack : 52.887
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 52.983
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|tx_pma_clk}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 52.983
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_avmm_csr_enabled.embedded_debug_soft_csr|g_control_reg.r_tx_digitalreset_override
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs~pld_8g_g3_tx_pld_rst_n_reg.reg
|
|
Info (332115): Launch Clock : SYS_RefClk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|tx_pma_clk
|
|
Info (332115): Exception : dcp_bbs.sdc:3192: set_min_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_8g_g3_tx_pld_rst_n}] -50.000
|
|
Info (332115): Min Delay Exception : -50.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 2.743 2.743 R clock network delay
|
|
Info (332115): 2.743 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_avmm_csr_enabled.embedded_debug_soft_csr|g_control_reg.r_tx_digitalreset_override
|
|
Info (332115): 2.847 0.104 FF uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_avmm_csr_enabled.embedded_debug_soft_csr|g_control_reg.r_tx_digitalreset_override|q
|
|
Info (332115): 2.882 0.035 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_avmm_csr_enabled.embedded_debug_soft_csr|g_control_reg.r_tx_digitalreset_override~la_lab/laboutt[13]
|
|
Info (332115): 3.157 0.275 FF IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0|dataa
|
|
Info (332115): 3.262 0.105 FR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0|combout
|
|
Info (332115): 3.264 0.002 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0~la_mlab/laboutb[18]
|
|
Info (332115): 5.267 2.003 RR IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_tx_pld_pcs_interface.inst_twentynm_hssi_tx_pld_pcs_interface|pld_8g_g3_tx_pld_rst_n
|
|
Info (332115): 5.267 0.000 RR CELL fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs~pld_8g_g3_tx_pld_rst_n_reg.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): -50.000 -50.000 latch edge time
|
|
Info (332115): -47.960 2.040 R clock network delay
|
|
Info (332115): -47.890 0.070 clock uncertainty
|
|
Info (332115): -47.716 0.174 uTh fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs~pld_8g_g3_tx_pld_rst_n_reg.reg
|
|
Info (332115): Data Arrival Time : 5.267
|
|
Info (332115): Data Required Time : -47.716
|
|
Info (332115): Slack : 52.983
|
|
Info (332115): ===================================================================
|
|
Info: Analyzing Fast 900mV 0C Model
|
|
Info (332146): Worst-case setup slack is 0.803
|
|
Info (332119): Slack End Point TNS Clock
|
|
Info (332119): ========= =================== =====================
|
|
Info (332119): 0.803 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_bonding_clocks[0]
|
|
Info (332119): 0.813 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk1
|
|
Info (332119): 1.462 0.000 mem|ddr4a|ddr4a_phy_clk_l_2
|
|
Info (332119): 1.470 0.000 mem|ddr4b|ddr4b_phy_clk_l_1
|
|
Info (332119): 1.471 0.000 mem|ddr4a|ddr4a_phy_clk_l_1
|
|
Info (332119): 1.477 0.000 mem|ddr4a|ddr4a_core_usr_clk
|
|
Info (332119): 1.619 0.000 mem|ddr4b|ddr4b_phy_clk_l_2
|
|
Info (332119): 1.635 0.000 mem|ddr4b|ddr4b_phy_clk_l_0
|
|
Info (332119): 1.643 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|wys~CORE_CLK_OUT
|
|
Info (332119): 1.903 0.000 mem|ddr4a|ddr4a_phy_clk_l_0
|
|
Info (332119): 1.970 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|pld_clk
|
|
Info (332119): 2.076 0.000 u0|dcp_iopll|dcp_iopll|clk1x
|
|
Info (332119): 2.160 0.000 u0|dcp_iopll|dcp_iopll|clk100
|
|
Info (332119): 2.690 0.000 ETH_RefClk
|
|
Info (332119): 2.696 0.000 hssi_pll_r_0_outclk0
|
|
Info (332119): 2.739 0.000 hssi_pll_t_outclk0
|
|
Info (332119): 2.958 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_clk
|
|
Info (332119): 2.993 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|rx_pma_clk
|
|
Info (332119): 3.044 0.000 DDR4_RefClk
|
|
Info (332119): 3.099 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|rx_pma_clk
|
|
Info (332119): 3.141 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|rx_pma_clk
|
|
Info (332119): 3.180 0.000 mem|ddr4a|ddr4a_core_cal_slave_clk
|
|
Info (332119): 3.325 0.000 hssi_pll_t_outclk1
|
|
Info (332119): 3.331 0.000 hssi_pll_r_0_outclk1
|
|
Info (332119): 3.723 0.000 vl_qph_user_clk_clkpsc_clk1
|
|
Info (332119): 4.474 0.000 PCIE_REFCLK
|
|
Info (332119): 4.698 0.000 SYS_RefClk
|
|
Info (332119): 5.652 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|avmmclk
|
|
Info (332119): 5.811 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|avmmclk
|
|
Info (332119): 5.882 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|avmmclk
|
|
Info (332119): 5.943 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|tx_pma_div_clk
|
|
Info (332119): 6.008 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_div_clk
|
|
Info (332119): 6.534 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|avmmclk
|
|
Info (332119): 6.632 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|avmmclk
|
|
Info (332119): 6.687 0.000 fspi_sclk
|
|
Info (332119): 6.801 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|avmmclk
|
|
Info (332119): 7.012 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|avmmclk
|
|
Info (332119): 7.200 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|avmmclk
|
|
Info (332119): 7.417 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|avmmclk
|
|
Info (332119): 7.553 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|avmmclk
|
|
Info (332119): 7.777 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|avmmclk
|
|
Info (332119): 8.268 0.000 vl_qph_user_clk_clkpsc_clk0
|
|
Info (332119): 8.372 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|avmmclk
|
|
Info (332119): 8.784 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk0
|
|
Info (332119): 11.846 0.000 pr_clk_enable_dclk_reg2_user_clk
|
|
Info (332119): 18.943 0.000 u0|dcp_iopll|dcp_iopll|clk25
|
|
Info (332119): 19.538 0.000 u0|dcp_iopll|dcp_iopll|clk50
|
|
Info (332119): 23.821 0.000 filtered_sclk_negedge
|
|
Info (332119): 43.761 0.000 altera_reserved_tck
|
|
Info (332146): Worst-case hold slack is 0.001
|
|
Info (332119): Slack End Point TNS Clock
|
|
Info (332119): ========= =================== =====================
|
|
Info (332119): 0.001 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk1
|
|
Info (332119): 0.011 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|wys~CORE_CLK_OUT
|
|
Info (332119): 0.012 0.000 SYS_RefClk
|
|
Info (332119): 0.013 0.000 u0|dcp_iopll|dcp_iopll|clk1x
|
|
Info (332119): 0.014 0.000 u0|dcp_iopll|dcp_iopll|clk100
|
|
Info (332119): 0.015 0.000 altera_reserved_tck
|
|
Info (332119): 0.016 0.000 u0|dcp_iopll|dcp_iopll|clk25
|
|
Info (332119): 0.017 0.000 mem|ddr4a|ddr4a_core_usr_clk
|
|
Info (332119): 0.018 0.000 PCIE_REFCLK
|
|
Info (332119): 0.018 0.000 hssi_pll_t_outclk1
|
|
Info (332119): 0.019 0.000 filtered_sclk_negedge
|
|
Info (332119): 0.019 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_clk
|
|
Info (332119): 0.019 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|rx_pma_clk
|
|
Info (332119): 0.019 0.000 hssi_pll_r_0_outclk0
|
|
Info (332119): 0.019 0.000 mem|ddr4a|ddr4a_core_cal_slave_clk
|
|
Info (332119): 0.020 0.000 DDR4_RefClk
|
|
Info (332119): 0.020 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_div_clk
|
|
Info (332119): 0.021 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk0
|
|
Info (332119): 0.021 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|tx_pma_div_clk
|
|
Info (332119): 0.021 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|rx_pma_clk
|
|
Info (332119): 0.022 0.000 hssi_pll_t_outclk0
|
|
Info (332119): 0.023 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|rx_pma_clk
|
|
Info (332119): 0.023 0.000 hssi_pll_r_0_outclk1
|
|
Info (332119): 0.024 0.000 ETH_RefClk
|
|
Info (332119): 0.029 0.000 u0|dcp_iopll|dcp_iopll|clk50
|
|
Info (332119): 0.079 0.000 mem|ddr4a|ddr4a_phy_clk_l_2
|
|
Info (332119): 0.081 0.000 mem|ddr4b|ddr4b_phy_clk_l_0
|
|
Info (332119): 0.084 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_bonding_clocks[0]
|
|
Info (332119): 0.085 0.000 mem|ddr4b|ddr4b_phy_clk_l_1
|
|
Info (332119): 0.088 0.000 mem|ddr4b|ddr4b_phy_clk_l_2
|
|
Info (332119): 0.092 0.000 fspi_sclk
|
|
Info (332119): 0.104 0.000 mem|ddr4a|ddr4a_phy_clk_l_1
|
|
Info (332119): 0.118 0.000 mem|ddr4a|ddr4a_phy_clk_l_0
|
|
Info (332119): 0.143 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|pld_clk
|
|
Info (332119): 0.355 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|avmmclk
|
|
Info (332119): 0.401 0.000 vl_qph_user_clk_clkpsc_clk0
|
|
Info (332119): 0.401 0.000 vl_qph_user_clk_clkpsc_clk1
|
|
Info (332119): 0.493 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|avmmclk
|
|
Info (332119): 0.505 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|avmmclk
|
|
Info (332119): 0.563 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|avmmclk
|
|
Info (332119): 0.587 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|avmmclk
|
|
Info (332119): 0.632 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|avmmclk
|
|
Info (332119): 0.705 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|avmmclk
|
|
Info (332119): 0.725 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|avmmclk
|
|
Info (332119): 0.751 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|avmmclk
|
|
Info (332119): 0.900 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|avmmclk
|
|
Info (332119): 1.020 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|avmmclk
|
|
Info (332119): 1.094 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|avmmclk
|
|
Info (332119): 6.253 0.000 pr_clk_enable_dclk_reg2_user_clk
|
|
Info (332146): Worst-case recovery slack is 1.594
|
|
Info (332119): Slack End Point TNS Clock
|
|
Info (332119): ========= =================== =====================
|
|
Info (332119): 1.594 0.000 mem|ddr4a|ddr4a_core_usr_clk
|
|
Info (332119): 2.035 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|wys~CORE_CLK_OUT
|
|
Info (332119): 2.374 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk1
|
|
Info (332119): 2.406 0.000 u0|dcp_iopll|dcp_iopll|clk1x
|
|
Info (332119): 2.692 0.000 u0|dcp_iopll|dcp_iopll|clk100
|
|
Info (332119): 3.285 0.000 DDR4_RefClk
|
|
Info (332119): 3.318 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|rx_pma_clk
|
|
Info (332119): 3.363 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_clk
|
|
Info (332119): 3.382 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|rx_pma_clk
|
|
Info (332119): 3.422 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|rx_pma_clk
|
|
Info (332119): 3.526 0.000 u0|dcp_iopll|dcp_iopll|clk25
|
|
Info (332119): 3.984 0.000 mem|ddr4a|ddr4a_core_cal_slave_clk
|
|
Info (332119): 4.943 0.000 SYS_RefClk
|
|
Info (332119): 6.580 0.000 fspi_sclk
|
|
Info (332119): 6.848 0.000 PCIE_REFCLK
|
|
Info (332119): 7.299 0.000 filtered_sclk_negedge
|
|
Info (332119): 17.694 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|rx_fref
|
|
Info (332119): 17.886 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|rx_fref
|
|
Info (332119): 17.940 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|rx_fref
|
|
Info (332119): 17.944 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|rx_fref
|
|
Info (332119): 17.982 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|rx_fref
|
|
Info (332119): 18.074 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|rx_fref
|
|
Info (332119): 18.097 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|rx_fref
|
|
Info (332119): 18.546 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332119): 18.648 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|rx_pma_clk
|
|
Info (332119): 18.848 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|rx_pma_clk
|
|
Info (332119): 18.902 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|rx_pma_clk
|
|
Info (332119): 18.906 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|rx_pma_clk
|
|
Info (332119): 18.944 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|rx_pma_clk
|
|
Info (332119): 18.954 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_pma_clk
|
|
Info (332119): 19.036 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|rx_pma_clk
|
|
Info (332119): 19.059 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|rx_pma_clk
|
|
Info (332119): 44.130 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|tx_pma_clk
|
|
Info (332119): 44.231 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|tx_pma_clk
|
|
Info (332119): 44.381 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|tx_pma_clk
|
|
Info (332119): 44.615 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|tx_pma_clk
|
|
Info (332119): 45.301 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|tx_coreclkin
|
|
Info (332119): 45.518 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|tx_coreclkin
|
|
Info (332119): 45.631 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|tx_coreclkin
|
|
Info (332119): 45.740 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|tx_coreclkin
|
|
Info (332119): 98.341 0.000 altera_reserved_tck
|
|
Info (332146): Worst-case removal slack is 0.104
|
|
Info (332119): Slack End Point TNS Clock
|
|
Info (332119): ========= =================== =====================
|
|
Info (332119): 0.104 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk1
|
|
Info (332119): 0.147 0.000 SYS_RefClk
|
|
Info (332119): 0.154 0.000 u0|dcp_iopll|dcp_iopll|clk1x
|
|
Info (332119): 0.159 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_clk
|
|
Info (332119): 0.161 0.000 mem|ddr4a|ddr4a_core_usr_clk
|
|
Info (332119): 0.172 0.000 mem|ddr4a|ddr4a_core_cal_slave_clk
|
|
Info (332119): 0.172 0.000 u0|dcp_iopll|dcp_iopll|clk100
|
|
Info (332119): 0.174 0.000 PCIE_REFCLK
|
|
Info (332119): 0.192 0.000 DDR4_RefClk
|
|
Info (332119): 0.193 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|wys~CORE_CLK_OUT
|
|
Info (332119): 0.202 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|rx_pma_clk
|
|
Info (332119): 0.215 0.000 u0|dcp_iopll|dcp_iopll|clk25
|
|
Info (332119): 0.221 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|rx_pma_clk
|
|
Info (332119): 0.243 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|rx_pma_clk
|
|
Info (332119): 0.526 0.000 altera_reserved_tck
|
|
Info (332119): 0.815 0.000 filtered_sclk_negedge
|
|
Info (332119): 1.306 0.000 fspi_sclk
|
|
Info (332119): 9.075 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|rx_pma_clk
|
|
Info (332119): 9.089 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|rx_pma_clk
|
|
Info (332119): 9.190 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|rx_pma_clk
|
|
Info (332119): 9.214 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|rx_pma_clk
|
|
Info (332119): 9.241 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|rx_pma_clk
|
|
Info (332119): 9.256 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|rx_pma_clk
|
|
Info (332119): 9.445 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|rx_pma_clk
|
|
Info (332119): 9.594 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_pma_clk
|
|
Info (332119): 10.008 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|rx_fref
|
|
Info (332119): 10.028 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|rx_fref
|
|
Info (332119): 10.109 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|rx_fref
|
|
Info (332119): 10.127 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|rx_fref
|
|
Info (332119): 10.166 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|rx_fref
|
|
Info (332119): 10.179 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|rx_fref
|
|
Info (332119): 10.347 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|rx_fref
|
|
Info (332119): 11.077 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332119): 51.216 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|tx_coreclkin
|
|
Info (332119): 51.432 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|tx_coreclkin
|
|
Info (332119): 51.544 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|tx_coreclkin
|
|
Info (332119): 51.605 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|tx_coreclkin
|
|
Info (332119): 52.054 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|tx_pma_clk
|
|
Info (332119): 52.142 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|tx_pma_clk
|
|
Info (332119): 52.287 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|tx_pma_clk
|
|
Info (332119): 52.343 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|tx_pma_clk
|
|
Info (332146): Worst-case minimum pulse width slack is 0.093
|
|
Info (332119): Slack End Point TNS Clock
|
|
Info (332119): ========= =================== =====================
|
|
Info (332119): 0.093 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|atx0|altera_xcvr_atx_pll_ip_inst|mcgb_serial_clk
|
|
Info (332119): 0.124 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|twentynm_atx_pll_inst~O_CLK0_8G
|
|
Info (332119): 0.200 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_serial_clk
|
|
Info (332119): 0.204 0.000 DDR4A_DQS_P[2]_IN
|
|
Info (332119): 0.204 0.000 DDR4A_DQS_P[3]_IN
|
|
Info (332119): 0.204 0.000 DDR4A_DQS_P[4]_IN
|
|
Info (332119): 0.204 0.000 DDR4A_DQS_P[5]_IN
|
|
Info (332119): 0.204 0.000 DDR4B_DQS_P[2]_IN
|
|
Info (332119): 0.204 0.000 DDR4B_DQS_P[3]_IN
|
|
Info (332119): 0.204 0.000 DDR4B_DQS_P[4]_IN
|
|
Info (332119): 0.204 0.000 DDR4B_DQS_P[5]_IN
|
|
Info (332119): 0.205 0.000 DDR4A_DQS_P[0]_IN
|
|
Info (332119): 0.205 0.000 DDR4A_DQS_P[1]_IN
|
|
Info (332119): 0.205 0.000 DDR4A_DQS_P[6]_IN
|
|
Info (332119): 0.205 0.000 DDR4A_DQS_P[7]_IN
|
|
Info (332119): 0.205 0.000 DDR4B_DQS_P[0]_IN
|
|
Info (332119): 0.205 0.000 DDR4B_DQS_P[1]_IN
|
|
Info (332119): 0.205 0.000 DDR4B_DQS_P[6]_IN
|
|
Info (332119): 0.205 0.000 DDR4B_DQS_P[7]_IN
|
|
Info (332119): 0.446 0.000 mem|ddr4a|ddr4a_wf_clk_10
|
|
Info (332119): 0.446 0.000 mem|ddr4a|ddr4a_wf_clk_3
|
|
Info (332119): 0.446 0.000 mem|ddr4a|ddr4a_wf_clk_4
|
|
Info (332119): 0.446 0.000 mem|ddr4a|ddr4a_wf_clk_5
|
|
Info (332119): 0.446 0.000 mem|ddr4a|ddr4a_wf_clk_6
|
|
Info (332119): 0.446 0.000 mem|ddr4a|ddr4a_wf_clk_7
|
|
Info (332119): 0.446 0.000 mem|ddr4a|ddr4a_wf_clk_8
|
|
Info (332119): 0.446 0.000 mem|ddr4a|ddr4a_wf_clk_9
|
|
Info (332119): 0.446 0.000 mem|ddr4b|ddr4b_wf_clk_10
|
|
Info (332119): 0.446 0.000 mem|ddr4b|ddr4b_wf_clk_3
|
|
Info (332119): 0.446 0.000 mem|ddr4b|ddr4b_wf_clk_4
|
|
Info (332119): 0.446 0.000 mem|ddr4b|ddr4b_wf_clk_5
|
|
Info (332119): 0.446 0.000 mem|ddr4b|ddr4b_wf_clk_6
|
|
Info (332119): 0.446 0.000 mem|ddr4b|ddr4b_wf_clk_7
|
|
Info (332119): 0.446 0.000 mem|ddr4b|ddr4b_wf_clk_8
|
|
Info (332119): 0.446 0.000 mem|ddr4b|ddr4b_wf_clk_9
|
|
Info (332119): 0.458 0.000 mem|ddr4a|ddr4a_vco_clk
|
|
Info (332119): 0.461 0.000 mem|ddr4a|ddr4a_wf_clk_0
|
|
Info (332119): 0.461 0.000 mem|ddr4b|ddr4b_wf_clk_0
|
|
Info (332119): 0.463 0.000 mem|ddr4a|ddr4a_wf_clk_1
|
|
Info (332119): 0.463 0.000 mem|ddr4a|ddr4a_wf_clk_2
|
|
Info (332119): 0.463 0.000 mem|ddr4b|ddr4b_wf_clk_1
|
|
Info (332119): 0.463 0.000 mem|ddr4b|ddr4b_wf_clk_2
|
|
Info (332119): 0.466 0.000 mem|ddr4a|ddr4a_vco_clk_1
|
|
Info (332119): 0.466 0.000 mem|ddr4a|ddr4a_vco_clk_2
|
|
Info (332119): 0.466 0.000 mem|ddr4b|ddr4b_vco_clk_0
|
|
Info (332119): 0.466 0.000 mem|ddr4b|ddr4b_vco_clk_1
|
|
Info (332119): 0.466 0.000 mem|ddr4b|ddr4b_vco_clk_2
|
|
Info (332119): 0.825 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_bonding_clocks[0]
|
|
Info (332119): 0.889 0.000 mem|ddr4a|ddr4a_phy_clk_0
|
|
Info (332119): 0.889 0.000 mem|ddr4a|ddr4a_phy_clk_1
|
|
Info (332119): 0.889 0.000 mem|ddr4a|ddr4a_phy_clk_2
|
|
Info (332119): 0.889 0.000 mem|ddr4b|ddr4b_phy_clk_0
|
|
Info (332119): 0.889 0.000 mem|ddr4b|ddr4b_phy_clk_1
|
|
Info (332119): 0.889 0.000 mem|ddr4b|ddr4b_phy_clk_2
|
|
Info (332119): 0.937 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_pma_clk
|
|
Info (332119): 0.937 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|rx_pma_clk
|
|
Info (332119): 0.937 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|rx_pma_clk
|
|
Info (332119): 0.937 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|rx_pma_clk
|
|
Info (332119): 0.937 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|rx_pma_clk
|
|
Info (332119): 0.937 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|rx_pma_clk
|
|
Info (332119): 0.937 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|rx_pma_clk
|
|
Info (332119): 0.937 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|rx_pma_clk
|
|
Info (332119): 0.947 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_pcs_clk_div_by_4[0]
|
|
Info (332119): 0.947 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_pcs_clk_div_by_4[1]
|
|
Info (332119): 0.947 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_pcs_clk_div_by_4[2]
|
|
Info (332119): 0.947 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_pcs_clk_div_by_4[3]
|
|
Info (332119): 0.947 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_pcs_clk_div_by_4[4]
|
|
Info (332119): 0.947 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_pcs_clk_div_by_4[5]
|
|
Info (332119): 0.947 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_pcs_clk_div_by_4[6]
|
|
Info (332119): 0.947 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_pcs_clk_div_by_4[7]
|
|
Info (332119): 0.950 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_clk
|
|
Info (332119): 0.950 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|rx_clk
|
|
Info (332119): 0.950 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|rx_clk
|
|
Info (332119): 0.950 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|rx_clk
|
|
Info (332119): 0.950 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|rx_clk
|
|
Info (332119): 0.950 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|rx_clk
|
|
Info (332119): 0.950 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|rx_clk
|
|
Info (332119): 0.950 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|rx_clk
|
|
Info (332119): 0.950 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|rx_pcs_clk_div_by_4[0]
|
|
Info (332119): 0.950 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|rx_pcs_clk_div_by_4[1]
|
|
Info (332119): 0.950 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|rx_pcs_clk_div_by_4[2]
|
|
Info (332119): 0.950 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|rx_pcs_clk_div_by_4[3]
|
|
Info (332119): 0.950 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|rx_pcs_clk_div_by_4[4]
|
|
Info (332119): 0.950 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|rx_pcs_clk_div_by_4[5]
|
|
Info (332119): 0.950 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|rx_pcs_clk_div_by_4[6]
|
|
Info (332119): 0.950 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|rx_pcs_clk_div_by_4[7]
|
|
Info (332119): 0.953 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|pll_pcie_clk
|
|
Info (332119): 0.969 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|hip_cmn_clk[0]
|
|
Info (332119): 1.456 0.000 ETH_RefClk
|
|
Info (332119): 1.538 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|tx_coreclkin
|
|
Info (332119): 1.538 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|tx_coreclkin
|
|
Info (332119): 1.538 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|tx_coreclkin
|
|
Info (332119): 1.538 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|tx_coreclkin
|
|
Info (332119): 1.548 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_coreclkin
|
|
Info (332119): 1.548 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|rx_coreclkin
|
|
Info (332119): 1.548 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|rx_coreclkin
|
|
Info (332119): 1.548 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|rx_coreclkin
|
|
Info (332119): 1.553 0.000 mem|ddr4a|ddr4a_core_usr_clk
|
|
Info (332119): 1.588 0.000 hssi_pll_r_0_outclk0
|
|
Info (332119): 1.589 0.000 hssi_pll_t_outclk0
|
|
Info (332119): 1.608 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|wys~CORE_CLK_OUT
|
|
Info (332119): 1.780 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|tx_pma_clk
|
|
Info (332119): 1.780 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|tx_pma_clk
|
|
Info (332119): 1.780 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|tx_pma_clk
|
|
Info (332119): 1.780 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|tx_pma_clk
|
|
Info (332119): 1.789 0.000 DDR4_RefClk
|
|
Info (332119): 1.827 0.000 mem|ddr4a|ddr4a_phy_clk_l_0
|
|
Info (332119): 1.827 0.000 mem|ddr4a|ddr4a_phy_clk_l_1
|
|
Info (332119): 1.827 0.000 mem|ddr4a|ddr4a_phy_clk_l_2
|
|
Info (332119): 1.827 0.000 mem|ddr4b|ddr4b_phy_clk_l_0
|
|
Info (332119): 1.827 0.000 mem|ddr4b|ddr4b_phy_clk_l_1
|
|
Info (332119): 1.827 0.000 mem|ddr4b|ddr4b_phy_clk_l_2
|
|
Info (332119): 1.876 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_clk
|
|
Info (332119): 1.876 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|rx_pma_clk
|
|
Info (332119): 1.876 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|rx_pma_clk
|
|
Info (332119): 1.876 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|rx_pma_clk
|
|
Info (332119): 1.887 0.000 hssi_pll_t_outclk1
|
|
Info (332119): 1.888 0.000 hssi_pll_r_0_outclk1
|
|
Info (332119): 1.938 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|pld_clk
|
|
Info (332119): 1.941 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|pma_hclk_by2
|
|
Info (332119): 1.941 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|pma_hclk_by2
|
|
Info (332119): 1.941 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|pma_hclk_by2
|
|
Info (332119): 1.941 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|pma_hclk_by2
|
|
Info (332119): 1.941 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|pma_hclk_by2
|
|
Info (332119): 1.941 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|pma_hclk_by2
|
|
Info (332119): 1.941 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|pma_hclk_by2
|
|
Info (332119): 1.941 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|pma_hclk_by2
|
|
Info (332119): 1.944 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk1
|
|
Info (332119): 2.177 0.000 u0|dcp_iopll|dcp_iopll|clk1x
|
|
Info (332119): 2.243 0.000 vl_qph_user_clk_clkpsc_clk1
|
|
Info (332119): 2.971 0.000 mem|ddr4a|ddr4a_core_cal_slave_clk
|
|
Info (332119): 3.111 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_div_clk
|
|
Info (332119): 3.114 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|tx_pma_div_clk
|
|
Info (332119): 3.934 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_clkout
|
|
Info (332119): 3.956 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|tx_clk
|
|
Info (332119): 3.956 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|tx_clk
|
|
Info (332119): 3.956 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|tx_clk
|
|
Info (332119): 3.956 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|tx_clk
|
|
Info (332119): 3.956 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|tx_clk
|
|
Info (332119): 3.956 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|tx_clk
|
|
Info (332119): 3.956 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|tx_clk
|
|
Info (332119): 3.956 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|tx_clk
|
|
Info (332119): 4.531 0.000 vl_qph_user_clk_clkpsc_clk0
|
|
Info (332119): 4.532 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk0
|
|
Info (332119): 4.675 0.000 PCIE_REFCLK
|
|
Info (332119): 4.681 0.000 u0|dcp_iopll|dcp_iopll|clk100
|
|
Info (332119): 4.689 0.000 SYS_RefClk
|
|
Info (332119): 4.939 0.000 pr_clk_enable_dclk_reg2_user_clk
|
|
Info (332119): 4.950 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332119): 4.951 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|rx_fref
|
|
Info (332119): 4.951 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|rx_fref
|
|
Info (332119): 4.951 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|rx_fref
|
|
Info (332119): 4.951 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|rx_fref
|
|
Info (332119): 4.951 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|rx_fref
|
|
Info (332119): 4.951 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|rx_fref
|
|
Info (332119): 4.951 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|rx_fref
|
|
Info (332119): 4.956 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|avmmclk
|
|
Info (332119): 4.956 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|avmmclk
|
|
Info (332119): 4.956 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|avmmclk
|
|
Info (332119): 4.956 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|avmmclk
|
|
Info (332119): 4.956 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|avmmclk
|
|
Info (332119): 4.956 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|avmmclk
|
|
Info (332119): 4.956 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|avmmclk
|
|
Info (332119): 4.956 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|avmmclk
|
|
Info (332119): 4.956 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|avmmclk
|
|
Info (332119): 4.956 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|avmmclk
|
|
Info (332119): 4.956 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|avmmclk
|
|
Info (332119): 4.956 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|avmmclk
|
|
Info (332119): 4.979 0.000 filtered_sclk_negedge
|
|
Info (332119): 9.988 0.000 u0|dcp_iopll|dcp_iopll|clk50
|
|
Info (332119): 19.685 0.000 u0|dcp_iopll|dcp_iopll|clk25
|
|
Info (332119): 19.880 0.000 flash_oe_clk
|
|
Info (332119): 49.786 0.000 altera_reserved_tck
|
|
Info (332119): 124.828 0.000 fspi_sclk
|
|
Info (332119): 500.000 0.000 altera_ts_clk
|
|
Warning (332182): No path is found satisfying assignment "set_max_skew -from [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|tcm_control_out|pio_0|data_out[0]}] -to [get_pins {fpga_top|inst_green_bs|ddr4*_reset_sync|resync_chains[0].synchronizer_nocut|*|clrn}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 ". This assignment will be ignored.
|
|
Info (332115): Worst-case slack is 2.763 for "set_max_skew -from [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Tx_fifo|C1Tx_fifo.inst_async_C1Tx_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Tx_fifo|C1Tx_fifo.inst_async_C1Tx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 "
|
|
Info (332115): Worst-case slack is 2.819 for "set_max_skew -from [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Tx_fifo|C0Tx_fifo.inst_async_C0Tx_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Tx_fifo|C0Tx_fifo.inst_async_C0Tx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 "
|
|
Info (332115): Worst-case slack is 2.920 for "set_max_skew -from [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_CfgTx_fifo|CfgTx_fifo.inst_async_CfgTx_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_CfgTx_fifo|CfgTx_fifo.inst_async_CfgTx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 "
|
|
Info (332115): Worst-case slack is 2.933 for "set_max_skew -from [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Rx_fifo|C0Rx_fifo.inst_async_C0Rx_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Rx_fifo|C0Rx_fifo.inst_async_C0Rx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 "
|
|
Info (332115): Worst-case slack is 2.963 for "set_max_skew -from [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Rx_fifo|C1Rx_fifo.inst_async_C1Rx_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Rx_fifo|C1Rx_fifo.inst_async_C1Rx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 "
|
|
Info (332115): Worst-case slack is 3.023 for "set_max_skew -from [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_msix_top|msix_brid|msix_dcfifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_msix_top|msix_brid|msix_dcfifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 "
|
|
Info (332115): Worst-case slack is 3.283 for "set_max_skew -from [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 "
|
|
Info (332115): Worst-case slack is 3.287 for "set_max_skew -from [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 "
|
|
Info (332115): Worst-case slack is 3.322 for "set_max_skew -from [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 "
|
|
Info (332115): Worst-case slack is 3.344 for "set_max_skew -from [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 "
|
|
Info (332115): Worst-case slack is 3.360 for "set_max_skew -from [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 "
|
|
Info (332115): Worst-case slack is 3.362 for "set_max_skew -from [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Tx_fifo|C0Tx_fifo.inst_async_C0Tx_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Tx_fifo|C0Tx_fifo.inst_async_C0Tx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 "
|
|
Info (332115): Worst-case slack is 3.396 for "set_max_skew -from [get_keepers {fpga_top|inst_blue_ccip_interface_reg|pck_cp2af_softReset_T0_q}] -to [get_pins {fpga_top|inst_green_bs|ddr4*_reset_sync|resync_chains[0].synchronizer_nocut|*|clrn}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 "
|
|
Info (332115): Worst-case slack is 3.473 for "set_max_skew -from [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 "
|
|
Info (332115): Worst-case slack is 3.542 for "set_max_skew -from [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Rx_fifo|C0Rx_fifo.inst_async_C0Rx_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Rx_fifo|C0Rx_fifo.inst_async_C0Rx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 "
|
|
Info (332115): Worst-case slack is 3.546 for "set_max_skew -from [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 "
|
|
Info (332115): Worst-case slack is 3.573 for "set_max_skew -from [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 "
|
|
Info (332115): Worst-case slack is 3.588 for "set_max_skew -from [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_CfgTx_fifo|CfgTx_fifo.inst_async_CfgTx_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_CfgTx_fifo|CfgTx_fifo.inst_async_CfgTx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 "
|
|
Info (332115): Worst-case slack is 3.606 for "set_max_skew -from [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Tx_fifo|C1Tx_fifo.inst_async_C1Tx_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Tx_fifo|C1Tx_fifo.inst_async_C1Tx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 "
|
|
Info (332115): Worst-case slack is 3.612 for "set_max_skew -from [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 "
|
|
Info (332115): Worst-case slack is 3.643 for "set_max_skew -from [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Rx_fifo|C1Rx_fifo.inst_async_C1Rx_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Rx_fifo|C1Rx_fifo.inst_async_C1Rx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 "
|
|
Info (332115): Worst-case slack is 3.656 for "set_max_skew -from [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 "
|
|
Info (332115): Worst-case slack is 3.661 for "set_max_skew -from [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_msix_top|msix_brid|msix_dcfifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_msix_top|msix_brid|msix_dcfifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 "
|
|
Info (332115): Worst-case slack is 3.682 for "set_max_skew -from [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|ddr_backchannel|mm_clock_crossing_bridge_0|cmd_fifo|in_wr_ptr_gray[*]}] -to [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|ddr_backchannel|mm_clock_crossing_bridge_0|cmd_fifo|write_crosser|sync[*].u|din_s1}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 "
|
|
Info (332115): Worst-case slack is 3.687 for "set_max_skew -from [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|ddr_backchannel|mm_clock_crossing_bridge_0|rsp_fifo|out_rd_ptr_gray[*]}] -to [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|ddr_backchannel|mm_clock_crossing_bridge_0|rsp_fifo|read_crosser|sync[*].u|din_s1}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 "
|
|
Info (332115): Worst-case slack is 7.644 for "set_max_skew -from [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|ddr_backchannel|mm_clock_crossing_bridge_0|cmd_fifo|out_rd_ptr_gray[*]}] -to [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|ddr_backchannel|mm_clock_crossing_bridge_0|cmd_fifo|read_crosser|sync[*].u|din_s1}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 "
|
|
Info (332115): Worst-case slack is 7.654 for "set_max_skew -from [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|ddr_backchannel|mm_clock_crossing_bridge_0|rsp_fifo|in_wr_ptr_gray[*]}] -to [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|ddr_backchannel|mm_clock_crossing_bridge_0|rsp_fifo|write_crosser|sync[*].u|din_s1}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 "
|
|
Info (332115): Worst-case slack is 7.705 for "set_max_skew -from [get_registers {auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|stfabric|t2h0_fifo|in_wr_ptr_gray[*]}] -to [get_registers {auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|stfabric|t2h0_fifo|write_crosser|sync[*].u|din_s1}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 "
|
|
Info (332115): Worst-case slack is 7.735 for "set_max_skew -from [get_registers {auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|stfabric|t2h0_fifo|out_rd_ptr_gray[*]}] -to [get_registers {auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|stfabric|t2h0_fifo|read_crosser|sync[*].u|din_s1}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 "
|
|
Info (332115): Worst-case slack is 7.747 for "set_max_skew -from [get_registers {auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|stfabric|h2t0_fifo|out_rd_ptr_gray[*]}] -to [get_registers {auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|stfabric|h2t0_fifo|read_crosser|sync[*].u|din_s1}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 "
|
|
Info (332115): Worst-case slack is 7.750 for "set_max_skew -from [get_registers {auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|stfabric|h2t0_fifo|in_wr_ptr_gray[*]}] -to [get_registers {auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|stfabric|h2t0_fifo|write_crosser|sync[*].u|din_s1}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 "
|
|
Info (332163): Fast 900mV 0C Model Net Delay Summary
|
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Info (332163): Name Slack Req Actual From To Type
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|
Info (332163): ============= ====== ====== ====== =============== =============== ====
|
|
Info (332163): set_net_delay 1.934 3.001 1.067 [get_pins -compatibility_mode {*|out_rd_ptr_gray[*]*}]
|
|
Info (332163): [get_registers {*|platform_utils_dcfifo_synchronizer_bundle:read_crosser|platform_utils_std_synchronizer_nocut:sync[*].u|din_s1}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 2.625 3.200 0.575 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Tx_fifo|C0Tx_fifo.inst_async_C0Tx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Tx_fifo|C0Tx_fifo.inst_async_C0Tx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 2.625 3.200 0.575 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Rx_fifo|C1Rx_fifo.inst_async_C1Rx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Rx_fifo|C1Rx_fifo.inst_async_C1Rx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 2.670 3.200 0.530 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Tx_fifo|C1Tx_fifo.inst_async_C1Tx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Tx_fifo|C1Tx_fifo.inst_async_C1Tx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 2.695 3.636 0.941 [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 2.706 3.001 0.295 [get_pins -compatibility_mode {*|in_wr_ptr_gray[*]*}]
|
|
Info (332163): [get_registers {*|platform_utils_dcfifo_synchronizer_bundle:write_crosser|platform_utils_std_synchronizer_nocut:sync[*].u|din_s1}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 2.791 3.200 0.409 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Rx_fifo|C0Rx_fifo.inst_async_C0Rx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Rx_fifo|C0Rx_fifo.inst_async_C0Rx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 2.793 3.200 0.407 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_CfgTx_fifo|CfgTx_fifo.inst_async_CfgTx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_CfgTx_fifo|CfgTx_fifo.inst_async_CfgTx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 2.843 3.200 0.357 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Tx_fifo|C0Tx_fifo.inst_async_C0Tx_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Tx_fifo|C0Tx_fifo.inst_async_C0Tx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 2.849 3.200 0.351 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_msix_top|msix_brid|msix_dcfifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_msix_top|msix_brid|msix_dcfifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 2.869 4.000 1.131 [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser|async_clock_crosser.clock_xer|out_data_toggle_flopped}]
|
|
Info (332163): [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser|async_clock_crosser.clock_xer|out_to_in_synchronizer|din_s1}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 2.874 3.200 0.326 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Rx_fifo|C0Rx_fifo.inst_async_C0Rx_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Rx_fifo|C0Rx_fifo.inst_async_C0Rx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 2.921 3.200 0.279 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_CfgTx_fifo|CfgTx_fifo.inst_async_CfgTx_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_CfgTx_fifo|CfgTx_fifo.inst_async_CfgTx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 2.929 3.200 0.271 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Tx_fifo|C1Tx_fifo.inst_async_C1Tx_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Tx_fifo|C1Tx_fifo.inst_async_C1Tx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 2.934 3.200 0.266 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Rx_fifo|C1Rx_fifo.inst_async_C1Rx_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Rx_fifo|C1Rx_fifo.inst_async_C1Rx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 2.951 3.200 0.249 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_msix_top|msix_brid|msix_dcfifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_msix_top|msix_brid|msix_dcfifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 3.008 3.636 0.628 [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 3.014 3.636 0.622 [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 3.018 3.636 0.618 [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 3.078 3.636 0.558 [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 3.127 4.000 0.873 [get_registers {*altera_avalon_st_clock_crosser:*|in_data_buffer*}]
|
|
Info (332163): [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_005|async_clock_crosser.clock_xer|out_data_buffer*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 3.151 4.000 0.849 [get_registers {*altera_avalon_st_clock_crosser:*|in_data_buffer*}]
|
|
Info (332163): [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_004|async_clock_crosser.clock_xer|out_data_buffer*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 3.235 3.636 0.401 [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|delayed_wrptr_g*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 3.261 4.000 0.739 [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_003|async_clock_crosser.clock_xer|out_data_toggle_flopped}]
|
|
Info (332163): [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_003|async_clock_crosser.clock_xer|out_to_in_synchronizer|din_s1}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 3.278 4.000 0.722 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Tx_fifo|C1Tx_fifo.inst_async_C1Tx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Tx_fifo|C1Tx_fifo.inst_async_C1Tx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 3.304 3.636 0.332 [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|*rdptr_g*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 3.323 4.000 0.677 [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_004|async_clock_crosser.clock_xer|in_data_toggle}]
|
|
Info (332163): [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_004|async_clock_crosser.clock_xer|in_to_out_synchronizer|din_s1}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 3.347 4.000 0.653 [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 3.347 3.636 0.289 [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|delayed_wrptr_g*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 3.351 3.636 0.285 [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|*rdptr_g*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 3.356 4.000 0.644 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Rx_fifo|C0Rx_fifo.inst_async_C0Rx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Rx_fifo|C0Rx_fifo.inst_async_C0Rx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 3.381 4.000 0.619 [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_001|async_clock_crosser.clock_xer|out_data_toggle_flopped}]
|
|
Info (332163): [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_001|async_clock_crosser.clock_xer|out_to_in_synchronizer|din_s1}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 3.383 3.636 0.253 [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|*rdptr_g*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 3.390 4.000 0.610 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Tx_fifo|C0Tx_fifo.inst_async_C0Tx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Tx_fifo|C0Tx_fifo.inst_async_C0Tx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 3.409 4.000 0.591 [get_registers {*altera_avalon_st_clock_crosser:*|in_data_buffer*}]
|
|
Info (332163): [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_006|async_clock_crosser.clock_xer|out_data_buffer*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 3.443 4.000 0.557 [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 3.523 4.000 0.477 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Rx_fifo|C1Rx_fifo.inst_async_C1Rx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Rx_fifo|C1Rx_fifo.inst_async_C1Rx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 3.526 4.000 0.474 [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 3.528 4.000 0.472 [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 3.543 4.000 0.457 [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 3.570 4.000 0.430 [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|delayed_wrptr_g*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 3.590 4.000 0.410 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_CfgTx_fifo|CfgTx_fifo.inst_async_CfgTx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_CfgTx_fifo|CfgTx_fifo.inst_async_CfgTx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 3.631 4.000 0.369 [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_002|async_clock_crosser.clock_xer|out_data_toggle_flopped}]
|
|
Info (332163): [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_002|async_clock_crosser.clock_xer|out_to_in_synchronizer|din_s1}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 3.636 4.000 0.364 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Tx_fifo|C1Tx_fifo.inst_async_C1Tx_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Tx_fifo|C1Tx_fifo.inst_async_C1Tx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 3.649 4.000 0.351 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_msix_top|msix_brid|msix_dcfifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_msix_top|msix_brid|msix_dcfifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 3.664 4.000 0.336 [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_005|async_clock_crosser.clock_xer|in_data_toggle}]
|
|
Info (332163): [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_005|async_clock_crosser.clock_xer|in_to_out_synchronizer|din_s1}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 3.664 4.000 0.336 [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|*rdptr_g*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 3.668 4.000 0.332 [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_007|async_clock_crosser.clock_xer|in_data_toggle}]
|
|
Info (332163): [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_007|async_clock_crosser.clock_xer|in_to_out_synchronizer|din_s1}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 3.696 4.000 0.304 [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|*rdptr_g*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 3.700 4.000 0.300 [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_006|async_clock_crosser.clock_xer|in_data_toggle}]
|
|
Info (332163): [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_006|async_clock_crosser.clock_xer|in_to_out_synchronizer|din_s1}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 3.710 4.000 0.290 [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|delayed_wrptr_g*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 3.723 4.000 0.277 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_CfgTx_fifo|CfgTx_fifo.inst_async_CfgTx_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_CfgTx_fifo|CfgTx_fifo.inst_async_CfgTx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 3.735 4.000 0.265 [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|delayed_wrptr_g*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 3.738 4.000 0.262 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Rx_fifo|C0Rx_fifo.inst_async_C0Rx_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Rx_fifo|C0Rx_fifo.inst_async_C0Rx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 3.758 4.000 0.242 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Tx_fifo|C0Tx_fifo.inst_async_C0Tx_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C0Tx_fifo|C0Tx_fifo.inst_async_C0Tx_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 3.766 4.000 0.234 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_msix_top|msix_brid|msix_dcfifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_msix_top|msix_brid|msix_dcfifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 3.779 4.000 0.221 [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Rx_fifo|C1Rx_fifo.inst_async_C1Rx_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}]
|
|
Info (332163): [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_pcie0_cdc|inst_async_C1Rx_fifo|C1Rx_fifo.inst_async_C1Rx_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 3.827 4.000 0.173 [get_pins -compatibility_mode {*|out_rd_ptr_gray[*]*}]
|
|
Info (332163): [get_registers {*|altera_dcfifo_synchronizer_bundle:read_crosser|altera_std_synchronizer_nocut:sync[*].u|din_s1}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 3.857 4.000 0.143 [get_pins -compatibility_mode {*|in_wr_ptr_gray[*]*}]
|
|
Info (332163): [get_registers {*|altera_dcfifo_synchronizer_bundle:write_crosser|altera_std_synchronizer_nocut:sync[*].u|din_s1}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 6.395 8.000 1.605 [get_registers {*altera_avalon_st_clock_crosser:*|in_data_buffer*}]
|
|
Info (332163): [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_003|async_clock_crosser.clock_xer|out_data_buffer*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 6.640 8.000 1.360 [get_registers {*altera_avalon_st_clock_crosser:*|in_data_buffer*}]
|
|
Info (332163): [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_002|async_clock_crosser.clock_xer|out_data_buffer*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 7.062 8.000 0.938 [get_registers {auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|host_link_jtag|jtag|normal.jtag_dc_streaming|sink_crosser|out_data_toggle_flopped}]
|
|
Info (332163): [get_registers {auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|host_link_jtag|jtag|normal.jtag_dc_streaming|sink_crosser|out_to_in_synchronizer|din_s1}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 7.444 8.000 0.556 [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_002|async_clock_crosser.clock_xer|in_data_toggle}]
|
|
Info (332163): [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_002|async_clock_crosser.clock_xer|in_to_out_synchronizer|din_s1}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 7.507 8.000 0.493 [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_006|async_clock_crosser.clock_xer|out_data_toggle_flopped}]
|
|
Info (332163): [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_006|async_clock_crosser.clock_xer|out_to_in_synchronizer|din_s1}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 7.650 8.000 0.350 [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_003|async_clock_crosser.clock_xer|in_data_toggle}]
|
|
Info (332163): [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_003|async_clock_crosser.clock_xer|in_to_out_synchronizer|din_s1}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 7.711 8.000 0.289 [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_007|async_clock_crosser.clock_xer|out_data_toggle_flopped}]
|
|
Info (332163): [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_007|async_clock_crosser.clock_xer|out_to_in_synchronizer|din_s1}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 31.060 32.000 0.940 [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser|async_clock_crosser.clock_xer|in_data_toggle}]
|
|
Info (332163): [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser|async_clock_crosser.clock_xer|in_to_out_synchronizer|din_s1}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 31.126 32.000 0.874 [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_005|async_clock_crosser.clock_xer|out_data_toggle_flopped}]
|
|
Info (332163): [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_005|async_clock_crosser.clock_xer|out_to_in_synchronizer|din_s1}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 31.269 32.000 0.731 [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_004|async_clock_crosser.clock_xer|out_data_toggle_flopped}]
|
|
Info (332163): [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_004|async_clock_crosser.clock_xer|out_to_in_synchronizer|din_s1}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 31.293 32.000 0.707 [get_registers {*altera_avalon_st_clock_crosser:*|in_data_buffer*}]
|
|
Info (332163): [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_001|async_clock_crosser.clock_xer|out_data_buffer*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 31.431 32.000 0.569 [get_registers {*altera_avalon_st_clock_crosser:*|in_data_buffer*}]
|
|
Info (332163): [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser|async_clock_crosser.clock_xer|out_data_buffer*}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 31.617 32.000 0.383 [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_001|async_clock_crosser.clock_xer|in_data_toggle}]
|
|
Info (332163): [get_registers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_001|async_clock_crosser.clock_xer|in_to_out_synchronizer|din_s1}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 76.174 80.000 3.826 [get_registers {auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|host_link_jtag|jtag|normal.jtag_dc_streaming|sink_crosser|in_data_toggle}]
|
|
Info (332163): [get_registers {auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|host_link_jtag|jtag|normal.jtag_dc_streaming|sink_crosser|in_to_out_synchronizer|din_s1}]
|
|
Info (332163): max
|
|
Info (332163): set_net_delay 79.368 80.000 0.632 [get_registers {*altera_avalon_st_clock_crosser:*|in_data_buffer*}]
|
|
Info (332163): [get_registers {auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|host_link_jtag|jtag|normal.jtag_dc_streaming|sink_crosser|out_data_buffer*}]
|
|
Info (332163): max
|
|
Info (332114): Report Metastability: Found 403 synchronizer chains.
|
|
Info (332114): Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds.
|
|
Info (332114): Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.
|
|
|
|
Info (332114): Number of Synchronizer Chains Found: 403
|
|
Info (332114): Shortest Synchronizer Chain: 2 Registers
|
|
Info (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 0.258
|
|
Info (332114): Worst Case Available Settling Time: 3.816 ns
|
|
Info (332114): Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions.
|
|
Info (332114): - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 78.2
|
|
Info (332114): Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions.
|
|
Info (332114): - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 4590.3
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 0.803
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_bonding_clocks[0]}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 0.803
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|sta_rx_clk2_by4_1
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs~byte_deserializer_pcs_clk_div_by_4_txclk_reg.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|rx_clk (INVERTED)
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_bonding_clocks[0]
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 1.000 1.000 launch edge time
|
|
Info (332115): 3.469 2.469 F clock network delay
|
|
Info (332115): 3.469 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|sta_rx_clk2_by4_1
|
|
Info (332115): 3.469 0.000 FF CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs~byte_deserializer_pcs_clk_div_by_4_txclk_reg.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 2.000 2.000 latch edge time
|
|
Info (332115): 3.516 1.516 R clock network delay
|
|
Info (332115): 4.251 0.735 clock pessimism removed
|
|
Info (332115): 4.272 0.021 uTsu fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs~byte_deserializer_pcs_clk_div_by_4_txclk_reg.reg
|
|
Info (332115): Data Arrival Time : 3.469
|
|
Info (332115): Data Required Time : 4.272
|
|
Info (332115): Slack : 0.803
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 0.813
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk1}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 0.813
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|mem_unit|icache|[0].bank|core_rsp_req|shift_reg[0][28]
|
|
Info (332115): To Node : fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|issue|ibuffer|q_data_out[2][8]
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk1
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk1
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 3.860 3.860 R clock network delay
|
|
Info (332115): 3.860 0.000 fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|mem_unit|icache|[0].bank|core_rsp_req|shift_reg[0][28]
|
|
Info (332115): 3.977 0.117 FF uTco fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|mem_unit|icache|[0].bank|core_rsp_req|shift_reg[0][28]|q
|
|
Info (332115): 4.019 0.042 FF CELL High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|mem_unit|icache|[0].bank|core_rsp_req|shift_reg[0][28]~la_lab/laboutt[17]
|
|
Info (332115): 4.471 0.452 FF IC High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|mem_unit|icache|[0].bank|core_rsp_req|data_out[28]~14|datad
|
|
Info (332115): 4.542 0.071 FF CELL High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|mem_unit|icache|[0].bank|core_rsp_req|data_out[28]~14|combout
|
|
Info (332115): 4.546 0.004 FF CELL High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|mem_unit|icache|[0].bank|core_rsp_req|data_out[28]~14~la_lab/laboutb[11]
|
|
Info (332115): 5.503 0.957 FF IC High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|decode|reduce_or_12~0|datab
|
|
Info (332115): 5.624 0.121 FR CELL High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|decode|reduce_or_12~0|combout
|
|
Info (332115): 5.628 0.004 RR CELL High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|decode|reduce_or_12~0~la_lab/laboutt[11]
|
|
Info (332115): 5.723 0.095 RR IC High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|decode|Select_52~3|dataf
|
|
Info (332115): 5.748 0.025 RR CELL High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|decode|Select_52~3|combout
|
|
Info (332115): 5.752 0.004 RR CELL High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|decode|Select_52~3~la_lab/laboutb[4]
|
|
Info (332115): 5.865 0.113 RR IC High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|decode|shift_left_0~20|dataf
|
|
Info (332115): 5.892 0.027 RF CELL High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|decode|shift_left_0~20|combout
|
|
Info (332115): 5.896 0.004 FF CELL High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|decode|shift_left_0~20~la_lab/laboutt[8]
|
|
Info (332115): 6.700 0.804 FF IC High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|decode|i571~1|dataf
|
|
Info (332115): 6.728 0.028 FF CELL High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|decode|i571~1|combout
|
|
Info (332115): 6.733 0.005 FF CELL High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|decode|i571~1~la_mlab/laboutb[12]
|
|
Info (332115): 6.850 0.117 FF IC High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|decode|i571~0|dataf
|
|
Info (332115): 6.875 0.025 FF CELL High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|decode|i571~0|combout
|
|
Info (332115): 6.880 0.005 FF CELL High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|decode|i571~0~la_mlab/laboutt[10]
|
|
Info (332115): 7.670 0.790 FF IC High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|issue|ibuffer|q_data_out[2][8]|asdata
|
|
Info (332115): 7.670 0.000 FF CELL High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|issue|ibuffer|q_data_out[2][8]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 4.545 4.545 latch edge time
|
|
Info (332115): 7.797 3.252 R clock network delay
|
|
Info (332115): 8.406 0.609 clock pessimism removed
|
|
Info (332115): 8.376 -0.030 clock uncertainty
|
|
Info (332115): 8.483 0.107 uTsu fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|issue|ibuffer|q_data_out[2][8]
|
|
Info (332115): Data Arrival Time : 7.670
|
|
Info (332115): Data Required Time : 8.483
|
|
Info (332115): Slack : 0.813
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 1.462
|
|
Info (20696): -to_clock [get_clocks {mem|ddr4a|ddr4a_phy_clk_l_2}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 1.462
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : mem|ddr4a_avmm_chkr|clearing
|
|
Info (332115): To Node : mem|ddr4a|ddr4a|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[0].lane_gen[2].lane_inst~phy_reg1
|
|
Info (332115): Launch Clock : mem|ddr4a|ddr4a_core_usr_clk
|
|
Info (332115): Latch Clock : mem|ddr4a|ddr4a_phy_clk_l_2
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.117 0.117 launch edge time
|
|
Info (332115): 1.863 1.746 R clock network delay
|
|
Info (332115): 1.863 0.000 mem|ddr4a_avmm_chkr|clearing
|
|
Info (332115): 1.981 0.118 RR uTco mem|ddr4a_avmm_chkr|clearing|q
|
|
Info (332115): 2.049 0.068 RR CELL High Speed mem|ddr4a_avmm_chkr|clearing~la_mlab/laboutt[13]
|
|
Info (332115): 2.754 0.705 RR IC High Speed mem|ddr4a_avmm_chkr|avm_writedata[23]~184|dataf
|
|
Info (332115): 2.782 0.028 RF CELL High Speed mem|ddr4a_avmm_chkr|avm_writedata[23]~184|combout
|
|
Info (332115): 2.786 0.004 FF CELL High Speed mem|ddr4a_avmm_chkr|avm_writedata[23]~184~la_lab/laboutb[2]
|
|
Info (332115): 3.590 0.804 FF IC High Speed mem|ddr4a|ddr4a|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[0].lane_gen[2].lane_inst|data_from_core[0]
|
|
Info (332115): 3.590 0.000 FF CELL mem|ddr4a|ddr4a|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[0].lane_gen[2].lane_inst~phy_reg1
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 3.869 3.869 latch edge time
|
|
Info (332115): 5.114 1.245 R clock network delay
|
|
Info (332115): 5.208 0.094 clock pessimism removed
|
|
Info (332115): 4.919 -0.289 clock uncertainty
|
|
Info (332115): 5.052 0.133 uTsu mem|ddr4a|ddr4a|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[0].lane_gen[2].lane_inst~phy_reg1
|
|
Info (332115): Data Arrival Time : 3.590
|
|
Info (332115): Data Required Time : 5.052
|
|
Info (332115): Slack : 1.462
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 1.470
|
|
Info (20696): -to_clock [get_clocks {mem|ddr4b|ddr4b_phy_clk_l_1}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 1.470
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : mem|ddr4b_avmm_chkr|clearing
|
|
Info (332115): To Node : mem|ddr4b|ddr4b|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[1].lane_gen[3].lane_inst~phy_reg1
|
|
Info (332115): Launch Clock : mem|ddr4a|ddr4a_core_usr_clk
|
|
Info (332115): Latch Clock : mem|ddr4b|ddr4b_phy_clk_l_1
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.117 0.117 launch edge time
|
|
Info (332115): 1.783 1.666 R clock network delay
|
|
Info (332115): 1.783 0.000 mem|ddr4b_avmm_chkr|clearing
|
|
Info (332115): 1.900 0.117 RR uTco mem|ddr4b_avmm_chkr|clearing|q
|
|
Info (332115): 1.965 0.065 RR CELL High Speed mem|ddr4b_avmm_chkr|clearing~la_lab/laboutb[17]
|
|
Info (332115): 2.748 0.783 RR IC High Speed mem|ddr4b_avmm_chkr|avm_writedata[0]~260|dataf
|
|
Info (332115): 2.775 0.027 RF CELL High Speed mem|ddr4b_avmm_chkr|avm_writedata[0]~260|combout
|
|
Info (332115): 2.779 0.004 FF CELL High Speed mem|ddr4b_avmm_chkr|avm_writedata[0]~260~la_lab/laboutb[5]
|
|
Info (332115): 3.513 0.734 FF IC High Speed mem|ddr4b|ddr4b|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[1].lane_gen[3].lane_inst|data_from_core[76]
|
|
Info (332115): 3.513 0.000 FF CELL mem|ddr4b|ddr4b|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[1].lane_gen[3].lane_inst~phy_reg1
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 3.869 3.869 latch edge time
|
|
Info (332115): 5.077 1.208 R clock network delay
|
|
Info (332115): 5.129 0.052 clock pessimism removed
|
|
Info (332115): 4.840 -0.289 clock uncertainty
|
|
Info (332115): 4.983 0.143 uTsu mem|ddr4b|ddr4b|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[1].lane_gen[3].lane_inst~phy_reg1
|
|
Info (332115): Data Arrival Time : 3.513
|
|
Info (332115): Data Required Time : 4.983
|
|
Info (332115): Slack : 1.470
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 1.471
|
|
Info (20696): -to_clock [get_clocks {mem|ddr4a|ddr4a_phy_clk_l_1}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 1.471
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : mem|ddr4a_avmm_chkr|clearing
|
|
Info (332115): To Node : mem|ddr4a|ddr4a|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[1].lane_gen[3].lane_inst~phy_reg1
|
|
Info (332115): Launch Clock : mem|ddr4a|ddr4a_core_usr_clk
|
|
Info (332115): Latch Clock : mem|ddr4a|ddr4a_phy_clk_l_1
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.117 0.117 launch edge time
|
|
Info (332115): 1.863 1.746 R clock network delay
|
|
Info (332115): 1.863 0.000 mem|ddr4a_avmm_chkr|clearing
|
|
Info (332115): 1.981 0.118 FF uTco mem|ddr4a_avmm_chkr|clearing|q
|
|
Info (332115): 2.027 0.046 FF CELL High Speed mem|ddr4a_avmm_chkr|clearing~la_mlab/laboutt[13]
|
|
Info (332115): 2.861 0.834 FF IC High Speed mem|ddr4a_avmm_chkr|avm_writedata[231]~315|dataf
|
|
Info (332115): 2.889 0.028 FR CELL High Speed mem|ddr4a_avmm_chkr|avm_writedata[231]~315|combout
|
|
Info (332115): 2.893 0.004 RR CELL High Speed mem|ddr4a_avmm_chkr|avm_writedata[231]~315~la_lab/laboutt[14]
|
|
Info (332115): 3.594 0.701 RR IC High Speed mem|ddr4a|ddr4a|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[1].lane_gen[3].lane_inst|data_from_core[83]
|
|
Info (332115): 3.594 0.000 RR CELL mem|ddr4a|ddr4a|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[1].lane_gen[3].lane_inst~phy_reg1
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 3.869 3.869 latch edge time
|
|
Info (332115): 5.118 1.249 R clock network delay
|
|
Info (332115): 5.212 0.094 clock pessimism removed
|
|
Info (332115): 4.923 -0.289 clock uncertainty
|
|
Info (332115): 5.065 0.142 uTsu mem|ddr4a|ddr4a|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[1].lane_gen[3].lane_inst~phy_reg1
|
|
Info (332115): Data Arrival Time : 3.594
|
|
Info (332115): Data Required Time : 5.065
|
|
Info (332115): Slack : 1.471
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 1.477
|
|
Info (20696): -to_clock [get_clocks {mem|ddr4a|ddr4a_core_usr_clk}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 1.477
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_green_bs|ddr4a_avmm_bridge|ddr_avmm_bridge|rsp_readdata[450]
|
|
Info (332115): To Node : fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_avalon_mem_if|c.mm_async[0].mem_async_shim|avmm_cross|rsp_fifo|mem_rtl_0|auto_generated|ram_block1a450~reg0
|
|
Info (332115): Launch Clock : mem|ddr4a|ddr4a_core_usr_clk
|
|
Info (332115): Latch Clock : mem|ddr4a|ddr4a_core_usr_clk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.117 0.117 launch edge time
|
|
Info (332115): 1.882 1.765 R clock network delay
|
|
Info (332115): 1.882 0.000 fpga_top|inst_green_bs|ddr4a_avmm_bridge|ddr_avmm_bridge|rsp_readdata[450]
|
|
Info (332115): 2.211 0.329 FF uTco fpga_top|inst_green_bs|ddr4a_avmm_bridge|ddr_avmm_bridge|rsp_readdata[450]|q
|
|
Info (332115): 2.258 0.047 FF CELL High Speed fpga_top|inst_green_bs|ddr4a_avmm_bridge|ddr_avmm_bridge|rsp_readdata[450]~la_lab/laboutb[1]
|
|
Info (332115): 4.123 1.865 FF IC High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_avalon_mem_if|c.mm_async[0].mem_async_shim|avmm_cross|rsp_fifo|mem_rtl_0|auto_generated|ram_block1a450|portadatain[0]
|
|
Info (332115): 4.123 0.000 FF CELL High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_avalon_mem_if|c.mm_async[0].mem_async_shim|avmm_cross|rsp_fifo|mem_rtl_0|auto_generated|ram_block1a450~reg0
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 3.869 3.869 latch edge time
|
|
Info (332115): 5.109 1.240 R clock network delay
|
|
Info (332115): 5.506 0.397 clock pessimism removed
|
|
Info (332115): 5.476 -0.030 clock uncertainty
|
|
Info (332115): 5.600 0.124 uTsu fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_avalon_mem_if|c.mm_async[0].mem_async_shim|avmm_cross|rsp_fifo|mem_rtl_0|auto_generated|ram_block1a450~reg0
|
|
Info (332115): Data Arrival Time : 4.123
|
|
Info (332115): Data Required Time : 5.600
|
|
Info (332115): Slack : 1.477
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 1.619
|
|
Info (20696): -to_clock [get_clocks {mem|ddr4b|ddr4b_phy_clk_l_2}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 1.619
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : mem|ddr4b_avmm_chkr|clearing
|
|
Info (332115): To Node : mem|ddr4b|ddr4b|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[0].lane_gen[0].lane_inst~phy_reg1
|
|
Info (332115): Launch Clock : mem|ddr4a|ddr4a_core_usr_clk
|
|
Info (332115): Latch Clock : mem|ddr4b|ddr4b_phy_clk_l_2
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.117 0.117 launch edge time
|
|
Info (332115): 1.783 1.666 R clock network delay
|
|
Info (332115): 1.783 0.000 mem|ddr4b_avmm_chkr|clearing
|
|
Info (332115): 1.900 0.117 FF uTco mem|ddr4b_avmm_chkr|clearing|q
|
|
Info (332115): 1.945 0.045 FF CELL High Speed mem|ddr4b_avmm_chkr|clearing~la_lab/laboutb[17]
|
|
Info (332115): 2.681 0.736 FF IC High Speed mem|ddr4b_avmm_chkr|avm_writedata[0]~9|datad
|
|
Info (332115): 2.761 0.080 FR CELL High Speed mem|ddr4b_avmm_chkr|avm_writedata[0]~9|combout
|
|
Info (332115): 2.765 0.004 RR CELL High Speed mem|ddr4b_avmm_chkr|avm_writedata[0]~9~la_lab/laboutt[12]
|
|
Info (332115): 3.354 0.589 RR IC High Speed mem|ddr4b|ddr4b|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[0].lane_gen[0].lane_inst|data_from_core[57]
|
|
Info (332115): 3.354 0.000 RR CELL mem|ddr4b|ddr4b|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[0].lane_gen[0].lane_inst~phy_reg1
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 3.869 3.869 latch edge time
|
|
Info (332115): 5.080 1.211 R clock network delay
|
|
Info (332115): 5.132 0.052 clock pessimism removed
|
|
Info (332115): 4.843 -0.289 clock uncertainty
|
|
Info (332115): 4.973 0.130 uTsu mem|ddr4b|ddr4b|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[0].lane_gen[0].lane_inst~phy_reg1
|
|
Info (332115): Data Arrival Time : 3.354
|
|
Info (332115): Data Required Time : 4.973
|
|
Info (332115): Slack : 1.619
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 1.635
|
|
Info (20696): -to_clock [get_clocks {mem|ddr4b|ddr4b_phy_clk_l_0}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 1.635
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : mem|ddr4b_bridge|ddr_avmm_bridge|cmd_burstcount[6]
|
|
Info (332115): To Node : mem|ddr4b|ddr4b|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[1].tile_ctrl_inst~hmc_reg1
|
|
Info (332115): Launch Clock : mem|ddr4a|ddr4a_core_usr_clk
|
|
Info (332115): Latch Clock : mem|ddr4b|ddr4b_phy_clk_l_0
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.117 0.117 launch edge time
|
|
Info (332115): 1.788 1.671 R clock network delay
|
|
Info (332115): 1.788 0.000 mem|ddr4b_bridge|ddr_avmm_bridge|cmd_burstcount[6]
|
|
Info (332115): 1.907 0.119 FF uTco mem|ddr4b_bridge|ddr_avmm_bridge|cmd_burstcount[6]|q
|
|
Info (332115): 1.955 0.048 FF CELL High Speed mem|ddr4b_bridge|ddr_avmm_bridge|cmd_burstcount[6]~la_mlab/laboutb[5]
|
|
Info (332115): 2.239 0.284 FF IC High Speed mem|ddr4b_avmm_chkr|LessThan_0~0|datab
|
|
Info (332115): 2.359 0.120 FR CELL High Speed mem|ddr4b_avmm_chkr|LessThan_0~0|combout
|
|
Info (332115): 2.364 0.005 RR CELL High Speed mem|ddr4b_avmm_chkr|LessThan_0~0~la_mlab/laboutt[17]
|
|
Info (332115): 2.546 0.182 RR IC High Speed mem|ddr4b_avmm_chkr|start_error|datad
|
|
Info (332115): 2.621 0.075 RF CELL High Speed mem|ddr4b_avmm_chkr|start_error|combout
|
|
Info (332115): 2.625 0.004 FF CELL High Speed mem|ddr4b_avmm_chkr|start_error~la_lab/laboutt[0]
|
|
Info (332115): 2.816 0.191 FF IC High Speed mem|ddr4b_emif_read_mux~0|datad
|
|
Info (332115): 2.886 0.070 FF CELL High Speed mem|ddr4b_emif_read_mux~0|combout
|
|
Info (332115): 2.890 0.004 FF CELL High Speed mem|ddr4b_emif_read_mux~0~la_lab/laboutt[7]
|
|
Info (332115): 3.289 0.399 FF IC High Speed mem|ddr4b|ddr4b|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[1].tile_ctrl_inst|core2ctl_avl0[0]
|
|
Info (332115): 3.289 0.000 FF CELL mem|ddr4b|ddr4b|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[1].tile_ctrl_inst~hmc_reg1
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 3.869 3.869 latch edge time
|
|
Info (332115): 5.094 1.225 R clock network delay
|
|
Info (332115): 5.146 0.052 clock pessimism removed
|
|
Info (332115): 4.857 -0.289 clock uncertainty
|
|
Info (332115): 4.924 0.067 uTsu mem|ddr4b|ddr4b|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[1].tile_ctrl_inst~hmc_reg1
|
|
Info (332115): Data Arrival Time : 3.289
|
|
Info (332115): Data Required Time : 4.924
|
|
Info (332115): Slack : 1.635
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 1.643
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|wys~CORE_CLK_OUT}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 1.643
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_sriov_2.sriov2.sriov_bridge|altpcie_pcie_sriov2_top_inst|altpcie_sriov2_tx_data_bridge_inst|poisoned_req_sent_vf_o
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_sriov_2.sriov2.sriov_bridge|altpcie_pcie_sriov2_top_inst|altpcie_sriov2_cfg_dataflow_inst|gen_vf_regset_pf0.altpcie_sriov2_cfg_vf_regset_pf0_inst|vf_pci_status_reg_mod|altpcie_sriov2_cfg_vf_poisoned_req_sent_error_status_fifo|write_ptr[1]~DUPLICATE
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|wys~CORE_CLK_OUT
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|wys~CORE_CLK_OUT
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 5.188 5.188 R clock network delay
|
|
Info (332115): 5.188 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_sriov_2.sriov2.sriov_bridge|altpcie_pcie_sriov2_top_inst|altpcie_sriov2_tx_data_bridge_inst|poisoned_req_sent_vf_o
|
|
Info (332115): 5.308 0.120 FF uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_sriov_2.sriov2.sriov_bridge|altpcie_pcie_sriov2_top_inst|altpcie_sriov2_tx_data_bridge_inst|poisoned_req_sent_vf_o|q
|
|
Info (332115): 5.350 0.042 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_sriov_2.sriov2.sriov_bridge|altpcie_pcie_sriov2_top_inst|altpcie_sriov2_tx_data_bridge_inst|poisoned_req_sent_vf_o~la_mlab/laboutb[5]
|
|
Info (332115): 7.397 2.047 FF IC High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_sriov_2.sriov2.sriov_bridge|altpcie_pcie_sriov2_top_inst|altpcie_sriov2_cfg_dataflow_inst|gen_vf_regset_pf0.altpcie_sriov2_cfg_vf_regset_pf0_inst|vf_pci_status_reg_mod|altpcie_sriov2_cfg_vf_poisoned_req_sent_error_status_fifo|write_ptr[1]~0|dataf
|
|
Info (332115): 7.424 0.027 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_sriov_2.sriov2.sriov_bridge|altpcie_pcie_sriov2_top_inst|altpcie_sriov2_cfg_dataflow_inst|gen_vf_regset_pf0.altpcie_sriov2_cfg_vf_regset_pf0_inst|vf_pci_status_reg_mod|altpcie_sriov2_cfg_vf_poisoned_req_sent_error_status_fifo|write_ptr[1]~0|combout
|
|
Info (332115): 7.428 0.004 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_sriov_2.sriov2.sriov_bridge|altpcie_pcie_sriov2_top_inst|altpcie_sriov2_cfg_dataflow_inst|gen_vf_regset_pf0.altpcie_sriov2_cfg_vf_regset_pf0_inst|vf_pci_status_reg_mod|altpcie_sriov2_cfg_vf_poisoned_req_sent_error_status_fifo|write_ptr[1]~0~la_lab/laboutb[0]
|
|
Info (332115): 7.523 0.095 FF IC High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_sriov_2.sriov2.sriov_bridge|altpcie_pcie_sriov2_top_inst|altpcie_sriov2_cfg_dataflow_inst|gen_vf_regset_pf0.altpcie_sriov2_cfg_vf_regset_pf0_inst|vf_pci_status_reg_mod|altpcie_sriov2_cfg_vf_poisoned_req_sent_error_status_fifo|write_ptr[1]~DUPLICATE|ena
|
|
Info (332115): 7.523 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_sriov_2.sriov2.sriov_bridge|altpcie_pcie_sriov2_top_inst|altpcie_sriov2_cfg_dataflow_inst|gen_vf_regset_pf0.altpcie_sriov2_cfg_vf_regset_pf0_inst|vf_pci_status_reg_mod|altpcie_sriov2_cfg_vf_poisoned_req_sent_error_status_fifo|write_ptr[1]~DUPLICATE
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 4.000 4.000 latch edge time
|
|
Info (332115): 8.432 4.432 R clock network delay
|
|
Info (332115): 9.141 0.709 clock pessimism removed
|
|
Info (332115): 9.166 0.025 uTsu fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_sriov_2.sriov2.sriov_bridge|altpcie_pcie_sriov2_top_inst|altpcie_sriov2_cfg_dataflow_inst|gen_vf_regset_pf0.altpcie_sriov2_cfg_vf_regset_pf0_inst|vf_pci_status_reg_mod|altpcie_sriov2_cfg_vf_poisoned_req_sent_error_status_fifo|write_ptr[1]~DUPLICATE
|
|
Info (332115): Data Arrival Time : 7.523
|
|
Info (332115): Data Required Time : 9.166
|
|
Info (332115): Slack : 1.643
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 1.903
|
|
Info (20696): -to_clock [get_clocks {mem|ddr4a|ddr4a_phy_clk_l_0}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 1.903
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : mem|ddr4a_bridge|ddr_avmm_bridge|cmd_burstcount[5]
|
|
Info (332115): To Node : mem|ddr4a|ddr4a|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[1].tile_ctrl_inst~hmc_reg1
|
|
Info (332115): Launch Clock : mem|ddr4a|ddr4a_core_usr_clk
|
|
Info (332115): Latch Clock : mem|ddr4a|ddr4a_phy_clk_l_0
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.117 0.117 launch edge time
|
|
Info (332115): 1.866 1.749 R clock network delay
|
|
Info (332115): 1.866 0.000 mem|ddr4a_bridge|ddr_avmm_bridge|cmd_burstcount[5]
|
|
Info (332115): 1.990 0.124 FF uTco mem|ddr4a_bridge|ddr_avmm_bridge|cmd_burstcount[5]|q
|
|
Info (332115): 2.060 0.070 FF CELL High Speed mem|ddr4a_bridge|ddr_avmm_bridge|cmd_burstcount[5]~la_mlab/laboutb[15]
|
|
Info (332115): 2.298 0.238 FF IC High Speed mem|ddr4a_avmm_chkr|LessThan_0~0|datab
|
|
Info (332115): 2.422 0.124 FR CELL High Speed mem|ddr4a_avmm_chkr|LessThan_0~0|combout
|
|
Info (332115): 2.426 0.004 RR CELL High Speed mem|ddr4a_avmm_chkr|LessThan_0~0~la_lab/laboutb[6]
|
|
Info (332115): 2.536 0.110 RR IC High Speed mem|ddr4a_avmm_chkr|start_error|datac
|
|
Info (332115): 2.623 0.087 RF CELL High Speed mem|ddr4a_avmm_chkr|start_error|combout
|
|
Info (332115): 2.628 0.005 FF CELL High Speed mem|ddr4a_avmm_chkr|start_error~la_mlab/laboutt[6]
|
|
Info (332115): 2.725 0.097 FF IC High Speed mem|ddr4a_avmm_chkr|avm_write~1|datae
|
|
Info (332115): 2.783 0.058 FF CELL High Speed mem|ddr4a_avmm_chkr|avm_write~1|combout
|
|
Info (332115): 2.788 0.005 FF CELL High Speed mem|ddr4a_avmm_chkr|avm_write~1~la_mlab/laboutt[9]
|
|
Info (332115): 3.431 0.643 FF IC High Speed mem|ddr4a|ddr4a|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[1].tile_ctrl_inst|core2ctl_avl0[1]
|
|
Info (332115): 3.431 0.000 FF CELL mem|ddr4a|ddr4a|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[1].tile_ctrl_inst~hmc_reg1
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 3.869 3.869 latch edge time
|
|
Info (332115): 5.135 1.266 R clock network delay
|
|
Info (332115): 5.410 0.275 clock pessimism removed
|
|
Info (332115): 5.218 -0.192 clock uncertainty
|
|
Info (332115): 5.334 0.116 uTsu mem|ddr4a|ddr4a|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[1].tile_ctrl_inst~hmc_reg1
|
|
Info (332115): Data Arrival Time : 3.431
|
|
Info (332115): Data Required Time : 5.334
|
|
Info (332115): Slack : 1.903
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 1.970
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|pld_clk}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 1.970
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_sriov_2.sriov2.sriov_bridge|altpcie_pcie_sriov2_top_inst|altpcie_sriov2_tx_data_bridge_inst|TxStData_hip_o[209]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~pld_clk.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|wys~CORE_CLK_OUT
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|pld_clk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 5.148 5.148 R clock network delay
|
|
Info (332115): 5.148 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_sriov_2.sriov2.sriov_bridge|altpcie_pcie_sriov2_top_inst|altpcie_sriov2_tx_data_bridge_inst|TxStData_hip_o[209]
|
|
Info (332115): 5.278 0.130 FF uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_sriov_2.sriov2.sriov_bridge|altpcie_pcie_sriov2_top_inst|altpcie_sriov2_tx_data_bridge_inst|TxStData_hip_o[209]|q
|
|
Info (332115): 5.330 0.052 FF CELL Low Power fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_sriov_2.sriov2.sriov_bridge|altpcie_pcie_sriov2_top_inst|altpcie_sriov2_tx_data_bridge_inst|TxStData_hip_o[209]~la_mlab/laboutt[18]
|
|
Info (332115): 7.411 2.081 FF IC Mixed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|tx_st_data[209]
|
|
Info (332115): 7.411 0.000 FF CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~pld_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 4.000 4.000 latch edge time
|
|
Info (332115): 8.506 4.506 R clock network delay
|
|
Info (332115): 9.215 0.709 clock pessimism removed
|
|
Info (332115): 9.196 -0.019 clock uncertainty
|
|
Info (332115): 9.381 0.185 uTsu fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~pld_clk.reg
|
|
Info (332115): Data Arrival Time : 7.411
|
|
Info (332115): Data Required Time : 9.381
|
|
Info (332115): Slack : 1.970
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 2.076
|
|
Info (20696): -to_clock [get_clocks {u0|dcp_iopll|dcp_iopll|clk1x}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 2.076
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|wrptr_g[2]
|
|
Info (332115): To Node : fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|fifo_ram|ram_block7a264~reg0
|
|
Info (332115): Launch Clock : u0|dcp_iopll|dcp_iopll|clk1x
|
|
Info (332115): Latch Clock : u0|dcp_iopll|dcp_iopll|clk1x
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 5.551 5.551 R clock network delay
|
|
Info (332115): 5.551 0.000 fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|wrptr_g[2]
|
|
Info (332115): 5.671 0.120 FF uTco fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|wrptr_g[2]|q
|
|
Info (332115): 5.713 0.042 FF CELL High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|wrptr_g[2]~la_mlab/laboutt[10]
|
|
Info (332115): 8.327 2.614 FF IC High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|fifo_ram|ram_block7a264|portaaddr[2]
|
|
Info (332115): 8.327 0.000 FF CELL High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|fifo_ram|ram_block7a264~reg0
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 5.000 5.000 latch edge time
|
|
Info (332115): 9.762 4.762 R clock network delay
|
|
Info (332115): 10.417 0.655 clock pessimism removed
|
|
Info (332115): 10.267 -0.150 clock uncertainty
|
|
Info (332115): 10.403 0.136 uTsu fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|fifo_ram|ram_block7a264~reg0
|
|
Info (332115): Data Arrival Time : 8.327
|
|
Info (332115): Data Required Time : 10.403
|
|
Info (332115): Slack : 2.076
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 2.160
|
|
Info (20696): -to_clock [get_clocks {u0|dcp_iopll|dcp_iopll|clk100}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 2.160
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_bitstream_host|alt_pr_bitstream_controller_v2|pr_data_reg[3]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_bitstream_host|alt_pr_bitstream_controller_v2|pr_data_reg2[3]
|
|
Info (332115): Launch Clock : u0|dcp_iopll|dcp_iopll|clk100
|
|
Info (332115): Latch Clock : u0|dcp_iopll|dcp_iopll|clk100 (INVERTED)
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 5.606 5.606 R clock network delay
|
|
Info (332115): 5.606 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_bitstream_host|alt_pr_bitstream_controller_v2|pr_data_reg[3]
|
|
Info (332115): 5.724 0.118 FF uTco fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_bitstream_host|alt_pr_bitstream_controller_v2|pr_data_reg[3]|q
|
|
Info (332115): 5.769 0.045 FF CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_bitstream_host|alt_pr_bitstream_controller_v2|pr_data_reg[3]~la_lab/laboutb[2]
|
|
Info (332115): 8.319 2.550 FF IC Mixed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_bitstream_host|alt_pr_bitstream_controller_v2|pr_data_reg2[3]|d
|
|
Info (332115): 8.319 0.000 FF CELL Low Power fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_bitstream_host|alt_pr_bitstream_controller_v2|pr_data_reg2[3]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 5.000 5.000 latch edge time
|
|
Info (332115): 9.840 4.840 F clock network delay
|
|
Info (332115): 10.504 0.664 clock pessimism removed
|
|
Info (332115): 10.334 -0.170 clock uncertainty
|
|
Info (332115): 10.479 0.145 uTsu fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_bitstream_host|alt_pr_bitstream_controller_v2|pr_data_reg2[3]
|
|
Info (332115): Data Arrival Time : 8.319
|
|
Info (332115): Data Required Time : 10.479
|
|
Info (332115): Slack : 2.160
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 2.690
|
|
Info (20696): -to_clock [get_clocks {ETH_RefClk}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 2.690
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[6].ct0|dout_r[5]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[6].sn0|ff_launch[0]
|
|
Info (332115): Launch Clock : ETH_RefClk
|
|
Info (332115): Latch Clock : ETH_RefClk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 3.436 3.436 R clock network delay
|
|
Info (332115): 3.436 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[6].ct0|dout_r[5]
|
|
Info (332115): 3.603 0.167 RR uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[6].ct0|dout_r[5]|q
|
|
Info (332115): 3.668 0.065 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[6].ct0|dout_r[5]~la_lab/laboutb[5]
|
|
Info (332115): 3.814 0.146 RR IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[6].sn0|ff_launch[0]|d
|
|
Info (332115): 3.814 0.000 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[6].sn0|ff_launch[0]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 3.103 3.103 latch edge time
|
|
Info (332115): 6.167 3.064 R clock network delay
|
|
Info (332115): 6.519 0.352 clock pessimism removed
|
|
Info (332115): 6.479 -0.040 clock uncertainty
|
|
Info (332115): 6.504 0.025 uTsu fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[6].sn0|ff_launch[0]
|
|
Info (332115): Data Arrival Time : 3.814
|
|
Info (332115): Data Required Time : 6.504
|
|
Info (332115): Slack : 2.690
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 2.696
|
|
Info (20696): -to_clock [get_clocks {hssi_pll_r_0_outclk0}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 2.696
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[2].ct0|dout_r[4]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[2].ct0|dout_r[5]
|
|
Info (332115): Launch Clock : hssi_pll_r_0_outclk0
|
|
Info (332115): Latch Clock : hssi_pll_r_0_outclk0
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 2.871 2.871 R clock network delay
|
|
Info (332115): 2.871 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[2].ct0|dout_r[4]
|
|
Info (332115): 3.057 0.186 RR uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[2].ct0|dout_r[4]|q
|
|
Info (332115): 3.144 0.087 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[2].ct0|dout_r[4]~la_lab/laboutt[12]
|
|
Info (332115): 3.407 0.263 RR IC Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[2].ct0|t5|dout|dataf
|
|
Info (332115): 3.434 0.027 RF CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[2].ct0|t5|dout|combout
|
|
Info (332115): 3.434 0.000 FF CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[2].ct0|dout_r[5]|d
|
|
Info (332115): 3.434 0.000 FF CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[2].ct0|dout_r[5]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 3.200 3.200 latch edge time
|
|
Info (332115): 5.774 2.574 R clock network delay
|
|
Info (332115): 6.070 0.296 clock pessimism removed
|
|
Info (332115): 5.960 -0.110 clock uncertainty
|
|
Info (332115): 6.130 0.170 uTsu fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[2].ct0|dout_r[5]
|
|
Info (332115): Data Arrival Time : 3.434
|
|
Info (332115): Data Required Time : 6.130
|
|
Info (332115): Slack : 2.696
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 2.739
|
|
Info (20696): -to_clock [get_clocks {hssi_pll_t_outclk0}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 2.739
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[3].ct0|dout_r[5]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[3].sn0|ff_launch[0]
|
|
Info (332115): Launch Clock : hssi_pll_t_outclk0
|
|
Info (332115): Latch Clock : hssi_pll_t_outclk0
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 2.698 2.698 R clock network delay
|
|
Info (332115): 2.698 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[3].ct0|dout_r[5]
|
|
Info (332115): 2.867 0.169 RR uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[3].ct0|dout_r[5]|q
|
|
Info (332115): 2.953 0.086 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[3].ct0|dout_r[5]~la_lab/laboutt[8]
|
|
Info (332115): 3.147 0.194 RR IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[3].sn0|ff_launch[0]|asdata
|
|
Info (332115): 3.147 0.000 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[3].sn0|ff_launch[0]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 3.200 3.200 latch edge time
|
|
Info (332115): 5.625 2.425 R clock network delay
|
|
Info (332115): 5.879 0.254 clock pessimism removed
|
|
Info (332115): 5.769 -0.110 clock uncertainty
|
|
Info (332115): 5.886 0.117 uTsu fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[3].sn0|ff_launch[0]
|
|
Info (332115): Data Arrival Time : 3.147
|
|
Info (332115): Data Required Time : 5.886
|
|
Info (332115): Slack : 2.739
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 2.958
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_clk}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 2.958
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_prbs_done_sync|resync_chains[0].sync_r[1]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_snapshot[1]
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_clk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_clk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 3.852 3.852 R clock network delay
|
|
Info (332115): 3.852 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_prbs_done_sync|resync_chains[0].sync_r[1]
|
|
Info (332115): 3.971 0.119 FF uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_prbs_done_sync|resync_chains[0].sync_r[1]|q
|
|
Info (332115): 4.037 0.066 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_prbs_done_sync|resync_chains[0].sync_r[1]~la_lab/laboutb[3]
|
|
Info (332115): 4.410 0.373 FF IC High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_snapshot[1]~0|datac
|
|
Info (332115): 4.487 0.077 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_snapshot[1]~0|combout
|
|
Info (332115): 4.491 0.004 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_snapshot[1]~0~la_lab/laboutt[7]
|
|
Info (332115): 4.738 0.247 FF IC High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_snapshot[1]|ena
|
|
Info (332115): 4.738 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_snapshot[1]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 3.878 3.878 latch edge time
|
|
Info (332115): 6.812 2.934 R clock network delay
|
|
Info (332115): 7.700 0.888 clock pessimism removed
|
|
Info (332115): 7.670 -0.030 clock uncertainty
|
|
Info (332115): 7.696 0.026 uTsu fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_snapshot[1]
|
|
Info (332115): Data Arrival Time : 4.738
|
|
Info (332115): Data Required Time : 7.696
|
|
Info (332115): Slack : 2.958
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 2.993
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|rx_pma_clk}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 2.993
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_prbs_reset_sync|resync_chains[0].sync_r[2]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_snapshot[6]
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|rx_pma_clk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|rx_pma_clk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 3.838 3.838 R clock network delay
|
|
Info (332115): 3.838 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_prbs_reset_sync|resync_chains[0].sync_r[2]
|
|
Info (332115): 3.956 0.118 RR uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_prbs_reset_sync|resync_chains[0].sync_r[2]|q
|
|
Info (332115): 4.014 0.058 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_prbs_reset_sync|resync_chains[0].sync_r[2]~la_lab/laboutt[14]
|
|
Info (332115): 4.288 0.274 RR IC High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_snapshot[0]~0|dataa
|
|
Info (332115): 4.412 0.124 RF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_snapshot[0]~0|combout
|
|
Info (332115): 4.416 0.004 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_snapshot[0]~0~la_lab/laboutt[8]
|
|
Info (332115): 4.711 0.295 FF IC High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_snapshot[6]|ena
|
|
Info (332115): 4.711 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_snapshot[6]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 3.878 3.878 latch edge time
|
|
Info (332115): 6.816 2.938 R clock network delay
|
|
Info (332115): 7.706 0.890 clock pessimism removed
|
|
Info (332115): 7.676 -0.030 clock uncertainty
|
|
Info (332115): 7.704 0.028 uTsu fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_snapshot[6]
|
|
Info (332115): Data Arrival Time : 4.711
|
|
Info (332115): Data Required Time : 7.704
|
|
Info (332115): Slack : 2.993
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 3.044
|
|
Info (20696): -to_clock [get_clocks {DDR4_RefClk}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 3.044
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|use_counter_lock.counter_lock_gen_master.cpa_count_to_lock[1]
|
|
Info (332115): To Node : mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|use_counter_lock.counter_lock_gen_master.cpa_count_to_lock[16]~LRTM_3
|
|
Info (332115): Launch Clock : DDR4_RefClk
|
|
Info (332115): Latch Clock : DDR4_RefClk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 2.537 2.537 R clock network delay
|
|
Info (332115): 2.537 0.000 mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|use_counter_lock.counter_lock_gen_master.cpa_count_to_lock[1]
|
|
Info (332115): 2.656 0.119 RR uTco mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|use_counter_lock.counter_lock_gen_master.cpa_count_to_lock[1]|q
|
|
Info (332115): 2.717 0.061 RR CELL High Speed mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|use_counter_lock.counter_lock_gen_master.cpa_count_to_lock[1]~la_lab/laboutt[1]
|
|
Info (332115): 2.805 0.088 RR IC High Speed mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|add_0~61|datac
|
|
Info (332115): 3.116 0.311 RR CELL High Speed mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|add_0~21|cin
|
|
Info (332115): 3.132 0.016 RF CELL High Speed mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|add_0~17|cout
|
|
Info (332115): 3.132 0.000 FF CELL High Speed mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|add_0~13|cin
|
|
Info (332115): 3.148 0.016 FR CELL High Speed mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|add_0~9|cout
|
|
Info (332115): 3.148 0.000 RR CELL High Speed mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|add_0~5|cin
|
|
Info (332115): 3.252 0.104 RR CELL High Speed mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|add_0~1|sumout
|
|
Info (332115): 3.256 0.004 RR CELL High Speed mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|add_0~1~la_lab/laboutb[10]
|
|
Info (332115): 3.339 0.083 RR IC High Speed mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|use_counter_lock.counter_lock_gen_master.cpa_count_to_lock[16]~LRTM_3|d
|
|
Info (332115): 3.339 0.000 RR CELL High Speed mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|use_counter_lock.counter_lock_gen_master.cpa_count_to_lock[16]~LRTM_3
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 3.752 3.752 latch edge time
|
|
Info (332115): 6.095 2.343 R clock network delay
|
|
Info (332115): 6.278 0.183 clock pessimism removed
|
|
Info (332115): 6.248 -0.030 clock uncertainty
|
|
Info (332115): 6.383 0.135 uTsu mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|use_counter_lock.counter_lock_gen_master.cpa_count_to_lock[16]~LRTM_3
|
|
Info (332115): Data Arrival Time : 3.339
|
|
Info (332115): Data Required Time : 6.383
|
|
Info (332115): Slack : 3.044
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 3.099
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|rx_pma_clk}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 3.099
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_prbs_reset_sync|resync_chains[0].sync_r[2]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_snapshot[1]
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|rx_pma_clk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|rx_pma_clk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 3.764 3.764 R clock network delay
|
|
Info (332115): 3.764 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_prbs_reset_sync|resync_chains[0].sync_r[2]
|
|
Info (332115): 3.889 0.125 RR uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_prbs_reset_sync|resync_chains[0].sync_r[2]|q
|
|
Info (332115): 3.978 0.089 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_prbs_reset_sync|resync_chains[0].sync_r[2]~la_mlab/laboutb[12]
|
|
Info (332115): 4.338 0.360 RR IC High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_snapshot[5]~0|datad
|
|
Info (332115): 4.409 0.071 RF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_snapshot[5]~0|combout
|
|
Info (332115): 4.413 0.004 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_snapshot[5]~0~la_lab/laboutb[0]
|
|
Info (332115): 4.511 0.098 FF IC High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_snapshot[1]|ena
|
|
Info (332115): 4.511 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_snapshot[1]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 3.878 3.878 latch edge time
|
|
Info (332115): 6.721 2.843 R clock network delay
|
|
Info (332115): 7.613 0.892 clock pessimism removed
|
|
Info (332115): 7.583 -0.030 clock uncertainty
|
|
Info (332115): 7.610 0.027 uTsu fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_snapshot[1]
|
|
Info (332115): Data Arrival Time : 4.511
|
|
Info (332115): Data Required Time : 7.610
|
|
Info (332115): Slack : 3.099
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 3.141
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|rx_pma_clk}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 3.141
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_prbs_err_sync|resync_chains[0].sync_r[1]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_count[0]
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|rx_pma_clk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|rx_pma_clk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 3.830 3.830 R clock network delay
|
|
Info (332115): 3.830 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_prbs_err_sync|resync_chains[0].sync_r[1]
|
|
Info (332115): 3.947 0.117 RR uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_prbs_err_sync|resync_chains[0].sync_r[1]|q
|
|
Info (332115): 4.005 0.058 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_prbs_err_sync|resync_chains[0].sync_r[1]~la_mlab/laboutt[14]
|
|
Info (332115): 4.222 0.217 RR IC High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|add_2~1|datab
|
|
Info (332115): 4.476 0.254 RF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|add_2~1|sumout
|
|
Info (332115): 4.480 0.004 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|add_2~1~la_lab/laboutb[1]
|
|
Info (332115): 4.612 0.132 FF IC High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|i58~0|datad
|
|
Info (332115): 4.702 0.090 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|i58~0|combout
|
|
Info (332115): 4.702 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_count[0]|d
|
|
Info (332115): 4.702 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_count[0]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 3.878 3.878 latch edge time
|
|
Info (332115): 6.792 2.914 R clock network delay
|
|
Info (332115): 7.708 0.916 clock pessimism removed
|
|
Info (332115): 7.678 -0.030 clock uncertainty
|
|
Info (332115): 7.843 0.165 uTsu fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_count[0]
|
|
Info (332115): Data Arrival Time : 4.702
|
|
Info (332115): Data Required Time : 7.843
|
|
Info (332115): Slack : 3.141
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 3.180
|
|
Info (20696): -to_clock [get_clocks {mem|ddr4a|ddr4a_core_cal_slave_clk}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 3.180
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : mem|ddr4b|ddr4b|arch|arch_inst|io_aux_inst|io_aux~soft_ram_reg
|
|
Info (332115): To Node : mem|ddr4b|ddr4b|cal_slave_component|ioaux_master_bridge|cmd_writedata[1]
|
|
Info (332115): Launch Clock : mem|ddr4a|ddr4a_core_cal_slave_clk
|
|
Info (332115): Latch Clock : mem|ddr4a|ddr4a_core_cal_slave_clk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 3.947 3.947 R clock network delay
|
|
Info (332115): 3.947 0.000 mem|ddr4b|ddr4b|arch|arch_inst|io_aux_inst|io_aux~soft_ram_reg
|
|
Info (332115): 4.355 0.408 FF uTco mem|ddr4b|ddr4b|arch|arch_inst|io_aux_inst|io_aux|soft_ram_write_data[1]
|
|
Info (332115): 7.100 2.745 FF IC High Speed mem|ddr4b|ddr4b|cal_slave_component|ioaux_master_bridge|cmd_writedata[1]|asdata
|
|
Info (332115): 7.100 0.000 FF CELL High Speed mem|ddr4b|ddr4b|cal_slave_component|ioaux_master_bridge|cmd_writedata[1]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 6.566 6.566 latch edge time
|
|
Info (332115): 9.800 3.234 R clock network delay
|
|
Info (332115): 10.244 0.444 clock pessimism removed
|
|
Info (332115): 10.194 -0.050 clock uncertainty
|
|
Info (332115): 10.280 0.086 uTsu mem|ddr4b|ddr4b|cal_slave_component|ioaux_master_bridge|cmd_writedata[1]
|
|
Info (332115): Data Arrival Time : 7.100
|
|
Info (332115): Data Required Time : 10.280
|
|
Info (332115): Slack : 3.180
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 3.325
|
|
Info (20696): -to_clock [get_clocks {hssi_pll_t_outclk1}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 3.325
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[1].ct0|dout_r[1]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[1].ct0|dout_r[3]
|
|
Info (332115): Launch Clock : hssi_pll_t_outclk1
|
|
Info (332115): Latch Clock : hssi_pll_t_outclk1
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 2.674 2.674 R clock network delay
|
|
Info (332115): 2.674 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[1].ct0|dout_r[1]
|
|
Info (332115): 2.822 0.148 RR uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[1].ct0|dout_r[1]|q
|
|
Info (332115): 2.904 0.082 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[1].ct0|dout_r[1]~la_mlab/laboutt[8]
|
|
Info (332115): 3.121 0.217 RR IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[1].ct0|t3|dout|dataf
|
|
Info (332115): 3.148 0.027 RF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[1].ct0|t3|dout|combout
|
|
Info (332115): 3.148 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[1].ct0|dout_r[3]|d
|
|
Info (332115): 3.148 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[1].ct0|dout_r[3]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 3.800 3.800 latch edge time
|
|
Info (332115): 6.211 2.411 R clock network delay
|
|
Info (332115): 6.474 0.263 clock pessimism removed
|
|
Info (332115): 6.364 -0.110 clock uncertainty
|
|
Info (332115): 6.473 0.109 uTsu fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[1].ct0|dout_r[3]
|
|
Info (332115): Data Arrival Time : 3.148
|
|
Info (332115): Data Required Time : 6.473
|
|
Info (332115): Slack : 3.325
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 3.331
|
|
Info (20696): -to_clock [get_clocks {hssi_pll_r_0_outclk1}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 3.331
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[0].ct0|dout_r[2]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[0].ct0|dout_r[4]
|
|
Info (332115): Launch Clock : hssi_pll_r_0_outclk1
|
|
Info (332115): Latch Clock : hssi_pll_r_0_outclk1
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 2.861 2.861 R clock network delay
|
|
Info (332115): 2.861 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[0].ct0|dout_r[2]
|
|
Info (332115): 3.041 0.180 RR uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[0].ct0|dout_r[2]|q
|
|
Info (332115): 3.132 0.091 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[0].ct0|dout_r[2]~la_lab/laboutt[19]
|
|
Info (332115): 3.216 0.084 RR IC Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[0].ct0|t4|dout|dataa
|
|
Info (332115): 3.355 0.139 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[0].ct0|t4|dout|combout
|
|
Info (332115): 3.355 0.000 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[0].ct0|dout_r[4]|d
|
|
Info (332115): 3.355 0.000 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[0].ct0|dout_r[4]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 3.800 3.800 latch edge time
|
|
Info (332115): 6.360 2.560 R clock network delay
|
|
Info (332115): 6.661 0.301 clock pessimism removed
|
|
Info (332115): 6.551 -0.110 clock uncertainty
|
|
Info (332115): 6.686 0.135 uTsu fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[0].ct0|dout_r[4]
|
|
Info (332115): Data Arrival Time : 3.355
|
|
Info (332115): Data Required Time : 6.686
|
|
Info (332115): Slack : 3.331
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 3.723
|
|
Info (20696): -to_clock [get_clocks {vl_qph_user_clk_clkpsc_clk1}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 3.723
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[0]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[1]
|
|
Info (332115): Launch Clock : vl_qph_user_clk_clkpsc_clk1
|
|
Info (332115): Latch Clock : vl_qph_user_clk_clkpsc_clk1
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 4.156 4.156 R clock network delay
|
|
Info (332115): 4.156 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[0]
|
|
Info (332115): 4.282 0.126 FF uTco fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[0]|q
|
|
Info (332115): 4.324 0.042 FF CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[0]~la_mlab/laboutb[9]
|
|
Info (332115): 4.971 0.647 FF IC Mixed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[1]~2|dataa
|
|
Info (332115): 5.090 0.119 FR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[1]~2|combout
|
|
Info (332115): 5.090 0.000 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[1]|d
|
|
Info (332115): 5.090 0.000 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[1]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 4.545 4.545 latch edge time
|
|
Info (332115): 8.029 3.484 R clock network delay
|
|
Info (332115): 8.699 0.670 clock pessimism removed
|
|
Info (332115): 8.669 -0.030 clock uncertainty
|
|
Info (332115): 8.813 0.144 uTsu fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[1]
|
|
Info (332115): Data Arrival Time : 5.090
|
|
Info (332115): Data Required Time : 8.813
|
|
Info (332115): Slack : 3.723
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 4.474
|
|
Info (20696): -to_clock [get_clocks {PCIE_REFCLK}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 4.474
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|sm_state.SM_POWERUP
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|timer_counter[20]
|
|
Info (332115): Launch Clock : PCIE_REFCLK
|
|
Info (332115): Latch Clock : PCIE_REFCLK
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 3.467 3.467 R clock network delay
|
|
Info (332115): 3.467 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|sm_state.SM_POWERUP
|
|
Info (332115): 3.586 0.119 FF uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|sm_state.SM_POWERUP|q
|
|
Info (332115): 3.628 0.042 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|sm_state.SM_POWERUP~la_mlab/laboutt[13]
|
|
Info (332115): 6.472 2.844 FF IC Mixed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|reduce_or_14|datac
|
|
Info (332115): 6.556 0.084 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|reduce_or_14|combout
|
|
Info (332115): 6.561 0.005 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|reduce_or_14~la_mlab/laboutb[16]
|
|
Info (332115): 8.904 2.343 FF IC Mixed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|timer_counter[20]|ena
|
|
Info (332115): 8.904 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|timer_counter[20]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 10.000 10.000 latch edge time
|
|
Info (332115): 13.134 3.134 R clock network delay
|
|
Info (332115): 13.393 0.259 clock pessimism removed
|
|
Info (332115): 13.353 -0.040 clock uncertainty
|
|
Info (332115): 13.378 0.025 uTsu fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|timer_counter[20]
|
|
Info (332115): Data Arrival Time : 8.904
|
|
Info (332115): Data Required Time : 13.378
|
|
Info (332115): Slack : 4.474
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 4.698
|
|
Info (20696): -to_clock [get_clocks {SYS_RefClk}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 4.698
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_cb_host|alt_pr_cb_controller_v2|freeze_reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi.f2a_prmgmt_freeze
|
|
Info (332115): Launch Clock : u0|dcp_iopll|dcp_iopll|clk100
|
|
Info (332115): Latch Clock : SYS_RefClk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 5.582 5.582 R clock network delay
|
|
Info (332115): 5.582 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_cb_host|alt_pr_cb_controller_v2|freeze_reg
|
|
Info (332115): 5.702 0.120 FF uTco fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_cb_host|alt_pr_cb_controller_v2|freeze_reg|q
|
|
Info (332115): 5.767 0.065 FF CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_cb_host|alt_pr_cb_controller_v2|freeze_reg~la_lab/laboutt[8]
|
|
Info (332115): 7.683 1.916 FF IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|i617~0|datae
|
|
Info (332115): 7.769 0.086 FF CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|i617~0|combout
|
|
Info (332115): 7.769 0.000 FF CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi.f2a_prmgmt_freeze|d
|
|
Info (332115): 7.769 0.000 FF CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi.f2a_prmgmt_freeze
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 10.000 10.000 latch edge time
|
|
Info (332115): 12.469 2.469 R clock network delay
|
|
Info (332115): 12.611 0.142 clock pessimism removed
|
|
Info (332115): 12.301 -0.310 clock uncertainty
|
|
Info (332115): 12.467 0.166 uTsu fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi.f2a_prmgmt_freeze
|
|
Info (332115): Data Arrival Time : 7.769
|
|
Info (332115): Data Required Time : 12.467
|
|
Info (332115): Slack : 4.698
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 5.652
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|avmmclk}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 5.652
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|reconfig_read
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Launch Clock : SYS_RefClk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|avmmclk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 2.695 2.695 R clock network delay
|
|
Info (332115): 2.695 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|reconfig_read
|
|
Info (332115): 2.825 0.130 FF uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|reconfig_read|q
|
|
Info (332115): 2.893 0.068 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|reconfig_read~la_mlab/laboutb[4]
|
|
Info (332115): 3.903 1.010 FF IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|avmm_read[1]~1|dataa
|
|
Info (332115): 4.014 0.111 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|avmm_read[1]~1|combout
|
|
Info (332115): 4.018 0.004 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|avmm_read[1]~1~la_lab/laboutt[7]
|
|
Info (332115): 7.167 3.149 FF IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst|avmmread
|
|
Info (332115): 7.167 0.000 FF CELL fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 10.000 10.000 latch edge time
|
|
Info (332115): 12.600 2.600 R clock network delay
|
|
Info (332115): 12.742 0.142 clock pessimism removed
|
|
Info (332115): 12.712 -0.030 clock uncertainty
|
|
Info (332115): 12.819 0.107 uTsu fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Arrival Time : 7.167
|
|
Info (332115): Data Required Time : 12.819
|
|
Info (332115): Slack : 5.652
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 5.811
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|avmmclk}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 5.811
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|reconfig_write
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Launch Clock : SYS_RefClk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|avmmclk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 2.695 2.695 R clock network delay
|
|
Info (332115): 2.695 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|reconfig_write
|
|
Info (332115): 2.831 0.136 FF uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|reconfig_write|q
|
|
Info (332115): 2.876 0.045 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|reconfig_write~la_mlab/laboutt[10]
|
|
Info (332115): 3.891 1.015 FF IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|avmm_write[2]~2|datac
|
|
Info (332115): 3.973 0.082 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|avmm_write[2]~2|combout
|
|
Info (332115): 3.977 0.004 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|avmm_write[2]~2~la_lab/laboutb[4]
|
|
Info (332115): 6.938 2.961 FF IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst|avmmwrite
|
|
Info (332115): 6.938 0.000 FF CELL fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 10.000 10.000 latch edge time
|
|
Info (332115): 12.600 2.600 R clock network delay
|
|
Info (332115): 12.742 0.142 clock pessimism removed
|
|
Info (332115): 12.712 -0.030 clock uncertainty
|
|
Info (332115): 12.749 0.037 uTsu fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Arrival Time : 6.938
|
|
Info (332115): Data Required Time : 12.749
|
|
Info (332115): Slack : 5.811
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 5.882
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|avmmclk}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 5.882
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|reconfig_read
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Launch Clock : SYS_RefClk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|avmmclk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 2.695 2.695 R clock network delay
|
|
Info (332115): 2.695 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|reconfig_read
|
|
Info (332115): 2.825 0.130 FF uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|reconfig_read|q
|
|
Info (332115): 2.893 0.068 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|reconfig_read~la_mlab/laboutb[4]
|
|
Info (332115): 3.903 1.010 FF IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|avmm_read[0]~0|dataa
|
|
Info (332115): 4.019 0.116 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|avmm_read[0]~0|combout
|
|
Info (332115): 4.023 0.004 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|avmm_read[0]~0~la_lab/laboutt[4]
|
|
Info (332115): 6.935 2.912 FF IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst|avmmread
|
|
Info (332115): 6.935 0.000 FF CELL fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 10.000 10.000 latch edge time
|
|
Info (332115): 12.598 2.598 R clock network delay
|
|
Info (332115): 12.740 0.142 clock pessimism removed
|
|
Info (332115): 12.710 -0.030 clock uncertainty
|
|
Info (332115): 12.817 0.107 uTsu fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Arrival Time : 6.935
|
|
Info (332115): Data Required Time : 12.817
|
|
Info (332115): Slack : 5.882
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 5.943
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|tx_pma_div_clk}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 5.943
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[5].ct0|dout_r[5]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[5].ct0|dout_r[5]
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|tx_pma_div_clk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|tx_pma_div_clk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 5.300 5.300 R clock network delay
|
|
Info (332115): 5.300 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[5].ct0|dout_r[5]
|
|
Info (332115): 5.419 0.119 RR uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[5].ct0|dout_r[5]|q
|
|
Info (332115): 5.501 0.082 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[5].ct0|dout_r[5]~la_lab/laboutb[8]
|
|
Info (332115): 5.774 0.273 RR IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[5].ct0|t5|dout|datae
|
|
Info (332115): 5.845 0.071 RF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[5].ct0|t5|dout|combout
|
|
Info (332115): 5.845 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[5].ct0|dout_r[5]|d
|
|
Info (332115): 5.845 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[5].ct0|dout_r[5]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 6.399 6.399 latch edge time
|
|
Info (332115): 10.562 4.163 R clock network delay
|
|
Info (332115): 11.698 1.136 clock pessimism removed
|
|
Info (332115): 11.678 -0.020 clock uncertainty
|
|
Info (332115): 11.788 0.110 uTsu fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[5].ct0|dout_r[5]
|
|
Info (332115): Data Arrival Time : 5.845
|
|
Info (332115): Data Required Time : 11.788
|
|
Info (332115): Slack : 5.943
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 6.008
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_div_clk}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 6.008
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[4].ct0|dout_r[4]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[4].ct0|dout_r[5]
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_div_clk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_div_clk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 5.775 5.775 R clock network delay
|
|
Info (332115): 5.775 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[4].ct0|dout_r[4]
|
|
Info (332115): 5.910 0.135 RR uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[4].ct0|dout_r[4]|q
|
|
Info (332115): 5.971 0.061 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[4].ct0|dout_r[4]~la_lab/laboutb[9]
|
|
Info (332115): 6.221 0.250 RR IC High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[4].ct0|t5|dout|dataf
|
|
Info (332115): 6.246 0.025 RF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[4].ct0|t5|dout|combout
|
|
Info (332115): 6.246 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[4].ct0|dout_r[5]|d
|
|
Info (332115): 6.246 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[4].ct0|dout_r[5]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 6.399 6.399 latch edge time
|
|
Info (332115): 10.935 4.536 R clock network delay
|
|
Info (332115): 12.174 1.239 clock pessimism removed
|
|
Info (332115): 12.144 -0.030 clock uncertainty
|
|
Info (332115): 12.254 0.110 uTsu fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[4].ct0|dout_r[5]
|
|
Info (332115): Data Arrival Time : 6.246
|
|
Info (332115): Data Required Time : 12.254
|
|
Info (332115): Slack : 6.008
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 6.534
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|avmmclk}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 6.534
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|reconfig_read
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Launch Clock : SYS_RefClk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|avmmclk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 2.695 2.695 R clock network delay
|
|
Info (332115): 2.695 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|reconfig_read
|
|
Info (332115): 2.825 0.130 FF uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|reconfig_read|q
|
|
Info (332115): 2.893 0.068 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|reconfig_read~la_mlab/laboutb[4]
|
|
Info (332115): 3.843 0.950 FF IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|avmm_read[3]~3|datab
|
|
Info (332115): 3.954 0.111 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|avmm_read[3]~3|combout
|
|
Info (332115): 3.959 0.005 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|avmm_read[3]~3~la_mlab/laboutt[2]
|
|
Info (332115): 6.355 2.396 FF IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst|avmmread
|
|
Info (332115): 6.355 0.000 FF CELL fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 10.000 10.000 latch edge time
|
|
Info (332115): 12.670 2.670 R clock network delay
|
|
Info (332115): 12.812 0.142 clock pessimism removed
|
|
Info (332115): 12.782 -0.030 clock uncertainty
|
|
Info (332115): 12.889 0.107 uTsu fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Arrival Time : 6.355
|
|
Info (332115): Data Required Time : 12.889
|
|
Info (332115): Slack : 6.534
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 6.632
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|avmmclk}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 6.632
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_address[3]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Launch Clock : PCIE_REFCLK
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|avmmclk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 3.477 3.477 R clock network delay
|
|
Info (332115): 3.477 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_address[3]
|
|
Info (332115): 3.602 0.125 FF uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_address[3]|q
|
|
Info (332115): 3.678 0.076 FF CELL Low Power fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_address[3]~la_lab/laboutt[19]
|
|
Info (332115): 4.411 0.733 FF IC Mixed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i1697|dataf
|
|
Info (332115): 4.436 0.025 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i1697|combout
|
|
Info (332115): 4.440 0.004 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i1697~la_lab/laboutb[0]
|
|
Info (332115): 6.847 2.407 FF IC Mixed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst|avmmaddress[3]
|
|
Info (332115): 6.847 0.000 FF CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 10.000 10.000 latch edge time
|
|
Info (332115): 13.218 3.218 R clock network delay
|
|
Info (332115): 13.530 0.312 clock pessimism removed
|
|
Info (332115): 13.490 -0.040 clock uncertainty
|
|
Info (332115): 13.479 -0.011 uTsu fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Arrival Time : 6.847
|
|
Info (332115): Data Required Time : 13.479
|
|
Info (332115): Slack : 6.632
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 6.687
|
|
Info (20696): -to_clock [get_clocks {fspi_sclk}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 6.687
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_altera_avalon_st_packets_to_bytes_inst_for_spichain|the_altera_avalon_st_packets_to_bytes|out_data[6]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MISOctl|rdshiftreg[0]
|
|
Info (332115): Launch Clock : u0|dcp_iopll|dcp_iopll|clk1x
|
|
Info (332115): Latch Clock : fspi_sclk
|
|
Info (332115): Exception : dcp_bbs.sdc:3006: set_multicycle_path -setup -to [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MISOctl|rdshiftreg*}] 2
|
|
Info (332115): Multicycle - Setup Start : 2
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 240.000 240.000 launch edge time
|
|
Info (332115): 245.566 5.566 R clock network delay
|
|
Info (332115): 245.566 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_altera_avalon_st_packets_to_bytes_inst_for_spichain|the_altera_avalon_st_packets_to_bytes|out_data[6]
|
|
Info (332115): 245.684 0.118 RR uTco fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_altera_avalon_st_packets_to_bytes_inst_for_spichain|the_altera_avalon_st_packets_to_bytes|out_data[6]|q
|
|
Info (332115): 245.766 0.082 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_altera_avalon_st_packets_to_bytes_inst_for_spichain|the_altera_avalon_st_packets_to_bytes|out_data[6]~la_lab/laboutb[8]
|
|
Info (332115): 245.909 0.143 RR IC High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_altera_avalon_st_idle_inserter|i15~1|datab
|
|
Info (332115): 246.041 0.132 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_altera_avalon_st_idle_inserter|i15~1|combout
|
|
Info (332115): 246.045 0.004 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_altera_avalon_st_idle_inserter|i15~1~la_lab/laboutb[5]
|
|
Info (332115): 246.138 0.093 RR IC High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MISOctl|i36~7|dataa
|
|
Info (332115): 246.271 0.133 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MISOctl|i36~7|combout
|
|
Info (332115): 246.271 0.000 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MISOctl|rdshiftreg[0]|d
|
|
Info (332115): 246.271 0.000 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MISOctl|rdshiftreg[0]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 250.000 250.000 latch edge time
|
|
Info (332115): 253.110 3.110 R clock network delay
|
|
Info (332115): 252.800 -0.310 clock uncertainty
|
|
Info (332115): 252.958 0.158 uTsu fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MISOctl|rdshiftreg[0]
|
|
Info (332115): Data Arrival Time : 246.271
|
|
Info (332115): Data Required Time : 252.958
|
|
Info (332115): Slack : 6.687
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 6.801
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|avmmclk}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 6.801
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_address[5]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Launch Clock : PCIE_REFCLK
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|avmmclk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 3.477 3.477 R clock network delay
|
|
Info (332115): 3.477 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_address[5]
|
|
Info (332115): 3.603 0.126 FF uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_address[5]|q
|
|
Info (332115): 3.673 0.070 FF CELL Low Power fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_address[5]~la_lab/laboutb[7]
|
|
Info (332115): 4.071 0.398 FF IC Low Power fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i1471|datac
|
|
Info (332115): 4.151 0.080 FF CELL Low Power fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i1471|combout
|
|
Info (332115): 4.155 0.004 FF CELL Low Power fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i1471~la_lab/laboutb[2]
|
|
Info (332115): 6.688 2.533 FF IC Mixed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst|avmmaddress[5]
|
|
Info (332115): 6.688 0.000 FF CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 10.000 10.000 latch edge time
|
|
Info (332115): 13.223 3.223 R clock network delay
|
|
Info (332115): 13.535 0.312 clock pessimism removed
|
|
Info (332115): 13.495 -0.040 clock uncertainty
|
|
Info (332115): 13.489 -0.006 uTsu fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Arrival Time : 6.688
|
|
Info (332115): Data Required Time : 13.489
|
|
Info (332115): Slack : 6.801
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 7.012
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|avmmclk}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 7.012
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|g_arb[5].arbiter_inst|grant[0]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Launch Clock : PCIE_REFCLK
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|avmmclk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 3.477 3.477 R clock network delay
|
|
Info (332115): 3.477 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|g_arb[5].arbiter_inst|grant[0]
|
|
Info (332115): 3.608 0.131 FF uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|g_arb[5].arbiter_inst|grant[0]|q
|
|
Info (332115): 3.678 0.070 FF CELL Low Power fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|g_arb[5].arbiter_inst|grant[0]~la_mlab/laboutb[11]
|
|
Info (332115): 4.199 0.521 FF IC Low Power fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i1215|dataf
|
|
Info (332115): 4.225 0.026 FF CELL Low Power fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i1215|combout
|
|
Info (332115): 4.229 0.004 FF CELL Low Power fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i1215~la_lab/laboutt[2]
|
|
Info (332115): 6.474 2.245 FF IC Mixed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst|avmmaddress[1]
|
|
Info (332115): 6.474 0.000 FF CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 10.000 10.000 latch edge time
|
|
Info (332115): 13.213 3.213 R clock network delay
|
|
Info (332115): 13.525 0.312 clock pessimism removed
|
|
Info (332115): 13.485 -0.040 clock uncertainty
|
|
Info (332115): 13.486 0.001 uTsu fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Arrival Time : 6.474
|
|
Info (332115): Data Required Time : 13.486
|
|
Info (332115): Slack : 7.012
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 7.200
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|avmmclk}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 7.200
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_address[2]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Launch Clock : PCIE_REFCLK
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|avmmclk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 3.477 3.477 R clock network delay
|
|
Info (332115): 3.477 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_address[2]
|
|
Info (332115): 3.602 0.125 FF uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_address[2]|q
|
|
Info (332115): 3.652 0.050 FF CELL Low Power fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_address[2]~la_lab/laboutb[13]
|
|
Info (332115): 4.407 0.755 FF IC Mixed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i984|datac
|
|
Info (332115): 4.490 0.083 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i984|combout
|
|
Info (332115): 4.495 0.005 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i984~la_mlab/laboutt[0]
|
|
Info (332115): 6.317 1.822 FF IC Mixed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst|avmmaddress[2]
|
|
Info (332115): 6.317 0.000 FF CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 10.000 10.000 latch edge time
|
|
Info (332115): 13.209 3.209 R clock network delay
|
|
Info (332115): 13.521 0.312 clock pessimism removed
|
|
Info (332115): 13.481 -0.040 clock uncertainty
|
|
Info (332115): 13.517 0.036 uTsu fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Arrival Time : 6.317
|
|
Info (332115): Data Required Time : 13.517
|
|
Info (332115): Slack : 7.200
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 7.417
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|avmmclk}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 7.417
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_address[5]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Launch Clock : PCIE_REFCLK
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|avmmclk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 3.477 3.477 R clock network delay
|
|
Info (332115): 3.477 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_address[5]
|
|
Info (332115): 3.603 0.126 FF uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_address[5]|q
|
|
Info (332115): 3.673 0.070 FF CELL Low Power fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_address[5]~la_lab/laboutb[7]
|
|
Info (332115): 4.330 0.657 FF IC Mixed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i763|dataf
|
|
Info (332115): 4.355 0.025 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i763|combout
|
|
Info (332115): 4.359 0.004 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i763~la_lab/laboutt[3]
|
|
Info (332115): 6.075 1.716 FF IC High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst|avmmaddress[5]
|
|
Info (332115): 6.075 0.000 FF CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 10.000 10.000 latch edge time
|
|
Info (332115): 13.226 3.226 R clock network delay
|
|
Info (332115): 13.538 0.312 clock pessimism removed
|
|
Info (332115): 13.498 -0.040 clock uncertainty
|
|
Info (332115): 13.492 -0.006 uTsu fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Arrival Time : 6.075
|
|
Info (332115): Data Required Time : 13.492
|
|
Info (332115): Slack : 7.417
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 7.553
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|avmmclk}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 7.553
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_write
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Launch Clock : PCIE_REFCLK
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|avmmclk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 3.475 3.475 R clock network delay
|
|
Info (332115): 3.475 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_write
|
|
Info (332115): 3.655 0.180 FF uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_write|q
|
|
Info (332115): 3.720 0.065 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_write~la_lab/laboutb[0]
|
|
Info (332115): 4.390 0.670 FF IC High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i480~0|datad
|
|
Info (332115): 4.467 0.077 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i480~0|combout
|
|
Info (332115): 4.472 0.005 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i480~0~la_mlab/laboutb[15]
|
|
Info (332115): 5.977 1.505 FF IC High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst|avmmwrite
|
|
Info (332115): 5.977 0.000 FF CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 10.000 10.000 latch edge time
|
|
Info (332115): 13.221 3.221 R clock network delay
|
|
Info (332115): 13.533 0.312 clock pessimism removed
|
|
Info (332115): 13.493 -0.040 clock uncertainty
|
|
Info (332115): 13.530 0.037 uTsu fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Arrival Time : 5.977
|
|
Info (332115): Data Required Time : 13.530
|
|
Info (332115): Slack : 7.553
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 7.777
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|avmmclk}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 7.777
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|g_arb[1].arbiter_inst|grant[0]~DUPLICATE
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Launch Clock : PCIE_REFCLK
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|avmmclk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 3.462 3.462 R clock network delay
|
|
Info (332115): 3.462 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|g_arb[1].arbiter_inst|grant[0]~DUPLICATE
|
|
Info (332115): 3.588 0.126 FF uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|g_arb[1].arbiter_inst|grant[0]~DUPLICATE|q
|
|
Info (332115): 3.653 0.065 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|g_arb[1].arbiter_inst|grant[0]~DUPLICATE~la_mlab/laboutb[16]
|
|
Info (332115): 4.020 0.367 FF IC Mixed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i276|dataa
|
|
Info (332115): 4.133 0.113 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i276|combout
|
|
Info (332115): 4.138 0.005 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i276~la_mlab/laboutb[9]
|
|
Info (332115): 5.822 1.684 FF IC Mixed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst|avmmaddress[2]
|
|
Info (332115): 5.822 0.000 FF CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 10.000 10.000 latch edge time
|
|
Info (332115): 13.277 3.277 R clock network delay
|
|
Info (332115): 13.603 0.326 clock pessimism removed
|
|
Info (332115): 13.563 -0.040 clock uncertainty
|
|
Info (332115): 13.599 0.036 uTsu fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Arrival Time : 5.822
|
|
Info (332115): Data Required Time : 13.599
|
|
Info (332115): Slack : 7.777
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 8.268
|
|
Info (20696): -to_clock [get_clocks {vl_qph_user_clk_clkpsc_clk0}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 8.268
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[0]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[1]
|
|
Info (332115): Launch Clock : vl_qph_user_clk_clkpsc_clk0
|
|
Info (332115): Latch Clock : vl_qph_user_clk_clkpsc_clk0
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 4.092 4.092 R clock network delay
|
|
Info (332115): 4.092 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[0]
|
|
Info (332115): 4.218 0.126 FF uTco fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[0]|q
|
|
Info (332115): 4.260 0.042 FF CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[0]~la_mlab/laboutb[9]
|
|
Info (332115): 4.907 0.647 FF IC Mixed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[1]~2|dataa
|
|
Info (332115): 5.026 0.119 FR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[1]~2|combout
|
|
Info (332115): 5.026 0.000 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[1]|d
|
|
Info (332115): 5.026 0.000 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[1]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 9.090 9.090 latch edge time
|
|
Info (332115): 12.524 3.434 R clock network delay
|
|
Info (332115): 13.180 0.656 clock pessimism removed
|
|
Info (332115): 13.150 -0.030 clock uncertainty
|
|
Info (332115): 13.294 0.144 uTsu fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[1]
|
|
Info (332115): Data Arrival Time : 5.026
|
|
Info (332115): Data Required Time : 13.294
|
|
Info (332115): Slack : 8.268
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 8.372
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|avmmclk}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 8.372
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_writedata[3]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Launch Clock : PCIE_REFCLK
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|avmmclk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 3.471 3.471 R clock network delay
|
|
Info (332115): 3.471 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_writedata[3]
|
|
Info (332115): 3.656 0.185 FF uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_writedata[3]|q
|
|
Info (332115): 3.698 0.042 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_writedata[3]~la_lab/laboutt[17]
|
|
Info (332115): 4.338 0.640 FF IC Mixed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i80~3|datae
|
|
Info (332115): 4.396 0.058 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i80~3|combout
|
|
Info (332115): 4.401 0.005 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i80~3~la_mlab/laboutb[8]
|
|
Info (332115): 5.258 0.857 FF IC High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst|avmmwritedata[3]
|
|
Info (332115): 5.258 0.000 FF CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 10.000 10.000 latch edge time
|
|
Info (332115): 13.270 3.270 R clock network delay
|
|
Info (332115): 13.596 0.326 clock pessimism removed
|
|
Info (332115): 13.556 -0.040 clock uncertainty
|
|
Info (332115): 13.630 0.074 uTsu fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Arrival Time : 5.258
|
|
Info (332115): Data Required Time : 13.630
|
|
Info (332115): Slack : 8.372
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 8.784
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk0}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 8.784
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_green_bs|uClk_usrDiv2_q1
|
|
Info (332115): To Node : fpga_top|inst_green_bs|uClk_usrDiv2_q2
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk0
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk0
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 3.880 3.880 R clock network delay
|
|
Info (332115): 3.880 0.000 fpga_top|inst_green_bs|uClk_usrDiv2_q1
|
|
Info (332115): 4.042 0.162 RR uTco fpga_top|inst_green_bs|uClk_usrDiv2_q1|q
|
|
Info (332115): 4.042 0.000 RR CELL High Speed fpga_top|inst_green_bs|uClk_usrDiv2_q2~0|datae
|
|
Info (332115): 4.265 0.223 RF CELL High Speed fpga_top|inst_green_bs|uClk_usrDiv2_q2~0|combout
|
|
Info (332115): 4.265 0.000 FF CELL High Speed fpga_top|inst_green_bs|uClk_usrDiv2_q2|d
|
|
Info (332115): 4.265 0.000 FF CELL High Speed fpga_top|inst_green_bs|uClk_usrDiv2_q2
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 9.090 9.090 latch edge time
|
|
Info (332115): 12.340 3.250 R clock network delay
|
|
Info (332115): 12.970 0.630 clock pessimism removed
|
|
Info (332115): 12.940 -0.030 clock uncertainty
|
|
Info (332115): 13.049 0.109 uTsu fpga_top|inst_green_bs|uClk_usrDiv2_q2
|
|
Info (332115): Data Arrival Time : 4.265
|
|
Info (332115): Data Required Time : 13.049
|
|
Info (332115): Slack : 8.784
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 11.846
|
|
Info (20696): -to_clock [get_clocks {pr_clk_enable_dclk_reg2_user_clk}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 11.846
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_cb_host|alt_pr_cb_controller_v2|pr_request_reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_cb_host|alt_pr_cb_controller_v2|alt_pr_cb_interface|m_prblock~cs_css/pr_clk_core.reg
|
|
Info (332115): Launch Clock : u0|dcp_iopll|dcp_iopll|clk100
|
|
Info (332115): Latch Clock : pr_clk_enable_dclk_reg2_user_clk
|
|
Info (332115): Exception : dcp_bbs.sdc:3118: set_multicycle_path -setup -from [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_cb_host|alt_pr_cb_controller_v2|pr_request_reg}] -to [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_cb_host|alt_pr_cb_controller_v2|alt_pr_cb_interface|m_prblock~cs_css/pr_clk_core.reg}] 2
|
|
Info (332115): Multicycle - Setup Start : 2
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 5.582 5.582 R clock network delay
|
|
Info (332115): 5.582 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_cb_host|alt_pr_cb_controller_v2|pr_request_reg
|
|
Info (332115): 5.765 0.183 FF uTco fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_cb_host|alt_pr_cb_controller_v2|pr_request_reg|q
|
|
Info (332115): 5.830 0.065 FF CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_cb_host|alt_pr_cb_controller_v2|pr_request_reg~la_lab/laboutt[0]
|
|
Info (332115): 9.430 3.600 FF IC High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_cb_host|alt_pr_cb_controller_v2|alt_pr_cb_interface|m_prblock|prrequest
|
|
Info (332115): 9.430 0.000 FF CELL fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_cb_host|alt_pr_cb_controller_v2|alt_pr_cb_interface|m_prblock~cs_css/pr_clk_core.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 15.000 15.000 latch edge time
|
|
Info (332115): 20.476 5.476 R clock network delay
|
|
Info (332115): 21.140 0.664 clock pessimism removed
|
|
Info (332115): 20.970 -0.170 clock uncertainty
|
|
Info (332115): 21.276 0.306 uTsu fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_cb_host|alt_pr_cb_controller_v2|alt_pr_cb_interface|m_prblock~cs_css/pr_clk_core.reg
|
|
Info (332115): Data Arrival Time : 9.430
|
|
Info (332115): Data Required Time : 21.276
|
|
Info (332115): Slack : 11.846
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 18.943
|
|
Info (20696): -to_clock [get_clocks {u0|dcp_iopll|dcp_iopll|clk25}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 18.943
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|generic_quad_spi_controller2_0|generic_quad_spi_controller2_0|asmi2_inst_qspi_ctrl|asmi2_cmd_generator_0|state.ST_SEND_ADDR
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|generic_quad_spi_controller2_0|generic_quad_spi_controller2_0|asmi2_inst_qspi_ctrl|asmi2_qspi_interface_0|dataout_reg[0]~RTM_7
|
|
Info (332115): Launch Clock : u0|dcp_iopll|dcp_iopll|clk25
|
|
Info (332115): Latch Clock : u0|dcp_iopll|dcp_iopll|clk25 (INVERTED)
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 5.709 5.709 R clock network delay
|
|
Info (332115): 5.709 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|generic_quad_spi_controller2_0|generic_quad_spi_controller2_0|asmi2_inst_qspi_ctrl|asmi2_cmd_generator_0|state.ST_SEND_ADDR
|
|
Info (332115): 5.833 0.124 FF uTco fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|generic_quad_spi_controller2_0|generic_quad_spi_controller2_0|asmi2_inst_qspi_ctrl|asmi2_cmd_generator_0|state.ST_SEND_ADDR|q
|
|
Info (332115): 5.875 0.042 FF CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|generic_quad_spi_controller2_0|generic_quad_spi_controller2_0|asmi2_inst_qspi_ctrl|asmi2_cmd_generator_0|state.ST_SEND_ADDR~la_lab/laboutb[13]
|
|
Info (332115): 6.225 0.350 FF IC High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|generic_quad_spi_controller2_0|generic_quad_spi_controller2_0|asmi2_inst_qspi_ctrl|asmi2_cmd_generator_0|Select_8~0|datac
|
|
Info (332115): 6.309 0.084 FF CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|generic_quad_spi_controller2_0|generic_quad_spi_controller2_0|asmi2_inst_qspi_ctrl|asmi2_cmd_generator_0|Select_8~0|combout
|
|
Info (332115): 6.313 0.004 FF CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|generic_quad_spi_controller2_0|generic_quad_spi_controller2_0|asmi2_inst_qspi_ctrl|asmi2_cmd_generator_0|Select_8~0~la_lab/laboutt[4]
|
|
Info (332115): 6.429 0.116 FF IC High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|generic_quad_spi_controller2_0|generic_quad_spi_controller2_0|asmi2_inst_qspi_ctrl|asmi2_qspi_interface_0|dataout_reg[1]~0|dataf
|
|
Info (332115): 6.455 0.026 FF CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|generic_quad_spi_controller2_0|generic_quad_spi_controller2_0|asmi2_inst_qspi_ctrl|asmi2_qspi_interface_0|dataout_reg[1]~0|combout
|
|
Info (332115): 6.459 0.004 FF CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|generic_quad_spi_controller2_0|generic_quad_spi_controller2_0|asmi2_inst_qspi_ctrl|asmi2_qspi_interface_0|dataout_reg[1]~0~la_lab/laboutb[18]
|
|
Info (332115): 6.646 0.187 FF IC High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|generic_quad_spi_controller2_0|generic_quad_spi_controller2_0|asmi2_inst_qspi_ctrl|asmi2_qspi_interface_0|dataout_reg[0]~RTM_7|d
|
|
Info (332115): 6.646 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|generic_quad_spi_controller2_0|generic_quad_spi_controller2_0|asmi2_inst_qspi_ctrl|asmi2_qspi_interface_0|dataout_reg[0]~RTM_7
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 20.000 20.000 latch edge time
|
|
Info (332115): 24.909 4.909 F clock network delay
|
|
Info (332115): 25.671 0.762 clock pessimism removed
|
|
Info (332115): 25.451 -0.220 clock uncertainty
|
|
Info (332115): 25.589 0.138 uTsu fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|generic_quad_spi_controller2_0|generic_quad_spi_controller2_0|asmi2_inst_qspi_ctrl|asmi2_qspi_interface_0|dataout_reg[0]~RTM_7
|
|
Info (332115): Data Arrival Time : 6.646
|
|
Info (332115): Data Required Time : 25.589
|
|
Info (332115): Slack : 18.943
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 19.538
|
|
Info (20696): -to_clock [get_clocks {u0|dcp_iopll|dcp_iopll|clk50}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 19.538
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_green_bs|pClkDiv4_q1
|
|
Info (332115): To Node : fpga_top|inst_green_bs|pClkDiv4_q2
|
|
Info (332115): Launch Clock : u0|dcp_iopll|dcp_iopll|clk50
|
|
Info (332115): Latch Clock : u0|dcp_iopll|dcp_iopll|clk50
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 5.679 5.679 R clock network delay
|
|
Info (332115): 5.679 0.000 fpga_top|inst_green_bs|pClkDiv4_q1
|
|
Info (332115): 5.833 0.154 RR uTco fpga_top|inst_green_bs|pClkDiv4_q1|q
|
|
Info (332115): 5.833 0.000 RR CELL High Speed fpga_top|inst_green_bs|pClkDiv4_q2~0|datae
|
|
Info (332115): 6.058 0.225 RF CELL High Speed fpga_top|inst_green_bs|pClkDiv4_q2~0|combout
|
|
Info (332115): 6.058 0.000 FF CELL High Speed fpga_top|inst_green_bs|pClkDiv4_q2|d
|
|
Info (332115): 6.058 0.000 FF CELL High Speed fpga_top|inst_green_bs|pClkDiv4_q2
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 20.000 20.000 latch edge time
|
|
Info (332115): 24.902 4.902 R clock network delay
|
|
Info (332115): 25.678 0.776 clock pessimism removed
|
|
Info (332115): 25.488 -0.190 clock uncertainty
|
|
Info (332115): 25.596 0.108 uTsu fpga_top|inst_green_bs|pClkDiv4_q2
|
|
Info (332115): Data Arrival Time : 6.058
|
|
Info (332115): Data Required Time : 25.596
|
|
Info (332115): Slack : 19.538
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 23.821
|
|
Info (20696): -to_clock [get_clocks {filtered_sclk_negedge}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 23.821
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MOSIctl|filtered_mosi_out
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MOSIctl|wrshiftreg[0]
|
|
Info (332115): Launch Clock : u0|dcp_iopll|dcp_iopll|clk1x
|
|
Info (332115): Latch Clock : filtered_sclk_negedge
|
|
Info (332115): Exception : dcp_bbs.sdc:3138: set_max_delay -from [get_keepers {*filtered_mosi*}] 30.000
|
|
Info (332115): Max Delay Exception : 30.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 5.565 5.565 R clock network delay
|
|
Info (332115): 5.565 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MOSIctl|filtered_mosi_out
|
|
Info (332115): 5.745 0.180 FF uTco fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MOSIctl|filtered_mosi_out|q
|
|
Info (332115): 5.787 0.042 FF CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MOSIctl|filtered_mosi_out~la_lab/laboutb[5]
|
|
Info (332115): 6.090 0.303 FF IC High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MOSIctl|wrshiftreg[0]|asdata
|
|
Info (332115): 6.090 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MOSIctl|wrshiftreg[0]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 30.000 30.000 latch edge time
|
|
Info (332115): 30.120 0.120 R clock network delay
|
|
Info (332115): 29.820 -0.300 clock uncertainty
|
|
Info (332115): 29.911 0.091 uTsu fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MOSIctl|wrshiftreg[0]
|
|
Info (332115): Data Arrival Time : 6.090
|
|
Info (332115): Data Required Time : 29.911
|
|
Info (332115): Slack : 23.821
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 setup paths (0 violated). Worst case slack is 43.761
|
|
Info (20696): -to_clock [get_clocks {altera_reserved_tck}]
|
|
Info (20696): -setup
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Setup slack is 43.761
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|nios2_gen2_0|nios2_gen2_0|cpu|the_tcm_nios2_gen2_0_altera_nios2_gen2_unit_191_dbuc52a_nios2_oci|the_tcm_nios2_gen2_0_altera_nios2_gen2_unit_191_dbuc52a_debug_slave_wrapper|the_tcm_nios2_gen2_0_altera_nios2_gen2_unit_191_dbuc52a_debug_slave_tck|sr[0]
|
|
Info (332115): To Node : auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|jtagpins|int_tdo_reg~LRTM_5
|
|
Info (332115): Launch Clock : altera_reserved_tck
|
|
Info (332115): Latch Clock : altera_reserved_tck (INVERTED)
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 3.438 3.438 R clock network delay
|
|
Info (332115): 3.438 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|nios2_gen2_0|nios2_gen2_0|cpu|the_tcm_nios2_gen2_0_altera_nios2_gen2_unit_191_dbuc52a_nios2_oci|the_tcm_nios2_gen2_0_altera_nios2_gen2_unit_191_dbuc52a_debug_slave_wrapper|the_tcm_nios2_gen2_0_altera_nios2_gen2_unit_191_dbuc52a_debug_slave_tck|sr[0]
|
|
Info (332115): 3.563 0.125 FF uTco fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|nios2_gen2_0|nios2_gen2_0|cpu|the_tcm_nios2_gen2_0_altera_nios2_gen2_unit_191_dbuc52a_nios2_oci|the_tcm_nios2_gen2_0_altera_nios2_gen2_unit_191_dbuc52a_debug_slave_wrapper|the_tcm_nios2_gen2_0_altera_nios2_gen2_unit_191_dbuc52a_debug_slave_tck|sr[0]|q
|
|
Info (332115): 3.605 0.042 FF CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|nios2_gen2_0|nios2_gen2_0|cpu|the_tcm_nios2_gen2_0_altera_nios2_gen2_unit_191_dbuc52a_nios2_oci|the_tcm_nios2_gen2_0_altera_nios2_gen2_unit_191_dbuc52a_debug_slave_wrapper|the_tcm_nios2_gen2_0_altera_nios2_gen2_unit_191_dbuc52a_debug_slave_tck|sr[0]~la_lab/laboutb[9]
|
|
Info (332115): 3.605 0.000 FF IC auto_fab_0|auto_export_alt_sld_fab_0_alt_sld_fab_0_splitter_send_2[0]|input
|
|
Info (332115): 3.605 0.000 FF CELL auto_fab_0|auto_export_alt_sld_fab_0_alt_sld_fab_0_splitter_send_2[0]
|
|
Info (332115): 8.485 4.880 FF IC High Speed auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|sldfabric|\jtag_hub_gen:real_sld_jtag_hub|i705~4|datab
|
|
Info (332115): 8.597 0.112 FF CELL High Speed auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|sldfabric|\jtag_hub_gen:real_sld_jtag_hub|i705~4|combout
|
|
Info (332115): 8.597 0.000 FF CELL High Speed auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|jtagpins|int_tdo_reg~LRTM_5|d
|
|
Info (332115): 8.597 0.000 FF CELL High Speed auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|jtagpins|int_tdo_reg~LRTM_5
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 50.000 50.000 latch edge time
|
|
Info (332115): 51.970 1.970 F clock network delay
|
|
Info (332115): 52.211 0.241 clock pessimism removed
|
|
Info (332115): 52.181 -0.030 clock uncertainty
|
|
Info (332115): 52.358 0.177 uTsu auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|jtagpins|int_tdo_reg~LRTM_5
|
|
Info (332115): Data Arrival Time : 8.597
|
|
Info (332115): Data Required Time : 52.358
|
|
Info (332115): Slack : 43.761
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.001
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk1}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.001
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|csr_arb|rsp_arb|out_buffer|shift_reg[1][15]
|
|
Info (332115): To Node : fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|cmd_csr_rdata[15]
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk1
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk1
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 3.277 3.277 R clock network delay
|
|
Info (332115): 3.277 0.000 fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|csr_arb|rsp_arb|out_buffer|shift_reg[1][15]
|
|
Info (332115): 3.374 0.097 FF uTco fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|csr_arb|rsp_arb|out_buffer|shift_reg[1][15]|q
|
|
Info (332115): 3.533 0.159 FF CELL High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|cmd_csr_rdata[15]|d
|
|
Info (332115): 3.533 0.000 FF CELL High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|cmd_csr_rdata[15]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 3.916 3.916 R clock network delay
|
|
Info (332115): 3.278 -0.638 clock pessimism removed
|
|
Info (332115): 3.278 0.000 clock uncertainty
|
|
Info (332115): 3.532 0.254 uTh fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|cmd_csr_rdata[15]
|
|
Info (332115): Data Arrival Time : 3.533
|
|
Info (332115): Data Required Time : 3.532
|
|
Info (332115): Slack : 0.001
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.011
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|wys~CORE_CLK_OUT}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.011
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|avl_cci_bridge|tr_cci_valid[61]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|avl_cci_bridge|tr_cci_valid[61]
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|wys~CORE_CLK_OUT
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|wys~CORE_CLK_OUT
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 4.386 4.386 R clock network delay
|
|
Info (332115): 4.386 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|avl_cci_bridge|tr_cci_valid[61]
|
|
Info (332115): 4.498 0.112 FF uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|avl_cci_bridge|tr_cci_valid[61]|q
|
|
Info (332115): 4.498 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|avl_cci_bridge|i12878~47|datad
|
|
Info (332115): 4.652 0.154 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|avl_cci_bridge|i12878~47|combout
|
|
Info (332115): 4.652 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|avl_cci_bridge|tr_cci_valid[61]|d
|
|
Info (332115): 4.652 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|avl_cci_bridge|tr_cci_valid[61]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 5.191 5.191 R clock network delay
|
|
Info (332115): 4.387 -0.804 clock pessimism removed
|
|
Info (332115): 4.641 0.254 uTh fpga_top|inst_fiu_top|inst_pcie0_ccib_top|avl_cci_bridge|tr_cci_valid[61]
|
|
Info (332115): Data Arrival Time : 4.652
|
|
Info (332115): Data Required Time : 4.641
|
|
Info (332115): Slack : 0.011
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.012
|
|
Info (20696): -to_clock [get_clocks {SYS_RefClk}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.012
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|pll_t_read0
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|pll_t_read0
|
|
Info (332115): Launch Clock : SYS_RefClk
|
|
Info (332115): Latch Clock : SYS_RefClk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 2.460 2.460 R clock network delay
|
|
Info (332115): 2.460 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|pll_t_read0
|
|
Info (332115): 2.567 0.107 FF uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|pll_t_read0|q
|
|
Info (332115): 2.567 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|i601~0|datad
|
|
Info (332115): 2.721 0.154 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|i601~0|combout
|
|
Info (332115): 2.721 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|pll_t_read0|d
|
|
Info (332115): 2.721 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|pll_t_read0
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 2.695 2.695 R clock network delay
|
|
Info (332115): 2.461 -0.234 clock pessimism removed
|
|
Info (332115): 2.461 0.000 clock uncertainty
|
|
Info (332115): 2.709 0.248 uTh fpga_top|inst_fiu_top|inst_hssi_ctrl|pll_t_read0
|
|
Info (332115): Data Arrival Time : 2.721
|
|
Info (332115): Data Required Time : 2.709
|
|
Info (332115): Slack : 0.012
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.013
|
|
Info (20696): -to_clock [get_clocks {u0|dcp_iopll|dcp_iopll|clk1x}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.013
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|nios2_gen2_0_data_master_to_tcm_to_bmc_mm_bridge_s0_cmd_width_adapter|use_reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|nios2_gen2_0_data_master_to_tcm_to_bmc_mm_bridge_s0_cmd_width_adapter|use_reg
|
|
Info (332115): Launch Clock : u0|dcp_iopll|dcp_iopll|clk1x
|
|
Info (332115): Latch Clock : u0|dcp_iopll|dcp_iopll|clk1x
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 4.815 4.815 R clock network delay
|
|
Info (332115): 4.815 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|nios2_gen2_0_data_master_to_tcm_to_bmc_mm_bridge_s0_cmd_width_adapter|use_reg
|
|
Info (332115): 4.932 0.117 FF uTco fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|nios2_gen2_0_data_master_to_tcm_to_bmc_mm_bridge_s0_cmd_width_adapter|use_reg|q
|
|
Info (332115): 4.932 0.000 FF CELL Low Power fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|nios2_gen2_0_data_master_to_tcm_to_bmc_mm_bridge_s0_cmd_width_adapter|i606~0|datae
|
|
Info (332115): 5.094 0.162 FF CELL Low Power fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|nios2_gen2_0_data_master_to_tcm_to_bmc_mm_bridge_s0_cmd_width_adapter|i606~0|combout
|
|
Info (332115): 5.094 0.000 FF CELL Low Power fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|nios2_gen2_0_data_master_to_tcm_to_bmc_mm_bridge_s0_cmd_width_adapter|use_reg|d
|
|
Info (332115): 5.094 0.000 FF CELL Low Power fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|nios2_gen2_0_data_master_to_tcm_to_bmc_mm_bridge_s0_cmd_width_adapter|use_reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 5.566 5.566 R clock network delay
|
|
Info (332115): 4.816 -0.750 clock pessimism removed
|
|
Info (332115): 4.816 0.000 clock uncertainty
|
|
Info (332115): 5.081 0.265 uTh fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|nios2_gen2_0_data_master_to_tcm_to_bmc_mm_bridge_s0_cmd_width_adapter|use_reg
|
|
Info (332115): Data Arrival Time : 5.094
|
|
Info (332115): Data Required Time : 5.081
|
|
Info (332115): Slack : 0.013
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.014
|
|
Info (20696): -to_clock [get_clocks {u0|dcp_iopll|dcp_iopll|clk100}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.014
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_ap_mach_C0|e_FSM_ap.vTRIGGER
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_ap_mach_C0|e_FSM_ap.vTRIGGER
|
|
Info (332115): Launch Clock : u0|dcp_iopll|dcp_iopll|clk100
|
|
Info (332115): Latch Clock : u0|dcp_iopll|dcp_iopll|clk100
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 4.861 4.861 R clock network delay
|
|
Info (332115): 4.861 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_ap_mach_C0|e_FSM_ap.vTRIGGER
|
|
Info (332115): 4.973 0.112 FF uTco fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_ap_mach_C0|e_FSM_ap.vTRIGGER|q
|
|
Info (332115): 4.973 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_ap_mach_C0|i66~0|datae
|
|
Info (332115): 5.128 0.155 FF CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_ap_mach_C0|i66~0|combout
|
|
Info (332115): 5.128 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_ap_mach_C0|e_FSM_ap.vTRIGGER|d
|
|
Info (332115): 5.128 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_ap_mach_C0|e_FSM_ap.vTRIGGER
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 5.625 5.625 R clock network delay
|
|
Info (332115): 4.861 -0.764 clock pessimism removed
|
|
Info (332115): 4.861 0.000 clock uncertainty
|
|
Info (332115): 5.114 0.253 uTh fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_ap_mach_C0|e_FSM_ap.vTRIGGER
|
|
Info (332115): Data Arrival Time : 5.128
|
|
Info (332115): Data Required Time : 5.114
|
|
Info (332115): Slack : 0.014
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.015
|
|
Info (20696): -to_clock [get_clocks {altera_reserved_tck}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.015
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|sldfabric|\jtag_hub_gen:real_sld_jtag_hub|jtag_ir_reg[8]
|
|
Info (332115): To Node : auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|sldfabric|\jtag_hub_gen:real_sld_jtag_hub|jtag_ir_reg[7]
|
|
Info (332115): Launch Clock : altera_reserved_tck
|
|
Info (332115): Latch Clock : altera_reserved_tck
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 1.778 1.778 R clock network delay
|
|
Info (332115): 1.778 0.000 auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|sldfabric|\jtag_hub_gen:real_sld_jtag_hub|jtag_ir_reg[8]
|
|
Info (332115): 1.885 0.107 FF uTco auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|sldfabric|\jtag_hub_gen:real_sld_jtag_hub|jtag_ir_reg[8]|q
|
|
Info (332115): 2.043 0.158 FF CELL High Speed auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|sldfabric|\jtag_hub_gen:real_sld_jtag_hub|jtag_ir_reg[7]|d
|
|
Info (332115): 2.043 0.000 FF CELL High Speed auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|sldfabric|\jtag_hub_gen:real_sld_jtag_hub|jtag_ir_reg[7]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 2.192 2.192 R clock network delay
|
|
Info (332115): 1.781 -0.411 clock pessimism removed
|
|
Info (332115): 1.781 0.000 clock uncertainty
|
|
Info (332115): 2.028 0.247 uTh auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|sldfabric|\jtag_hub_gen:real_sld_jtag_hub|jtag_ir_reg[7]
|
|
Info (332115): Data Arrival Time : 2.043
|
|
Info (332115): Data Required Time : 2.028
|
|
Info (332115): Slack : 0.015
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.016
|
|
Info (20696): -to_clock [get_clocks {u0|dcp_iopll|dcp_iopll|clk25}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.016
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|generic_quad_spi_controller2_0|generic_quad_spi_controller2_0|asmi2_inst_qspi_ctrl|asmi2_qspi_interface_0|datain_reg[5]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|generic_quad_spi_controller2_0|generic_quad_spi_controller2_0|asmi2_inst_qspi_ctrl|asmi2_qspi_interface_0|datain_reg[6]
|
|
Info (332115): Launch Clock : u0|dcp_iopll|dcp_iopll|clk25 (INVERTED)
|
|
Info (332115): Latch Clock : u0|dcp_iopll|dcp_iopll|clk25 (INVERTED)
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 20.000 20.000 launch edge time
|
|
Info (332115): 24.912 4.912 F clock network delay
|
|
Info (332115): 24.912 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|generic_quad_spi_controller2_0|generic_quad_spi_controller2_0|asmi2_inst_qspi_ctrl|asmi2_qspi_interface_0|datain_reg[5]
|
|
Info (332115): 25.022 0.110 FF uTco fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|generic_quad_spi_controller2_0|generic_quad_spi_controller2_0|asmi2_inst_qspi_ctrl|asmi2_qspi_interface_0|datain_reg[5]|q
|
|
Info (332115): 25.190 0.168 FF CELL Low Power fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|generic_quad_spi_controller2_0|generic_quad_spi_controller2_0|asmi2_inst_qspi_ctrl|asmi2_qspi_interface_0|datain_reg[6]|d
|
|
Info (332115): 25.190 0.000 FF CELL Low Power fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|generic_quad_spi_controller2_0|generic_quad_spi_controller2_0|asmi2_inst_qspi_ctrl|asmi2_qspi_interface_0|datain_reg[6]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 20.000 20.000 latch edge time
|
|
Info (332115): 25.705 5.705 F clock network delay
|
|
Info (332115): 24.912 -0.793 clock pessimism removed
|
|
Info (332115): 24.912 0.000 clock uncertainty
|
|
Info (332115): 25.174 0.262 uTh fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|generic_quad_spi_controller2_0|generic_quad_spi_controller2_0|asmi2_inst_qspi_ctrl|asmi2_qspi_interface_0|datain_reg[6]
|
|
Info (332115): Data Arrival Time : 25.190
|
|
Info (332115): Data Required Time : 25.174
|
|
Info (332115): Slack : 0.016
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.017
|
|
Info (20696): -to_clock [get_clocks {mem|ddr4a|ddr4a_core_usr_clk}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.017
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_green_bs|ddr4a_avmm_bridge|ddr_avmm_bridge|wr_reg_writedata[90]
|
|
Info (332115): To Node : fpga_top|inst_green_bs|ddr4a_avmm_bridge|ddr_avmm_bridge|cmd_writedata[90]
|
|
Info (332115): Launch Clock : mem|ddr4a|ddr4a_core_usr_clk
|
|
Info (332115): Latch Clock : mem|ddr4a|ddr4a_core_usr_clk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.117 0.117 launch edge time
|
|
Info (332115): 1.325 1.208 R clock network delay
|
|
Info (332115): 1.325 0.000 fpga_top|inst_green_bs|ddr4a_avmm_bridge|ddr_avmm_bridge|wr_reg_writedata[90]
|
|
Info (332115): 1.423 0.098 FF uTco fpga_top|inst_green_bs|ddr4a_avmm_bridge|ddr_avmm_bridge|wr_reg_writedata[90]|q
|
|
Info (332115): 1.583 0.160 FF CELL High Speed fpga_top|inst_green_bs|ddr4a_avmm_bridge|ddr_avmm_bridge|cmd_writedata[90]|d
|
|
Info (332115): 1.583 0.000 FF CELL High Speed fpga_top|inst_green_bs|ddr4a_avmm_bridge|ddr_avmm_bridge|cmd_writedata[90]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.117 0.117 latch edge time
|
|
Info (332115): 1.815 1.698 R clock network delay
|
|
Info (332115): 1.325 -0.490 clock pessimism removed
|
|
Info (332115): 1.325 0.000 clock uncertainty
|
|
Info (332115): 1.566 0.241 uTh fpga_top|inst_green_bs|ddr4a_avmm_bridge|ddr_avmm_bridge|cmd_writedata[90]
|
|
Info (332115): Data Arrival Time : 1.583
|
|
Info (332115): Data Required Time : 1.566
|
|
Info (332115): Slack : 0.017
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.018
|
|
Info (20696): -to_clock [get_clocks {PCIE_REFCLK}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.018
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|ltssm_state_sync_inst|resync_chains[2].sync_r[0]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|ltssm_state_sync_inst|resync_chains[2].sync_r[1]
|
|
Info (332115): Launch Clock : PCIE_REFCLK
|
|
Info (332115): Latch Clock : PCIE_REFCLK
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 3.104 3.104 R clock network delay
|
|
Info (332115): 3.104 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|ltssm_state_sync_inst|resync_chains[2].sync_r[0]
|
|
Info (332115): 3.201 0.097 FF uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|ltssm_state_sync_inst|resync_chains[2].sync_r[0]|q
|
|
Info (332115): 3.361 0.160 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|ltssm_state_sync_inst|resync_chains[2].sync_r[1]|d
|
|
Info (332115): 3.361 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|ltssm_state_sync_inst|resync_chains[2].sync_r[1]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 3.461 3.461 R clock network delay
|
|
Info (332115): 3.104 -0.357 clock pessimism removed
|
|
Info (332115): 3.104 0.000 clock uncertainty
|
|
Info (332115): 3.343 0.239 uTh fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|ltssm_state_sync_inst|resync_chains[2].sync_r[1]
|
|
Info (332115): Data Arrival Time : 3.361
|
|
Info (332115): Data Required Time : 3.343
|
|
Info (332115): Slack : 0.018
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.018
|
|
Info (20696): -to_clock [get_clocks {hssi_pll_t_outclk1}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.018
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[1].ct0|dout_r[1]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[1].ct0|dout_r[1]
|
|
Info (332115): Launch Clock : hssi_pll_t_outclk1
|
|
Info (332115): Latch Clock : hssi_pll_t_outclk1
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 2.411 2.411 R clock network delay
|
|
Info (332115): 2.411 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[1].ct0|dout_r[1]
|
|
Info (332115): 2.512 0.101 FF uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[1].ct0|dout_r[1]|q
|
|
Info (332115): 2.512 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[1].ct0|t1|dout|datae
|
|
Info (332115): 2.667 0.155 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[1].ct0|t1|dout|combout
|
|
Info (332115): 2.667 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[1].ct0|dout_r[1]|d
|
|
Info (332115): 2.667 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[1].ct0|dout_r[1]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 2.674 2.674 R clock network delay
|
|
Info (332115): 2.411 -0.263 clock pessimism removed
|
|
Info (332115): 2.411 0.000 clock uncertainty
|
|
Info (332115): 2.649 0.238 uTh fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[1].ct0|dout_r[1]
|
|
Info (332115): Data Arrival Time : 2.667
|
|
Info (332115): Data Required Time : 2.649
|
|
Info (332115): Slack : 0.018
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.019
|
|
Info (20696): -to_clock [get_clocks {filtered_sclk_negedge}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.019
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MOSIctl|wrshiftreg[0]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MOSIctl|wrshiftreg[1]
|
|
Info (332115): Launch Clock : filtered_sclk_negedge
|
|
Info (332115): Latch Clock : filtered_sclk_negedge
|
|
Info (332115): Exception : dcp_bbs.sdc:3040: set_multicycle_path -hold -to [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MOSIctl|wrshiftreg[1]}] 1
|
|
Info (332115): Multicycle - Setup Start : 2
|
|
Info (332115): Multicycle - Hold Start : 1
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 0.120 0.120 R clock network delay
|
|
Info (332115): 0.120 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MOSIctl|wrshiftreg[0]
|
|
Info (332115): 0.224 0.104 FF uTco fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MOSIctl|wrshiftreg[0]|q
|
|
Info (332115): 0.390 0.166 FF CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MOSIctl|wrshiftreg[1]|d
|
|
Info (332115): 0.390 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MOSIctl|wrshiftreg[1]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 0.144 0.144 R clock network delay
|
|
Info (332115): 0.123 -0.021 clock pessimism removed
|
|
Info (332115): 0.371 0.248 uTh fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MOSIctl|wrshiftreg[1]
|
|
Info (332115): Data Arrival Time : 0.390
|
|
Info (332115): Data Required Time : 0.371
|
|
Info (332115): Slack : 0.019
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.019
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_clk}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.019
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[7].ct0|dout_r[1]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[7].ct0|dout_r[1]
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_clk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_clk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 2.939 2.939 R clock network delay
|
|
Info (332115): 2.939 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[7].ct0|dout_r[1]
|
|
Info (332115): 3.037 0.098 FF uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[7].ct0|dout_r[1]|q
|
|
Info (332115): 3.037 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[7].ct0|t1|dout|datae
|
|
Info (332115): 3.192 0.155 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[7].ct0|t1|dout|combout
|
|
Info (332115): 3.192 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[7].ct0|dout_r[1]|d
|
|
Info (332115): 3.192 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[7].ct0|dout_r[1]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 3.853 3.853 R clock network delay
|
|
Info (332115): 2.939 -0.914 clock pessimism removed
|
|
Info (332115): 2.939 0.000 clock uncertainty
|
|
Info (332115): 3.173 0.234 uTh fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[7].ct0|dout_r[1]
|
|
Info (332115): Data Arrival Time : 3.192
|
|
Info (332115): Data Required Time : 3.173
|
|
Info (332115): Slack : 0.019
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.019
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|rx_pma_clk}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.019
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_prbs_err_sync|resync_chains[0].sync_r[0]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_prbs_err_sync|resync_chains[0].sync_r[1]
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|rx_pma_clk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|rx_pma_clk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 2.848 2.848 R clock network delay
|
|
Info (332115): 2.848 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_prbs_err_sync|resync_chains[0].sync_r[0]
|
|
Info (332115): 2.945 0.097 FF uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_prbs_err_sync|resync_chains[0].sync_r[0]|q
|
|
Info (332115): 3.105 0.160 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_prbs_err_sync|resync_chains[0].sync_r[1]|d
|
|
Info (332115): 3.105 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_prbs_err_sync|resync_chains[0].sync_r[1]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 3.767 3.767 R clock network delay
|
|
Info (332115): 2.848 -0.919 clock pessimism removed
|
|
Info (332115): 2.848 0.000 clock uncertainty
|
|
Info (332115): 3.086 0.238 uTh fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_prbs_err_sync|resync_chains[0].sync_r[1]
|
|
Info (332115): Data Arrival Time : 3.105
|
|
Info (332115): Data Required Time : 3.086
|
|
Info (332115): Slack : 0.019
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.019
|
|
Info (20696): -to_clock [get_clocks {hssi_pll_r_0_outclk0}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.019
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[2].ct0|dout_r[3]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[2].ct0|dout_r[3]
|
|
Info (332115): Launch Clock : hssi_pll_r_0_outclk0
|
|
Info (332115): Latch Clock : hssi_pll_r_0_outclk0
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 2.574 2.574 R clock network delay
|
|
Info (332115): 2.574 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[2].ct0|dout_r[3]
|
|
Info (332115): 2.678 0.104 FF uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[2].ct0|dout_r[3]|q
|
|
Info (332115): 2.678 0.000 FF CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[2].ct0|t3|dout|datae
|
|
Info (332115): 2.840 0.162 FF CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[2].ct0|t3|dout|combout
|
|
Info (332115): 2.840 0.000 FF CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[2].ct0|dout_r[3]|d
|
|
Info (332115): 2.840 0.000 FF CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[2].ct0|dout_r[3]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 2.871 2.871 R clock network delay
|
|
Info (332115): 2.575 -0.296 clock pessimism removed
|
|
Info (332115): 2.575 0.000 clock uncertainty
|
|
Info (332115): 2.821 0.246 uTh fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[2].ct0|dout_r[3]
|
|
Info (332115): Data Arrival Time : 2.840
|
|
Info (332115): Data Required Time : 2.821
|
|
Info (332115): Slack : 0.019
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.019
|
|
Info (20696): -to_clock [get_clocks {mem|ddr4a|ddr4a_core_cal_slave_clk}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.019
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : mem|ddr4b|ddr4b|arch|arch_inst|non_hps.core_clks_rsts_inst|per_if_cal_slave_reset_sync[8]
|
|
Info (332115): To Node : mem|ddr4b|ddr4b|arch|arch_inst|non_hps.core_clks_rsts_inst|per_if_cal_slave_reset_sync[9]
|
|
Info (332115): Launch Clock : mem|ddr4a|ddr4a_core_cal_slave_clk
|
|
Info (332115): Latch Clock : mem|ddr4a|ddr4a_core_cal_slave_clk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 3.231 3.231 R clock network delay
|
|
Info (332115): 3.231 0.000 mem|ddr4b|ddr4b|arch|arch_inst|non_hps.core_clks_rsts_inst|per_if_cal_slave_reset_sync[8]
|
|
Info (332115): 3.329 0.098 FF uTco mem|ddr4b|ddr4b|arch|arch_inst|non_hps.core_clks_rsts_inst|per_if_cal_slave_reset_sync[8]|q
|
|
Info (332115): 3.489 0.160 FF CELL High Speed mem|ddr4b|ddr4b|arch|arch_inst|non_hps.core_clks_rsts_inst|per_if_cal_slave_reset_sync[9]|d
|
|
Info (332115): 3.489 0.000 FF CELL High Speed mem|ddr4b|ddr4b|arch|arch_inst|non_hps.core_clks_rsts_inst|per_if_cal_slave_reset_sync[9]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 3.776 3.776 R clock network delay
|
|
Info (332115): 3.231 -0.545 clock pessimism removed
|
|
Info (332115): 3.231 0.000 clock uncertainty
|
|
Info (332115): 3.470 0.239 uTh mem|ddr4b|ddr4b|arch|arch_inst|non_hps.core_clks_rsts_inst|per_if_cal_slave_reset_sync[9]
|
|
Info (332115): Data Arrival Time : 3.489
|
|
Info (332115): Data Required Time : 3.470
|
|
Info (332115): Slack : 0.019
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.020
|
|
Info (20696): -to_clock [get_clocks {DDR4_RefClk}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.020
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|use_counter_lock.counter_lock_gen_master.pll_ref_clk_reset_n_sync_rr
|
|
Info (332115): To Node : mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|use_counter_lock.counter_lock_gen_master.pll_ref_clk_reset_n_sync_rrr
|
|
Info (332115): Launch Clock : DDR4_RefClk
|
|
Info (332115): Latch Clock : DDR4_RefClk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 2.343 2.343 R clock network delay
|
|
Info (332115): 2.343 0.000 mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|use_counter_lock.counter_lock_gen_master.pll_ref_clk_reset_n_sync_rr
|
|
Info (332115): 2.441 0.098 FF uTco mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|use_counter_lock.counter_lock_gen_master.pll_ref_clk_reset_n_sync_rr|q
|
|
Info (332115): 2.601 0.160 FF CELL High Speed mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|use_counter_lock.counter_lock_gen_master.pll_ref_clk_reset_n_sync_rrr|d
|
|
Info (332115): 2.601 0.000 FF CELL High Speed mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|use_counter_lock.counter_lock_gen_master.pll_ref_clk_reset_n_sync_rrr
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 2.537 2.537 R clock network delay
|
|
Info (332115): 2.342 -0.195 clock pessimism removed
|
|
Info (332115): 2.342 0.000 clock uncertainty
|
|
Info (332115): 2.581 0.239 uTh mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|use_counter_lock.counter_lock_gen_master.pll_ref_clk_reset_n_sync_rrr
|
|
Info (332115): Data Arrival Time : 2.601
|
|
Info (332115): Data Required Time : 2.581
|
|
Info (332115): Slack : 0.020
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.020
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_div_clk}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.020
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[4].ct0|dout_r[5]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[4].ct0|dout_r[5]
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_div_clk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_div_clk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 4.536 4.536 R clock network delay
|
|
Info (332115): 4.536 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[4].ct0|dout_r[5]
|
|
Info (332115): 4.634 0.098 FF uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[4].ct0|dout_r[5]|q
|
|
Info (332115): 4.634 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[4].ct0|t5|dout|datae
|
|
Info (332115): 4.789 0.155 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[4].ct0|t5|dout|combout
|
|
Info (332115): 4.789 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[4].ct0|dout_r[5]|d
|
|
Info (332115): 4.789 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[4].ct0|dout_r[5]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 5.775 5.775 R clock network delay
|
|
Info (332115): 4.536 -1.239 clock pessimism removed
|
|
Info (332115): 4.536 0.000 clock uncertainty
|
|
Info (332115): 4.769 0.233 uTh fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[4].ct0|dout_r[5]
|
|
Info (332115): Data Arrival Time : 4.789
|
|
Info (332115): Data Required Time : 4.769
|
|
Info (332115): Slack : 0.020
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.021
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk0}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.021
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_green_bs|uClk_usrDiv2_q1
|
|
Info (332115): To Node : fpga_top|inst_green_bs|uClk_usrDiv2_q2
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk0
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk0
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 3.250 3.250 R clock network delay
|
|
Info (332115): 3.250 0.000 fpga_top|inst_green_bs|uClk_usrDiv2_q1
|
|
Info (332115): 3.350 0.100 FF uTco fpga_top|inst_green_bs|uClk_usrDiv2_q1|q
|
|
Info (332115): 3.350 0.000 FF CELL High Speed fpga_top|inst_green_bs|uClk_usrDiv2_q2~0|datae
|
|
Info (332115): 3.507 0.157 FR CELL High Speed fpga_top|inst_green_bs|uClk_usrDiv2_q2~0|combout
|
|
Info (332115): 3.507 0.000 RR CELL High Speed fpga_top|inst_green_bs|uClk_usrDiv2_q2|d
|
|
Info (332115): 3.507 0.000 RR CELL High Speed fpga_top|inst_green_bs|uClk_usrDiv2_q2
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 3.880 3.880 R clock network delay
|
|
Info (332115): 3.250 -0.630 clock pessimism removed
|
|
Info (332115): 3.250 0.000 clock uncertainty
|
|
Info (332115): 3.486 0.236 uTh fpga_top|inst_green_bs|uClk_usrDiv2_q2
|
|
Info (332115): Data Arrival Time : 3.507
|
|
Info (332115): Data Required Time : 3.486
|
|
Info (332115): Slack : 0.021
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.021
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|tx_pma_div_clk}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.021
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[5].ct0|dout_r[3]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[5].ct0|dout_r[3]
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|tx_pma_div_clk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|tx_pma_div_clk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 4.163 4.163 R clock network delay
|
|
Info (332115): 4.163 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[5].ct0|dout_r[3]
|
|
Info (332115): 4.260 0.097 FF uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[5].ct0|dout_r[3]|q
|
|
Info (332115): 4.260 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[5].ct0|t3|dout|datae
|
|
Info (332115): 4.415 0.155 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[5].ct0|t3|dout|combout
|
|
Info (332115): 4.415 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[5].ct0|dout_r[3]|d
|
|
Info (332115): 4.415 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[5].ct0|dout_r[3]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 5.300 5.300 R clock network delay
|
|
Info (332115): 4.164 -1.136 clock pessimism removed
|
|
Info (332115): 4.164 0.000 clock uncertainty
|
|
Info (332115): 4.394 0.230 uTh fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[5].ct0|dout_r[3]
|
|
Info (332115): Data Arrival Time : 4.415
|
|
Info (332115): Data Required Time : 4.394
|
|
Info (332115): Slack : 0.021
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.021
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|rx_pma_clk}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.021
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_consecutive_error[0]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_consecutive_error[0]
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|rx_pma_clk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|rx_pma_clk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 2.938 2.938 R clock network delay
|
|
Info (332115): 2.938 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_consecutive_error[0]
|
|
Info (332115): 3.035 0.097 FF uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_consecutive_error[0]|q
|
|
Info (332115): 3.035 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|i41~1|datae
|
|
Info (332115): 3.189 0.154 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|i41~1|combout
|
|
Info (332115): 3.189 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_consecutive_error[0]|d
|
|
Info (332115): 3.189 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_consecutive_error[0]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 3.854 3.854 R clock network delay
|
|
Info (332115): 2.938 -0.916 clock pessimism removed
|
|
Info (332115): 2.938 0.000 clock uncertainty
|
|
Info (332115): 3.168 0.230 uTh fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_consecutive_error[0]
|
|
Info (332115): Data Arrival Time : 3.189
|
|
Info (332115): Data Required Time : 3.168
|
|
Info (332115): Slack : 0.021
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.022
|
|
Info (20696): -to_clock [get_clocks {hssi_pll_t_outclk0}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.022
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[3].ct0|dout_r[5]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[3].ct0|dout_r[5]
|
|
Info (332115): Launch Clock : hssi_pll_t_outclk0
|
|
Info (332115): Latch Clock : hssi_pll_t_outclk0
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 2.431 2.431 R clock network delay
|
|
Info (332115): 2.431 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[3].ct0|dout_r[5]
|
|
Info (332115): 2.534 0.103 FF uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[3].ct0|dout_r[5]|q
|
|
Info (332115): 2.534 0.000 FF CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[3].ct0|t5|dout|datae
|
|
Info (332115): 2.696 0.162 FF CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[3].ct0|t5|dout|combout
|
|
Info (332115): 2.696 0.000 FF CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[3].ct0|dout_r[5]|d
|
|
Info (332115): 2.696 0.000 FF CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[3].ct0|dout_r[5]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 2.698 2.698 R clock network delay
|
|
Info (332115): 2.432 -0.266 clock pessimism removed
|
|
Info (332115): 2.432 0.000 clock uncertainty
|
|
Info (332115): 2.674 0.242 uTh fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[3].ct0|dout_r[5]
|
|
Info (332115): Data Arrival Time : 2.696
|
|
Info (332115): Data Required Time : 2.674
|
|
Info (332115): Slack : 0.022
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.023
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|rx_pma_clk}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.023
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_consecutive_error[0]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_consecutive_error[0]
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|rx_pma_clk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|rx_pma_clk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 2.913 2.913 R clock network delay
|
|
Info (332115): 2.913 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_consecutive_error[0]
|
|
Info (332115): 3.010 0.097 FF uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_consecutive_error[0]|q
|
|
Info (332115): 3.010 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|i41~1|datae
|
|
Info (332115): 3.168 0.158 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|i41~1|combout
|
|
Info (332115): 3.168 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_consecutive_error[0]|d
|
|
Info (332115): 3.168 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_consecutive_error[0]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 3.829 3.829 R clock network delay
|
|
Info (332115): 2.913 -0.916 clock pessimism removed
|
|
Info (332115): 2.913 0.000 clock uncertainty
|
|
Info (332115): 3.145 0.232 uTh fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_consecutive_error[0]
|
|
Info (332115): Data Arrival Time : 3.168
|
|
Info (332115): Data Required Time : 3.145
|
|
Info (332115): Slack : 0.023
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.023
|
|
Info (20696): -to_clock [get_clocks {hssi_pll_r_0_outclk1}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.023
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[0].ct0|dout_r[4]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[0].ct0|dout_r[4]
|
|
Info (332115): Launch Clock : hssi_pll_r_0_outclk1
|
|
Info (332115): Latch Clock : hssi_pll_r_0_outclk1
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 2.560 2.560 R clock network delay
|
|
Info (332115): 2.560 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[0].ct0|dout_r[4]
|
|
Info (332115): 2.663 0.103 FF uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[0].ct0|dout_r[4]|q
|
|
Info (332115): 2.663 0.000 FF CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[0].ct0|t4|dout|datae
|
|
Info (332115): 2.825 0.162 FF CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[0].ct0|t4|dout|combout
|
|
Info (332115): 2.825 0.000 FF CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[0].ct0|dout_r[4]|d
|
|
Info (332115): 2.825 0.000 FF CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[0].ct0|dout_r[4]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 2.861 2.861 R clock network delay
|
|
Info (332115): 2.560 -0.301 clock pessimism removed
|
|
Info (332115): 2.560 0.000 clock uncertainty
|
|
Info (332115): 2.802 0.242 uTh fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[0].ct0|dout_r[4]
|
|
Info (332115): Data Arrival Time : 2.825
|
|
Info (332115): Data Required Time : 2.802
|
|
Info (332115): Slack : 0.023
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.024
|
|
Info (20696): -to_clock [get_clocks {ETH_RefClk}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.024
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[6].ct0|dout_r[1]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[6].ct0|dout_r[1]
|
|
Info (332115): Launch Clock : ETH_RefClk
|
|
Info (332115): Latch Clock : ETH_RefClk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 3.071 3.071 R clock network delay
|
|
Info (332115): 3.071 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[6].ct0|dout_r[1]
|
|
Info (332115): 3.174 0.103 FF uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[6].ct0|dout_r[1]|q
|
|
Info (332115): 3.174 0.000 FF CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[6].ct0|t1|dout|datae
|
|
Info (332115): 3.339 0.165 FF CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[6].ct0|t1|dout|combout
|
|
Info (332115): 3.339 0.000 FF CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[6].ct0|dout_r[1]|d
|
|
Info (332115): 3.339 0.000 FF CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[6].ct0|dout_r[1]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 3.436 3.436 R clock network delay
|
|
Info (332115): 3.072 -0.364 clock pessimism removed
|
|
Info (332115): 3.072 0.000 clock uncertainty
|
|
Info (332115): 3.315 0.243 uTh fpga_top|inst_fiu_top|inst_hssi_ctrl|fmon0|lp0[6].ct0|dout_r[1]
|
|
Info (332115): Data Arrival Time : 3.339
|
|
Info (332115): Data Required Time : 3.315
|
|
Info (332115): Slack : 0.024
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.029
|
|
Info (20696): -to_clock [get_clocks {u0|dcp_iopll|dcp_iopll|clk50}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.029
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_green_bs|pClkDiv4_q1
|
|
Info (332115): To Node : fpga_top|inst_green_bs|pClkDiv4_q2
|
|
Info (332115): Launch Clock : u0|dcp_iopll|dcp_iopll|clk50
|
|
Info (332115): Latch Clock : u0|dcp_iopll|dcp_iopll|clk50
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 4.902 4.902 R clock network delay
|
|
Info (332115): 4.902 0.000 fpga_top|inst_green_bs|pClkDiv4_q1
|
|
Info (332115): 5.007 0.105 FF uTco fpga_top|inst_green_bs|pClkDiv4_q1|q
|
|
Info (332115): 5.007 0.000 FF CELL High Speed fpga_top|inst_green_bs|pClkDiv4_q2~0|datae
|
|
Info (332115): 5.166 0.159 FR CELL High Speed fpga_top|inst_green_bs|pClkDiv4_q2~0|combout
|
|
Info (332115): 5.166 0.000 RR CELL High Speed fpga_top|inst_green_bs|pClkDiv4_q2|d
|
|
Info (332115): 5.166 0.000 RR CELL High Speed fpga_top|inst_green_bs|pClkDiv4_q2
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 5.679 5.679 R clock network delay
|
|
Info (332115): 4.903 -0.776 clock pessimism removed
|
|
Info (332115): 4.903 0.000 clock uncertainty
|
|
Info (332115): 5.137 0.234 uTh fpga_top|inst_green_bs|pClkDiv4_q2
|
|
Info (332115): Data Arrival Time : 5.166
|
|
Info (332115): Data Required Time : 5.137
|
|
Info (332115): Slack : 0.029
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.079
|
|
Info (20696): -to_clock [get_clocks {mem|ddr4a|ddr4a_phy_clk_l_2}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.079
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : mem|ddr4a_bridge|ddr_avmm_bridge|cmd_writedata[414]
|
|
Info (332115): To Node : mem|ddr4a|ddr4a|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[0].lane_gen[3].lane_inst~phy_reg1
|
|
Info (332115): Launch Clock : mem|ddr4a|ddr4a_core_usr_clk
|
|
Info (332115): Latch Clock : mem|ddr4a|ddr4a_phy_clk_l_2
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.117 0.117 launch edge time
|
|
Info (332115): 1.371 1.254 R clock network delay
|
|
Info (332115): 1.371 0.000 mem|ddr4a_bridge|ddr_avmm_bridge|cmd_writedata[414]
|
|
Info (332115): 1.469 0.098 RR uTco mem|ddr4a_bridge|ddr_avmm_bridge|cmd_writedata[414]|q
|
|
Info (332115): 1.531 0.062 RR CELL High Speed mem|ddr4a_bridge|ddr_avmm_bridge|cmd_writedata[414]~la_lab/laboutt[8]
|
|
Info (332115): 1.777 0.246 RR IC High Speed mem|ddr4a_avmm_chkr|avm_writedata[414]~246|datac
|
|
Info (332115): 1.839 0.062 RR CELL High Speed mem|ddr4a_avmm_chkr|avm_writedata[414]~246|combout
|
|
Info (332115): 1.840 0.001 RR CELL High Speed mem|ddr4a_avmm_chkr|avm_writedata[414]~246~la_lab/laboutb[19]
|
|
Info (332115): 2.239 0.399 RR IC High Speed mem|ddr4a|ddr4a|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[0].lane_gen[3].lane_inst|data_from_core[22]
|
|
Info (332115): 2.239 0.000 RR CELL mem|ddr4a|ddr4a|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[0].lane_gen[3].lane_inst~phy_reg1
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.117 0.117 latch edge time
|
|
Info (332115): 1.744 1.627 R clock network delay
|
|
Info (332115): 1.650 -0.094 clock pessimism removed
|
|
Info (332115): 1.970 0.320 clock uncertainty
|
|
Info (332115): 2.160 0.190 uTh mem|ddr4a|ddr4a|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[0].lane_gen[3].lane_inst~phy_reg1
|
|
Info (332115): Data Arrival Time : 2.239
|
|
Info (332115): Data Required Time : 2.160
|
|
Info (332115): Slack : 0.079
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.081
|
|
Info (20696): -to_clock [get_clocks {mem|ddr4b|ddr4b_phy_clk_l_0}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.081
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : mem|ddr4b_bridge|ddr_avmm_bridge|cmd_address[23]
|
|
Info (332115): To Node : mem|ddr4b|ddr4b|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[1].tile_ctrl_inst~hmc_reg1
|
|
Info (332115): Launch Clock : mem|ddr4a|ddr4a_core_usr_clk
|
|
Info (332115): Latch Clock : mem|ddr4b|ddr4b_phy_clk_l_0
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.117 0.117 launch edge time
|
|
Info (332115): 1.296 1.179 R clock network delay
|
|
Info (332115): 1.296 0.000 mem|ddr4b_bridge|ddr_avmm_bridge|cmd_address[23]
|
|
Info (332115): 1.394 0.098 RR uTco mem|ddr4b_bridge|ddr_avmm_bridge|cmd_address[23]|q
|
|
Info (332115): 1.440 0.046 RR CELL High Speed mem|ddr4b_bridge|ddr_avmm_bridge|cmd_address[23]~la_mlab/laboutb[13]
|
|
Info (332115): 1.702 0.262 RR IC High Speed mem|ddr4b_emif_address_mux[23]~23|datab
|
|
Info (332115): 1.809 0.107 RR CELL High Speed mem|ddr4b_emif_address_mux[23]~23|combout
|
|
Info (332115): 1.811 0.002 RR CELL High Speed mem|ddr4b_emif_address_mux[23]~23~la_mlab/laboutt[12]
|
|
Info (332115): 2.274 0.463 RR IC High Speed mem|ddr4b|ddr4b|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[1].tile_ctrl_inst|core2ctl_avl0[25]
|
|
Info (332115): 2.274 0.000 RR CELL mem|ddr4b|ddr4b|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[1].tile_ctrl_inst~hmc_reg1
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.117 0.117 latch edge time
|
|
Info (332115): 1.694 1.577 R clock network delay
|
|
Info (332115): 1.642 -0.052 clock pessimism removed
|
|
Info (332115): 1.962 0.320 clock uncertainty
|
|
Info (332115): 2.193 0.231 uTh mem|ddr4b|ddr4b|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[1].tile_ctrl_inst~hmc_reg1
|
|
Info (332115): Data Arrival Time : 2.274
|
|
Info (332115): Data Required Time : 2.193
|
|
Info (332115): Slack : 0.081
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.084
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_bonding_clocks[0]}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.084
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|sta_rx_clk2_by4_1
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs~byte_deserializer_pcs_clk_div_by_4_txclk_reg.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|rx_clk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|tx_bonding_clocks[0]
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 1.692 1.692 R clock network delay
|
|
Info (332115): 1.692 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|sta_rx_clk2_by4_1
|
|
Info (332115): 1.692 0.000 RR CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs~byte_deserializer_pcs_clk_div_by_4_txclk_reg.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 2.251 2.251 R clock network delay
|
|
Info (332115): 1.516 -0.735 clock pessimism removed
|
|
Info (332115): 1.608 0.092 uTh fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs~byte_deserializer_pcs_clk_div_by_4_txclk_reg.reg
|
|
Info (332115): Data Arrival Time : 1.692
|
|
Info (332115): Data Required Time : 1.608
|
|
Info (332115): Slack : 0.084
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.085
|
|
Info (20696): -to_clock [get_clocks {mem|ddr4b|ddr4b_phy_clk_l_1}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.085
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : mem|ddr4b_bridge|ddr_avmm_bridge|cmd_writedata[305]
|
|
Info (332115): To Node : mem|ddr4b|ddr4b|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[2].lane_gen[1].lane_inst~phy_reg1
|
|
Info (332115): Launch Clock : mem|ddr4a|ddr4a_core_usr_clk
|
|
Info (332115): Latch Clock : mem|ddr4b|ddr4b_phy_clk_l_1
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.117 0.117 launch edge time
|
|
Info (332115): 1.303 1.186 R clock network delay
|
|
Info (332115): 1.303 0.000 mem|ddr4b_bridge|ddr_avmm_bridge|cmd_writedata[305]
|
|
Info (332115): 1.400 0.097 RR uTco mem|ddr4b_bridge|ddr_avmm_bridge|cmd_writedata[305]|q
|
|
Info (332115): 1.444 0.044 RR CELL High Speed mem|ddr4b_bridge|ddr_avmm_bridge|cmd_writedata[305]~la_mlab/laboutt[14]
|
|
Info (332115): 1.682 0.238 RR IC High Speed mem|ddr4b_avmm_chkr|avm_writedata[0]~396|datae
|
|
Info (332115): 1.722 0.040 RR CELL High Speed mem|ddr4b_avmm_chkr|avm_writedata[0]~396|combout
|
|
Info (332115): 1.724 0.002 RR CELL High Speed mem|ddr4b_avmm_chkr|avm_writedata[0]~396~la_mlab/laboutt[2]
|
|
Info (332115): 2.227 0.503 RR IC High Speed mem|ddr4b|ddr4b|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[2].lane_gen[1].lane_inst|data_from_core[76]
|
|
Info (332115): 2.227 0.000 RR CELL mem|ddr4b|ddr4b|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[2].lane_gen[1].lane_inst~phy_reg1
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.117 0.117 latch edge time
|
|
Info (332115): 1.694 1.577 R clock network delay
|
|
Info (332115): 1.642 -0.052 clock pessimism removed
|
|
Info (332115): 1.962 0.320 clock uncertainty
|
|
Info (332115): 2.142 0.180 uTh mem|ddr4b|ddr4b|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[2].lane_gen[1].lane_inst~phy_reg1
|
|
Info (332115): Data Arrival Time : 2.227
|
|
Info (332115): Data Required Time : 2.142
|
|
Info (332115): Slack : 0.085
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.088
|
|
Info (20696): -to_clock [get_clocks {mem|ddr4b|ddr4b_phy_clk_l_2}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.088
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : mem|ddr4b_bridge|ddr_avmm_bridge|cmd_writedata[87]
|
|
Info (332115): To Node : mem|ddr4b|ddr4b|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[0].lane_gen[2].lane_inst~phy_reg1
|
|
Info (332115): Launch Clock : mem|ddr4a|ddr4a_core_usr_clk
|
|
Info (332115): Latch Clock : mem|ddr4b|ddr4b_phy_clk_l_2
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.117 0.117 launch edge time
|
|
Info (332115): 1.302 1.185 R clock network delay
|
|
Info (332115): 1.302 0.000 mem|ddr4b_bridge|ddr_avmm_bridge|cmd_writedata[87]
|
|
Info (332115): 1.399 0.097 RR uTco mem|ddr4b_bridge|ddr_avmm_bridge|cmd_writedata[87]|q
|
|
Info (332115): 1.445 0.046 RR CELL High Speed mem|ddr4b_bridge|ddr_avmm_bridge|cmd_writedata[87]~la_lab/laboutb[13]
|
|
Info (332115): 1.737 0.292 RR IC High Speed mem|ddr4b_avmm_chkr|avm_writedata[0]~185|datae
|
|
Info (332115): 1.783 0.046 RR CELL High Speed mem|ddr4b_avmm_chkr|avm_writedata[0]~185|combout
|
|
Info (332115): 1.784 0.001 RR CELL High Speed mem|ddr4b_avmm_chkr|avm_writedata[0]~185~la_lab/laboutb[7]
|
|
Info (332115): 2.243 0.459 RR IC High Speed mem|ddr4b|ddr4b|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[0].lane_gen[2].lane_inst|data_from_core[49]
|
|
Info (332115): 2.243 0.000 RR CELL mem|ddr4b|ddr4b|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[0].lane_gen[2].lane_inst~phy_reg1
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.117 0.117 latch edge time
|
|
Info (332115): 1.691 1.574 R clock network delay
|
|
Info (332115): 1.639 -0.052 clock pessimism removed
|
|
Info (332115): 1.959 0.320 clock uncertainty
|
|
Info (332115): 2.155 0.196 uTh mem|ddr4b|ddr4b|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[0].lane_gen[2].lane_inst~phy_reg1
|
|
Info (332115): Data Arrival Time : 2.243
|
|
Info (332115): Data Required Time : 2.155
|
|
Info (332115): Slack : 0.088
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.092
|
|
Info (20696): -to_clock [get_clocks {fspi_sclk}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.092
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MISOctl|rdshiftreg[4]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MISOctl|rdshiftreg[5]
|
|
Info (332115): Launch Clock : fspi_sclk
|
|
Info (332115): Latch Clock : fspi_sclk
|
|
Info (332115): Exception : dcp_bbs.sdc:3007: set_multicycle_path -hold -to [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MISOctl|rdshiftreg*}] 1
|
|
Info (332115): Multicycle - Setup Start : 2
|
|
Info (332115): Multicycle - Hold Start : 1
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 3.110 3.110 R clock network delay
|
|
Info (332115): 3.110 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MISOctl|rdshiftreg[4]
|
|
Info (332115): 3.208 0.098 FF uTco fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MISOctl|rdshiftreg[4]|q
|
|
Info (332115): 3.240 0.032 FF CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MISOctl|rdshiftreg[4]~la_lab/laboutt[10]
|
|
Info (332115): 3.342 0.102 FF IC High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MISOctl|i36~2|datab
|
|
Info (332115): 3.434 0.092 FF CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MISOctl|i36~2|combout
|
|
Info (332115): 3.434 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MISOctl|rdshiftreg[5]|d
|
|
Info (332115): 3.434 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MISOctl|rdshiftreg[5]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 3.608 3.608 R clock network delay
|
|
Info (332115): 3.110 -0.498 clock pessimism removed
|
|
Info (332115): 3.110 0.000 clock uncertainty
|
|
Info (332115): 3.342 0.232 uTh fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MISOctl|rdshiftreg[5]
|
|
Info (332115): Data Arrival Time : 3.434
|
|
Info (332115): Data Required Time : 3.342
|
|
Info (332115): Slack : 0.092
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.104
|
|
Info (20696): -to_clock [get_clocks {mem|ddr4a|ddr4a_phy_clk_l_1}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.104
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : mem|ddr4a_bridge|ddr_avmm_bridge|cmd_writedata[42]
|
|
Info (332115): To Node : mem|ddr4a|ddr4a|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[2].lane_gen[0].lane_inst~phy_reg1
|
|
Info (332115): Launch Clock : mem|ddr4a|ddr4a_core_usr_clk
|
|
Info (332115): Latch Clock : mem|ddr4a|ddr4a_phy_clk_l_1
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.117 0.117 launch edge time
|
|
Info (332115): 1.341 1.224 R clock network delay
|
|
Info (332115): 1.341 0.000 mem|ddr4a_bridge|ddr_avmm_bridge|cmd_writedata[42]
|
|
Info (332115): 1.439 0.098 RR uTco mem|ddr4a_bridge|ddr_avmm_bridge|cmd_writedata[42]|q
|
|
Info (332115): 1.501 0.062 RR CELL High Speed mem|ddr4a_bridge|ddr_avmm_bridge|cmd_writedata[42]~la_lab/laboutt[8]
|
|
Info (332115): 1.800 0.299 RR IC High Speed mem|ddr4a_avmm_chkr|avm_writedata[42]~336|datac
|
|
Info (332115): 1.862 0.062 RR CELL High Speed mem|ddr4a_avmm_chkr|avm_writedata[42]~336|combout
|
|
Info (332115): 1.863 0.001 RR CELL High Speed mem|ddr4a_avmm_chkr|avm_writedata[42]~336~la_lab/laboutt[10]
|
|
Info (332115): 2.261 0.398 RR IC High Speed mem|ddr4a|ddr4a|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[2].lane_gen[0].lane_inst|data_from_core[72]
|
|
Info (332115): 2.261 0.000 RR CELL mem|ddr4a|ddr4a|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[2].lane_gen[0].lane_inst~phy_reg1
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.117 0.117 latch edge time
|
|
Info (332115): 1.743 1.626 R clock network delay
|
|
Info (332115): 1.649 -0.094 clock pessimism removed
|
|
Info (332115): 1.969 0.320 clock uncertainty
|
|
Info (332115): 2.157 0.188 uTh mem|ddr4a|ddr4a|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[2].lane_gen[0].lane_inst~phy_reg1
|
|
Info (332115): Data Arrival Time : 2.261
|
|
Info (332115): Data Required Time : 2.157
|
|
Info (332115): Slack : 0.104
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.118
|
|
Info (20696): -to_clock [get_clocks {mem|ddr4a|ddr4a_phy_clk_l_0}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.118
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : mem|ddr4a_avmm_chkr|clearing
|
|
Info (332115): To Node : mem|ddr4a|ddr4a|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[1].tile_ctrl_inst~hmc_reg1
|
|
Info (332115): Launch Clock : mem|ddr4a|ddr4a_core_usr_clk
|
|
Info (332115): Latch Clock : mem|ddr4a|ddr4a_phy_clk_l_0
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.117 0.117 launch edge time
|
|
Info (332115): 1.370 1.253 R clock network delay
|
|
Info (332115): 1.370 0.000 mem|ddr4a_avmm_chkr|clearing
|
|
Info (332115): 1.467 0.097 RR uTco mem|ddr4a_avmm_chkr|clearing|q
|
|
Info (332115): 1.513 0.046 RR CELL High Speed mem|ddr4a_avmm_chkr|clearing~la_mlab/laboutt[13]
|
|
Info (332115): 1.807 0.294 RR IC High Speed mem|ddr4a_avmm_chkr|avm_address[4]~4|dataf
|
|
Info (332115): 1.829 0.022 RF CELL High Speed mem|ddr4a_avmm_chkr|avm_address[4]~4|combout
|
|
Info (332115): 1.830 0.001 FF CELL High Speed mem|ddr4a_avmm_chkr|avm_address[4]~4~la_lab/laboutt[2]
|
|
Info (332115): 2.049 0.219 FF IC High Speed mem|ddr4a|ddr4a|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[1].tile_ctrl_inst|core2ctl_avl0[6]
|
|
Info (332115): 2.049 0.000 FF CELL mem|ddr4a|ddr4a|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[1].tile_ctrl_inst~hmc_reg1
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.117 0.117 latch edge time
|
|
Info (332115): 1.743 1.626 R clock network delay
|
|
Info (332115): 1.468 -0.275 clock pessimism removed
|
|
Info (332115): 1.691 0.223 clock uncertainty
|
|
Info (332115): 1.931 0.240 uTh mem|ddr4a|ddr4a|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[1].tile_ctrl_inst~hmc_reg1
|
|
Info (332115): Data Arrival Time : 2.049
|
|
Info (332115): Data Required Time : 1.931
|
|
Info (332115): Slack : 0.118
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.143
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|pld_clk}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.143
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_sriov_2.sriov2.sriov_bridge|altpcie_pcie_sriov2_top_inst|altpcie_sriov2_cfg_dataflow_inst|device_control_reg_max_payload_size_o[0]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~pld_clk.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|wys~CORE_CLK_OUT
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|pld_clk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 4.401 4.401 R clock network delay
|
|
Info (332115): 4.401 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_sriov_2.sriov2.sriov_bridge|altpcie_pcie_sriov2_top_inst|altpcie_sriov2_cfg_dataflow_inst|device_control_reg_max_payload_size_o[0]
|
|
Info (332115): 4.502 0.101 FF uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_sriov_2.sriov2.sriov_bridge|altpcie_pcie_sriov2_top_inst|altpcie_sriov2_cfg_dataflow_inst|device_control_reg_max_payload_size_o[0]|q
|
|
Info (332115): 4.552 0.050 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_sriov_2.sriov2.sriov_bridge|altpcie_pcie_sriov2_top_inst|altpcie_sriov2_cfg_dataflow_inst|device_control_reg_max_payload_size_o[0]~la_mlab/laboutb[8]
|
|
Info (332115): 4.936 0.384 FF IC High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|app_msi_num[0]
|
|
Info (332115): 4.936 0.000 FF CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~pld_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 5.372 5.372 R clock network delay
|
|
Info (332115): 4.596 -0.776 clock pessimism removed
|
|
Info (332115): 4.663 0.067 clock uncertainty
|
|
Info (332115): 4.793 0.130 uTh fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~pld_clk.reg
|
|
Info (332115): Data Arrival Time : 4.936
|
|
Info (332115): Data Required Time : 4.793
|
|
Info (332115): Slack : 0.143
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.355
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|avmmclk}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.355
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|channel_count[2]~RTMDUPLICATE
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Launch Clock : PCIE_REFCLK
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|avmmclk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 3.107 3.107 R clock network delay
|
|
Info (332115): 3.107 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|channel_count[2]~RTMDUPLICATE
|
|
Info (332115): 3.205 0.098 FF uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|channel_count[2]~RTMDUPLICATE|q
|
|
Info (332115): 3.237 0.032 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|channel_count[2]~RTMDUPLICATE~la_mlab/laboutt[2]
|
|
Info (332115): 3.334 0.097 FF IC High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i8~0|datab
|
|
Info (332115): 3.434 0.100 FR CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i8~0|combout
|
|
Info (332115): 3.436 0.002 RR CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i8~0~la_mlab/laboutb[15]
|
|
Info (332115): 3.914 0.478 RR IC Mixed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst|avmmwrite
|
|
Info (332115): 3.914 0.000 RR CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 3.709 3.709 R clock network delay
|
|
Info (332115): 3.383 -0.326 clock pessimism removed
|
|
Info (332115): 3.423 0.040 clock uncertainty
|
|
Info (332115): 3.559 0.136 uTh fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Arrival Time : 3.914
|
|
Info (332115): Data Required Time : 3.559
|
|
Info (332115): Slack : 0.355
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.401
|
|
Info (20696): -to_clock [get_clocks {vl_qph_user_clk_clkpsc_clk0}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.401
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[3]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[3]
|
|
Info (332115): Launch Clock : vl_qph_user_clk_clkpsc_clk0
|
|
Info (332115): Latch Clock : vl_qph_user_clk_clkpsc_clk0
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 3.434 3.434 R clock network delay
|
|
Info (332115): 3.434 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[3]
|
|
Info (332115): 3.538 0.104 RR uTco fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[3]|q
|
|
Info (332115): 3.582 0.044 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[3]~la_mlab/laboutb[6]
|
|
Info (332115): 4.002 0.420 RR IC High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[3]~0|datac
|
|
Info (332115): 4.075 0.073 RF CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[3]~0|combout
|
|
Info (332115): 4.075 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[3]|d
|
|
Info (332115): 4.075 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[3]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 4.092 4.092 R clock network delay
|
|
Info (332115): 3.434 -0.658 clock pessimism removed
|
|
Info (332115): 3.434 0.000 clock uncertainty
|
|
Info (332115): 3.674 0.240 uTh fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[3]
|
|
Info (332115): Data Arrival Time : 4.075
|
|
Info (332115): Data Required Time : 3.674
|
|
Info (332115): Slack : 0.401
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.401
|
|
Info (20696): -to_clock [get_clocks {vl_qph_user_clk_clkpsc_clk1}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.401
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[3]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[3]
|
|
Info (332115): Launch Clock : vl_qph_user_clk_clkpsc_clk1
|
|
Info (332115): Latch Clock : vl_qph_user_clk_clkpsc_clk1
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 3.484 3.484 R clock network delay
|
|
Info (332115): 3.484 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[3]
|
|
Info (332115): 3.588 0.104 RR uTco fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[3]|q
|
|
Info (332115): 3.632 0.044 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[3]~la_mlab/laboutb[6]
|
|
Info (332115): 4.052 0.420 RR IC High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[3]~0|datac
|
|
Info (332115): 4.125 0.073 RF CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[3]~0|combout
|
|
Info (332115): 4.125 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[3]|d
|
|
Info (332115): 4.125 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[3]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 4.156 4.156 R clock network delay
|
|
Info (332115): 3.484 -0.672 clock pessimism removed
|
|
Info (332115): 3.484 0.000 clock uncertainty
|
|
Info (332115): 3.724 0.240 uTh fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_freq_u0|ffs_ckpsc_vl4_prescaler[3]
|
|
Info (332115): Data Arrival Time : 4.125
|
|
Info (332115): Data Required Time : 3.724
|
|
Info (332115): Slack : 0.401
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.493
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|avmmclk}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.493
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|reconfig_address[8]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Launch Clock : SYS_RefClk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|avmmclk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 2.448 2.448 R clock network delay
|
|
Info (332115): 2.448 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|reconfig_address[8]
|
|
Info (332115): 2.549 0.101 FF uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|reconfig_address[8]|q
|
|
Info (332115): 2.602 0.053 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|reconfig_address[8]~la_mlab/laboutt[19]
|
|
Info (332115): 3.466 0.864 FF IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst|avmmaddress[8]
|
|
Info (332115): 3.466 0.000 FF CELL fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 2.897 2.897 R clock network delay
|
|
Info (332115): 2.755 -0.142 clock pessimism removed
|
|
Info (332115): 2.785 0.030 clock uncertainty
|
|
Info (332115): 2.973 0.188 uTh fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Arrival Time : 3.466
|
|
Info (332115): Data Required Time : 2.973
|
|
Info (332115): Slack : 0.493
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.505
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|avmmclk}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.505
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|channel_count[2]~RTMDUPLICATE
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Launch Clock : PCIE_REFCLK
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|avmmclk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 3.107 3.107 R clock network delay
|
|
Info (332115): 3.107 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|channel_count[2]~RTMDUPLICATE
|
|
Info (332115): 3.205 0.098 FF uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|channel_count[2]~RTMDUPLICATE|q
|
|
Info (332115): 3.237 0.032 FF CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|channel_count[2]~RTMDUPLICATE~la_mlab/laboutt[2]
|
|
Info (332115): 3.334 0.097 FF IC High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i244~0|datab
|
|
Info (332115): 3.432 0.098 FR CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i244~0|combout
|
|
Info (332115): 3.434 0.002 RR CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i244~0~la_mlab/laboutb[13]
|
|
Info (332115): 4.073 0.639 RR IC High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst|avmmwrite
|
|
Info (332115): 4.073 0.000 RR CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 3.718 3.718 R clock network delay
|
|
Info (332115): 3.392 -0.326 clock pessimism removed
|
|
Info (332115): 3.432 0.040 clock uncertainty
|
|
Info (332115): 3.568 0.136 uTh fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Arrival Time : 4.073
|
|
Info (332115): Data Required Time : 3.568
|
|
Info (332115): Slack : 0.505
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.563
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|avmmclk}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.563
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|reconfig_address[8]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Launch Clock : SYS_RefClk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|avmmclk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 2.448 2.448 R clock network delay
|
|
Info (332115): 2.448 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|reconfig_address[8]
|
|
Info (332115): 2.549 0.101 RR uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|reconfig_address[8]|q
|
|
Info (332115): 2.617 0.068 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|reconfig_address[8]~la_mlab/laboutt[19]
|
|
Info (332115): 3.531 0.914 RR IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst|avmmaddress[8]
|
|
Info (332115): 3.531 0.000 RR CELL fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 2.897 2.897 R clock network delay
|
|
Info (332115): 2.755 -0.142 clock pessimism removed
|
|
Info (332115): 2.785 0.030 clock uncertainty
|
|
Info (332115): 2.968 0.183 uTh fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Arrival Time : 3.531
|
|
Info (332115): Data Required Time : 2.968
|
|
Info (332115): Slack : 0.563
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.587
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|avmmclk}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.587
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_address[4]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Launch Clock : PCIE_REFCLK
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|avmmclk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 3.120 3.120 R clock network delay
|
|
Info (332115): 3.120 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_address[4]
|
|
Info (332115): 3.224 0.104 RR uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_address[4]|q
|
|
Info (332115): 3.275 0.051 RR CELL Low Power fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_address[4]~la_lab/laboutb[1]
|
|
Info (332115): 3.603 0.328 RR IC Mixed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i522|dataf
|
|
Info (332115): 3.623 0.020 RR CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i522|combout
|
|
Info (332115): 3.624 0.001 RR CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i522~la_lab/laboutt[16]
|
|
Info (332115): 4.146 0.522 RR IC High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst|avmmaddress[4]
|
|
Info (332115): 4.146 0.000 RR CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 3.658 3.658 R clock network delay
|
|
Info (332115): 3.346 -0.312 clock pessimism removed
|
|
Info (332115): 3.386 0.040 clock uncertainty
|
|
Info (332115): 3.559 0.173 uTh fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Arrival Time : 4.146
|
|
Info (332115): Data Required Time : 3.559
|
|
Info (332115): Slack : 0.587
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.632
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|avmmclk}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.632
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|g_arb[3].arbiter_inst|grant[0]~DUPLICATE
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Launch Clock : PCIE_REFCLK
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|avmmclk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 3.105 3.105 R clock network delay
|
|
Info (332115): 3.105 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|g_arb[3].arbiter_inst|grant[0]~DUPLICATE
|
|
Info (332115): 3.203 0.098 RR uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|g_arb[3].arbiter_inst|grant[0]~DUPLICATE|q
|
|
Info (332115): 3.247 0.044 RR CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|g_arb[3].arbiter_inst|grant[0]~DUPLICATE~la_mlab/laboutb[6]
|
|
Info (332115): 3.503 0.256 RR IC Mixed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i768|datac
|
|
Info (332115): 3.581 0.078 RR CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i768|combout
|
|
Info (332115): 3.583 0.002 RR CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i768~la_mlab/laboutt[14]
|
|
Info (332115): 4.215 0.632 RR IC High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst|avmmaddress[6]
|
|
Info (332115): 4.215 0.000 RR CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 3.664 3.664 R clock network delay
|
|
Info (332115): 3.352 -0.312 clock pessimism removed
|
|
Info (332115): 3.392 0.040 clock uncertainty
|
|
Info (332115): 3.583 0.191 uTh fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Arrival Time : 4.215
|
|
Info (332115): Data Required Time : 3.583
|
|
Info (332115): Slack : 0.632
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.705
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|avmmclk}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.705
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|reconfig_address[8]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Launch Clock : SYS_RefClk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|avmmclk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 2.448 2.448 R clock network delay
|
|
Info (332115): 2.448 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|reconfig_address[8]
|
|
Info (332115): 2.549 0.101 RR uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|reconfig_address[8]|q
|
|
Info (332115): 2.617 0.068 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|reconfig_address[8]~la_mlab/laboutt[19]
|
|
Info (332115): 3.671 1.054 RR IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst|avmmaddress[8]
|
|
Info (332115): 3.671 0.000 RR CELL fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 2.895 2.895 R clock network delay
|
|
Info (332115): 2.753 -0.142 clock pessimism removed
|
|
Info (332115): 2.783 0.030 clock uncertainty
|
|
Info (332115): 2.966 0.183 uTh fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Arrival Time : 3.671
|
|
Info (332115): Data Required Time : 2.966
|
|
Info (332115): Slack : 0.705
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.725
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|avmmclk}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.725
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_writedata[3]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Launch Clock : PCIE_REFCLK
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|avmmclk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 3.114 3.114 R clock network delay
|
|
Info (332115): 3.114 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_writedata[3]
|
|
Info (332115): 3.215 0.101 RR uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_writedata[3]|q
|
|
Info (332115): 3.261 0.046 RR CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|av_writedata[3]~la_lab/laboutt[17]
|
|
Info (332115): 3.687 0.426 RR IC Mixed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i1024~3|dataf
|
|
Info (332115): 3.706 0.019 RR CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i1024~3|combout
|
|
Info (332115): 3.708 0.002 RR CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i1024~3~la_mlab/laboutb[19]
|
|
Info (332115): 4.309 0.601 RR IC High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst|avmmwritedata[3]
|
|
Info (332115): 4.309 0.000 RR CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 3.645 3.645 R clock network delay
|
|
Info (332115): 3.333 -0.312 clock pessimism removed
|
|
Info (332115): 3.373 0.040 clock uncertainty
|
|
Info (332115): 3.584 0.211 uTh fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Arrival Time : 4.309
|
|
Info (332115): Data Required Time : 3.584
|
|
Info (332115): Slack : 0.725
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.751
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|avmmclk}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.751
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|channel_count[2]~RTM_1
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Launch Clock : PCIE_REFCLK
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|avmmclk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 3.110 3.110 R clock network delay
|
|
Info (332115): 3.110 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|channel_count[2]~RTM_1
|
|
Info (332115): 3.207 0.097 RR uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|channel_count[2]~RTM_1|q
|
|
Info (332115): 3.251 0.044 RR CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|channel_count[2]~RTM_1~la_lab/laboutb[14]
|
|
Info (332115): 3.554 0.303 RR IC Mixed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i1188~0|dataf
|
|
Info (332115): 3.573 0.019 RR CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i1188~0|combout
|
|
Info (332115): 3.575 0.002 RR CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i1188~0~la_mlab/laboutt[14]
|
|
Info (332115): 4.263 0.688 RR IC Mixed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst|avmmwrite
|
|
Info (332115): 4.263 0.000 RR CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 3.648 3.648 R clock network delay
|
|
Info (332115): 3.336 -0.312 clock pessimism removed
|
|
Info (332115): 3.376 0.040 clock uncertainty
|
|
Info (332115): 3.512 0.136 uTh fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Arrival Time : 4.263
|
|
Info (332115): Data Required Time : 3.512
|
|
Info (332115): Slack : 0.751
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 0.900
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|avmmclk}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 0.900
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|g_arb[7].arbiter_inst|grant[0]~DUPLICATE
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Launch Clock : PCIE_REFCLK
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|avmmclk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 3.119 3.119 R clock network delay
|
|
Info (332115): 3.119 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|g_arb[7].arbiter_inst|grant[0]~DUPLICATE
|
|
Info (332115): 3.223 0.104 RR uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|g_arb[7].arbiter_inst|grant[0]~DUPLICATE|q
|
|
Info (332115): 3.270 0.047 RR CELL Low Power fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|g_arb[7].arbiter_inst|grant[0]~DUPLICATE~la_mlab/laboutb[6]
|
|
Info (332115): 3.403 0.133 RR IC Low Power fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i1702|dataf
|
|
Info (332115): 3.424 0.021 RR CELL Low Power fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i1702|combout
|
|
Info (332115): 3.425 0.001 RR CELL Low Power fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i1702~la_lab/laboutb[5]
|
|
Info (332115): 4.454 1.029 RR IC Mixed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst|avmmaddress[4]
|
|
Info (332115): 4.454 0.000 RR CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 3.653 3.653 R clock network delay
|
|
Info (332115): 3.341 -0.312 clock pessimism removed
|
|
Info (332115): 3.381 0.040 clock uncertainty
|
|
Info (332115): 3.554 0.173 uTh fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Arrival Time : 4.454
|
|
Info (332115): Data Required Time : 3.554
|
|
Info (332115): Slack : 0.900
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 1.020
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|avmmclk}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 1.020
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|reconfig_address[0]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Launch Clock : SYS_RefClk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|avmmclk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 2.448 2.448 R clock network delay
|
|
Info (332115): 2.448 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|reconfig_address[0]
|
|
Info (332115): 2.552 0.104 RR uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|reconfig_address[0]|q
|
|
Info (332115): 2.620 0.068 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|reconfig_address[0]~la_mlab/laboutb[19]
|
|
Info (332115): 4.086 1.466 RR IC High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst|avmmaddress[0]
|
|
Info (332115): 4.086 0.000 RR CELL fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 2.990 2.990 R clock network delay
|
|
Info (332115): 2.848 -0.142 clock pessimism removed
|
|
Info (332115): 2.878 0.030 clock uncertainty
|
|
Info (332115): 3.066 0.188 uTh fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Arrival Time : 4.086
|
|
Info (332115): Data Required Time : 3.066
|
|
Info (332115): Slack : 1.020
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 1.094
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|avmmclk}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 1.094
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|g_arb[6].arbiter_inst|grant[0]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Launch Clock : PCIE_REFCLK
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|avmmclk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 3.119 3.119 R clock network delay
|
|
Info (332115): 3.119 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|g_arb[6].arbiter_inst|grant[0]
|
|
Info (332115): 3.222 0.103 RR uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|g_arb[6].arbiter_inst|grant[0]|q
|
|
Info (332115): 3.271 0.049 RR CELL Low Power fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|g_arb[6].arbiter_inst|grant[0]~la_mlab/laboutt[9]
|
|
Info (332115): 3.490 0.219 RR IC Low Power fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i1481|dataf
|
|
Info (332115): 3.511 0.021 RR CELL Low Power fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i1481|combout
|
|
Info (332115): 3.512 0.001 RR CELL Low Power fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_arbiber_enable.alt_xcvr_rcfg_arb|i1481~la_lab/laboutt[14]
|
|
Info (332115): 4.677 1.165 RR IC Mixed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst|avmmaddress[7]
|
|
Info (332115): 4.677 0.000 RR CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 3.660 3.660 R clock network delay
|
|
Info (332115): 3.348 -0.312 clock pessimism removed
|
|
Info (332115): 3.388 0.040 clock uncertainty
|
|
Info (332115): 3.583 0.195 uTh fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst~pld_avmm1_clk.reg
|
|
Info (332115): Data Arrival Time : 4.677
|
|
Info (332115): Data Required Time : 3.583
|
|
Info (332115): Slack : 1.094
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 hold paths (0 violated). Worst case slack is 6.253
|
|
Info (20696): -to_clock [get_clocks {pr_clk_enable_dclk_reg2_user_clk}]
|
|
Info (20696): -hold
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Hold slack is 6.253
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_cb_host|alt_pr_cb_controller_v2|pr_request_reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_cb_host|alt_pr_cb_controller_v2|alt_pr_cb_interface|m_prblock~cs_css/pr_clk_core.reg
|
|
Info (332115): Launch Clock : u0|dcp_iopll|dcp_iopll|clk100
|
|
Info (332115): Latch Clock : pr_clk_enable_dclk_reg2_user_clk
|
|
Info (332115): Exception : dcp_bbs.sdc:3119: set_multicycle_path -hold -from [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_cb_host|alt_pr_cb_controller_v2|pr_request_reg}] -to [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_cb_host|alt_pr_cb_controller_v2|alt_pr_cb_interface|m_prblock~cs_css/pr_clk_core.reg}] 1
|
|
Info (332115): Multicycle - Setup Start : 2
|
|
Info (332115): Multicycle - Hold Start : 1
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 10.000 10.000 launch edge time
|
|
Info (332115): 14.821 4.821 R clock network delay
|
|
Info (332115): 14.821 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_cb_host|alt_pr_cb_controller_v2|pr_request_reg
|
|
Info (332115): 14.921 0.100 RR uTco fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_cb_host|alt_pr_cb_controller_v2|pr_request_reg|q
|
|
Info (332115): 14.984 0.063 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_cb_host|alt_pr_cb_controller_v2|pr_request_reg~la_lab/laboutt[0]
|
|
Info (332115): 17.608 2.624 RR IC High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_cb_host|alt_pr_cb_controller_v2|alt_pr_cb_interface|m_prblock|prrequest
|
|
Info (332115): 17.608 0.000 RR CELL fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_cb_host|alt_pr_cb_controller_v2|alt_pr_cb_interface|m_prblock~cs_css/pr_clk_core.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 5.000 5.000 latch edge time
|
|
Info (332115): 11.455 6.455 R clock network delay
|
|
Info (332115): 10.791 -0.664 clock pessimism removed
|
|
Info (332115): 10.961 0.170 clock uncertainty
|
|
Info (332115): 11.355 0.394 uTh fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_cb_host|alt_pr_cb_controller_v2|alt_pr_cb_interface|m_prblock~cs_css/pr_clk_core.reg
|
|
Info (332115): Data Arrival Time : 17.608
|
|
Info (332115): Data Required Time : 11.355
|
|
Info (332115): Slack : 6.253
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 1.594
|
|
Info (20696): -to_clock [get_clocks {mem|ddr4a|ddr4a_core_usr_clk}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 1.594
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_green_bs|ddr4a_reset_sync|resync_chains[0].synchronizer_nocut|dreg[0]
|
|
Info (332115): To Node : fpga_top|inst_green_bs|ddr4a_avmm_bridge|ddr_avmm_bridge|rsp_readdata[73]
|
|
Info (332115): Launch Clock : mem|ddr4a|ddr4a_core_usr_clk
|
|
Info (332115): Latch Clock : mem|ddr4a|ddr4a_core_usr_clk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.117 0.117 launch edge time
|
|
Info (332115): 1.830 1.713 R clock network delay
|
|
Info (332115): 1.830 0.000 fpga_top|inst_green_bs|ddr4a_reset_sync|resync_chains[0].synchronizer_nocut|dreg[0]
|
|
Info (332115): 2.003 0.173 RR uTco fpga_top|inst_green_bs|ddr4a_reset_sync|resync_chains[0].synchronizer_nocut|dreg[0]|q
|
|
Info (332115): 2.068 0.065 RR CELL High Speed fpga_top|inst_green_bs|ddr4a_reset_sync|resync_chains[0].synchronizer_nocut|dreg[0]~la_lab/laboutb[6]
|
|
Info (332115): 3.865 1.797 RR IC High Speed fpga_top|inst_green_bs|ddr4a_avmm_bridge|ddr_avmm_bridge|rsp_readdata[73]|clrn
|
|
Info (332115): 3.865 0.000 RR CELL High Speed fpga_top|inst_green_bs|ddr4a_avmm_bridge|ddr_avmm_bridge|rsp_readdata[73]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 3.869 3.869 latch edge time
|
|
Info (332115): 5.148 1.279 R clock network delay
|
|
Info (332115): 5.545 0.397 clock pessimism removed
|
|
Info (332115): 5.515 -0.030 clock uncertainty
|
|
Info (332115): 5.459 -0.056 uTsu fpga_top|inst_green_bs|ddr4a_avmm_bridge|ddr_avmm_bridge|rsp_readdata[73]
|
|
Info (332115): Data Arrival Time : 3.865
|
|
Info (332115): Data Required Time : 5.459
|
|
Info (332115): Slack : 1.594
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 2.035
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|wys~CORE_CLK_OUT}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 2.035
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_sriov_2.sriov2.sriov_bridge|rs_hip|npor_sync_pld_clk
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_sriov_2.sriov2.sriov_bridge|rs_hip|recovery_cnt[8]
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|wys~CORE_CLK_OUT
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|wys~CORE_CLK_OUT
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 5.196 5.196 R clock network delay
|
|
Info (332115): 5.196 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_sriov_2.sriov2.sriov_bridge|rs_hip|npor_sync_pld_clk
|
|
Info (332115): 5.322 0.126 RR uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_sriov_2.sriov2.sriov_bridge|rs_hip|npor_sync_pld_clk|q
|
|
Info (332115): 5.415 0.093 RR CELL Low Power fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_sriov_2.sriov2.sriov_bridge|rs_hip|npor_sync_pld_clk~la_lab/laboutb[8]
|
|
Info (332115): 7.048 1.633 RR IC Mixed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_sriov_2.sriov2.sriov_bridge|rs_hip|recovery_cnt[8]|clrn
|
|
Info (332115): 7.048 0.000 RR CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_sriov_2.sriov2.sriov_bridge|rs_hip|recovery_cnt[8]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 4.000 4.000 latch edge time
|
|
Info (332115): 8.430 4.430 R clock network delay
|
|
Info (332115): 9.139 0.709 clock pessimism removed
|
|
Info (332115): 9.083 -0.056 uTsu fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_sriov_2.sriov2.sriov_bridge|rs_hip|recovery_cnt[8]
|
|
Info (332115): Data Arrival Time : 7.048
|
|
Info (332115): Data Required Time : 9.083
|
|
Info (332115): Slack : 2.035
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 2.374
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk1}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 2.374
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[3].core|pipeline|execute|fpu_unit|fpu_fpga|fp_div|[3].reset_relay|reset_r[0]
|
|
Info (332115): To Node : fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[3].core|pipeline|execute|fpu_unit|fpu_fpga|fp_div|[3].fdiv|memoryC1_uid115_invTables_lutmem_dmem|auto_generated|altsyncram1|ram_block2a20~reg0
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk1
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk1
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 3.880 3.880 R clock network delay
|
|
Info (332115): 3.880 0.000 fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[3].core|pipeline|execute|fpu_unit|fpu_fpga|fp_div|[3].reset_relay|reset_r[0]
|
|
Info (332115): 4.001 0.121 FF uTco fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[3].core|pipeline|execute|fpu_unit|fpu_fpga|fp_div|[3].reset_relay|reset_r[0]|q
|
|
Info (332115): 4.074 0.073 FF CELL High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[3].core|pipeline|execute|fpu_unit|fpu_fpga|fp_div|[3].reset_relay|reset_r[0]~la_mlab/laboutb[15]
|
|
Info (332115): 5.599 1.525 FF IC Mixed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[3].core|pipeline|execute|fpu_unit|fpu_fpga|fp_div|[3].fdiv|memoryC1_uid115_invTables_lutmem_dmem|auto_generated|altsyncram1|ram_block2a20|clr0
|
|
Info (332115): 5.599 0.000 FF CELL High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[3].core|pipeline|execute|fpu_unit|fpu_fpga|fp_div|[3].fdiv|memoryC1_uid115_invTables_lutmem_dmem|auto_generated|altsyncram1|ram_block2a20~reg0
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 4.545 4.545 latch edge time
|
|
Info (332115): 7.753 3.208 R clock network delay
|
|
Info (332115): 8.294 0.541 clock pessimism removed
|
|
Info (332115): 8.264 -0.030 clock uncertainty
|
|
Info (332115): 7.973 -0.291 uTsu fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[3].core|pipeline|execute|fpu_unit|fpu_fpga|fp_div|[3].fdiv|memoryC1_uid115_invTables_lutmem_dmem|auto_generated|altsyncram1|ram_block2a20~reg0
|
|
Info (332115): Data Arrival Time : 5.599
|
|
Info (332115): Data Required Time : 7.973
|
|
Info (332115): Slack : 2.374
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 2.406
|
|
Info (20696): -to_clock [get_clocks {u0|dcp_iopll|dcp_iopll|clk1x}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 2.406
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|c32ui_SystemReset_n
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|tcm_to_bmc_mm_bridge_s0_agent_rdata_fifo|infer_mem_rtl_0|auto_generated|ram_block1a7~reg0
|
|
Info (332115): Launch Clock : u0|dcp_iopll|dcp_iopll|clk1x
|
|
Info (332115): Latch Clock : u0|dcp_iopll|dcp_iopll|clk1x
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 5.584 5.584 R clock network delay
|
|
Info (332115): 5.584 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|c32ui_SystemReset_n
|
|
Info (332115): 5.701 0.117 RR uTco fpga_top|inst_fiu_top|inst_ccip_fabric_top|c32ui_SystemReset_n|q
|
|
Info (332115): 5.760 0.059 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|c32ui_SystemReset_n~la_lab/laboutb[18]
|
|
Info (332115): 6.792 1.032 RR IC Mixed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|tcm_master_reset~0|dataf
|
|
Info (332115): 6.818 0.026 RF CELL Low Power fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|tcm_master_reset~0|combout
|
|
Info (332115): 6.823 0.005 FF CELL Low Power fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|tcm_master_reset~0~la_mlab/laboutb[10]
|
|
Info (332115): 7.682 0.859 FF IC Mixed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|tcm_to_bmc_mm_bridge_s0_agent_rdata_fifo|infer_mem_rtl_0|auto_generated|ram_block1a7|clr0
|
|
Info (332115): 7.682 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|tcm_to_bmc_mm_bridge_s0_agent_rdata_fifo|infer_mem_rtl_0|auto_generated|ram_block1a7~reg0
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 5.000 5.000 latch edge time
|
|
Info (332115): 9.818 4.818 R clock network delay
|
|
Info (332115): 10.527 0.709 clock pessimism removed
|
|
Info (332115): 10.377 -0.150 clock uncertainty
|
|
Info (332115): 10.088 -0.289 uTsu fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|tcm_to_bmc_mm_bridge_s0_agent_rdata_fifo|infer_mem_rtl_0|auto_generated|ram_block1a7~reg0
|
|
Info (332115): Data Arrival Time : 7.682
|
|
Info (332115): Data Required Time : 10.088
|
|
Info (332115): Slack : 2.406
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 2.692
|
|
Info (20696): -to_clock [get_clocks {u0|dcp_iopll|dcp_iopll|clk100}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 2.692
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|c32ui_SystemReset_n
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|ddr_backchannel|mm_clock_crossing_bridge_0|pending_read_count[1]
|
|
Info (332115): Launch Clock : u0|dcp_iopll|dcp_iopll|clk1x
|
|
Info (332115): Latch Clock : u0|dcp_iopll|dcp_iopll|clk100
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 5.000 5.000 launch edge time
|
|
Info (332115): 10.584 5.584 R clock network delay
|
|
Info (332115): 10.584 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|c32ui_SystemReset_n
|
|
Info (332115): 10.701 0.117 RR uTco fpga_top|inst_fiu_top|inst_ccip_fabric_top|c32ui_SystemReset_n|q
|
|
Info (332115): 10.760 0.059 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|c32ui_SystemReset_n~la_lab/laboutb[18]
|
|
Info (332115): 11.792 1.032 RR IC Mixed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|tcm_master_reset~0|dataf
|
|
Info (332115): 11.818 0.026 RF CELL Low Power fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|tcm_master_reset~0|combout
|
|
Info (332115): 11.823 0.005 FF CELL Low Power fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|tcm_master_reset~0~la_mlab/laboutb[10]
|
|
Info (332115): 12.433 0.610 FF IC Mixed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|ddr_backchannel|mm_clock_crossing_bridge_0|pending_read_count[1]|clrn
|
|
Info (332115): 12.433 0.000 FF CELL Low Power fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|ddr_backchannel|mm_clock_crossing_bridge_0|pending_read_count[1]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 10.000 10.000 latch edge time
|
|
Info (332115): 14.859 4.859 R clock network delay
|
|
Info (332115): 15.351 0.492 clock pessimism removed
|
|
Info (332115): 15.191 -0.160 clock uncertainty
|
|
Info (332115): 15.125 -0.066 uTsu fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|ddr_backchannel|mm_clock_crossing_bridge_0|pending_read_count[1]
|
|
Info (332115): Data Arrival Time : 12.433
|
|
Info (332115): Data Required Time : 15.125
|
|
Info (332115): Slack : 2.692
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 3.285
|
|
Info (20696): -to_clock [get_clocks {DDR4_RefClk}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 3.285
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|use_counter_lock.counter_lock_gen_master.pll_ref_clk_reset_n_sync_rrr
|
|
Info (332115): To Node : mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|use_counter_lock.counter_lock_gen_master.cpa_count_to_lock[7]
|
|
Info (332115): Launch Clock : DDR4_RefClk
|
|
Info (332115): Latch Clock : DDR4_RefClk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 2.537 2.537 R clock network delay
|
|
Info (332115): 2.537 0.000 mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|use_counter_lock.counter_lock_gen_master.pll_ref_clk_reset_n_sync_rrr
|
|
Info (332115): 2.662 0.125 RR uTco mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|use_counter_lock.counter_lock_gen_master.pll_ref_clk_reset_n_sync_rrr|q
|
|
Info (332115): 2.744 0.082 RR CELL High Speed mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|use_counter_lock.counter_lock_gen_master.pll_ref_clk_reset_n_sync_rrr~la_mlab/laboutb[4]
|
|
Info (332115): 2.888 0.144 RR IC High Speed mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|use_counter_lock.counter_lock_gen_master.cpa_count_to_lock[7]|clrn
|
|
Info (332115): 2.888 0.000 RR CELL High Speed mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|use_counter_lock.counter_lock_gen_master.cpa_count_to_lock[7]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 3.752 3.752 latch edge time
|
|
Info (332115): 6.094 2.342 R clock network delay
|
|
Info (332115): 6.277 0.183 clock pessimism removed
|
|
Info (332115): 6.247 -0.030 clock uncertainty
|
|
Info (332115): 6.173 -0.074 uTsu mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|use_counter_lock.counter_lock_gen_master.cpa_count_to_lock[7]
|
|
Info (332115): Data Arrival Time : 2.888
|
|
Info (332115): Data Required Time : 6.173
|
|
Info (332115): Slack : 3.285
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 3.318
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|rx_pma_clk}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 3.318
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_reset_sync|resync_chains[0].sync_r[2]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_consecutive_error[3]
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|rx_pma_clk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|rx_pma_clk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 3.850 3.850 R clock network delay
|
|
Info (332115): 3.850 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_reset_sync|resync_chains[0].sync_r[2]
|
|
Info (332115): 3.969 0.119 RR uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_reset_sync|resync_chains[0].sync_r[2]|q
|
|
Info (332115): 4.037 0.068 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_reset_sync|resync_chains[0].sync_r[2]~la_mlab/laboutb[5]
|
|
Info (332115): 4.302 0.265 RR IC High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_consecutive_error[3]|clrn
|
|
Info (332115): 4.302 0.000 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_consecutive_error[3]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 3.878 3.878 latch edge time
|
|
Info (332115): 6.816 2.938 R clock network delay
|
|
Info (332115): 7.706 0.890 clock pessimism removed
|
|
Info (332115): 7.676 -0.030 clock uncertainty
|
|
Info (332115): 7.620 -0.056 uTsu fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_consecutive_error[3]
|
|
Info (332115): Data Arrival Time : 4.302
|
|
Info (332115): Data Required Time : 7.620
|
|
Info (332115): Slack : 3.318
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 3.363
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_clk}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 3.363
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_reset_sync|resync_chains[0].sync_r[2]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_consecutive_error[1]
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_clk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_clk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 3.853 3.853 R clock network delay
|
|
Info (332115): 3.853 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_reset_sync|resync_chains[0].sync_r[2]
|
|
Info (332115): 3.970 0.117 RR uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_reset_sync|resync_chains[0].sync_r[2]|q
|
|
Info (332115): 4.029 0.059 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_reset_sync|resync_chains[0].sync_r[2]~la_lab/laboutb[18]
|
|
Info (332115): 4.255 0.226 RR IC High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_consecutive_error[1]|clrn
|
|
Info (332115): 4.255 0.000 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_consecutive_error[1]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 3.878 3.878 latch edge time
|
|
Info (332115): 6.816 2.938 R clock network delay
|
|
Info (332115): 7.704 0.888 clock pessimism removed
|
|
Info (332115): 7.674 -0.030 clock uncertainty
|
|
Info (332115): 7.618 -0.056 uTsu fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_consecutive_error[1]
|
|
Info (332115): Data Arrival Time : 4.255
|
|
Info (332115): Data Required Time : 7.618
|
|
Info (332115): Slack : 3.363
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 3.382
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|rx_pma_clk}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 3.382
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_reset_sync|resync_chains[0].sync_r[2]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_error_high
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|rx_pma_clk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|rx_pma_clk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 3.764 3.764 R clock network delay
|
|
Info (332115): 3.764 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_reset_sync|resync_chains[0].sync_r[2]
|
|
Info (332115): 3.883 0.119 RR uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_reset_sync|resync_chains[0].sync_r[2]|q
|
|
Info (332115): 3.941 0.058 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_reset_sync|resync_chains[0].sync_r[2]~la_mlab/laboutb[2]
|
|
Info (332115): 4.150 0.209 RR IC High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_error_high|clrn
|
|
Info (332115): 4.150 0.000 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_error_high
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 3.878 3.878 latch edge time
|
|
Info (332115): 6.726 2.848 R clock network delay
|
|
Info (332115): 7.618 0.892 clock pessimism removed
|
|
Info (332115): 7.588 -0.030 clock uncertainty
|
|
Info (332115): 7.532 -0.056 uTsu fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_error_high
|
|
Info (332115): Data Arrival Time : 4.150
|
|
Info (332115): Data Required Time : 7.532
|
|
Info (332115): Slack : 3.382
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 3.422
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|rx_pma_clk}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 3.422
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_reset_sync|resync_chains[0].sync_r[2]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_count[2]
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|rx_pma_clk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|rx_pma_clk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 3.829 3.829 R clock network delay
|
|
Info (332115): 3.829 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_reset_sync|resync_chains[0].sync_r[2]
|
|
Info (332115): 3.946 0.117 RR uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_reset_sync|resync_chains[0].sync_r[2]|q
|
|
Info (332115): 4.005 0.059 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_reset_sync|resync_chains[0].sync_r[2]~la_lab/laboutb[18]
|
|
Info (332115): 4.188 0.183 RR IC High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_count[2]|clrn
|
|
Info (332115): 4.188 0.000 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_count[2]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 3.878 3.878 latch edge time
|
|
Info (332115): 6.792 2.914 R clock network delay
|
|
Info (332115): 7.696 0.904 clock pessimism removed
|
|
Info (332115): 7.666 -0.030 clock uncertainty
|
|
Info (332115): 7.610 -0.056 uTsu fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_count[2]
|
|
Info (332115): Data Arrival Time : 4.188
|
|
Info (332115): Data Required Time : 7.610
|
|
Info (332115): Slack : 3.422
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 3.526
|
|
Info (20696): -to_clock [get_clocks {u0|dcp_iopll|dcp_iopll|clk25}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 3.526
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|c32ui_SystemReset_n
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|tcm_flash_reset_sync_reg[3]
|
|
Info (332115): Launch Clock : u0|dcp_iopll|dcp_iopll|clk1x
|
|
Info (332115): Latch Clock : u0|dcp_iopll|dcp_iopll|clk25
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 35.000 35.000 launch edge time
|
|
Info (332115): 40.584 5.584 R clock network delay
|
|
Info (332115): 40.584 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|c32ui_SystemReset_n
|
|
Info (332115): 40.701 0.117 RR uTco fpga_top|inst_fiu_top|inst_ccip_fabric_top|c32ui_SystemReset_n|q
|
|
Info (332115): 40.760 0.059 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|c32ui_SystemReset_n~la_lab/laboutb[18]
|
|
Info (332115): 41.632 0.872 RR IC Mixed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|tcm_flash_reset_sync_reg[3]|clrn
|
|
Info (332115): 41.632 0.000 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|tcm_flash_reset_sync_reg[3]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 40.000 40.000 latch edge time
|
|
Info (332115): 44.903 4.903 R clock network delay
|
|
Info (332115): 45.395 0.492 clock pessimism removed
|
|
Info (332115): 45.215 -0.180 clock uncertainty
|
|
Info (332115): 45.158 -0.057 uTsu fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|tcm_flash_reset_sync_reg[3]
|
|
Info (332115): Data Arrival Time : 41.632
|
|
Info (332115): Data Required Time : 45.158
|
|
Info (332115): Slack : 3.526
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 3.984
|
|
Info (20696): -to_clock [get_clocks {mem|ddr4a|ddr4a_core_cal_slave_clk}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 3.984
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : mem|ddr4b|ddr4b|arch|arch_inst|non_hps.core_clks_rsts_inst|per_if_cal_slave_reset_sync[9]
|
|
Info (332115): To Node : mem|ddr4b|ddr4b|arch|arch_inst|io_aux_inst|io_aux~soft_ram_reg
|
|
Info (332115): Launch Clock : mem|ddr4a|ddr4a_core_cal_slave_clk
|
|
Info (332115): Latch Clock : mem|ddr4a|ddr4a_core_cal_slave_clk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 3.776 3.776 R clock network delay
|
|
Info (332115): 3.776 0.000 mem|ddr4b|ddr4b|arch|arch_inst|non_hps.core_clks_rsts_inst|per_if_cal_slave_reset_sync[9]
|
|
Info (332115): 3.901 0.125 RR uTco mem|ddr4b|ddr4b|arch|arch_inst|non_hps.core_clks_rsts_inst|per_if_cal_slave_reset_sync[9]|q
|
|
Info (332115): 3.983 0.082 RR CELL High Speed mem|ddr4b|ddr4b|arch|arch_inst|non_hps.core_clks_rsts_inst|per_if_cal_slave_reset_sync[9]~la_mlab/laboutb[8]
|
|
Info (332115): 6.301 2.318 RR IC Mixed mem|ddr4b|ddr4b|arch|arch_inst|io_aux_inst|io_aux|soft_ram_reset_n
|
|
Info (332115): 6.301 0.000 RR CELL mem|ddr4b|ddr4b|arch|arch_inst|io_aux_inst|io_aux~soft_ram_reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 6.566 6.566 latch edge time
|
|
Info (332115): 9.907 3.341 R clock network delay
|
|
Info (332115): 10.351 0.444 clock pessimism removed
|
|
Info (332115): 10.301 -0.050 clock uncertainty
|
|
Info (332115): 10.285 -0.016 uTsu mem|ddr4b|ddr4b|arch|arch_inst|io_aux_inst|io_aux~soft_ram_reg
|
|
Info (332115): Data Arrival Time : 6.301
|
|
Info (332115): Data Required Time : 10.285
|
|
Info (332115): Slack : 3.984
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 4.943
|
|
Info (20696): -to_clock [get_clocks {SYS_RefClk}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 4.943
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_cb_host|alt_pr_cb_controller_v2|freeze_reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|pr_freeze_rsync
|
|
Info (332115): Launch Clock : u0|dcp_iopll|dcp_iopll|clk100
|
|
Info (332115): Latch Clock : SYS_RefClk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 5.582 5.582 R clock network delay
|
|
Info (332115): 5.582 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_cb_host|alt_pr_cb_controller_v2|freeze_reg
|
|
Info (332115): 5.702 0.120 FF uTco fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_cb_host|alt_pr_cb_controller_v2|freeze_reg|q
|
|
Info (332115): 5.767 0.065 FF CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|alt_pr_0|alt_pr_0|alt_pr_cb_host|alt_pr_cb_controller_v2|freeze_reg~la_lab/laboutt[8]
|
|
Info (332115): 7.283 1.516 FF IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|pr_freeze_rsync|clrn
|
|
Info (332115): 7.283 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|pr_freeze_rsync
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 10.000 10.000 latch edge time
|
|
Info (332115): 12.454 2.454 R clock network delay
|
|
Info (332115): 12.596 0.142 clock pessimism removed
|
|
Info (332115): 12.286 -0.310 clock uncertainty
|
|
Info (332115): 12.226 -0.060 uTsu fpga_top|inst_fiu_top|inst_hssi_ctrl|pr_freeze_rsync
|
|
Info (332115): Data Arrival Time : 7.283
|
|
Info (332115): Data Required Time : 12.226
|
|
Info (332115): Slack : 4.943
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 6.580
|
|
Info (20696): -to_clock [get_clocks {fspi_sclk}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 6.580
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|SPISlaveToAvalonMasterBridge_reset_clk_domain_synch|data_out
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MISOctl|rdshiftreg[0]
|
|
Info (332115): Launch Clock : u0|dcp_iopll|dcp_iopll|clk1x
|
|
Info (332115): Latch Clock : fspi_sclk
|
|
Info (332115): Exception : dcp_bbs.sdc:3056: set_multicycle_path -setup -from [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|SPISlaveToAvalonMasterBridge_reset_clk_domain_synch|data_out}] -to [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MISOctl|*}] 2
|
|
Info (332115): Multicycle - Setup Start : 2
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 240.000 240.000 launch edge time
|
|
Info (332115): 245.570 5.570 R clock network delay
|
|
Info (332115): 245.570 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|SPISlaveToAvalonMasterBridge_reset_clk_domain_synch|data_out
|
|
Info (332115): 245.706 0.136 RR uTco fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|SPISlaveToAvalonMasterBridge_reset_clk_domain_synch|data_out|q
|
|
Info (332115): 245.774 0.068 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|SPISlaveToAvalonMasterBridge_reset_clk_domain_synch|data_out~la_mlab/laboutt[1]
|
|
Info (332115): 246.016 0.242 RR IC High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MOSIctl|i5|dataf
|
|
Info (332115): 246.041 0.025 RF CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MOSIctl|i5|combout
|
|
Info (332115): 246.046 0.005 FF CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MOSIctl|i5~la_mlab/laboutt[18]
|
|
Info (332115): 246.137 0.091 FF IC High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MISOctl|rdshiftreg[0]|clrn
|
|
Info (332115): 246.137 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MISOctl|rdshiftreg[0]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 250.000 250.000 latch edge time
|
|
Info (332115): 253.110 3.110 R clock network delay
|
|
Info (332115): 252.800 -0.310 clock uncertainty
|
|
Info (332115): 252.717 -0.083 uTsu fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MISOctl|rdshiftreg[0]
|
|
Info (332115): Data Arrival Time : 246.137
|
|
Info (332115): Data Required Time : 252.717
|
|
Info (332115): Slack : 6.580
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 6.848
|
|
Info (20696): -to_clock [get_clocks {PCIE_REFCLK}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 6.848
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|reset_pulse_inst|resync_chains[0].sync_r[2]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|cpu_memory[71][28]
|
|
Info (332115): Launch Clock : PCIE_REFCLK
|
|
Info (332115): Latch Clock : PCIE_REFCLK
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 3.472 3.472 R clock network delay
|
|
Info (332115): 3.472 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|reset_pulse_inst|resync_chains[0].sync_r[2]
|
|
Info (332115): 3.597 0.125 RR uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|reset_pulse_inst|resync_chains[0].sync_r[2]|q
|
|
Info (332115): 3.661 0.064 RR CELL Low Power fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|reset_pulse_inst|resync_chains[0].sync_r[2]~la_mlab/laboutb[13]
|
|
Info (332115): 6.428 2.767 RR IC Mixed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|cpu_memory[71][28]|clrn
|
|
Info (332115): 6.428 0.000 RR CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|cpu_memory[71][28]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 10.000 10.000 latch edge time
|
|
Info (332115): 13.132 3.132 R clock network delay
|
|
Info (332115): 13.391 0.259 clock pessimism removed
|
|
Info (332115): 13.351 -0.040 clock uncertainty
|
|
Info (332115): 13.276 -0.075 uTsu fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|alt_xcvr_native_optional_rcfg_logic|g_pcie_dfe_ip.altera_xcvr_native_pcie_dfe_ip_inst|pcie_mgmt_master_for_dfe|mgmt_cpu_inst|cpu_memory[71][28]
|
|
Info (332115): Data Arrival Time : 6.428
|
|
Info (332115): Data Required Time : 13.276
|
|
Info (332115): Slack : 6.848
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 7.299
|
|
Info (20696): -to_clock [get_clocks {filtered_sclk_negedge}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 7.299
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|SPISlaveToAvalonMasterBridge_reset_clk_domain_synch|data_out
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MOSIctl|stsourcedata[4]
|
|
Info (332115): Launch Clock : u0|dcp_iopll|dcp_iopll|clk1x
|
|
Info (332115): Latch Clock : filtered_sclk_negedge
|
|
Info (332115): Exception : dcp_bbs.sdc:3060: set_multicycle_path -setup -from [get_keepers {*SPISlaveToAvalonMasterBridge_reset_clk_domain_synch|data_out}] -to [get_keepers {*SPIPhy_MOSIctl|stsourcedata*}] 3
|
|
Info (332115): Multicycle - Setup Start : 3
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 235.000 235.000 launch edge time
|
|
Info (332115): 240.570 5.570 R clock network delay
|
|
Info (332115): 240.570 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|SPISlaveToAvalonMasterBridge_reset_clk_domain_synch|data_out
|
|
Info (332115): 240.706 0.136 RR uTco fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|SPISlaveToAvalonMasterBridge_reset_clk_domain_synch|data_out|q
|
|
Info (332115): 240.774 0.068 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|SPISlaveToAvalonMasterBridge_reset_clk_domain_synch|data_out~la_mlab/laboutt[1]
|
|
Info (332115): 242.456 1.682 RR IC Mixed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MOSIctl|stsourcedata[4]|clrn
|
|
Info (332115): 242.456 0.000 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MOSIctl|stsourcedata[4]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 250.000 250.000 latch edge time
|
|
Info (332115): 250.120 0.120 R clock network delay
|
|
Info (332115): 249.820 -0.300 clock uncertainty
|
|
Info (332115): 249.755 -0.065 uTsu fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MOSIctl|stsourcedata[4]
|
|
Info (332115): Data Arrival Time : 242.456
|
|
Info (332115): Data Required Time : 249.755
|
|
Info (332115): Slack : 7.299
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 17.694
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|rx_fref}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 17.694
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|rx_fref
|
|
Info (332115): Exception : dcp_bbs.sdc:3148: set_max_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pma_rxpma_rstb}] 20.000
|
|
Info (332115): Max Delay Exception : 20.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 1.846 1.846 R clock network delay
|
|
Info (332115): 1.846 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): 3.023 1.177 RR uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|rx_pma_rstb7
|
|
Info (332115): 3.023 0.000 RR IC fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_pma_rxpma_rstb
|
|
Info (332115): 3.023 0.000 RR CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 20.000 20.000 latch edge time
|
|
Info (332115): 21.042 1.042 R clock network delay
|
|
Info (332115): 20.922 -0.120 clock uncertainty
|
|
Info (332115): 20.717 -0.205 uTsu fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Data Arrival Time : 3.023
|
|
Info (332115): Data Required Time : 20.717
|
|
Info (332115): Slack : 17.694
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 17.886
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|rx_fref}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 17.886
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|rx_fref
|
|
Info (332115): Exception : dcp_bbs.sdc:3148: set_max_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pma_rxpma_rstb}] 20.000
|
|
Info (332115): Max Delay Exception : 20.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 1.846 1.846 R clock network delay
|
|
Info (332115): 1.846 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): 2.831 0.985 RR uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|rx_pma_rstb6
|
|
Info (332115): 2.831 0.000 RR IC fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_pma_rxpma_rstb
|
|
Info (332115): 2.831 0.000 RR CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 20.000 20.000 latch edge time
|
|
Info (332115): 21.042 1.042 R clock network delay
|
|
Info (332115): 20.922 -0.120 clock uncertainty
|
|
Info (332115): 20.717 -0.205 uTsu fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Data Arrival Time : 2.831
|
|
Info (332115): Data Required Time : 20.717
|
|
Info (332115): Slack : 17.886
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 17.940
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|rx_fref}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 17.940
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|rx_fref
|
|
Info (332115): Exception : dcp_bbs.sdc:3148: set_max_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pma_rxpma_rstb}] 20.000
|
|
Info (332115): Max Delay Exception : 20.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 1.846 1.846 R clock network delay
|
|
Info (332115): 1.846 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): 2.705 0.859 RR uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|rx_pma_rstb1
|
|
Info (332115): 2.705 0.000 RR IC fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_pma_rxpma_rstb
|
|
Info (332115): 2.705 0.000 RR CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 20.000 20.000 latch edge time
|
|
Info (332115): 20.970 0.970 R clock network delay
|
|
Info (332115): 20.850 -0.120 clock uncertainty
|
|
Info (332115): 20.645 -0.205 uTsu fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Data Arrival Time : 2.705
|
|
Info (332115): Data Required Time : 20.645
|
|
Info (332115): Slack : 17.940
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 17.944
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|rx_fref}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 17.944
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|rx_fref
|
|
Info (332115): Exception : dcp_bbs.sdc:3148: set_max_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pma_rxpma_rstb}] 20.000
|
|
Info (332115): Max Delay Exception : 20.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 1.846 1.846 R clock network delay
|
|
Info (332115): 1.846 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): 2.773 0.927 RR uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|rx_pma_rstb5
|
|
Info (332115): 2.773 0.000 RR IC fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_pma_rxpma_rstb
|
|
Info (332115): 2.773 0.000 RR CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 20.000 20.000 latch edge time
|
|
Info (332115): 21.042 1.042 R clock network delay
|
|
Info (332115): 20.922 -0.120 clock uncertainty
|
|
Info (332115): 20.717 -0.205 uTsu fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Data Arrival Time : 2.773
|
|
Info (332115): Data Required Time : 20.717
|
|
Info (332115): Slack : 17.944
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 17.982
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|rx_fref}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 17.982
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|rx_fref
|
|
Info (332115): Exception : dcp_bbs.sdc:3148: set_max_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pma_rxpma_rstb}] 20.000
|
|
Info (332115): Max Delay Exception : 20.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 1.846 1.846 R clock network delay
|
|
Info (332115): 1.846 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): 2.697 0.851 RR uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|rx_pma_rstb4
|
|
Info (332115): 2.698 0.001 RR IC fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_pma_rxpma_rstb
|
|
Info (332115): 2.698 0.000 RR CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 20.000 20.000 latch edge time
|
|
Info (332115): 21.005 1.005 R clock network delay
|
|
Info (332115): 20.885 -0.120 clock uncertainty
|
|
Info (332115): 20.680 -0.205 uTsu fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Data Arrival Time : 2.698
|
|
Info (332115): Data Required Time : 20.680
|
|
Info (332115): Slack : 17.982
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 18.074
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|rx_fref}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 18.074
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|rx_fref
|
|
Info (332115): Exception : dcp_bbs.sdc:3148: set_max_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pma_rxpma_rstb}] 20.000
|
|
Info (332115): Max Delay Exception : 20.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 1.846 1.846 R clock network delay
|
|
Info (332115): 1.846 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): 2.606 0.760 RR uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|rx_pma_rstb2
|
|
Info (332115): 2.606 0.000 RR IC fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_pma_rxpma_rstb
|
|
Info (332115): 2.606 0.000 RR CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 20.000 20.000 latch edge time
|
|
Info (332115): 21.005 1.005 R clock network delay
|
|
Info (332115): 20.885 -0.120 clock uncertainty
|
|
Info (332115): 20.680 -0.205 uTsu fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Data Arrival Time : 2.606
|
|
Info (332115): Data Required Time : 20.680
|
|
Info (332115): Slack : 18.074
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 18.097
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|rx_fref}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 18.097
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|rx_fref
|
|
Info (332115): Exception : dcp_bbs.sdc:3148: set_max_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pma_rxpma_rstb}] 20.000
|
|
Info (332115): Max Delay Exception : 20.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 1.846 1.846 R clock network delay
|
|
Info (332115): 1.846 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): 2.583 0.737 RR uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|rx_pma_rstb3
|
|
Info (332115): 2.583 0.000 RR IC fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_pma_rxpma_rstb
|
|
Info (332115): 2.583 0.000 RR CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 20.000 20.000 latch edge time
|
|
Info (332115): 21.005 1.005 R clock network delay
|
|
Info (332115): 20.885 -0.120 clock uncertainty
|
|
Info (332115): 20.680 -0.205 uTsu fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Data Arrival Time : 2.583
|
|
Info (332115): Data Required Time : 20.680
|
|
Info (332115): Slack : 18.097
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 18.546
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 18.546
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332115): Exception : dcp_bbs.sdc:3148: set_max_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pma_rxpma_rstb}] 20.000
|
|
Info (332115): Max Delay Exception : 20.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 1.846 1.846 R clock network delay
|
|
Info (332115): 1.846 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): 2.867 1.021 RR uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|rx_pma_rstb0
|
|
Info (332115): 2.867 0.000 RR IC fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_pma_rxpma_rstb
|
|
Info (332115): 2.867 0.000 RR CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 20.000 20.000 latch edge time
|
|
Info (332115): 20.970 0.970 R clock network delay
|
|
Info (332115): 21.648 0.678 clock pessimism removed
|
|
Info (332115): 21.618 -0.030 clock uncertainty
|
|
Info (332115): 21.413 -0.205 uTsu fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Data Arrival Time : 2.867
|
|
Info (332115): Data Required Time : 21.413
|
|
Info (332115): Slack : 18.546
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 18.648
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|rx_pma_clk}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 18.648
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|rx_pma_clk
|
|
Info (332115): Exception : dcp_bbs.sdc:3148: set_max_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pma_rxpma_rstb}] 20.000
|
|
Info (332115): Max Delay Exception : 20.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 1.846 1.846 R clock network delay
|
|
Info (332115): 1.846 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): 3.031 1.185 FF uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|rx_pma_rstb7
|
|
Info (332115): 3.031 0.000 FF IC fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_pma_rxpma_rstb
|
|
Info (332115): 3.031 0.000 FF CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 20.000 20.000 latch edge time
|
|
Info (332115): 21.799 1.799 R clock network delay
|
|
Info (332115): 21.679 -0.120 clock uncertainty
|
|
Info (332115): 21.679 0.000 uTsu fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Data Arrival Time : 3.031
|
|
Info (332115): Data Required Time : 21.679
|
|
Info (332115): Slack : 18.648
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 18.848
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|rx_pma_clk}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 18.848
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|rx_pma_clk
|
|
Info (332115): Exception : dcp_bbs.sdc:3148: set_max_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pma_rxpma_rstb}] 20.000
|
|
Info (332115): Max Delay Exception : 20.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 1.846 1.846 R clock network delay
|
|
Info (332115): 1.846 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): 2.831 0.985 RR uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|rx_pma_rstb6
|
|
Info (332115): 2.831 0.000 RR IC fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_pma_rxpma_rstb
|
|
Info (332115): 2.831 0.000 RR CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 20.000 20.000 latch edge time
|
|
Info (332115): 21.799 1.799 R clock network delay
|
|
Info (332115): 21.679 -0.120 clock uncertainty
|
|
Info (332115): 21.679 0.000 uTsu fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Data Arrival Time : 2.831
|
|
Info (332115): Data Required Time : 21.679
|
|
Info (332115): Slack : 18.848
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 18.902
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|rx_pma_clk}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 18.902
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|rx_pma_clk
|
|
Info (332115): Exception : dcp_bbs.sdc:3148: set_max_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pma_rxpma_rstb}] 20.000
|
|
Info (332115): Max Delay Exception : 20.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 1.846 1.846 R clock network delay
|
|
Info (332115): 1.846 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): 2.705 0.859 RR uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|rx_pma_rstb1
|
|
Info (332115): 2.705 0.000 RR IC fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_pma_rxpma_rstb
|
|
Info (332115): 2.705 0.000 RR CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 20.000 20.000 latch edge time
|
|
Info (332115): 21.727 1.727 R clock network delay
|
|
Info (332115): 21.607 -0.120 clock uncertainty
|
|
Info (332115): 21.607 0.000 uTsu fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Data Arrival Time : 2.705
|
|
Info (332115): Data Required Time : 21.607
|
|
Info (332115): Slack : 18.902
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 18.906
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|rx_pma_clk}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 18.906
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|rx_pma_clk
|
|
Info (332115): Exception : dcp_bbs.sdc:3148: set_max_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pma_rxpma_rstb}] 20.000
|
|
Info (332115): Max Delay Exception : 20.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 1.846 1.846 R clock network delay
|
|
Info (332115): 1.846 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): 2.773 0.927 RR uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|rx_pma_rstb5
|
|
Info (332115): 2.773 0.000 RR IC fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_pma_rxpma_rstb
|
|
Info (332115): 2.773 0.000 RR CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 20.000 20.000 latch edge time
|
|
Info (332115): 21.799 1.799 R clock network delay
|
|
Info (332115): 21.679 -0.120 clock uncertainty
|
|
Info (332115): 21.679 0.000 uTsu fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Data Arrival Time : 2.773
|
|
Info (332115): Data Required Time : 21.679
|
|
Info (332115): Slack : 18.906
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 18.944
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|rx_pma_clk}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 18.944
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|rx_pma_clk
|
|
Info (332115): Exception : dcp_bbs.sdc:3148: set_max_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pma_rxpma_rstb}] 20.000
|
|
Info (332115): Max Delay Exception : 20.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 1.846 1.846 R clock network delay
|
|
Info (332115): 1.846 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): 2.697 0.851 RR uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|rx_pma_rstb4
|
|
Info (332115): 2.698 0.001 RR IC fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_pma_rxpma_rstb
|
|
Info (332115): 2.698 0.000 RR CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 20.000 20.000 latch edge time
|
|
Info (332115): 21.762 1.762 R clock network delay
|
|
Info (332115): 21.642 -0.120 clock uncertainty
|
|
Info (332115): 21.642 0.000 uTsu fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Data Arrival Time : 2.698
|
|
Info (332115): Data Required Time : 21.642
|
|
Info (332115): Slack : 18.944
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 18.954
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_pma_clk}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 18.954
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_pma_clk
|
|
Info (332115): Exception : dcp_bbs.sdc:3148: set_max_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pma_rxpma_rstb}] 20.000
|
|
Info (332115): Max Delay Exception : 20.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 1.846 1.846 R clock network delay
|
|
Info (332115): 1.846 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): 2.867 1.021 RR uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|rx_pma_rstb0
|
|
Info (332115): 2.867 0.000 RR IC fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_pma_rxpma_rstb
|
|
Info (332115): 2.867 0.000 RR CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 20.000 20.000 latch edge time
|
|
Info (332115): 21.727 1.727 R clock network delay
|
|
Info (332115): 21.841 0.114 clock pessimism removed
|
|
Info (332115): 21.821 -0.020 clock uncertainty
|
|
Info (332115): 21.821 0.000 uTsu fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Data Arrival Time : 2.867
|
|
Info (332115): Data Required Time : 21.821
|
|
Info (332115): Slack : 18.954
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 19.036
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|rx_pma_clk}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 19.036
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|rx_pma_clk
|
|
Info (332115): Exception : dcp_bbs.sdc:3148: set_max_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pma_rxpma_rstb}] 20.000
|
|
Info (332115): Max Delay Exception : 20.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 1.846 1.846 R clock network delay
|
|
Info (332115): 1.846 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): 2.606 0.760 RR uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|rx_pma_rstb2
|
|
Info (332115): 2.606 0.000 RR IC fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_pma_rxpma_rstb
|
|
Info (332115): 2.606 0.000 RR CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 20.000 20.000 latch edge time
|
|
Info (332115): 21.762 1.762 R clock network delay
|
|
Info (332115): 21.642 -0.120 clock uncertainty
|
|
Info (332115): 21.642 0.000 uTsu fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Data Arrival Time : 2.606
|
|
Info (332115): Data Required Time : 21.642
|
|
Info (332115): Slack : 19.036
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 19.059
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|rx_pma_clk}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 19.059
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|rx_pma_clk
|
|
Info (332115): Exception : dcp_bbs.sdc:3148: set_max_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pma_rxpma_rstb}] 20.000
|
|
Info (332115): Max Delay Exception : 20.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 1.846 1.846 R clock network delay
|
|
Info (332115): 1.846 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): 2.583 0.737 RR uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|rx_pma_rstb3
|
|
Info (332115): 2.583 0.000 RR IC fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_pma_rxpma_rstb
|
|
Info (332115): 2.583 0.000 RR CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 20.000 20.000 latch edge time
|
|
Info (332115): 21.762 1.762 R clock network delay
|
|
Info (332115): 21.642 -0.120 clock uncertainty
|
|
Info (332115): 21.642 0.000 uTsu fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Data Arrival Time : 2.583
|
|
Info (332115): Data Required Time : 21.642
|
|
Info (332115): Slack : 19.059
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 44.130
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|tx_pma_clk}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 44.130
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi_txdig_ena
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_tx_pld_pcs_interface.inst_twentynm_hssi_tx_pld_pcs_interface~pld_pmaif_tx_pld_rst_n_reg.reg
|
|
Info (332115): Launch Clock : SYS_RefClk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|tx_pma_clk
|
|
Info (332115): Exception : dcp_bbs.sdc:3144: set_max_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pmaif_tx_pld_rst_n}] 50.000
|
|
Info (332115): Max Delay Exception : 50.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 2.726 2.726 R clock network delay
|
|
Info (332115): 2.726 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi_txdig_ena
|
|
Info (332115): 2.903 0.177 RR uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi_txdig_ena|q
|
|
Info (332115): 2.963 0.060 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi_txdig_ena~la_mlab/laboutb[17]
|
|
Info (332115): 4.598 1.635 RR IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0|datac
|
|
Info (332115): 4.691 0.093 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0|combout
|
|
Info (332115): 4.696 0.005 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0~la_mlab/laboutb[18]
|
|
Info (332115): 7.059 2.363 RR IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_tx_pld_pcs_interface.inst_twentynm_hssi_tx_pld_pcs_interface|pld_pmaif_tx_pld_rst_n
|
|
Info (332115): 7.059 0.000 RR CELL fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_tx_pld_pcs_interface.inst_twentynm_hssi_tx_pld_pcs_interface~pld_pmaif_tx_pld_rst_n_reg.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 50.000 50.000 latch edge time
|
|
Info (332115): 51.387 1.387 R clock network delay
|
|
Info (332115): 51.317 -0.070 clock uncertainty
|
|
Info (332115): 51.189 -0.128 uTsu fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_tx_pld_pcs_interface.inst_twentynm_hssi_tx_pld_pcs_interface~pld_pmaif_tx_pld_rst_n_reg.reg
|
|
Info (332115): Data Arrival Time : 7.059
|
|
Info (332115): Data Required Time : 51.189
|
|
Info (332115): Slack : 44.130
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 44.231
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|tx_pma_clk}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 44.231
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi_txdig_ena
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_tx_pld_pcs_interface.inst_twentynm_hssi_tx_pld_pcs_interface~pld_pmaif_tx_pld_rst_n_reg.reg
|
|
Info (332115): Launch Clock : SYS_RefClk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|tx_pma_clk
|
|
Info (332115): Exception : dcp_bbs.sdc:3144: set_max_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pmaif_tx_pld_rst_n}] 50.000
|
|
Info (332115): Max Delay Exception : 50.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 2.726 2.726 R clock network delay
|
|
Info (332115): 2.726 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi_txdig_ena
|
|
Info (332115): 2.903 0.177 RR uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi_txdig_ena|q
|
|
Info (332115): 2.963 0.060 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi_txdig_ena~la_mlab/laboutb[17]
|
|
Info (332115): 4.466 1.503 RR IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0|datac
|
|
Info (332115): 4.551 0.085 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0|combout
|
|
Info (332115): 4.555 0.004 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0~la_lab/laboutt[8]
|
|
Info (332115): 6.958 2.403 RR IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_tx_pld_pcs_interface.inst_twentynm_hssi_tx_pld_pcs_interface|pld_pmaif_tx_pld_rst_n
|
|
Info (332115): 6.958 0.000 RR CELL fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_tx_pld_pcs_interface.inst_twentynm_hssi_tx_pld_pcs_interface~pld_pmaif_tx_pld_rst_n_reg.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 50.000 50.000 latch edge time
|
|
Info (332115): 51.387 1.387 R clock network delay
|
|
Info (332115): 51.317 -0.070 clock uncertainty
|
|
Info (332115): 51.189 -0.128 uTsu fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_tx_pld_pcs_interface.inst_twentynm_hssi_tx_pld_pcs_interface~pld_pmaif_tx_pld_rst_n_reg.reg
|
|
Info (332115): Data Arrival Time : 6.958
|
|
Info (332115): Data Required Time : 51.189
|
|
Info (332115): Slack : 44.231
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 44.381
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|tx_pma_clk}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 44.381
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi_txdig_ena
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs~pld_8g_g3_tx_pld_rst_n_reg.reg
|
|
Info (332115): Launch Clock : SYS_RefClk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|tx_pma_clk
|
|
Info (332115): Exception : dcp_bbs.sdc:3145: set_max_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_8g_g3_tx_pld_rst_n}] 50.000
|
|
Info (332115): Max Delay Exception : 50.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 2.726 2.726 R clock network delay
|
|
Info (332115): 2.726 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi_txdig_ena
|
|
Info (332115): 2.903 0.177 RR uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi_txdig_ena|q
|
|
Info (332115): 2.963 0.060 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi_txdig_ena~la_mlab/laboutb[17]
|
|
Info (332115): 4.505 1.542 RR IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0|datac
|
|
Info (332115): 4.598 0.093 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0|combout
|
|
Info (332115): 4.603 0.005 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0~la_mlab/laboutb[18]
|
|
Info (332115): 6.896 2.293 RR IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_tx_pld_pcs_interface.inst_twentynm_hssi_tx_pld_pcs_interface|pld_8g_g3_tx_pld_rst_n
|
|
Info (332115): 6.896 0.000 RR CELL fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs~pld_8g_g3_tx_pld_rst_n_reg.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 50.000 50.000 latch edge time
|
|
Info (332115): 51.406 1.406 R clock network delay
|
|
Info (332115): 51.336 -0.070 clock uncertainty
|
|
Info (332115): 51.277 -0.059 uTsu fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs~pld_8g_g3_tx_pld_rst_n_reg.reg
|
|
Info (332115): Data Arrival Time : 6.896
|
|
Info (332115): Data Required Time : 51.277
|
|
Info (332115): Slack : 44.381
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 44.615
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|tx_pma_clk}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 44.615
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi_txdig_ena
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs~pld_8g_g3_tx_pld_rst_n_reg.reg
|
|
Info (332115): Launch Clock : SYS_RefClk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|tx_pma_clk
|
|
Info (332115): Exception : dcp_bbs.sdc:3145: set_max_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_8g_g3_tx_pld_rst_n}] 50.000
|
|
Info (332115): Max Delay Exception : 50.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 2.726 2.726 R clock network delay
|
|
Info (332115): 2.726 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi_txdig_ena
|
|
Info (332115): 2.903 0.177 RR uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi_txdig_ena|q
|
|
Info (332115): 2.963 0.060 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi_txdig_ena~la_mlab/laboutb[17]
|
|
Info (332115): 4.445 1.482 RR IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0|dataa
|
|
Info (332115): 4.585 0.140 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0|combout
|
|
Info (332115): 4.589 0.004 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0~la_lab/laboutb[16]
|
|
Info (332115): 6.662 2.073 RR IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_tx_pld_pcs_interface.inst_twentynm_hssi_tx_pld_pcs_interface|pld_8g_g3_tx_pld_rst_n
|
|
Info (332115): 6.662 0.000 RR CELL fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs~pld_8g_g3_tx_pld_rst_n_reg.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 50.000 50.000 latch edge time
|
|
Info (332115): 51.406 1.406 R clock network delay
|
|
Info (332115): 51.336 -0.070 clock uncertainty
|
|
Info (332115): 51.277 -0.059 uTsu fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs~pld_8g_g3_tx_pld_rst_n_reg.reg
|
|
Info (332115): Data Arrival Time : 6.662
|
|
Info (332115): Data Required Time : 51.277
|
|
Info (332115): Slack : 44.615
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 45.301
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|tx_coreclkin}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 45.301
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi_txdig_ena
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_10g_tx_pcs.inst_twentynm_hssi_10g_tx_pcs~pld_10g_krfec_tx_pld_rst_n_fifo.reg
|
|
Info (332115): Launch Clock : SYS_RefClk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|tx_coreclkin
|
|
Info (332115): Exception : dcp_bbs.sdc:3146: set_max_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_10g_krfec_tx_pld_rst_n}] 50.000
|
|
Info (332115): Max Delay Exception : 50.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 2.726 2.726 R clock network delay
|
|
Info (332115): 2.726 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi_txdig_ena
|
|
Info (332115): 2.903 0.177 RR uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi_txdig_ena|q
|
|
Info (332115): 2.963 0.060 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi_txdig_ena~la_mlab/laboutb[17]
|
|
Info (332115): 4.598 1.635 RR IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0|datac
|
|
Info (332115): 4.691 0.093 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0|combout
|
|
Info (332115): 4.696 0.005 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0~la_mlab/laboutb[18]
|
|
Info (332115): 7.104 2.408 RR IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_tx_pld_pcs_interface.inst_twentynm_hssi_tx_pld_pcs_interface|pld_10g_krfec_tx_pld_rst_n
|
|
Info (332115): 7.104 0.000 RR CELL fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_10g_tx_pcs.inst_twentynm_hssi_10g_tx_pcs~pld_10g_krfec_tx_pld_rst_n_fifo.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 50.000 50.000 latch edge time
|
|
Info (332115): 52.507 2.507 R clock network delay
|
|
Info (332115): 52.467 -0.040 clock uncertainty
|
|
Info (332115): 52.405 -0.062 uTsu fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_10g_tx_pcs.inst_twentynm_hssi_10g_tx_pcs~pld_10g_krfec_tx_pld_rst_n_fifo.reg
|
|
Info (332115): Data Arrival Time : 7.104
|
|
Info (332115): Data Required Time : 52.405
|
|
Info (332115): Slack : 45.301
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 45.518
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|tx_coreclkin}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 45.518
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi_txdig_ena
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_10g_tx_pcs.inst_twentynm_hssi_10g_tx_pcs~pld_10g_krfec_tx_pld_rst_n_fifo.reg
|
|
Info (332115): Launch Clock : SYS_RefClk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|tx_coreclkin
|
|
Info (332115): Exception : dcp_bbs.sdc:3146: set_max_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_10g_krfec_tx_pld_rst_n}] 50.000
|
|
Info (332115): Max Delay Exception : 50.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 2.726 2.726 R clock network delay
|
|
Info (332115): 2.726 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi_txdig_ena
|
|
Info (332115): 2.903 0.177 RR uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi_txdig_ena|q
|
|
Info (332115): 2.963 0.060 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi_txdig_ena~la_mlab/laboutb[17]
|
|
Info (332115): 4.466 1.503 RR IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0|datac
|
|
Info (332115): 4.551 0.085 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0|combout
|
|
Info (332115): 4.555 0.004 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0~la_lab/laboutt[8]
|
|
Info (332115): 6.890 2.335 RR IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_tx_pld_pcs_interface.inst_twentynm_hssi_tx_pld_pcs_interface|pld_10g_krfec_tx_pld_rst_n
|
|
Info (332115): 6.890 0.000 RR CELL fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_10g_tx_pcs.inst_twentynm_hssi_10g_tx_pcs~pld_10g_krfec_tx_pld_rst_n_fifo.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 50.000 50.000 latch edge time
|
|
Info (332115): 52.510 2.510 R clock network delay
|
|
Info (332115): 52.470 -0.040 clock uncertainty
|
|
Info (332115): 52.408 -0.062 uTsu fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_10g_tx_pcs.inst_twentynm_hssi_10g_tx_pcs~pld_10g_krfec_tx_pld_rst_n_fifo.reg
|
|
Info (332115): Data Arrival Time : 6.890
|
|
Info (332115): Data Required Time : 52.408
|
|
Info (332115): Slack : 45.518
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 45.631
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|tx_coreclkin}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 45.631
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi_txdig_ena
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_10g_tx_pcs.inst_twentynm_hssi_10g_tx_pcs~pld_10g_krfec_tx_pld_rst_n_fifo.reg
|
|
Info (332115): Launch Clock : SYS_RefClk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|tx_coreclkin
|
|
Info (332115): Exception : dcp_bbs.sdc:3146: set_max_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_10g_krfec_tx_pld_rst_n}] 50.000
|
|
Info (332115): Max Delay Exception : 50.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 2.726 2.726 R clock network delay
|
|
Info (332115): 2.726 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi_txdig_ena
|
|
Info (332115): 2.903 0.177 RR uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi_txdig_ena|q
|
|
Info (332115): 2.963 0.060 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi_txdig_ena~la_mlab/laboutb[17]
|
|
Info (332115): 4.505 1.542 RR IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0|datac
|
|
Info (332115): 4.598 0.093 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0|combout
|
|
Info (332115): 4.603 0.005 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0~la_mlab/laboutb[18]
|
|
Info (332115): 6.834 2.231 RR IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_tx_pld_pcs_interface.inst_twentynm_hssi_tx_pld_pcs_interface|pld_10g_krfec_tx_pld_rst_n
|
|
Info (332115): 6.834 0.000 RR CELL fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_10g_tx_pcs.inst_twentynm_hssi_10g_tx_pcs~pld_10g_krfec_tx_pld_rst_n_fifo.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 50.000 50.000 latch edge time
|
|
Info (332115): 52.567 2.567 R clock network delay
|
|
Info (332115): 52.527 -0.040 clock uncertainty
|
|
Info (332115): 52.465 -0.062 uTsu fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_10g_tx_pcs.inst_twentynm_hssi_10g_tx_pcs~pld_10g_krfec_tx_pld_rst_n_fifo.reg
|
|
Info (332115): Data Arrival Time : 6.834
|
|
Info (332115): Data Required Time : 52.465
|
|
Info (332115): Slack : 45.631
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 45.740
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|tx_coreclkin}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 45.740
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi_txdig_ena
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_10g_tx_pcs.inst_twentynm_hssi_10g_tx_pcs~pld_10g_krfec_tx_pld_rst_n_fifo.reg
|
|
Info (332115): Launch Clock : SYS_RefClk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|tx_coreclkin
|
|
Info (332115): Exception : dcp_bbs.sdc:3146: set_max_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_10g_krfec_tx_pld_rst_n}] 50.000
|
|
Info (332115): Max Delay Exception : 50.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 2.726 2.726 R clock network delay
|
|
Info (332115): 2.726 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi_txdig_ena
|
|
Info (332115): 2.903 0.177 RR uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi_txdig_ena|q
|
|
Info (332115): 2.963 0.060 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|hssi_txdig_ena~la_mlab/laboutb[17]
|
|
Info (332115): 4.445 1.482 RR IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0|dataa
|
|
Info (332115): 4.585 0.140 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0|combout
|
|
Info (332115): 4.589 0.004 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0~la_lab/laboutb[16]
|
|
Info (332115): 6.662 2.073 RR IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_tx_pld_pcs_interface.inst_twentynm_hssi_tx_pld_pcs_interface|pld_10g_krfec_tx_pld_rst_n
|
|
Info (332115): 6.662 0.000 RR CELL fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_10g_tx_pcs.inst_twentynm_hssi_10g_tx_pcs~pld_10g_krfec_tx_pld_rst_n_fifo.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 50.000 50.000 latch edge time
|
|
Info (332115): 52.504 2.504 R clock network delay
|
|
Info (332115): 52.464 -0.040 clock uncertainty
|
|
Info (332115): 52.402 -0.062 uTsu fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_10g_tx_pcs.inst_twentynm_hssi_10g_tx_pcs~pld_10g_krfec_tx_pld_rst_n_fifo.reg
|
|
Info (332115): Data Arrival Time : 6.662
|
|
Info (332115): Data Required Time : 52.402
|
|
Info (332115): Slack : 45.740
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 recovery paths (0 violated). Worst case slack is 98.341
|
|
Info (20696): -to_clock [get_clocks {altera_reserved_tck}]
|
|
Info (20696): -recovery
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Recovery slack is 98.341
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|host_link_jtag|jtag|normal.jtag_dc_streaming|synchronizer|dreg[1]
|
|
Info (332115): To Node : auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|host_link_jtag|jtag|normal.jtag_dc_streaming|jtag_streaming|idle_inserter|received_esc
|
|
Info (332115): Launch Clock : altera_reserved_tck
|
|
Info (332115): Latch Clock : altera_reserved_tck
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 2.365 2.365 R clock network delay
|
|
Info (332115): 2.365 0.000 auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|host_link_jtag|jtag|normal.jtag_dc_streaming|synchronizer|dreg[1]
|
|
Info (332115): 2.491 0.126 RR uTco auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|host_link_jtag|jtag|normal.jtag_dc_streaming|synchronizer|dreg[1]|q
|
|
Info (332115): 2.579 0.088 RR CELL High Speed auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|host_link_jtag|jtag|normal.jtag_dc_streaming|synchronizer|dreg[1]~la_lab/laboutt[0]
|
|
Info (332115): 3.471 0.892 RR IC High Speed auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|host_link_jtag|jtag|normal.jtag_dc_streaming|jtag_streaming|idle_inserter|received_esc|clrn
|
|
Info (332115): 3.471 0.000 RR CELL High Speed auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|host_link_jtag|jtag|normal.jtag_dc_streaming|jtag_streaming|idle_inserter|received_esc
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 100.000 100.000 latch edge time
|
|
Info (332115): 101.812 1.812 R clock network delay
|
|
Info (332115): 101.904 0.092 clock pessimism removed
|
|
Info (332115): 101.874 -0.030 clock uncertainty
|
|
Info (332115): 101.812 -0.062 uTsu auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|host_link_jtag|jtag|normal.jtag_dc_streaming|jtag_streaming|idle_inserter|received_esc
|
|
Info (332115): Data Arrival Time : 3.471
|
|
Info (332115): Data Required Time : 101.812
|
|
Info (332115): Slack : 98.341
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 0.104
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk1}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 0.104
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|execute|fpu_unit|fpu_fpga|fp_div|[3].reset_relay|reset_r[0]
|
|
Info (332115): To Node : fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|execute|fpu_unit|fpu_fpga|fp_div|[3].fdiv|redist8_yAddr_uid51_fpDivTest_b_3|delays[0][3]
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk1
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk1
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 3.233 3.233 R clock network delay
|
|
Info (332115): 3.233 0.000 fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|execute|fpu_unit|fpu_fpga|fp_div|[3].reset_relay|reset_r[0]
|
|
Info (332115): 3.331 0.098 FF uTco fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|execute|fpu_unit|fpu_fpga|fp_div|[3].reset_relay|reset_r[0]|q
|
|
Info (332115): 3.364 0.033 FF CELL High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|execute|fpu_unit|fpu_fpga|fp_div|[3].reset_relay|reset_r[0]~la_mlab/laboutb[10]
|
|
Info (332115): 3.494 0.130 FF IC High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|execute|fpu_unit|fpu_fpga|fp_div|[3].fdiv|redist8_yAddr_uid51_fpDivTest_b_3|delays[0][3]|clrn
|
|
Info (332115): 3.494 0.000 FF CELL High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|execute|fpu_unit|fpu_fpga|fp_div|[3].fdiv|redist8_yAddr_uid51_fpDivTest_b_3|delays[0][3]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 3.875 3.875 R clock network delay
|
|
Info (332115): 3.334 -0.541 clock pessimism removed
|
|
Info (332115): 3.334 0.000 clock uncertainty
|
|
Info (332115): 3.390 0.056 uTh fpga_top|inst_green_bs|platform_shim_ccip_std_afu|ccip_std_afu|afu|vortex|[2].cluster|[0].core|pipeline|execute|fpu_unit|fpu_fpga|fp_div|[3].fdiv|redist8_yAddr_uid51_fpDivTest_b_3|delays[0][3]
|
|
Info (332115): Data Arrival Time : 3.494
|
|
Info (332115): Data Required Time : 3.390
|
|
Info (332115): Slack : 0.104
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 0.147
|
|
Info (20696): -to_clock [get_clocks {SYS_RefClk}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 0.147
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].avmm_reset_sync_inst|resync_chains[0].sync_r[1]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_read_cycles_cnt[2]
|
|
Info (332115): Launch Clock : SYS_RefClk
|
|
Info (332115): Latch Clock : SYS_RefClk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 2.482 2.482 R clock network delay
|
|
Info (332115): 2.482 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].avmm_reset_sync_inst|resync_chains[0].sync_r[1]
|
|
Info (332115): 2.579 0.097 RR uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].avmm_reset_sync_inst|resync_chains[0].sync_r[1]|q
|
|
Info (332115): 2.625 0.046 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].avmm_reset_sync_inst|resync_chains[0].sync_r[1]~la_lab/laboutb[14]
|
|
Info (332115): 2.702 0.077 RR IC High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_read_cycles_cnt[2]|clrn
|
|
Info (332115): 2.702 0.000 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_read_cycles_cnt[2]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 2.717 2.717 R clock network delay
|
|
Info (332115): 2.494 -0.223 clock pessimism removed
|
|
Info (332115): 2.494 0.000 clock uncertainty
|
|
Info (332115): 2.555 0.061 uTh fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_read_cycles_cnt[2]
|
|
Info (332115): Data Arrival Time : 2.702
|
|
Info (332115): Data Required Time : 2.555
|
|
Info (332115): Slack : 0.147
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 0.154
|
|
Info (20696): -to_clock [get_clocks {u0|dcp_iopll|dcp_iopll|clk1x}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 0.154
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|rdaclr|dffe7a[0]
|
|
Info (332115): To Node : fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|fifo_ram|ram_block7a563~reg1
|
|
Info (332115): Launch Clock : u0|dcp_iopll|dcp_iopll|clk1x
|
|
Info (332115): Latch Clock : u0|dcp_iopll|dcp_iopll|clk1x
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 4.811 4.811 R clock network delay
|
|
Info (332115): 4.811 0.000 fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|rdaclr|dffe7a[0]
|
|
Info (332115): 4.914 0.103 RR uTco fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|rdaclr|dffe7a[0]|q
|
|
Info (332115): 4.962 0.048 RR CELL High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|rdaclr|dffe7a[0]~la_lab/laboutt[5]
|
|
Info (332115): 5.067 0.105 RR IC High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|fifo_ram|ram_block7a563|clr1
|
|
Info (332115): 5.067 0.000 RR CELL High Speed fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|fifo_ram|ram_block7a563~reg1
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 5.557 5.557 R clock network delay
|
|
Info (332115): 4.818 -0.739 clock pessimism removed
|
|
Info (332115): 4.818 0.000 clock uncertainty
|
|
Info (332115): 4.913 0.095 uTh fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|fifo_ram|ram_block7a563~reg1
|
|
Info (332115): Data Arrival Time : 5.067
|
|
Info (332115): Data Required Time : 4.913
|
|
Info (332115): Slack : 0.154
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 0.159
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_clk}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 0.159
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_reset_sync|resync_chains[0].sync_r[2]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_snapshot[6]
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_clk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|rx_pma_clk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 2.939 2.939 R clock network delay
|
|
Info (332115): 2.939 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_reset_sync|resync_chains[0].sync_r[2]
|
|
Info (332115): 3.035 0.096 RR uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_reset_sync|resync_chains[0].sync_r[2]|q
|
|
Info (332115): 3.079 0.044 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_reset_sync|resync_chains[0].sync_r[2]~la_lab/laboutb[18]
|
|
Info (332115): 3.171 0.092 RR IC High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_snapshot[6]|clrn
|
|
Info (332115): 3.171 0.000 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_snapshot[6]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 3.847 3.847 R clock network delay
|
|
Info (332115): 2.946 -0.901 clock pessimism removed
|
|
Info (332115): 2.946 0.000 clock uncertainty
|
|
Info (332115): 3.012 0.066 uTh fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_err_snapshot[6]
|
|
Info (332115): Data Arrival Time : 3.171
|
|
Info (332115): Data Required Time : 3.012
|
|
Info (332115): Slack : 0.159
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 0.161
|
|
Info (20696): -to_clock [get_clocks {mem|ddr4a|ddr4a_core_usr_clk}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 0.161
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|reset_sync_pri_sdc_anchor
|
|
Info (332115): To Node : mem|ddr4a|ddr4a|arch|arch_inst|seq_if_inst|afi_cal_fail_sync_inst|dreg[0]
|
|
Info (332115): Launch Clock : mem|ddr4a|ddr4a_core_usr_clk
|
|
Info (332115): Latch Clock : mem|ddr4a|ddr4a_core_usr_clk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.117 0.117 launch edge time
|
|
Info (332115): 1.370 1.253 R clock network delay
|
|
Info (332115): 1.370 0.000 mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|reset_sync_pri_sdc_anchor
|
|
Info (332115): 1.468 0.098 RR uTco mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|reset_sync_pri_sdc_anchor|q
|
|
Info (332115): 1.516 0.048 RR CELL High Speed mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|reset_sync_pri_sdc_anchor~la_mlab/laboutb[13]
|
|
Info (332115): 1.608 0.092 RR IC High Speed mem|ddr4a|ddr4a|arch|arch_inst|seq_if_inst|afi_cal_fail_sync_inst|dreg[0]|clrn
|
|
Info (332115): 1.608 0.000 RR CELL High Speed mem|ddr4a|ddr4a|arch|arch_inst|seq_if_inst|afi_cal_fail_sync_inst|dreg[0]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.117 0.117 latch edge time
|
|
Info (332115): 1.864 1.747 R clock network delay
|
|
Info (332115): 1.382 -0.482 clock pessimism removed
|
|
Info (332115): 1.382 0.000 clock uncertainty
|
|
Info (332115): 1.447 0.065 uTh mem|ddr4a|ddr4a|arch|arch_inst|seq_if_inst|afi_cal_fail_sync_inst|dreg[0]
|
|
Info (332115): Data Arrival Time : 1.608
|
|
Info (332115): Data Required Time : 1.447
|
|
Info (332115): Slack : 0.161
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 0.172
|
|
Info (20696): -to_clock [get_clocks {mem|ddr4a|ddr4a_core_cal_slave_clk}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 0.172
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : mem|ddr4b|ddr4b|cal_slave_component|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out
|
|
Info (332115): To Node : mem|ddr4b|ddr4b|cal_slave_component|ioaux_master_bridge|wr_reg_write
|
|
Info (332115): Launch Clock : mem|ddr4a|ddr4a_core_cal_slave_clk
|
|
Info (332115): Latch Clock : mem|ddr4a|ddr4a_core_cal_slave_clk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 3.235 3.235 R clock network delay
|
|
Info (332115): 3.235 0.000 mem|ddr4b|ddr4b|cal_slave_component|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out
|
|
Info (332115): 3.338 0.103 RR uTco mem|ddr4b|ddr4b|cal_slave_component|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out|q
|
|
Info (332115): 3.403 0.065 RR CELL High Speed mem|ddr4b|ddr4b|cal_slave_component|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~la_mlab/laboutb[11]
|
|
Info (332115): 3.483 0.080 RR IC High Speed mem|ddr4b|ddr4b|cal_slave_component|ioaux_master_bridge|wr_reg_write|clrn
|
|
Info (332115): 3.483 0.000 RR CELL High Speed mem|ddr4b|ddr4b|cal_slave_component|ioaux_master_bridge|wr_reg_write
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 3.779 3.779 R clock network delay
|
|
Info (332115): 3.235 -0.544 clock pessimism removed
|
|
Info (332115): 3.235 0.000 clock uncertainty
|
|
Info (332115): 3.311 0.076 uTh mem|ddr4b|ddr4b|cal_slave_component|ioaux_master_bridge|wr_reg_write
|
|
Info (332115): Data Arrival Time : 3.483
|
|
Info (332115): Data Required Time : 3.311
|
|
Info (332115): Slack : 0.172
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 0.172
|
|
Info (20696): -to_clock [get_clocks {u0|dcp_iopll|dcp_iopll|clk100}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 0.172
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|tcm_control_out|pio_0|data_out[0]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_006|async_clock_crosser.clock_xer|in_data_buffer[5]
|
|
Info (332115): Launch Clock : u0|dcp_iopll|dcp_iopll|clk1x
|
|
Info (332115): Latch Clock : u0|dcp_iopll|dcp_iopll|clk100
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 4.825 4.825 R clock network delay
|
|
Info (332115): 4.825 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|tcm_control_out|pio_0|data_out[0]
|
|
Info (332115): 4.927 0.102 FF uTco fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|tcm_control_out|pio_0|data_out[0]|q
|
|
Info (332115): 4.962 0.035 FF CELL Low Power fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|tcm_control_out|pio_0|data_out[0]~la_lab/laboutt[17]
|
|
Info (332115): 5.486 0.524 FF IC Mixed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_006|async_clock_crosser.clock_xer|in_data_buffer[5]|clrn
|
|
Info (332115): 5.486 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_006|async_clock_crosser.clock_xer|in_data_buffer[5]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 5.594 5.594 R clock network delay
|
|
Info (332115): 5.102 -0.492 clock pessimism removed
|
|
Info (332115): 5.262 0.160 clock uncertainty
|
|
Info (332115): 5.314 0.052 uTh fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|mm_interconnect_0|crosser_006|async_clock_crosser.clock_xer|in_data_buffer[5]
|
|
Info (332115): Data Arrival Time : 5.486
|
|
Info (332115): Data Required Time : 5.314
|
|
Info (332115): Slack : 0.172
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 0.174
|
|
Info (20696): -to_clock [get_clocks {PCIE_REFCLK}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 0.174
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].avmm_reset_sync_inst|resync_chains[0].sync_r[1]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_read_cycles_cnt[1]
|
|
Info (332115): Launch Clock : PCIE_REFCLK
|
|
Info (332115): Latch Clock : PCIE_REFCLK
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 3.113 3.113 R clock network delay
|
|
Info (332115): 3.113 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].avmm_reset_sync_inst|resync_chains[0].sync_r[1]
|
|
Info (332115): 3.210 0.097 RR uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].avmm_reset_sync_inst|resync_chains[0].sync_r[1]|q
|
|
Info (332115): 3.256 0.046 RR CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].avmm_reset_sync_inst|resync_chains[0].sync_r[1]~la_lab/laboutt[10]
|
|
Info (332115): 3.344 0.088 RR IC High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_read_cycles_cnt[1]|clrn
|
|
Info (332115): 3.344 0.000 RR CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_read_cycles_cnt[1]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 3.470 3.470 R clock network delay
|
|
Info (332115): 3.113 -0.357 clock pessimism removed
|
|
Info (332115): 3.113 0.000 clock uncertainty
|
|
Info (332115): 3.170 0.057 uTh fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_read_cycles_cnt[1]
|
|
Info (332115): Data Arrival Time : 3.344
|
|
Info (332115): Data Required Time : 3.170
|
|
Info (332115): Slack : 0.174
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 0.192
|
|
Info (20696): -to_clock [get_clocks {DDR4_RefClk}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 0.192
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|use_counter_lock.counter_lock_gen_master.pll_ref_clk_reset_n_sync_rrr
|
|
Info (332115): To Node : mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|use_counter_lock.counter_lock_gen_master.cpa_count_to_lock[16]~LRTM_3
|
|
Info (332115): Launch Clock : DDR4_RefClk
|
|
Info (332115): Latch Clock : DDR4_RefClk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 2.343 2.343 R clock network delay
|
|
Info (332115): 2.343 0.000 mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|use_counter_lock.counter_lock_gen_master.pll_ref_clk_reset_n_sync_rrr
|
|
Info (332115): 2.446 0.103 RR uTco mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|use_counter_lock.counter_lock_gen_master.pll_ref_clk_reset_n_sync_rrr|q
|
|
Info (332115): 2.509 0.063 RR CELL High Speed mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|use_counter_lock.counter_lock_gen_master.pll_ref_clk_reset_n_sync_rrr~la_mlab/laboutb[4]
|
|
Info (332115): 2.592 0.083 RR IC High Speed mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|use_counter_lock.counter_lock_gen_master.cpa_count_to_lock[16]~LRTM_3|clrn
|
|
Info (332115): 2.592 0.000 RR CELL High Speed mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|use_counter_lock.counter_lock_gen_master.cpa_count_to_lock[16]~LRTM_3
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 2.537 2.537 R clock network delay
|
|
Info (332115): 2.342 -0.195 clock pessimism removed
|
|
Info (332115): 2.342 0.000 clock uncertainty
|
|
Info (332115): 2.400 0.058 uTh mem|ddr4a|ddr4a|arch|arch_inst|non_hps.core_clks_rsts_inst|use_counter_lock.counter_lock_gen_master.cpa_count_to_lock[16]~LRTM_3
|
|
Info (332115): Data Arrival Time : 2.592
|
|
Info (332115): Data Required Time : 2.400
|
|
Info (332115): Slack : 0.192
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 0.193
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|wys~CORE_CLK_OUT}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 0.193
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_rst_sync.syncrstn_avmm_sriov.app_rstn_altpcie_reset_delay_sync_altpcie_a10_hip_hwtcl|sync_rst[1]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_sriov_2.sriov2.lmi_burst_intf|hip_lmi_addr_o[4]
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|wys~CORE_CLK_OUT
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|wys~CORE_CLK_OUT
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 4.407 4.407 R clock network delay
|
|
Info (332115): 4.407 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_rst_sync.syncrstn_avmm_sriov.app_rstn_altpcie_reset_delay_sync_altpcie_a10_hip_hwtcl|sync_rst[1]
|
|
Info (332115): 4.504 0.097 RR uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_rst_sync.syncrstn_avmm_sriov.app_rstn_altpcie_reset_delay_sync_altpcie_a10_hip_hwtcl|sync_rst[1]|q
|
|
Info (332115): 4.550 0.046 RR CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_rst_sync.syncrstn_avmm_sriov.app_rstn_altpcie_reset_delay_sync_altpcie_a10_hip_hwtcl|sync_rst[1]~la_mlab/laboutt[9]
|
|
Info (332115): 4.681 0.131 RR IC High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_sriov_2.sriov2.lmi_burst_intf|hip_lmi_addr_o[4]|clrn
|
|
Info (332115): 4.681 0.000 RR CELL High Speed fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_sriov_2.sriov2.lmi_burst_intf|hip_lmi_addr_o[4]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 5.213 5.213 R clock network delay
|
|
Info (332115): 4.419 -0.794 clock pessimism removed
|
|
Info (332115): 4.488 0.069 uTh fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_sriov_2.sriov2.lmi_burst_intf|hip_lmi_addr_o[4]
|
|
Info (332115): Data Arrival Time : 4.681
|
|
Info (332115): Data Required Time : 4.488
|
|
Info (332115): Slack : 0.193
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 0.202
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|rx_pma_clk}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 0.202
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_reset_sync|resync_chains[0].sync_r[2]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_error_high
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|rx_pma_clk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|rx_pma_clk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 2.913 2.913 R clock network delay
|
|
Info (332115): 2.913 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_reset_sync|resync_chains[0].sync_r[2]
|
|
Info (332115): 3.009 0.096 RR uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_reset_sync|resync_chains[0].sync_r[2]|q
|
|
Info (332115): 3.053 0.044 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_reset_sync|resync_chains[0].sync_r[2]~la_lab/laboutb[18]
|
|
Info (332115): 3.191 0.138 RR IC High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_error_high|clrn
|
|
Info (332115): 3.191 0.000 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_error_high
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 3.829 3.829 R clock network delay
|
|
Info (332115): 2.925 -0.904 clock pessimism removed
|
|
Info (332115): 2.925 0.000 clock uncertainty
|
|
Info (332115): 2.989 0.064 uTh fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_error_high
|
|
Info (332115): Data Arrival Time : 3.191
|
|
Info (332115): Data Required Time : 2.989
|
|
Info (332115): Slack : 0.202
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 0.215
|
|
Info (20696): -to_clock [get_clocks {u0|dcp_iopll|dcp_iopll|clk25}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 0.215
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|generic_quad_spi_controller2_0|generic_quad_spi_controller2_0|asmi2_inst_qspi_ctrl|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|generic_quad_spi_controller2_0|generic_quad_spi_controller2_0|asmi2_inst_qspi_ctrl|asmi2_qspi_interface_0|read_cnt_q[2]
|
|
Info (332115): Launch Clock : u0|dcp_iopll|dcp_iopll|clk25
|
|
Info (332115): Latch Clock : u0|dcp_iopll|dcp_iopll|clk25
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 4.918 4.918 R clock network delay
|
|
Info (332115): 4.918 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|generic_quad_spi_controller2_0|generic_quad_spi_controller2_0|asmi2_inst_qspi_ctrl|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out
|
|
Info (332115): 5.026 0.108 RR uTco fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|generic_quad_spi_controller2_0|generic_quad_spi_controller2_0|asmi2_inst_qspi_ctrl|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out|q
|
|
Info (332115): 5.074 0.048 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|generic_quad_spi_controller2_0|generic_quad_spi_controller2_0|asmi2_inst_qspi_ctrl|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~la_mlab/laboutb[5]
|
|
Info (332115): 5.195 0.121 RR IC High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|generic_quad_spi_controller2_0|generic_quad_spi_controller2_0|asmi2_inst_qspi_ctrl|asmi2_qspi_interface_0|read_cnt_q[2]|clrn
|
|
Info (332115): 5.195 0.000 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|generic_quad_spi_controller2_0|generic_quad_spi_controller2_0|asmi2_inst_qspi_ctrl|asmi2_qspi_interface_0|read_cnt_q[2]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 5.709 5.709 R clock network delay
|
|
Info (332115): 4.919 -0.790 clock pessimism removed
|
|
Info (332115): 4.919 0.000 clock uncertainty
|
|
Info (332115): 4.980 0.061 uTh fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|inst_tcm|generic_quad_spi_controller2_0|generic_quad_spi_controller2_0|asmi2_inst_qspi_ctrl|asmi2_qspi_interface_0|read_cnt_q[2]
|
|
Info (332115): Data Arrival Time : 5.195
|
|
Info (332115): Data Required Time : 4.980
|
|
Info (332115): Slack : 0.215
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 0.221
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|rx_pma_clk}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 0.221
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_reset_sync|resync_chains[0].sync_r[2]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_prbs_err_sync|resync_chains[0].sync_r[1]
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|rx_pma_clk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|rx_pma_clk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 2.845 2.845 R clock network delay
|
|
Info (332115): 2.845 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_reset_sync|resync_chains[0].sync_r[2]
|
|
Info (332115): 2.943 0.098 RR uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_reset_sync|resync_chains[0].sync_r[2]|q
|
|
Info (332115): 2.987 0.044 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_reset_sync|resync_chains[0].sync_r[2]~la_mlab/laboutb[2]
|
|
Info (332115): 3.163 0.176 RR IC High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_prbs_err_sync|resync_chains[0].sync_r[1]|clrn
|
|
Info (332115): 3.163 0.000 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_prbs_err_sync|resync_chains[0].sync_r[1]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 3.767 3.767 R clock network delay
|
|
Info (332115): 2.875 -0.892 clock pessimism removed
|
|
Info (332115): 2.875 0.000 clock uncertainty
|
|
Info (332115): 2.942 0.067 uTh fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_prbs_err_sync|resync_chains[0].sync_r[1]
|
|
Info (332115): Data Arrival Time : 3.163
|
|
Info (332115): Data Required Time : 2.942
|
|
Info (332115): Slack : 0.221
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 0.243
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|rx_pma_clk}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 0.243
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_reset_sync|resync_chains[0].sync_r[2]
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_bit_count[1]
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|rx_pma_clk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|rx_pma_clk
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 2.935 2.935 R clock network delay
|
|
Info (332115): 2.935 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_reset_sync|resync_chains[0].sync_r[2]
|
|
Info (332115): 3.033 0.098 RR uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_reset_sync|resync_chains[0].sync_r[2]|q
|
|
Info (332115): 3.081 0.048 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_clk_reset_sync|resync_chains[0].sync_r[2]~la_mlab/laboutb[5]
|
|
Info (332115): 3.259 0.178 RR IC High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_bit_count[1]|clrn
|
|
Info (332115): 3.259 0.000 RR CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_bit_count[1]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 3.838 3.838 R clock network delay
|
|
Info (332115): 2.948 -0.890 clock pessimism removed
|
|
Info (332115): 2.948 0.000 clock uncertainty
|
|
Info (332115): 3.016 0.068 uTh fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_prbs_accumulators_enable.prbs_soft_accumulators|rx_prbs_bit_count[1]
|
|
Info (332115): Data Arrival Time : 3.259
|
|
Info (332115): Data Required Time : 3.016
|
|
Info (332115): Slack : 0.243
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 0.526
|
|
Info (20696): -to_clock [get_clocks {altera_reserved_tck}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 0.526
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|host_link_jtag|jtag|normal.jtag_dc_streaming|synchronizer|dreg[1]
|
|
Info (332115): To Node : auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|host_link_jtag|jtag|normal.jtag_dc_streaming|sink_crosser|in_to_out_synchronizer|dreg[1]
|
|
Info (332115): Launch Clock : altera_reserved_tck
|
|
Info (332115): Latch Clock : altera_reserved_tck
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 1.917 1.917 R clock network delay
|
|
Info (332115): 1.917 0.000 auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|host_link_jtag|jtag|normal.jtag_dc_streaming|synchronizer|dreg[1]
|
|
Info (332115): 2.021 0.104 RR uTco auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|host_link_jtag|jtag|normal.jtag_dc_streaming|synchronizer|dreg[1]|q
|
|
Info (332115): 2.085 0.064 RR CELL High Speed auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|host_link_jtag|jtag|normal.jtag_dc_streaming|synchronizer|dreg[1]~la_lab/laboutt[0]
|
|
Info (332115): 2.519 0.434 RR IC High Speed auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|host_link_jtag|jtag|normal.jtag_dc_streaming|sink_crosser|in_to_out_synchronizer|dreg[1]|clrn
|
|
Info (332115): 2.519 0.000 RR CELL High Speed auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|host_link_jtag|jtag|normal.jtag_dc_streaming|sink_crosser|in_to_out_synchronizer|dreg[1]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 2.365 2.365 R clock network delay
|
|
Info (332115): 1.920 -0.445 clock pessimism removed
|
|
Info (332115): 1.920 0.000 clock uncertainty
|
|
Info (332115): 1.993 0.073 uTh auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|host_link_jtag|jtag|normal.jtag_dc_streaming|sink_crosser|in_to_out_synchronizer|dreg[1]
|
|
Info (332115): Data Arrival Time : 2.519
|
|
Info (332115): Data Required Time : 1.993
|
|
Info (332115): Slack : 0.526
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 0.815
|
|
Info (20696): -to_clock [get_clocks {filtered_sclk_negedge}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 0.815
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|SPISlaveToAvalonMasterBridge_reset_clk_domain_synch|data_out
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MOSIctl|stsourcedata[4]
|
|
Info (332115): Launch Clock : u0|dcp_iopll|dcp_iopll|clk1x
|
|
Info (332115): Latch Clock : filtered_sclk_negedge
|
|
Info (332115): Exception : dcp_bbs.sdc:3061: set_multicycle_path -hold -from [get_keepers {*SPISlaveToAvalonMasterBridge_reset_clk_domain_synch|data_out}] -to [get_keepers {*SPIPhy_MOSIctl|stsourcedata*}] 1
|
|
Info (332115): Multicycle - Setup Start : 3
|
|
Info (332115): Multicycle - Hold Start : 1
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 245.000 245.000 launch edge time
|
|
Info (332115): 249.820 4.820 R clock network delay
|
|
Info (332115): 249.820 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|SPISlaveToAvalonMasterBridge_reset_clk_domain_synch|data_out
|
|
Info (332115): 249.933 0.113 RR uTco fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|SPISlaveToAvalonMasterBridge_reset_clk_domain_synch|data_out|q
|
|
Info (332115): 249.981 0.048 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|SPISlaveToAvalonMasterBridge_reset_clk_domain_synch|data_out~la_mlab/laboutt[1]
|
|
Info (332115): 251.327 1.346 RR IC Mixed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MOSIctl|stsourcedata[4]|clrn
|
|
Info (332115): 251.327 0.000 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MOSIctl|stsourcedata[4]
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 250.000 250.000 latch edge time
|
|
Info (332115): 250.144 0.144 R clock network delay
|
|
Info (332115): 250.444 0.300 clock uncertainty
|
|
Info (332115): 250.512 0.068 uTh fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MOSIctl|stsourcedata[4]
|
|
Info (332115): Data Arrival Time : 251.327
|
|
Info (332115): Data Required Time : 250.512
|
|
Info (332115): Slack : 0.815
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 1.306
|
|
Info (20696): -to_clock [get_clocks {fspi_sclk}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 1.306
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|SPISlaveToAvalonMasterBridge_reset_clk_domain_synch|data_out
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MISOctl|loadstsinkdata
|
|
Info (332115): Launch Clock : u0|dcp_iopll|dcp_iopll|clk1x
|
|
Info (332115): Latch Clock : fspi_sclk
|
|
Info (332115): Exception : dcp_bbs.sdc:3057: set_multicycle_path -hold -from [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|SPISlaveToAvalonMasterBridge_reset_clk_domain_synch|data_out}] -to [get_keepers {fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MISOctl|*}] 1
|
|
Info (332115): Multicycle - Setup Start : 2
|
|
Info (332115): Multicycle - Hold Start : 1
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 4.820 4.820 R clock network delay
|
|
Info (332115): 4.820 0.000 fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|SPISlaveToAvalonMasterBridge_reset_clk_domain_synch|data_out
|
|
Info (332115): 4.933 0.113 RR uTco fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|SPISlaveToAvalonMasterBridge_reset_clk_domain_synch|data_out|q
|
|
Info (332115): 4.981 0.048 RR CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|SPISlaveToAvalonMasterBridge_reset_clk_domain_synch|data_out~la_mlab/laboutt[1]
|
|
Info (332115): 5.191 0.210 RR IC High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MOSIctl|i5|dataf
|
|
Info (332115): 5.211 0.020 RF CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MOSIctl|i5|combout
|
|
Info (332115): 5.213 0.002 FF CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MOSIctl|i5~la_mlab/laboutt[19]
|
|
Info (332115): 5.285 0.072 FF IC High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MISOctl|loadstsinkdata|clrn
|
|
Info (332115): 5.285 0.000 FF CELL High Speed fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MISOctl|loadstsinkdata
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 latch edge time
|
|
Info (332115): 3.609 3.609 R clock network delay
|
|
Info (332115): 3.919 0.310 clock uncertainty
|
|
Info (332115): 3.979 0.060 uTh fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MISOctl|loadstsinkdata
|
|
Info (332115): Data Arrival Time : 5.285
|
|
Info (332115): Data Required Time : 3.979
|
|
Info (332115): Slack : 1.306
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 9.075
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|rx_pma_clk}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 9.075
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|rx_pma_clk
|
|
Info (332115): Exception : dcp_bbs.sdc:3195: set_min_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pma_rxpma_rstb}] -10.000
|
|
Info (332115): Min Delay Exception : -10.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 1.109 1.109 R clock network delay
|
|
Info (332115): 1.109 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): 1.704 0.595 FF uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|rx_pma_rstb3
|
|
Info (332115): 1.704 0.000 FF IC fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_pma_rxpma_rstb
|
|
Info (332115): 1.704 0.000 FF CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): -10.000 -10.000 latch edge time
|
|
Info (332115): -7.491 2.509 R clock network delay
|
|
Info (332115): -7.371 0.120 clock uncertainty
|
|
Info (332115): -7.371 0.000 uTh fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Data Arrival Time : 1.704
|
|
Info (332115): Data Required Time : -7.371
|
|
Info (332115): Slack : 9.075
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 9.089
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|rx_pma_clk}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 9.089
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|rx_pma_clk
|
|
Info (332115): Exception : dcp_bbs.sdc:3195: set_min_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pma_rxpma_rstb}] -10.000
|
|
Info (332115): Min Delay Exception : -10.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 1.109 1.109 R clock network delay
|
|
Info (332115): 1.109 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): 1.718 0.609 FF uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|rx_pma_rstb2
|
|
Info (332115): 1.718 0.000 FF IC fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_pma_rxpma_rstb
|
|
Info (332115): 1.718 0.000 FF CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): -10.000 -10.000 latch edge time
|
|
Info (332115): -7.491 2.509 R clock network delay
|
|
Info (332115): -7.371 0.120 clock uncertainty
|
|
Info (332115): -7.371 0.000 uTh fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Data Arrival Time : 1.718
|
|
Info (332115): Data Required Time : -7.371
|
|
Info (332115): Slack : 9.089
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 9.190
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|rx_pma_clk}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 9.190
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|rx_pma_clk
|
|
Info (332115): Exception : dcp_bbs.sdc:3195: set_min_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pma_rxpma_rstb}] -10.000
|
|
Info (332115): Min Delay Exception : -10.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 1.109 1.109 R clock network delay
|
|
Info (332115): 1.109 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): 1.818 0.709 FF uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|rx_pma_rstb4
|
|
Info (332115): 1.819 0.001 FF IC fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_pma_rxpma_rstb
|
|
Info (332115): 1.819 0.000 FF CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): -10.000 -10.000 latch edge time
|
|
Info (332115): -7.491 2.509 R clock network delay
|
|
Info (332115): -7.371 0.120 clock uncertainty
|
|
Info (332115): -7.371 0.000 uTh fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Data Arrival Time : 1.819
|
|
Info (332115): Data Required Time : -7.371
|
|
Info (332115): Slack : 9.190
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 9.214
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|rx_pma_clk}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 9.214
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|rx_pma_clk
|
|
Info (332115): Exception : dcp_bbs.sdc:3195: set_min_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pma_rxpma_rstb}] -10.000
|
|
Info (332115): Min Delay Exception : -10.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 1.109 1.109 R clock network delay
|
|
Info (332115): 1.109 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): 1.890 0.781 FF uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|rx_pma_rstb5
|
|
Info (332115): 1.890 0.000 FF IC fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_pma_rxpma_rstb
|
|
Info (332115): 1.890 0.000 FF CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): -10.000 -10.000 latch edge time
|
|
Info (332115): -7.444 2.556 R clock network delay
|
|
Info (332115): -7.324 0.120 clock uncertainty
|
|
Info (332115): -7.324 0.000 uTh fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Data Arrival Time : 1.890
|
|
Info (332115): Data Required Time : -7.324
|
|
Info (332115): Slack : 9.214
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 9.241
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|rx_pma_clk}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 9.241
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|rx_pma_clk
|
|
Info (332115): Exception : dcp_bbs.sdc:3195: set_min_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pma_rxpma_rstb}] -10.000
|
|
Info (332115): Min Delay Exception : -10.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 1.109 1.109 R clock network delay
|
|
Info (332115): 1.109 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): 1.818 0.709 FF uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|rx_pma_rstb1
|
|
Info (332115): 1.818 0.000 FF IC fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_pma_rxpma_rstb
|
|
Info (332115): 1.818 0.000 FF CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): -10.000 -10.000 latch edge time
|
|
Info (332115): -7.543 2.457 R clock network delay
|
|
Info (332115): -7.423 0.120 clock uncertainty
|
|
Info (332115): -7.423 0.000 uTh fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Data Arrival Time : 1.818
|
|
Info (332115): Data Required Time : -7.423
|
|
Info (332115): Slack : 9.241
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 9.256
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|rx_pma_clk}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 9.256
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|rx_pma_clk
|
|
Info (332115): Exception : dcp_bbs.sdc:3195: set_min_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pma_rxpma_rstb}] -10.000
|
|
Info (332115): Min Delay Exception : -10.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 1.109 1.109 R clock network delay
|
|
Info (332115): 1.109 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): 1.932 0.823 FF uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|rx_pma_rstb6
|
|
Info (332115): 1.932 0.000 FF IC fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_pma_rxpma_rstb
|
|
Info (332115): 1.932 0.000 FF CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): -10.000 -10.000 latch edge time
|
|
Info (332115): -7.444 2.556 R clock network delay
|
|
Info (332115): -7.324 0.120 clock uncertainty
|
|
Info (332115): -7.324 0.000 uTh fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Data Arrival Time : 1.932
|
|
Info (332115): Data Required Time : -7.324
|
|
Info (332115): Slack : 9.256
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 9.445
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|rx_pma_clk}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 9.445
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|rx_pma_clk
|
|
Info (332115): Exception : dcp_bbs.sdc:3195: set_min_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pma_rxpma_rstb}] -10.000
|
|
Info (332115): Min Delay Exception : -10.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 1.109 1.109 R clock network delay
|
|
Info (332115): 1.109 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): 2.121 1.012 RR uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|rx_pma_rstb7
|
|
Info (332115): 2.121 0.000 RR IC fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_pma_rxpma_rstb
|
|
Info (332115): 2.121 0.000 RR CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): -10.000 -10.000 latch edge time
|
|
Info (332115): -7.444 2.556 R clock network delay
|
|
Info (332115): -7.324 0.120 clock uncertainty
|
|
Info (332115): -7.324 0.000 uTh fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Data Arrival Time : 2.121
|
|
Info (332115): Data Required Time : -7.324
|
|
Info (332115): Slack : 9.445
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 9.594
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_pma_clk}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 9.594
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_pma_clk
|
|
Info (332115): Exception : dcp_bbs.sdc:3195: set_min_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pma_rxpma_rstb}] -10.000
|
|
Info (332115): Min Delay Exception : -10.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 1.109 1.109 R clock network delay
|
|
Info (332115): 1.109 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): 1.957 0.848 FF uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|rx_pma_rstb0
|
|
Info (332115): 1.957 0.000 FF IC fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_pma_rxpma_rstb
|
|
Info (332115): 1.957 0.000 FF CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): -10.000 -10.000 latch edge time
|
|
Info (332115): -7.543 2.457 R clock network delay
|
|
Info (332115): -7.657 -0.114 clock pessimism removed
|
|
Info (332115): -7.637 0.020 clock uncertainty
|
|
Info (332115): -7.637 0.000 uTh fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_pma_interface.inst_twentynm_hssi_rx_pcs_pma_interface~pma_rx_pma_clk.reg
|
|
Info (332115): Data Arrival Time : 1.957
|
|
Info (332115): Data Required Time : -7.637
|
|
Info (332115): Slack : 9.594
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 10.008
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|rx_fref}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 10.008
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[3]|rx_fref
|
|
Info (332115): Exception : dcp_bbs.sdc:3195: set_min_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pma_rxpma_rstb}] -10.000
|
|
Info (332115): Min Delay Exception : -10.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 1.109 1.109 R clock network delay
|
|
Info (332115): 1.109 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): 1.735 0.626 RR uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|rx_pma_rstb3
|
|
Info (332115): 1.735 0.000 RR IC fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_pma_rxpma_rstb
|
|
Info (332115): 1.735 0.000 RR CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): -10.000 -10.000 latch edge time
|
|
Info (332115): -8.300 1.700 R clock network delay
|
|
Info (332115): -8.180 0.120 clock uncertainty
|
|
Info (332115): -8.273 -0.093 uTh fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Data Arrival Time : 1.735
|
|
Info (332115): Data Required Time : -8.273
|
|
Info (332115): Slack : 10.008
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 10.028
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|rx_fref}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 10.028
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[2]|rx_fref
|
|
Info (332115): Exception : dcp_bbs.sdc:3195: set_min_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pma_rxpma_rstb}] -10.000
|
|
Info (332115): Min Delay Exception : -10.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 1.109 1.109 R clock network delay
|
|
Info (332115): 1.109 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): 1.755 0.646 RR uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|rx_pma_rstb2
|
|
Info (332115): 1.755 0.000 RR IC fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_pma_rxpma_rstb
|
|
Info (332115): 1.755 0.000 RR CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): -10.000 -10.000 latch edge time
|
|
Info (332115): -8.300 1.700 R clock network delay
|
|
Info (332115): -8.180 0.120 clock uncertainty
|
|
Info (332115): -8.273 -0.093 uTh fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Data Arrival Time : 1.755
|
|
Info (332115): Data Required Time : -8.273
|
|
Info (332115): Slack : 10.028
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 10.109
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|rx_fref}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 10.109
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[4]|rx_fref
|
|
Info (332115): Exception : dcp_bbs.sdc:3195: set_min_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pma_rxpma_rstb}] -10.000
|
|
Info (332115): Min Delay Exception : -10.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 1.109 1.109 R clock network delay
|
|
Info (332115): 1.109 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): 1.835 0.726 RR uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|rx_pma_rstb4
|
|
Info (332115): 1.836 0.001 RR IC fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_pma_rxpma_rstb
|
|
Info (332115): 1.836 0.000 RR CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): -10.000 -10.000 latch edge time
|
|
Info (332115): -8.300 1.700 R clock network delay
|
|
Info (332115): -8.180 0.120 clock uncertainty
|
|
Info (332115): -8.273 -0.093 uTh fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[4].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Data Arrival Time : 1.836
|
|
Info (332115): Data Required Time : -8.273
|
|
Info (332115): Slack : 10.109
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 10.127
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|rx_fref}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 10.127
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[5]|rx_fref
|
|
Info (332115): Exception : dcp_bbs.sdc:3195: set_min_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pma_rxpma_rstb}] -10.000
|
|
Info (332115): Min Delay Exception : -10.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 1.109 1.109 R clock network delay
|
|
Info (332115): 1.109 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): 1.901 0.792 RR uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|rx_pma_rstb5
|
|
Info (332115): 1.901 0.000 RR IC fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_pma_rxpma_rstb
|
|
Info (332115): 1.901 0.000 RR CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): -10.000 -10.000 latch edge time
|
|
Info (332115): -8.253 1.747 R clock network delay
|
|
Info (332115): -8.133 0.120 clock uncertainty
|
|
Info (332115): -8.226 -0.093 uTh fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Data Arrival Time : 1.901
|
|
Info (332115): Data Required Time : -8.226
|
|
Info (332115): Slack : 10.127
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 10.166
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|rx_fref}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 10.166
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[1]|rx_fref
|
|
Info (332115): Exception : dcp_bbs.sdc:3195: set_min_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pma_rxpma_rstb}] -10.000
|
|
Info (332115): Min Delay Exception : -10.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 1.109 1.109 R clock network delay
|
|
Info (332115): 1.109 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): 1.841 0.732 RR uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|rx_pma_rstb1
|
|
Info (332115): 1.841 0.000 RR IC fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_pma_rxpma_rstb
|
|
Info (332115): 1.841 0.000 RR CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): -10.000 -10.000 latch edge time
|
|
Info (332115): -8.352 1.648 R clock network delay
|
|
Info (332115): -8.232 0.120 clock uncertainty
|
|
Info (332115): -8.325 -0.093 uTh fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Data Arrival Time : 1.841
|
|
Info (332115): Data Required Time : -8.325
|
|
Info (332115): Slack : 10.166
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 10.179
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|rx_fref}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 10.179
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[6]|rx_fref
|
|
Info (332115): Exception : dcp_bbs.sdc:3195: set_min_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pma_rxpma_rstb}] -10.000
|
|
Info (332115): Min Delay Exception : -10.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 1.109 1.109 R clock network delay
|
|
Info (332115): 1.109 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): 1.953 0.844 RR uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|rx_pma_rstb6
|
|
Info (332115): 1.953 0.000 RR IC fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_pma_rxpma_rstb
|
|
Info (332115): 1.953 0.000 RR CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): -10.000 -10.000 latch edge time
|
|
Info (332115): -8.253 1.747 R clock network delay
|
|
Info (332115): -8.133 0.120 clock uncertainty
|
|
Info (332115): -8.226 -0.093 uTh fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[6].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Data Arrival Time : 1.953
|
|
Info (332115): Data Required Time : -8.226
|
|
Info (332115): Slack : 10.179
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 10.347
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|rx_fref}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 10.347
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[7]|rx_fref
|
|
Info (332115): Exception : dcp_bbs.sdc:3195: set_min_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pma_rxpma_rstb}] -10.000
|
|
Info (332115): Min Delay Exception : -10.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 1.109 1.109 R clock network delay
|
|
Info (332115): 1.109 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): 2.121 1.012 RR uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|rx_pma_rstb7
|
|
Info (332115): 2.121 0.000 RR IC fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_pma_rxpma_rstb
|
|
Info (332115): 2.121 0.000 RR CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): -10.000 -10.000 latch edge time
|
|
Info (332115): -8.253 1.747 R clock network delay
|
|
Info (332115): -8.133 0.120 clock uncertainty
|
|
Info (332115): -8.226 -0.093 uTh fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Data Arrival Time : 2.121
|
|
Info (332115): Data Required Time : -8.226
|
|
Info (332115): Slack : 10.347
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 11.077
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 11.077
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Launch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|g_xcvr_native_insts[0]|rx_fref
|
|
Info (332115): Exception : dcp_bbs.sdc:3195: set_min_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pma_rxpma_rstb}] -10.000
|
|
Info (332115): Min Delay Exception : -10.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 1.109 1.109 R clock network delay
|
|
Info (332115): 1.109 0.000 fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys~ch0_pcs_chnl_hip_clk_out[2].reg
|
|
Info (332115): 1.984 0.875 RR uTco fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|rx_pma_rstb0
|
|
Info (332115): 1.984 0.000 RR IC fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface|pld_pma_rxpma_rstb
|
|
Info (332115): 1.984 0.000 RR CELL fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): -10.000 -10.000 latch edge time
|
|
Info (332115): -8.352 1.648 R clock network delay
|
|
Info (332115): -9.030 -0.678 clock pessimism removed
|
|
Info (332115): -9.000 0.030 clock uncertainty
|
|
Info (332115): -9.093 -0.093 uTh fpga_top|inst_fiu_top|inst_pcie0_ccib_top|pcie_hip0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_common_pcs_pma_interface.inst_twentynm_hssi_common_pcs_pma_interface~pma_fref.reg
|
|
Info (332115): Data Arrival Time : 1.984
|
|
Info (332115): Data Required Time : -9.093
|
|
Info (332115): Slack : 11.077
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 51.216
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|tx_coreclkin}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 51.216
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_avmm_csr_enabled.embedded_debug_soft_csr|g_control_reg.r_tx_digitalreset_override
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_10g_tx_pcs.inst_twentynm_hssi_10g_tx_pcs~pld_10g_krfec_tx_pld_rst_n_fifo.reg
|
|
Info (332115): Launch Clock : SYS_RefClk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|tx_coreclkin
|
|
Info (332115): Exception : dcp_bbs.sdc:3193: set_min_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_10g_krfec_tx_pld_rst_n}] -50.000
|
|
Info (332115): Min Delay Exception : -50.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 2.484 2.484 R clock network delay
|
|
Info (332115): 2.484 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_avmm_csr_enabled.embedded_debug_soft_csr|g_control_reg.r_tx_digitalreset_override
|
|
Info (332115): 2.596 0.112 FF uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_avmm_csr_enabled.embedded_debug_soft_csr|g_control_reg.r_tx_digitalreset_override|q
|
|
Info (332115): 2.650 0.054 FF CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_avmm_csr_enabled.embedded_debug_soft_csr|g_control_reg.r_tx_digitalreset_override~la_mlab/laboutb[16]
|
|
Info (332115): 2.735 0.085 FF IC Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0|datab
|
|
Info (332115): 2.839 0.104 FR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0|combout
|
|
Info (332115): 2.841 0.002 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0~la_mlab/laboutb[18]
|
|
Info (332115): 4.218 1.377 RR IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_tx_pld_pcs_interface.inst_twentynm_hssi_tx_pld_pcs_interface|pld_10g_krfec_tx_pld_rst_n
|
|
Info (332115): 4.218 0.000 RR CELL fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_10g_tx_pcs.inst_twentynm_hssi_10g_tx_pcs~pld_10g_krfec_tx_pld_rst_n_fifo.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): -50.000 -50.000 latch edge time
|
|
Info (332115): -47.088 2.912 R clock network delay
|
|
Info (332115): -47.019 0.069 clock uncertainty
|
|
Info (332115): -46.998 0.021 uTh fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_10g_tx_pcs.inst_twentynm_hssi_10g_tx_pcs~pld_10g_krfec_tx_pld_rst_n_fifo.reg
|
|
Info (332115): Data Arrival Time : 4.218
|
|
Info (332115): Data Required Time : -46.998
|
|
Info (332115): Slack : 51.216
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 51.432
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|tx_coreclkin}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 51.432
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_avmm_csr_enabled.embedded_debug_soft_csr|g_control_reg.r_tx_digitalreset_override
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_10g_tx_pcs.inst_twentynm_hssi_10g_tx_pcs~pld_10g_krfec_tx_pld_rst_n_fifo.reg
|
|
Info (332115): Launch Clock : SYS_RefClk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|tx_coreclkin
|
|
Info (332115): Exception : dcp_bbs.sdc:3193: set_min_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_10g_krfec_tx_pld_rst_n}] -50.000
|
|
Info (332115): Min Delay Exception : -50.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 2.486 2.486 R clock network delay
|
|
Info (332115): 2.486 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_avmm_csr_enabled.embedded_debug_soft_csr|g_control_reg.r_tx_digitalreset_override
|
|
Info (332115): 2.588 0.102 FF uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_avmm_csr_enabled.embedded_debug_soft_csr|g_control_reg.r_tx_digitalreset_override|q
|
|
Info (332115): 2.588 0.000 FF CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0|datae
|
|
Info (332115): 2.761 0.173 FR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0|combout
|
|
Info (332115): 2.762 0.001 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0~la_lab/laboutb[16]
|
|
Info (332115): 4.349 1.587 RR IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_tx_pld_pcs_interface.inst_twentynm_hssi_tx_pld_pcs_interface|pld_10g_krfec_tx_pld_rst_n
|
|
Info (332115): 4.349 0.000 RR CELL fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_10g_tx_pcs.inst_twentynm_hssi_10g_tx_pcs~pld_10g_krfec_tx_pld_rst_n_fifo.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): -50.000 -50.000 latch edge time
|
|
Info (332115): -47.173 2.827 R clock network delay
|
|
Info (332115): -47.104 0.069 clock uncertainty
|
|
Info (332115): -47.083 0.021 uTh fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_10g_tx_pcs.inst_twentynm_hssi_10g_tx_pcs~pld_10g_krfec_tx_pld_rst_n_fifo.reg
|
|
Info (332115): Data Arrival Time : 4.349
|
|
Info (332115): Data Required Time : -47.083
|
|
Info (332115): Slack : 51.432
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 51.544
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|tx_coreclkin}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 51.544
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_avmm_csr_enabled.embedded_debug_soft_csr|g_control_reg.r_tx_digitalreset_override
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_10g_tx_pcs.inst_twentynm_hssi_10g_tx_pcs~pld_10g_krfec_tx_pld_rst_n_fifo.reg
|
|
Info (332115): Launch Clock : SYS_RefClk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|tx_coreclkin
|
|
Info (332115): Exception : dcp_bbs.sdc:3193: set_min_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_10g_krfec_tx_pld_rst_n}] -50.000
|
|
Info (332115): Min Delay Exception : -50.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 2.486 2.486 R clock network delay
|
|
Info (332115): 2.486 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_avmm_csr_enabled.embedded_debug_soft_csr|g_control_reg.r_tx_digitalreset_override
|
|
Info (332115): 2.593 0.107 FF uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_avmm_csr_enabled.embedded_debug_soft_csr|g_control_reg.r_tx_digitalreset_override|q
|
|
Info (332115): 2.593 0.000 FF CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0|datae
|
|
Info (332115): 2.766 0.173 FR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0|combout
|
|
Info (332115): 2.767 0.001 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0~la_lab/laboutt[8]
|
|
Info (332115): 4.469 1.702 RR IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_tx_pld_pcs_interface.inst_twentynm_hssi_tx_pld_pcs_interface|pld_10g_krfec_tx_pld_rst_n
|
|
Info (332115): 4.469 0.000 RR CELL fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_10g_tx_pcs.inst_twentynm_hssi_10g_tx_pcs~pld_10g_krfec_tx_pld_rst_n_fifo.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): -50.000 -50.000 latch edge time
|
|
Info (332115): -47.165 2.835 R clock network delay
|
|
Info (332115): -47.096 0.069 clock uncertainty
|
|
Info (332115): -47.075 0.021 uTh fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_10g_tx_pcs.inst_twentynm_hssi_10g_tx_pcs~pld_10g_krfec_tx_pld_rst_n_fifo.reg
|
|
Info (332115): Data Arrival Time : 4.469
|
|
Info (332115): Data Required Time : -47.075
|
|
Info (332115): Slack : 51.544
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 51.605
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|tx_coreclkin}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 51.605
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_avmm_csr_enabled.embedded_debug_soft_csr|g_control_reg.r_tx_digitalreset_override
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_10g_tx_pcs.inst_twentynm_hssi_10g_tx_pcs~pld_10g_krfec_tx_pld_rst_n_fifo.reg
|
|
Info (332115): Launch Clock : SYS_RefClk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|tx_coreclkin
|
|
Info (332115): Exception : dcp_bbs.sdc:3193: set_min_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_10g_krfec_tx_pld_rst_n}] -50.000
|
|
Info (332115): Min Delay Exception : -50.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 2.481 2.481 R clock network delay
|
|
Info (332115): 2.481 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_avmm_csr_enabled.embedded_debug_soft_csr|g_control_reg.r_tx_digitalreset_override
|
|
Info (332115): 2.582 0.101 FF uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_avmm_csr_enabled.embedded_debug_soft_csr|g_control_reg.r_tx_digitalreset_override|q
|
|
Info (332115): 2.616 0.034 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_avmm_csr_enabled.embedded_debug_soft_csr|g_control_reg.r_tx_digitalreset_override~la_lab/laboutt[13]
|
|
Info (332115): 2.838 0.222 FF IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0|dataa
|
|
Info (332115): 2.944 0.106 FR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0|combout
|
|
Info (332115): 2.946 0.002 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0~la_mlab/laboutb[18]
|
|
Info (332115): 4.527 1.581 RR IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_tx_pld_pcs_interface.inst_twentynm_hssi_tx_pld_pcs_interface|pld_10g_krfec_tx_pld_rst_n
|
|
Info (332115): 4.527 0.000 RR CELL fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_10g_tx_pcs.inst_twentynm_hssi_10g_tx_pcs~pld_10g_krfec_tx_pld_rst_n_fifo.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): -50.000 -50.000 latch edge time
|
|
Info (332115): -47.168 2.832 R clock network delay
|
|
Info (332115): -47.099 0.069 clock uncertainty
|
|
Info (332115): -47.078 0.021 uTh fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_10g_tx_pcs.inst_twentynm_hssi_10g_tx_pcs~pld_10g_krfec_tx_pld_rst_n_fifo.reg
|
|
Info (332115): Data Arrival Time : 4.527
|
|
Info (332115): Data Required Time : -47.078
|
|
Info (332115): Slack : 51.605
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 52.054
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|tx_pma_clk}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 52.054
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_avmm_csr_enabled.embedded_debug_soft_csr|g_control_reg.r_tx_digitalreset_override
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_10g_tx_pcs.inst_twentynm_hssi_10g_tx_pcs~pld_10g_krfec_tx_pld_rst_n_reg.reg
|
|
Info (332115): Launch Clock : SYS_RefClk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3]|tx_pma_clk
|
|
Info (332115): Exception : dcp_bbs.sdc:3193: set_min_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_10g_krfec_tx_pld_rst_n}] -50.000
|
|
Info (332115): Min Delay Exception : -50.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 2.484 2.484 R clock network delay
|
|
Info (332115): 2.484 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_avmm_csr_enabled.embedded_debug_soft_csr|g_control_reg.r_tx_digitalreset_override
|
|
Info (332115): 2.596 0.112 FF uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_avmm_csr_enabled.embedded_debug_soft_csr|g_control_reg.r_tx_digitalreset_override|q
|
|
Info (332115): 2.650 0.054 FF CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_avmm_csr_enabled.embedded_debug_soft_csr|g_control_reg.r_tx_digitalreset_override~la_mlab/laboutb[16]
|
|
Info (332115): 2.735 0.085 FF IC Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0|datab
|
|
Info (332115): 2.839 0.104 FR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0|combout
|
|
Info (332115): 2.841 0.002 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[3].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0~la_mlab/laboutb[18]
|
|
Info (332115): 4.218 1.377 RR IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_tx_pld_pcs_interface.inst_twentynm_hssi_tx_pld_pcs_interface|pld_10g_krfec_tx_pld_rst_n
|
|
Info (332115): 4.218 0.000 RR CELL fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_10g_tx_pcs.inst_twentynm_hssi_10g_tx_pcs~pld_10g_krfec_tx_pld_rst_n_reg.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): -50.000 -50.000 latch edge time
|
|
Info (332115): -48.027 1.973 R clock network delay
|
|
Info (332115): -47.957 0.070 clock uncertainty
|
|
Info (332115): -47.836 0.121 uTh fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_10g_tx_pcs.inst_twentynm_hssi_10g_tx_pcs~pld_10g_krfec_tx_pld_rst_n_reg.reg
|
|
Info (332115): Data Arrival Time : 4.218
|
|
Info (332115): Data Required Time : -47.836
|
|
Info (332115): Slack : 52.054
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 52.142
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|tx_pma_clk}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 52.142
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_avmm_csr_enabled.embedded_debug_soft_csr|g_control_reg.r_tx_digitalreset_override
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs~pld_8g_g3_tx_pld_rst_n_reg.reg
|
|
Info (332115): Launch Clock : SYS_RefClk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2]|tx_pma_clk
|
|
Info (332115): Exception : dcp_bbs.sdc:3192: set_min_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_8g_g3_tx_pld_rst_n}] -50.000
|
|
Info (332115): Min Delay Exception : -50.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 2.486 2.486 R clock network delay
|
|
Info (332115): 2.486 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_avmm_csr_enabled.embedded_debug_soft_csr|g_control_reg.r_tx_digitalreset_override
|
|
Info (332115): 2.588 0.102 FF uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_avmm_csr_enabled.embedded_debug_soft_csr|g_control_reg.r_tx_digitalreset_override|q
|
|
Info (332115): 2.588 0.000 FF CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0|datae
|
|
Info (332115): 2.761 0.173 FR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0|combout
|
|
Info (332115): 2.762 0.001 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[2].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0~la_lab/laboutb[16]
|
|
Info (332115): 4.349 1.587 RR IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_tx_pld_pcs_interface.inst_twentynm_hssi_tx_pld_pcs_interface|pld_8g_g3_tx_pld_rst_n
|
|
Info (332115): 4.349 0.000 RR CELL fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs~pld_8g_g3_tx_pld_rst_n_reg.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): -50.000 -50.000 latch edge time
|
|
Info (332115): -48.027 1.973 R clock network delay
|
|
Info (332115): -47.957 0.070 clock uncertainty
|
|
Info (332115): -47.793 0.164 uTh fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs~pld_8g_g3_tx_pld_rst_n_reg.reg
|
|
Info (332115): Data Arrival Time : 4.349
|
|
Info (332115): Data Required Time : -47.793
|
|
Info (332115): Slack : 52.142
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 52.287
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|tx_pma_clk}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 52.287
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_avmm_csr_enabled.embedded_debug_soft_csr|g_control_reg.r_tx_digitalreset_override
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs~pld_8g_g3_tx_pld_rst_n_reg.reg
|
|
Info (332115): Launch Clock : SYS_RefClk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0]|tx_pma_clk
|
|
Info (332115): Exception : dcp_bbs.sdc:3192: set_min_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_8g_g3_tx_pld_rst_n}] -50.000
|
|
Info (332115): Min Delay Exception : -50.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 2.486 2.486 R clock network delay
|
|
Info (332115): 2.486 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_avmm_csr_enabled.embedded_debug_soft_csr|g_control_reg.r_tx_digitalreset_override
|
|
Info (332115): 2.593 0.107 FF uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_avmm_csr_enabled.embedded_debug_soft_csr|g_control_reg.r_tx_digitalreset_override|q
|
|
Info (332115): 2.593 0.000 FF CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0|datae
|
|
Info (332115): 2.766 0.173 FR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0|combout
|
|
Info (332115): 2.767 0.001 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[0].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0~la_lab/laboutt[8]
|
|
Info (332115): 4.471 1.704 RR IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_tx_pld_pcs_interface.inst_twentynm_hssi_tx_pld_pcs_interface|pld_8g_g3_tx_pld_rst_n
|
|
Info (332115): 4.471 0.000 RR CELL fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs~pld_8g_g3_tx_pld_rst_n_reg.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): -50.000 -50.000 latch edge time
|
|
Info (332115): -48.050 1.950 R clock network delay
|
|
Info (332115): -47.980 0.070 clock uncertainty
|
|
Info (332115): -47.816 0.164 uTh fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs~pld_8g_g3_tx_pld_rst_n_reg.reg
|
|
Info (332115): Data Arrival Time : 4.471
|
|
Info (332115): Data Required Time : -47.816
|
|
Info (332115): Slack : 52.287
|
|
Info (332115): ===================================================================
|
|
Info (332115): Report Timing: Found 1 removal paths (0 violated). Worst case slack is 52.343
|
|
Info (20696): -to_clock [get_clocks {fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|tx_pma_clk}]
|
|
Info (20696): -removal
|
|
Info (20696): -stdout
|
|
Info (332115): Path #1: Removal slack is 52.343
|
|
Info (332115): ===================================================================
|
|
Info (332115): From Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_avmm_csr_enabled.embedded_debug_soft_csr|g_control_reg.r_tx_digitalreset_override
|
|
Info (332115): To Node : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs~pld_8g_g3_tx_pld_rst_n_reg.reg
|
|
Info (332115): Launch Clock : SYS_RefClk
|
|
Info (332115): Latch Clock : fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1]|tx_pma_clk
|
|
Info (332115): Exception : dcp_bbs.sdc:3192: set_min_delay -to [get_pins -compatibility_mode {*twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_8g_g3_tx_pld_rst_n}] -50.000
|
|
Info (332115): Min Delay Exception : -50.000
|
|
Info (332115): Data Arrival Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): 0.000 0.000 launch edge time
|
|
Info (332115): 2.481 2.481 R clock network delay
|
|
Info (332115): 2.481 0.000 fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_avmm_csr_enabled.embedded_debug_soft_csr|g_control_reg.r_tx_digitalreset_override
|
|
Info (332115): 2.582 0.101 FF uTco fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_avmm_csr_enabled.embedded_debug_soft_csr|g_control_reg.r_tx_digitalreset_override|q
|
|
Info (332115): 2.616 0.034 FF CELL High Speed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_avmm_csr_enabled.embedded_debug_soft_csr|g_control_reg.r_tx_digitalreset_override~la_lab/laboutt[13]
|
|
Info (332115): 2.838 0.222 FF IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0|dataa
|
|
Info (332115): 2.944 0.106 FR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0|combout
|
|
Info (332115): 2.946 0.002 RR CELL Low Power fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic|g_optional_chnl_reconfig_logic[1].g_avmm_csr_enabled.embedded_debug_soft_csr|csr_tx_digitalreset~0~la_mlab/laboutb[18]
|
|
Info (332115): 4.527 1.581 RR IC Mixed fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_tx_pld_pcs_interface.inst_twentynm_hssi_tx_pld_pcs_interface|pld_8g_g3_tx_pld_rst_n
|
|
Info (332115): 4.527 0.000 RR CELL fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs~pld_8g_g3_tx_pld_rst_n_reg.reg
|
|
Info (332115): Data Required Path:
|
|
Info (332115): Total (ns) Incr (ns) Type HS/LP Element
|
|
Info (332115): ========== ========= == ==== ========== ===================================
|
|
Info (332115): -50.000 -50.000 latch edge time
|
|
Info (332115): -48.050 1.950 R clock network delay
|
|
Info (332115): -47.980 0.070 clock uncertainty
|
|
Info (332115): -47.816 0.164 uTh fpga_top|inst_fiu_top|inst_hssi_ctrl|ntv0|xcvr_native_a10_0|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs~pld_8g_g3_tx_pld_rst_n_reg.reg
|
|
Info (332115): Data Arrival Time : 4.527
|
|
Info (332115): Data Required Time : -47.816
|
|
Info (332115): Slack : 52.343
|
|
Info (332115): ===================================================================
|
|
Info (332102): Design is not fully constrained for setup requirements
|
|
Info (332102): Design is not fully constrained for hold requirements
|
|
Info: Quartus Prime Timing Analyzer was successful. 0 errors, 237 warnings
|
|
Info: Peak virtual memory: 26350 megabytes
|
|
Info: Processing ended: Sat Mar 6 08:52:33 2021
|
|
Info: Elapsed time: 00:06:19
|
|
Info (19538): Reading SDC files took 00:00:10 cumulatively in this process.
|
|
Info (293026): Skipped module Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER
|
|
Info: *******************************************************************
|
|
Info: Running Quartus Prime Assembler
|
|
Info: Version 19.2.0 Build 57 06/24/2019 Patches 0.01rc SJ Pro Edition
|
|
Info: Processing started: Sat Mar 6 08:52:38 2021
|
|
Info: Command: quartus_asm --read_settings_files=on --write_settings_files=off dcp -c afu_default
|
|
Info (16677): Loading final database
|
|
Info (16734): Loading "final" snapshot for partition "root_partition".
|
|
Info (16734): Loading "final" snapshot for partition "root_partition_2cedade0".
|
|
Info (16734): Loading "final" snapshot for partition "green_region".
|
|
Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design contains file: "/opt/opae/1.1.2/share/opae/platform/platform_if/rtl/platform_shims/utils/quartus_ip/platform_utils_dc_fifo.sdc", assignment in base design does not contain file). Check that the assignment in the current design is correct.
|
|
Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design contains file: "/opt/opae/1.1.2/share/opae/platform/platform_if/rtl/platform_shims/utils/quartus_ip/platform_utils_avalon_dc_fifo.sdc", assignment in base design does not contain file). Check that the assignment in the current design is correct.
|
|
Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design contains file: "/opt/opae/1.1.2/share/opae/platform/platform_if/par/platform_if.sdc", assignment in base design does not contain file). Check that the assignment in the current design is correct.
|
|
Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design contains file: "dcp_bbs.sdc", assignment in base design does not contain file). Check that the assignment in the current design is correct.
|
|
Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design contains file: "platform/green_bs.sdc", assignment in base design does not contain file). Check that the assignment in the current design is correct.
|
|
Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design contains file: "dcp_user_clocks.sdc", assignment in base design does not contain file). Check that the assignment in the current design is correct.
|
|
Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/hssi_eth/e10/phy/altera_eth_10gbaser_phy/altera_xcvr_native_a10_191/synth/altera_xcvr_native_a10_false_paths.sdc"). Check that the assignment in the current design is correct.
|
|
Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/hssi_eth/native_xcvr/altera_xcvr_native_a10_191/synth/altera_xcvr_native_a10_false_paths.sdc"). Check that the assignment in the current design is correct.
|
|
Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/remote_stp/QSYS_IPs/PR_190/ip/SLD_HUB_CONT_SYS_WO_SLD_EP/SLD_HUB_CONT_SYS_WO_SLD_EP_sld_hub_controller_system_without_sldep_0/altera_streaming_sld_hub_controller_core_without_sldep_180/synth/altera_streaming_sld_hub_controller_without_sldep.sdc"). Check that the assignment in the current design is correct.
|
|
Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/fme/ptmgr/TEMPERATURE_SourceTree/ptmgr_temp_sensor/altera_temp_sense_191/synth/altera_temp_sense.sdc"). Check that the assignment in the current design is correct.
|
|
Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/top/dcp_top.sdc"). Check that the assignment in the current design is correct.
|
|
Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/sdc/fabric.sdc"). Check that the assignment in the current design is correct.
|
|
Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/sdc/fme.sdc"). Check that the assignment in the current design is correct.
|
|
Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/sdc/fiu.sdc"). Check that the assignment in the current design is correct.
|
|
Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/afu/green_bs.sdc"). Check that the assignment in the current design is correct.
|
|
Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/partial_reconfig/PR_IP/alt_pr_191/synth/rtl/alt_pr.sdc"). Check that the assignment in the current design is correct.
|
|
Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/pcie/ips/pcie_sriov_ep_g3x8/pcie_sriov_ep_g3x8/altera_xcvr_native_a10_191/synth/altera_xcvr_native_a10_false_paths.sdc"). Check that the assignment in the current design is correct.
|
|
Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/pcie/ips/pcie_sriov_ep_g3x8/pcie_sriov_ep_g3x8/altera_pcie_a10_hip_191/synth/altera_pci_express.sdc"). Check that the assignment in the current design is correct.
|
|
Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/afu/nlb_400/nlb_400.sdc"). Check that the assignment in the current design is correct.
|
|
Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/bmc_mailbox/ip/bmc_mailbox/bmc_mailbox_spi_slave_to_avalon_mm_master_bridge_1/spi_slave_to_avalon_mm_master_bridge_191/synth/spiphyslave.sdc"). Check that the assignment in the current design is correct.
|
|
Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/tcm/ip/tcm/tcm_alt_pr_0/alt_pr_191/synth/rtl/alt_pr.sdc"). Check that the assignment in the current design is correct.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_aeb", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|rdemp_eq_comp_msb_aeb", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|wrptr_g[0]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|wrptr_g[1]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|wrptr_g[2]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|wrptr_g[3]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|wrptr_g[4]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|wrptr_g[5]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|wrptr_g[6]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|rdptr_g1p|counter1a0", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_aeb", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|rdemp_eq_comp_msb_aeb", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|wrptr_g[0]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|wrptr_g[1]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|wrptr_g[2]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|wrptr_g[3]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|wrptr_g[4]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|wrptr_g[5]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|wrptr_g[6]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|rdptr_g1p|counter1a0", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_aeb", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|rdemp_eq_comp_msb_aeb", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|wrptr_g[0]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|wrptr_g[1]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|wrptr_g[2]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|wrptr_g[3]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|wrptr_g[4]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|wrptr_g[5]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|rdptr_g1p|counter1a0", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|wrptr_g1p|counter4a0", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|rdptr_g1p|parity2", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|wrptr_g1p|counter4a0", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|rdptr_g1p|parity2", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|wrptr_g1p|counter3a0", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|rdptr_g1p|parity2", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|wrptr_g1p|parity5", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|wrptr_g1p|parity5", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|wrptr_g1p|parity4", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_aeb", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|rdemp_eq_comp_msb_aeb", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|wrptr_g[0]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|wrptr_g[1]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|wrptr_g[2]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|wrptr_g[3]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|wrptr_g[4]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|wrptr_g[5]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|wrptr_g[6]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|wrptr_g[7]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|wrptr_g[8]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|wrptr_g[9]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|rdptr_g1p|counter1a0", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_aeb", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|rdemp_eq_comp_msb_aeb", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|wrptr_g[0]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|wrptr_g[1]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|wrptr_g[2]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|wrptr_g[3]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|wrptr_g[4]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|wrptr_g[5]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|wrptr_g[6]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|wrptr_g[7]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|wrptr_g[8]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|rdptr_g1p|counter1a0", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|wrptr_g1p|counter4a0", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|rdptr_g1p|parity2", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|wrptr_g1p|counter4a0", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|rdptr_g1p|parity2", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|wrptr_g1p|parity5", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|wrptr_g1p|parity5", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|wrptr_g1p|counter4a0~DUPLICATE", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|wrptr_g1p|parity5~DUPLICATE", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Info (16678): Successfully loaded final database: elapsed time is 00:00:55
|
|
Info (18936): Using revision output_files/dcp.green_region.pmsf as a baseline for afu_default.green_region mask verification
|
|
Info (18938): Using revision output_files/dcp.static.msf as a baseline for static mask verification
|
|
Info (18937): Using revision output_files/dcp.sof as a baseline for logic preservation verification
|
|
Warning (20536): Programming file generation feature has been removed from compilation flow and the corresponding legacy settings in Quartus Prime Setting File (.qsf) have been ignored. Please use Programmer File Generator or Convert Programming File Tool to generate programming file.
|
|
Warning (18890): The CRC error detection clock divisor has been changed to 2, because the previous divisor 1 is not supported by the current device.
|
|
Info (14757): The PR bitstream ID is 0x30901D8F
|
|
Info: Quartus Prime Assembler was successful. 0 errors, 94 warnings
|
|
Info: Peak virtual memory: 16761 megabytes
|
|
Info: Processing ended: Sat Mar 6 08:56:29 2021
|
|
Info: Elapsed time: 00:03:51
|
|
Info (293000): Quartus Prime Full Compilation was successful. 0 errors, 2999 warnings
|
|
Info: Successfully completed A10 PR compile.
|
|
Info (23030): Evaluation of Tcl script ./a10_partial_reconfig/flow.tcl was successful
|
|
Info: Quartus Prime Shell was successful. 0 errors, 2999 warnings
|
|
Info: Peak virtual memory: 1207 megabytes
|
|
Info: Processing ended: Sat Mar 6 08:56:30 2021
|
|
Info: Elapsed time: 04:13:57
|
|
Info: *******************************************************************
|
|
Info: Running Quartus Prime Shell
|
|
Info: Version 19.2.0 Build 57 06/24/2019 Patches 0.01rc SJ Pro Edition
|
|
Info: Copyright (C) 2019 Intel Corporation. All rights reserved.
|
|
Info: Your use of Intel Corporation's design tools, logic functions
|
|
Info: and other software and tools, and any partner logic
|
|
Info: functions, and any output files from any of the foregoing
|
|
Info: (including device programming or simulation files), and any
|
|
Info: associated documentation or information are expressly subject
|
|
Info: to the terms and conditions of the Intel Program License
|
|
Info: Subscription Agreement, the Intel Quartus Prime License Agreement,
|
|
Info: the Intel FPGA IP License Agreement, or other applicable license
|
|
Info: agreement, including, without limitation, that your use is for
|
|
Info: the sole purpose of programming logic devices manufactured by
|
|
Info: Intel and sold by Intel or its authorized distributors. Please
|
|
Info: refer to the applicable agreement for further details, at
|
|
Info: https://fpgasoftware.intel.com/eula.
|
|
Info: Processing started: Sat Mar 6 08:56:32 2021
|
|
Info: Command: quartus_sh -t ./a10_partial_reconfig/compute_user_clock_freqs.tcl --project=dcp --revision=afu_default
|
|
Info: Quartus(args): --project=dcp --revision=afu_default
|
|
Info: Project name: dcp
|
|
Info: Revision name: afu_default
|
|
Info (16677): Loading final database
|
|
Info (16734): Loading "final" snapshot for partition "root_partition".
|
|
Info (16734): Loading "final" snapshot for partition "root_partition_2cedade0".
|
|
Info (16734): Loading "final" snapshot for partition "green_region".
|
|
Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design contains file: "/opt/opae/1.1.2/share/opae/platform/platform_if/rtl/platform_shims/utils/quartus_ip/platform_utils_dc_fifo.sdc", assignment in base design does not contain file). Check that the assignment in the current design is correct.
|
|
Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design contains file: "/opt/opae/1.1.2/share/opae/platform/platform_if/rtl/platform_shims/utils/quartus_ip/platform_utils_avalon_dc_fifo.sdc", assignment in base design does not contain file). Check that the assignment in the current design is correct.
|
|
Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design contains file: "/opt/opae/1.1.2/share/opae/platform/platform_if/par/platform_if.sdc", assignment in base design does not contain file). Check that the assignment in the current design is correct.
|
|
Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design contains file: "dcp_bbs.sdc", assignment in base design does not contain file). Check that the assignment in the current design is correct.
|
|
Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design contains file: "platform/green_bs.sdc", assignment in base design does not contain file). Check that the assignment in the current design is correct.
|
|
Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design contains file: "dcp_user_clocks.sdc", assignment in base design does not contain file). Check that the assignment in the current design is correct.
|
|
Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/hssi_eth/e10/phy/altera_eth_10gbaser_phy/altera_xcvr_native_a10_191/synth/altera_xcvr_native_a10_false_paths.sdc"). Check that the assignment in the current design is correct.
|
|
Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/hssi_eth/native_xcvr/altera_xcvr_native_a10_191/synth/altera_xcvr_native_a10_false_paths.sdc"). Check that the assignment in the current design is correct.
|
|
Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/remote_stp/QSYS_IPs/PR_190/ip/SLD_HUB_CONT_SYS_WO_SLD_EP/SLD_HUB_CONT_SYS_WO_SLD_EP_sld_hub_controller_system_without_sldep_0/altera_streaming_sld_hub_controller_core_without_sldep_180/synth/altera_streaming_sld_hub_controller_without_sldep.sdc"). Check that the assignment in the current design is correct.
|
|
Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/fme/ptmgr/TEMPERATURE_SourceTree/ptmgr_temp_sensor/altera_temp_sense_191/synth/altera_temp_sense.sdc"). Check that the assignment in the current design is correct.
|
|
Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/top/dcp_top.sdc"). Check that the assignment in the current design is correct.
|
|
Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/sdc/fabric.sdc"). Check that the assignment in the current design is correct.
|
|
Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/sdc/fme.sdc"). Check that the assignment in the current design is correct.
|
|
Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/sdc/fiu.sdc"). Check that the assignment in the current design is correct.
|
|
Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/afu/green_bs.sdc"). Check that the assignment in the current design is correct.
|
|
Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/partial_reconfig/PR_IP/alt_pr_191/synth/rtl/alt_pr.sdc"). Check that the assignment in the current design is correct.
|
|
Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/pcie/ips/pcie_sriov_ep_g3x8/pcie_sriov_ep_g3x8/altera_xcvr_native_a10_191/synth/altera_xcvr_native_a10_false_paths.sdc"). Check that the assignment in the current design is correct.
|
|
Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/pcie/ips/pcie_sriov_ep_g3x8/pcie_sriov_ep_g3x8/altera_pcie_a10_hip_191/synth/altera_pci_express.sdc"). Check that the assignment in the current design is correct.
|
|
Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/afu/nlb_400/nlb_400.sdc"). Check that the assignment in the current design is correct.
|
|
Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/bmc_mailbox/ip/bmc_mailbox/bmc_mailbox_spi_slave_to_avalon_mm_master_bridge_1/spi_slave_to_avalon_mm_master_bridge_191/synth/spiphyslave.sdc"). Check that the assignment in the current design is correct.
|
|
Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/tcm/ip/tcm/tcm_alt_pr_0/alt_pr_191/synth/rtl/alt_pr.sdc"). Check that the assignment in the current design is correct.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_aeb", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|rdemp_eq_comp_msb_aeb", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|wrptr_g[0]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|wrptr_g[1]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|wrptr_g[2]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|wrptr_g[3]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|wrptr_g[4]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|wrptr_g[5]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|wrptr_g[6]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|rdptr_g1p|counter1a0", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_aeb", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|rdemp_eq_comp_msb_aeb", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|wrptr_g[0]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|wrptr_g[1]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|wrptr_g[2]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|wrptr_g[3]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|wrptr_g[4]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|wrptr_g[5]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|wrptr_g[6]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|rdptr_g1p|counter1a0", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_aeb", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|rdemp_eq_comp_msb_aeb", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|wrptr_g[0]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|wrptr_g[1]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|wrptr_g[2]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|wrptr_g[3]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|wrptr_g[4]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|wrptr_g[5]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|rdptr_g1p|counter1a0", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|wrptr_g1p|counter4a0", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|rdptr_g1p|parity2", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|wrptr_g1p|counter4a0", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|rdptr_g1p|parity2", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|wrptr_g1p|counter3a0", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|rdptr_g1p|parity2", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|wrptr_g1p|parity5", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|wrptr_g1p|parity5", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|wrptr_g1p|parity4", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_aeb", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|rdemp_eq_comp_msb_aeb", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|wrptr_g[0]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|wrptr_g[1]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|wrptr_g[2]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|wrptr_g[3]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|wrptr_g[4]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|wrptr_g[5]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|wrptr_g[6]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|wrptr_g[7]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|wrptr_g[8]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|wrptr_g[9]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|rdptr_g1p|counter1a0", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_aeb", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|rdemp_eq_comp_msb_aeb", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|wrptr_g[0]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|wrptr_g[1]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|wrptr_g[2]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|wrptr_g[3]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|wrptr_g[4]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|wrptr_g[5]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|wrptr_g[6]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|wrptr_g[7]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|wrptr_g[8]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|rdptr_g1p|counter1a0", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|wrptr_g1p|counter4a0", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|rdptr_g1p|parity2", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|wrptr_g1p|counter4a0", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|rdptr_g1p|parity2", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|wrptr_g1p|parity5", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|wrptr_g1p|parity5", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|wrptr_g1p|counter4a0~DUPLICATE", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|wrptr_g1p|parity5~DUPLICATE", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Info (16678): Successfully loaded final database: elapsed time is 00:00:56
|
|
Info: Device part name is 10AX115N2F40E2LG
|
|
Info: Speedgrade is 2
|
|
Info: User clocks auto mode: computing FMax
|
|
Info: Clock fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk0
|
|
Info: Period: 9.090
|
|
Info: Restricted Fmax from STA: 645.16
|
|
Info: Setup slack: 8.509
|
|
Info: Recovery slack: N/A
|
|
Info: Minimum Pulse Width slack: 4.456
|
|
Info: Adjusted period: 4.644 (-4.456, Minimum Pulse Width)
|
|
Info: Fmax: 215.33
|
|
Info: Clock fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk1
|
|
Info: Period: 4.545
|
|
Info: Restricted Fmax from STA: 167.36
|
|
Info: Setup slack: -1.430
|
|
Info: Recovery slack: 1.183
|
|
Info: normalized Recovery slack: 0.29575
|
|
Info: Minimum Pulse Width slack: 1.829
|
|
Info: Adjusted period: 5.985 (+1.430, Setup)
|
|
Info: Fmax: 167.08
|
|
Info: Target user clock high: auto (220)
|
|
Info: Target user clock low: auto (110.0)
|
|
Info: User clock high is auto
|
|
Info: Saved actual user clock high: 167
|
|
Info: Saved actual user clock low: 83.5
|
|
Info (23030): Evaluation of Tcl script ./a10_partial_reconfig/compute_user_clock_freqs.tcl was successful
|
|
Info: Quartus Prime Shell was successful. 0 errors, 92 warnings
|
|
Info: Peak virtual memory: 8331 megabytes
|
|
Info: Processing ended: Sat Mar 6 08:57:34 2021
|
|
Info: Elapsed time: 00:01:02
|
|
Info: *******************************************************************
|
|
Info: Running Quartus Prime Timing Analyzer
|
|
Info: Version 19.2.0 Build 57 06/24/2019 Patches 0.01rc SJ Pro Edition
|
|
Info: Copyright (C) 2019 Intel Corporation. All rights reserved.
|
|
Info: Your use of Intel Corporation's design tools, logic functions
|
|
Info: and other software and tools, and any partner logic
|
|
Info: functions, and any output files from any of the foregoing
|
|
Info: (including device programming or simulation files), and any
|
|
Info: associated documentation or information are expressly subject
|
|
Info: to the terms and conditions of the Intel Program License
|
|
Info: Subscription Agreement, the Intel Quartus Prime License Agreement,
|
|
Info: the Intel FPGA IP License Agreement, or other applicable license
|
|
Info: agreement, including, without limitation, that your use is for
|
|
Info: the sole purpose of programming logic devices manufactured by
|
|
Info: Intel and sold by Intel or its authorized distributors. Please
|
|
Info: refer to the applicable agreement for further details, at
|
|
Info: https://fpgasoftware.intel.com/eula.
|
|
Info: Processing started: Sat Mar 6 08:57:36 2021
|
|
Info: Command: quartus_sta -t ./a10_partial_reconfig/report_timing.tcl --project=dcp --revision=afu_default
|
|
Info: Quartus(args): --project=dcp --revision=afu_default
|
|
Info (16677): Loading final database
|
|
Info (16734): Loading "final" snapshot for partition "root_partition".
|
|
Info (16734): Loading "final" snapshot for partition "root_partition_2cedade0".
|
|
Info (16734): Loading "final" snapshot for partition "green_region".
|
|
Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design contains file: "/opt/opae/1.1.2/share/opae/platform/platform_if/rtl/platform_shims/utils/quartus_ip/platform_utils_dc_fifo.sdc", assignment in base design does not contain file). Check that the assignment in the current design is correct.
|
|
Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design contains file: "/opt/opae/1.1.2/share/opae/platform/platform_if/rtl/platform_shims/utils/quartus_ip/platform_utils_avalon_dc_fifo.sdc", assignment in base design does not contain file). Check that the assignment in the current design is correct.
|
|
Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design contains file: "/opt/opae/1.1.2/share/opae/platform/platform_if/par/platform_if.sdc", assignment in base design does not contain file). Check that the assignment in the current design is correct.
|
|
Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design contains file: "dcp_bbs.sdc", assignment in base design does not contain file). Check that the assignment in the current design is correct.
|
|
Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design contains file: "platform/green_bs.sdc", assignment in base design does not contain file). Check that the assignment in the current design is correct.
|
|
Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design contains file: "dcp_user_clocks.sdc", assignment in base design does not contain file). Check that the assignment in the current design is correct.
|
|
Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/hssi_eth/e10/phy/altera_eth_10gbaser_phy/altera_xcvr_native_a10_191/synth/altera_xcvr_native_a10_false_paths.sdc"). Check that the assignment in the current design is correct.
|
|
Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/hssi_eth/native_xcvr/altera_xcvr_native_a10_191/synth/altera_xcvr_native_a10_false_paths.sdc"). Check that the assignment in the current design is correct.
|
|
Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/remote_stp/QSYS_IPs/PR_190/ip/SLD_HUB_CONT_SYS_WO_SLD_EP/SLD_HUB_CONT_SYS_WO_SLD_EP_sld_hub_controller_system_without_sldep_0/altera_streaming_sld_hub_controller_core_without_sldep_180/synth/altera_streaming_sld_hub_controller_without_sldep.sdc"). Check that the assignment in the current design is correct.
|
|
Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/fme/ptmgr/TEMPERATURE_SourceTree/ptmgr_temp_sensor/altera_temp_sense_191/synth/altera_temp_sense.sdc"). Check that the assignment in the current design is correct.
|
|
Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/top/dcp_top.sdc"). Check that the assignment in the current design is correct.
|
|
Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/sdc/fabric.sdc"). Check that the assignment in the current design is correct.
|
|
Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/sdc/fme.sdc"). Check that the assignment in the current design is correct.
|
|
Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/sdc/fiu.sdc"). Check that the assignment in the current design is correct.
|
|
Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/afu/green_bs.sdc"). Check that the assignment in the current design is correct.
|
|
Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/partial_reconfig/PR_IP/alt_pr_191/synth/rtl/alt_pr.sdc"). Check that the assignment in the current design is correct.
|
|
Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/pcie/ips/pcie_sriov_ep_g3x8/pcie_sriov_ep_g3x8/altera_xcvr_native_a10_191/synth/altera_xcvr_native_a10_false_paths.sdc"). Check that the assignment in the current design is correct.
|
|
Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/pcie/ips/pcie_sriov_ep_g3x8/pcie_sriov_ep_g3x8/altera_pcie_a10_hip_191/synth/altera_pci_express.sdc"). Check that the assignment in the current design is correct.
|
|
Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/afu/nlb_400/nlb_400.sdc"). Check that the assignment in the current design is correct.
|
|
Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/bmc_mailbox/ip/bmc_mailbox/bmc_mailbox_spi_slave_to_avalon_mm_master_bridge_1/spi_slave_to_avalon_mm_master_bridge_191/synth/spiphyslave.sdc"). Check that the assignment in the current design is correct.
|
|
Warning (18502): The SDC_FILE assignment in the current design does not match the base design (assignment in current design does not contain file, assignment in base design contains file: "../design/tcm/ip/tcm/tcm_alt_pr_0/alt_pr_191/synth/rtl/alt_pr.sdc"). Check that the assignment in the current design is correct.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_aeb", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|rdemp_eq_comp_msb_aeb", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|wrptr_g[0]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|wrptr_g[1]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|wrptr_g[2]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|wrptr_g[3]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|wrptr_g[4]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|wrptr_g[5]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|wrptr_g[6]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|rdptr_g1p|counter1a0", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_aeb", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|rdemp_eq_comp_msb_aeb", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|wrptr_g[0]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|wrptr_g[1]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|wrptr_g[2]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|wrptr_g[3]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|wrptr_g[4]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|wrptr_g[5]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|wrptr_g[6]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|rdptr_g1p|counter1a0", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_aeb", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|rdemp_eq_comp_msb_aeb", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|wrptr_g[0]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|wrptr_g[1]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|wrptr_g[2]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|wrptr_g[3]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|wrptr_g[4]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|wrptr_g[5]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|rdptr_g1p|counter1a0", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|wrptr_g1p|counter4a0", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|rdptr_g1p|parity2", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|wrptr_g1p|counter4a0", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|rdptr_g1p|parity2", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|wrptr_g1p|counter3a0", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|rdptr_g1p|parity2", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c2tx_afifo|dcfifo_component|auto_generated|wrptr_g1p|parity5", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|wrptr_g1p|parity5", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0tx_afifo|dcfifo_component|auto_generated|wrptr_g1p|parity4", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_aeb", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|rdemp_eq_comp_msb_aeb", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|wrptr_g[0]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|wrptr_g[1]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|wrptr_g[2]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|wrptr_g[3]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|wrptr_g[4]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|wrptr_g[5]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|wrptr_g[6]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|wrptr_g[7]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|wrptr_g[8]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|wrptr_g[9]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|rdptr_g1p|counter1a0", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_aeb", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|rdemp_eq_comp_msb_aeb", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|wrptr_g[0]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|wrptr_g[1]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|wrptr_g[2]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|wrptr_g[3]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|wrptr_g[4]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|wrptr_g[5]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|wrptr_g[6]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|wrptr_g[7]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|wrptr_g[8]", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|rdptr_g1p|counter1a0", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|wrptr_g1p|counter4a0", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|rdptr_g1p|parity2", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|wrptr_g1p|counter4a0", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|rdptr_g1p|parity2", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c0rx_afifo|dcfifo_component|auto_generated|wrptr_g1p|parity5", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1rx_afifo|dcfifo_component|auto_generated|wrptr_g1p|parity5", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|wrptr_g1p|counter4a0~DUPLICATE", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Critical Warning (19519): The instance assignment "POWER_UP_LEVEL" on register "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|platform_shim_ccip|c.ccip_async_shim|c1tx_afifo|dcfifo_component|auto_generated|wrptr_g1p|parity5~DUPLICATE", in reconfigurable partition "fpga_top|inst_green_bs", is ignored. Initial condition is not guaranteed during partial reconfiguration.
|
|
Info (16678): Successfully loaded final database: elapsed time is 00:00:56
|
|
Info (20030): Parallel compilation is enabled and will use 16 of the 32 processors detected
|
|
Info (21076): Core supply voltage operating condition is not set. Assuming a default value of '0.9V'.
|
|
Info (21077): Low junction temperature is 0 degrees C
|
|
Info (21077): High junction temperature is 100 degrees C
|
|
Info (332164): Evaluating HDL-embedded SDC commands
|
|
Info (332165): Entity MISOctl
|
|
Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *SPIPhy_altera_avalon_st_idle_inserter|received_esc*|*] -to [get_pins -no_case -compatibility_mode *|rdshiftreg*|*]
|
|
Info (332165): Entity MOSIctl
|
|
Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *]
|
|
Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *]
|
|
Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *]
|
|
Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *]
|
|
Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *]
|
|
Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *]
|
|
Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *]
|
|
Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *]
|
|
Info (332166): set_false_path -from [get_pins -no_case -compatibility_mode *|stsourcedata*|*] -to [get_registers *]
|
|
Info (332165): Entity alt_jtag_atlantic
|
|
Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|jupdate}] -to [get_registers {*|alt_jtag_atlantic:*|jupdate1*}]
|
|
Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rdata[*]}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}]
|
|
Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|read}] -to [get_registers {*|alt_jtag_atlantic:*|read1*}]
|
|
Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|read_req}]
|
|
Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rvalid}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}]
|
|
Info (332166): set_false_path -from [get_registers {*|t_dav}] -to [get_registers {*|alt_jtag_atlantic:*|tck_t_dav}]
|
|
Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|user_saw_rvalid}] -to [get_registers {*|alt_jtag_atlantic:*|rvalid0*}]
|
|
Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|wdata[*]}] -to [get_registers {*}]
|
|
Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|write}] -to [get_registers {*|alt_jtag_atlantic:*|write1*}]
|
|
Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|write_stalled}] -to [get_registers {*|alt_jtag_atlantic:*|t_ena*}]
|
|
Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|write_stalled}] -to [get_registers {*|alt_jtag_atlantic:*|t_pause*}]
|
|
Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|write_valid}]
|
|
Info (332165): Entity alt_sync1r1
|
|
Info (332166): set_false_path -to [get_keepers *alt_sync1r1*ff_meta[*]]
|
|
Info (332165): Entity alt_sync_regs_m2
|
|
Info (332166): set_multicycle_path -to [get_keepers *sync_regs_m*din_meta[*]] 2
|
|
Info (332166): set_multicycle_path -to [get_keepers *sync_regs_m*din_meta[*]] 2
|
|
Info (332166): set_false_path -hold -to [get_keepers *sync_regs_m*din_meta[*]]
|
|
Info (332166): set_false_path -hold -to [get_keepers *sync_regs_m*din_meta[*]]
|
|
Info (332165): Entity alt_xcvr_resync
|
|
Info (332166): set regs [get_registers -nowarn *alt_xcvr_resync*sync_r[0]]; if {[llength [query_collection -report -all $regs]] > 0} {set_false_path -to $regs}
|
|
Info (332165): Entity altera_std_synchronizer
|
|
Info (332166): set_false_path -to [get_keepers {*altera_std_synchronizer:*|din_s1}]
|
|
Info (332165): Entity altpcie_reset_delay_sync
|
|
Info (332166): set_false_path -from [get_fanins -async *app_rstn_altpcie_reset_delay_sync_altpcie_a10_hip_hwtcl*rs_meta[*]] -to [get_keepers *app_rstn_altpcie_reset_delay_sync_altpcie_a10_hip_hwtcl*rs_meta[*]]
|
|
Info (332166): set_false_path -from [get_fanins -async *por_sync_altpcie_reset_delay_sync*rs_meta[*]] -to [get_keepers *por_sync_altpcie_reset_delay_sync*rs_meta[*]]
|
|
Info (332165): Entity altpcie_sc_bitsync
|
|
Info (332166): set_multicycle_path -to [get_keepers *pld_clk_in_use_altpcie_sc_bitsync*altpcie_sc_bitsync_meta_dff[*]] 3
|
|
Info (332166): set_false_path -hold -to [get_keepers *pld_clk_in_use_altpcie_sc_bitsync*altpcie_sc_bitsync_meta_dff[*]]
|
|
Info (332166): set_multicycle_path -to [get_keepers *reset_status_altpcie_sc_bitsync*altpcie_sc_bitsync_meta_dff[*]] 3
|
|
Info (332166): set_false_path -hold -to [get_keepers *reset_status_altpcie_sc_bitsync*altpcie_sc_bitsync_meta_dff[*]]
|
|
Info (332165): Entity dcfifo_tsr1
|
|
Info (332166): set_false_path -from *rdptr_g* -to *ws_dgrp|dffpipe_t5c:dffpipe16|dffe17a*
|
|
Info (332166): set_false_path -from *delayed_wrptr_g* -to *rs_dgwp|dffpipe_r5c:dffpipe12|dffe13a*
|
|
Info (332165): Entity alt_sld_fab_0_altera_a10_xcvr_reset_sequencer_191_yjmdoba
|
|
Info (332166): if { [get_collection_size [get_pins -compatibility_mode -nowarn ~ALTERA_CLKUSR~~ibuf|o]] > 0 } { create_clock -name ~ALTERA_CLKUSR~ -period 8 [get_pins -compatibility_mode -nowarn ~ALTERA_CLKUSR~~ibuf|o] }
|
|
Info (19539): Reading the HDL-embedded SDC files elapsed 00:00:28.
|
|
Info (332104): Reading SDC File: '/opt/opae/1.1.2/share/opae/platform/platform_if/rtl/platform_shims/utils/quartus_ip/platform_utils_dc_fifo.sdc'
|
|
Info (332104): Reading SDC File: '/opt/opae/1.1.2/share/opae/platform/platform_if/rtl/platform_shims/utils/quartus_ip/platform_utils_avalon_dc_fifo.sdc'
|
|
Info (332104): Reading SDC File: '/opt/opae/1.1.2/share/opae/platform/platform_if/par/platform_if.sdc'
|
|
Warning (332174): Ignored filter at platform_if.sdc(10): *|platform_shim_ccip|c.ccip_async_shim|error[0] could not be matched with a keeper File: /opt/opae/1.1.2/share/opae/platform/platform_if/par/platform_if.sdc Line: 10
|
|
Warning (332049): Ignored set_false_path at platform_if.sdc(10): Argument <from> is an empty collection File: /opt/opae/1.1.2/share/opae/platform/platform_if/par/platform_if.sdc Line: 10
|
|
Info (332050): set_false_path -from [get_keepers *|platform_shim_ccip|c.ccip_async_shim|error[0]] File: /opt/opae/1.1.2/share/opae/platform/platform_if/par/platform_if.sdc Line: 10
|
|
Warning (332174): Ignored filter at platform_if.sdc(11): *|platform_shim_ccip|c.ccip_async_shim|pwrState[0]* could not be matched with a keeper File: /opt/opae/1.1.2/share/opae/platform/platform_if/par/platform_if.sdc Line: 11
|
|
Warning (332049): Ignored set_false_path at platform_if.sdc(11): Argument <from> is an empty collection File: /opt/opae/1.1.2/share/opae/platform/platform_if/par/platform_if.sdc Line: 11
|
|
Info (332050): set_false_path -from [get_keepers *|platform_shim_ccip|c.ccip_async_shim|pwrState[0]*] File: /opt/opae/1.1.2/share/opae/platform/platform_if/par/platform_if.sdc Line: 11
|
|
Info (332104): Reading SDC File: 'dcp_bbs.sdc'
|
|
Warning (332174): Ignored filter at dcp_bbs.sdc(2863): *aclr_filter*aclr_meta[*] could not be matched with a keeper File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 2863
|
|
Warning (332049): Ignored get_fanins at dcp_bbs.sdc(2863): Argument with value [get_keepers {*aclr_filter*aclr_meta[*]}] contains zero elements File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 2863
|
|
Info (332050): get_fanins -asynch [get_keepers {*aclr_filter*aclr_meta[*]}] File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 2863
|
|
Warning (332049): Ignored set_false_path at dcp_bbs.sdc(2863): Argument <from> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 2863
|
|
Info (332050): set_false_path -from [get_fanins -asynch [get_keepers {*aclr_filter*aclr_meta[*]}]] -to [get_keepers {*aclr_filter*aclr_meta[*]}] File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 2863
|
|
Warning (332049): Ignored set_false_path at dcp_bbs.sdc(2863): Argument <to> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 2863
|
|
Warning (332174): Ignored filter at dcp_bbs.sdc(2864): *flag_mx_meta[*] could not be matched with a keeper File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 2864
|
|
Warning (332049): Ignored set_false_path at dcp_bbs.sdc(2864): Argument <to> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 2864
|
|
Info (332050): set_false_path -to [get_keepers {*flag_mx_meta[*]}] File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 2864
|
|
Warning (332174): Ignored filter at dcp_bbs.sdc(3092): mem|ddr4b|ddr4b|arch|arch_inst|seq_if_inst|afi_cal_success_sync_inst|din_s1|d could not be matched with a pin File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3092
|
|
Warning (332174): Ignored filter at dcp_bbs.sdc(3094): mem|ddr4b|ddr4b|arch|arch_inst|seq_if_inst|afi_cal_fail_sync_inst|din_s1|*data could not be matched with a pin File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3094
|
|
Warning (332174): Ignored filter at dcp_bbs.sdc(3106): mem|ddr4a|ddr4a|arch|arch_inst|seq_if_inst|afi_cal_success_sync_inst|din_s1|d could not be matched with a pin File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3106
|
|
Warning (332174): Ignored filter at dcp_bbs.sdc(3108): mem|ddr4a|ddr4a|arch|arch_inst|seq_if_inst|afi_cal_fail_sync_inst|din_s1|d could not be matched with a pin File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3108
|
|
Warning (332174): Ignored filter at dcp_bbs.sdc(3153): fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g* could not be matched with a keeper File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3153
|
|
Warning (332174): Ignored filter at dcp_bbs.sdc(3153): fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe* could not be matched with a keeper File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3153
|
|
Warning (332049): Ignored set_max_delay at dcp_bbs.sdc(3153): Argument <from> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3153
|
|
Info (332050): set_max_delay -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] 100.000 File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3153
|
|
Warning (332049): Ignored set_max_delay at dcp_bbs.sdc(3153): Argument <to> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3153
|
|
Warning (332174): Ignored filter at dcp_bbs.sdc(3154): fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g* could not be matched with a keeper File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3154
|
|
Warning (332174): Ignored filter at dcp_bbs.sdc(3154): fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe* could not be matched with a keeper File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3154
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|
Warning (332049): Ignored set_max_delay at dcp_bbs.sdc(3154): Argument <from> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3154
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|
Info (332050): set_max_delay -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] 100.000 File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3154
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|
Warning (332049): Ignored set_max_delay at dcp_bbs.sdc(3154): Argument <to> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3154
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|
Warning (332174): Ignored filter at dcp_bbs.sdc(3155): fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g* could not be matched with a keeper File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3155
|
|
Warning (332174): Ignored filter at dcp_bbs.sdc(3155): fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe* could not be matched with a keeper File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3155
|
|
Warning (332049): Ignored set_max_delay at dcp_bbs.sdc(3155): Argument <from> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3155
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|
Info (332050): set_max_delay -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] 100.000 File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3155
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|
Warning (332049): Ignored set_max_delay at dcp_bbs.sdc(3155): Argument <to> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3155
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|
Warning (332174): Ignored filter at dcp_bbs.sdc(3156): fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g* could not be matched with a keeper File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3156
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|
Warning (332174): Ignored filter at dcp_bbs.sdc(3156): fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe* could not be matched with a keeper File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3156
|
|
Warning (332049): Ignored set_max_delay at dcp_bbs.sdc(3156): Argument <from> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3156
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|
Info (332050): set_max_delay -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] 100.000 File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3156
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|
Warning (332049): Ignored set_max_delay at dcp_bbs.sdc(3156): Argument <to> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3156
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|
Warning (332174): Ignored filter at dcp_bbs.sdc(3157): fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g* could not be matched with a keeper File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3157
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|
Warning (332174): Ignored filter at dcp_bbs.sdc(3157): fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe* could not be matched with a keeper File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3157
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|
Warning (332049): Ignored set_max_delay at dcp_bbs.sdc(3157): Argument <from> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3157
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|
Info (332050): set_max_delay -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] 100.000 File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3157
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|
Warning (332049): Ignored set_max_delay at dcp_bbs.sdc(3157): Argument <to> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3157
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|
Warning (332174): Ignored filter at dcp_bbs.sdc(3158): fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g* could not be matched with a keeper File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3158
|
|
Warning (332174): Ignored filter at dcp_bbs.sdc(3158): fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe* could not be matched with a keeper File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3158
|
|
Warning (332049): Ignored set_max_delay at dcp_bbs.sdc(3158): Argument <from> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3158
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|
Info (332050): set_max_delay -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] 100.000 File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3158
|
|
Warning (332049): Ignored set_max_delay at dcp_bbs.sdc(3158): Argument <to> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3158
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|
Warning (332174): Ignored filter at dcp_bbs.sdc(3159): fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g* could not be matched with a keeper File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3159
|
|
Warning (332174): Ignored filter at dcp_bbs.sdc(3159): fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe* could not be matched with a keeper File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3159
|
|
Warning (332049): Ignored set_max_delay at dcp_bbs.sdc(3159): Argument <from> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3159
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|
Info (332050): set_max_delay -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] 100.000 File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3159
|
|
Warning (332049): Ignored set_max_delay at dcp_bbs.sdc(3159): Argument <to> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3159
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|
Warning (332174): Ignored filter at dcp_bbs.sdc(3160): fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g* could not be matched with a keeper File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3160
|
|
Warning (332174): Ignored filter at dcp_bbs.sdc(3160): fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe* could not be matched with a keeper File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3160
|
|
Warning (332049): Ignored set_max_delay at dcp_bbs.sdc(3160): Argument <from> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3160
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|
Info (332050): set_max_delay -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] 100.000 File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3160
|
|
Warning (332049): Ignored set_max_delay at dcp_bbs.sdc(3160): Argument <to> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3160
|
|
Warning (332174): Ignored filter at dcp_bbs.sdc(3161): fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|SoftReset_mem could not be matched with a keeper File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3161
|
|
Warning (332174): Ignored filter at dcp_bbs.sdc(3161): fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4*_mem_if|ddr_reset_sync|resync_chains[0].synchronizer_nocut|*|clrn could not be matched with a pin File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3161
|
|
Warning (332049): Ignored set_max_delay at dcp_bbs.sdc(3161): Argument <from> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3161
|
|
Info (332050): set_max_delay -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|SoftReset_mem}] -to [get_pins {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4*_mem_if|ddr_reset_sync|resync_chains[0].synchronizer_nocut|*|clrn}] 100.000 File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3161
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|
Warning (332049): Ignored set_max_delay at dcp_bbs.sdc(3161): Argument <to> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3161
|
|
Warning (332174): Ignored filter at dcp_bbs.sdc(3162): fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4*_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|wraclr|*|clrn could not be matched with a pin File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3162
|
|
Warning (332049): Ignored set_max_delay at dcp_bbs.sdc(3162): Argument <from> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3162
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|
Info (332050): set_max_delay -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|SoftReset_mem}] -to [get_pins {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4*_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|wraclr|*|clrn}] 100.000 File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3162
|
|
Warning (332049): Ignored set_max_delay at dcp_bbs.sdc(3162): Argument <to> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3162
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|
Warning (332174): Ignored filter at dcp_bbs.sdc(3163): fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4*_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|rdaclr|*|clrn could not be matched with a pin File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3163
|
|
Warning (332049): Ignored set_max_delay at dcp_bbs.sdc(3163): Argument <from> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3163
|
|
Info (332050): set_max_delay -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|SoftReset_mem}] -to [get_pins {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4*_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|rdaclr|*|clrn}] 100.000 File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3163
|
|
Warning (332049): Ignored set_max_delay at dcp_bbs.sdc(3163): Argument <to> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3163
|
|
Warning (332174): Ignored filter at dcp_bbs.sdc(3164): fpga_top|inst_green_bs|inst_ccip_std_afu|inst_green_ccip_interface_reg|pck_cp2af_softReset_T0_q could not be matched with a keeper File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3164
|
|
Warning (332174): Ignored filter at dcp_bbs.sdc(3164): fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|Clk_100_reset_sync|resync_chains[0].synchronizer_nocut|*|clrn could not be matched with a pin File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3164
|
|
Warning (332049): Ignored set_max_delay at dcp_bbs.sdc(3164): Argument <from> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3164
|
|
Info (332050): set_max_delay -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|inst_green_ccip_interface_reg|pck_cp2af_softReset_T0_q}] -to [get_pins {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|Clk_100_reset_sync|resync_chains[0].synchronizer_nocut|*|clrn}] 100.000 File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3164
|
|
Warning (332049): Ignored set_max_delay at dcp_bbs.sdc(3164): Argument <to> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3164
|
|
Warning (332049): Ignored set_min_delay at dcp_bbs.sdc(3200): Argument <from> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3200
|
|
Info (332050): set_min_delay -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -100.000 File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3200
|
|
Warning (332049): Ignored set_min_delay at dcp_bbs.sdc(3200): Argument <to> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3200
|
|
Warning (332049): Ignored set_min_delay at dcp_bbs.sdc(3201): Argument <from> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3201
|
|
Info (332050): set_min_delay -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -100.000 File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3201
|
|
Warning (332049): Ignored set_min_delay at dcp_bbs.sdc(3201): Argument <to> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3201
|
|
Warning (332049): Ignored set_min_delay at dcp_bbs.sdc(3202): Argument <from> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3202
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Info (332050): set_min_delay -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -100.000 File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3202
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|
Warning (332049): Ignored set_min_delay at dcp_bbs.sdc(3202): Argument <to> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3202
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Warning (332049): Ignored set_min_delay at dcp_bbs.sdc(3203): Argument <from> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3203
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|
Info (332050): set_min_delay -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -100.000 File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3203
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|
Warning (332049): Ignored set_min_delay at dcp_bbs.sdc(3203): Argument <to> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3203
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|
Warning (332049): Ignored set_min_delay at dcp_bbs.sdc(3204): Argument <from> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3204
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|
Info (332050): set_min_delay -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -100.000 File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3204
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|
Warning (332049): Ignored set_min_delay at dcp_bbs.sdc(3204): Argument <to> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3204
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|
Warning (332049): Ignored set_min_delay at dcp_bbs.sdc(3205): Argument <from> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3205
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|
Info (332050): set_min_delay -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -100.000 File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3205
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|
Warning (332049): Ignored set_min_delay at dcp_bbs.sdc(3205): Argument <to> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3205
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|
Warning (332049): Ignored set_min_delay at dcp_bbs.sdc(3206): Argument <from> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3206
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Info (332050): set_min_delay -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -100.000 File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3206
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|
Warning (332049): Ignored set_min_delay at dcp_bbs.sdc(3206): Argument <to> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3206
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|
Warning (332049): Ignored set_min_delay at dcp_bbs.sdc(3207): Argument <from> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3207
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|
Info (332050): set_min_delay -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -100.000 File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3207
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|
Warning (332049): Ignored set_min_delay at dcp_bbs.sdc(3207): Argument <to> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3207
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Warning (332049): Ignored set_min_delay at dcp_bbs.sdc(3208): Argument <from> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3208
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Info (332050): set_min_delay -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|SoftReset_mem}] -to [get_pins {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4*_mem_if|ddr_reset_sync|resync_chains[0].synchronizer_nocut|*|clrn}] -100.000 File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3208
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Warning (332049): Ignored set_min_delay at dcp_bbs.sdc(3208): Argument <to> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3208
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Warning (332049): Ignored set_min_delay at dcp_bbs.sdc(3209): Argument <from> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3209
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|
Info (332050): set_min_delay -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|SoftReset_mem}] -to [get_pins {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4*_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|wraclr|*|clrn}] -100.000 File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3209
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|
Warning (332049): Ignored set_min_delay at dcp_bbs.sdc(3209): Argument <to> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3209
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|
Warning (332049): Ignored set_min_delay at dcp_bbs.sdc(3210): Argument <from> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3210
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|
Info (332050): set_min_delay -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|SoftReset_mem}] -to [get_pins {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4*_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|rdaclr|*|clrn}] -100.000 File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3210
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Warning (332049): Ignored set_min_delay at dcp_bbs.sdc(3210): Argument <to> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3210
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Warning (332049): Ignored set_min_delay at dcp_bbs.sdc(3211): Argument <from> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3211
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Info (332050): set_min_delay -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|inst_green_ccip_interface_reg|pck_cp2af_softReset_T0_q}] -to [get_pins {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|Clk_100_reset_sync|resync_chains[0].synchronizer_nocut|*|clrn}] -100.000 File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3211
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Warning (332049): Ignored set_min_delay at dcp_bbs.sdc(3211): Argument <to> is an empty collection File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3211
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Warning (332049): Ignored set_net_delay at dcp_bbs.sdc(3252): argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] contains zero elements File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3252
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|
Info (332050): set_net_delay -max -value_multiplier 0.800 -get_value_from_clock_period dst_clock_period -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3252
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Warning (332049): Ignored set_net_delay at dcp_bbs.sdc(3253): argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] contains zero elements File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3253
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|
Info (332050): set_net_delay -max -value_multiplier 0.800 -get_value_from_clock_period dst_clock_period -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3253
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|
Warning (332049): Ignored set_net_delay at dcp_bbs.sdc(3254): argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] contains zero elements File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3254
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|
Info (332050): set_net_delay -max -value_multiplier 0.800 -get_value_from_clock_period dst_clock_period -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3254
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|
Warning (332049): Ignored set_net_delay at dcp_bbs.sdc(3255): argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] contains zero elements File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3255
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|
Info (332050): set_net_delay -max -value_multiplier 0.800 -get_value_from_clock_period dst_clock_period -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3255
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|
Warning (332049): Ignored set_net_delay at dcp_bbs.sdc(3256): argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] contains zero elements File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3256
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|
Info (332050): set_net_delay -max -value_multiplier 0.800 -get_value_from_clock_period dst_clock_period -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3256
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|
Warning (332049): Ignored set_net_delay at dcp_bbs.sdc(3257): argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] contains zero elements File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3257
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|
Info (332050): set_net_delay -max -value_multiplier 0.800 -get_value_from_clock_period dst_clock_period -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3257
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|
Warning (332049): Ignored set_net_delay at dcp_bbs.sdc(3258): argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] contains zero elements File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3258
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|
Info (332050): set_net_delay -max -value_multiplier 0.800 -get_value_from_clock_period dst_clock_period -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3258
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|
Warning (332049): Ignored set_net_delay at dcp_bbs.sdc(3259): argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] contains zero elements File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3259
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|
Info (332050): set_net_delay -max -value_multiplier 0.800 -get_value_from_clock_period dst_clock_period -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3259
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|
Warning (332049): Ignored set_net_delay at dcp_bbs.sdc(3260): argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] contains zero elements File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3260
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|
Info (332050): set_net_delay -max -value_multiplier 0.800 -get_value_from_clock_period dst_clock_period -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3260
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|
Warning (332049): Ignored set_net_delay at dcp_bbs.sdc(3261): argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] contains zero elements File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3261
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Info (332050): set_net_delay -max -value_multiplier 0.800 -get_value_from_clock_period dst_clock_period -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3261
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Warning (332049): Ignored set_net_delay at dcp_bbs.sdc(3262): argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] contains zero elements File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3262
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Info (332050): set_net_delay -max -value_multiplier 0.800 -get_value_from_clock_period dst_clock_period -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3262
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Warning (332049): Ignored set_net_delay at dcp_bbs.sdc(3263): argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] contains zero elements File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3263
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Info (332050): set_net_delay -max -value_multiplier 0.800 -get_value_from_clock_period dst_clock_period -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3263
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Warning (332049): Ignored set_net_delay at dcp_bbs.sdc(3264): argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] contains zero elements File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3264
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Info (332050): set_net_delay -max -value_multiplier 0.800 -get_value_from_clock_period dst_clock_period -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3264
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Warning (332049): Ignored set_net_delay at dcp_bbs.sdc(3265): argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] contains zero elements File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3265
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Info (332050): set_net_delay -max -value_multiplier 0.800 -get_value_from_clock_period dst_clock_period -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3265
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Warning (332049): Ignored set_net_delay at dcp_bbs.sdc(3266): argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] contains zero elements File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3266
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Info (332050): set_net_delay -max -value_multiplier 0.800 -get_value_from_clock_period dst_clock_period -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3266
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Warning (332049): Ignored set_net_delay at dcp_bbs.sdc(3267): argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] contains zero elements File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3267
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Info (332050): set_net_delay -max -value_multiplier 0.800 -get_value_from_clock_period dst_clock_period -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3267
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Warning (332049): Ignored set_max_skew at dcp_bbs.sdc(3316): Argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] contains zero elements File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3316
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Info (332050): set_max_skew -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3316
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Warning (332049): Ignored set_max_skew at dcp_bbs.sdc(3316): Argument -to with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] contains zero elements File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3316
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Warning (332049): Ignored set_max_skew at dcp_bbs.sdc(3317): Argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] contains zero elements File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3317
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Info (332050): set_max_skew -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3317
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Warning (332049): Ignored set_max_skew at dcp_bbs.sdc(3317): Argument -to with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] contains zero elements File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3317
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Warning (332049): Ignored set_max_skew at dcp_bbs.sdc(3318): Argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] contains zero elements File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3318
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Info (332050): set_max_skew -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3318
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Warning (332049): Ignored set_max_skew at dcp_bbs.sdc(3318): Argument -to with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] contains zero elements File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3318
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Warning (332049): Ignored set_max_skew at dcp_bbs.sdc(3319): Argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] contains zero elements File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3319
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Info (332050): set_max_skew -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3319
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Warning (332049): Ignored set_max_skew at dcp_bbs.sdc(3319): Argument -to with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] contains zero elements File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3319
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Warning (332049): Ignored set_max_skew at dcp_bbs.sdc(3320): Argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] contains zero elements File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3320
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Info (332050): set_max_skew -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3320
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Warning (332049): Ignored set_max_skew at dcp_bbs.sdc(3320): Argument -to with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] contains zero elements File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3320
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Warning (332049): Ignored set_max_skew at dcp_bbs.sdc(3321): Argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] contains zero elements File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3321
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Info (332050): set_max_skew -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3321
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Warning (332049): Ignored set_max_skew at dcp_bbs.sdc(3321): Argument -to with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4a_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] contains zero elements File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3321
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Warning (332049): Ignored set_max_skew at dcp_bbs.sdc(3322): Argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] contains zero elements File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3322
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Info (332050): set_max_skew -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3322
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Warning (332049): Ignored set_max_skew at dcp_bbs.sdc(3322): Argument -to with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] contains zero elements File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3322
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Warning (332049): Ignored set_max_skew at dcp_bbs.sdc(3323): Argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] contains zero elements File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3323
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Info (332050): set_max_skew -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|delayed_wrptr_g*}] -to [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3323
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Warning (332049): Ignored set_max_skew at dcp_bbs.sdc(3323): Argument -to with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4b_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}] contains zero elements File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3323
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Warning (332049): Ignored set_max_skew at dcp_bbs.sdc(3324): Argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|SoftReset_mem}] contains zero elements File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3324
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Info (332050): set_max_skew -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|SoftReset_mem}] -to [get_pins {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4*_mem_if|ddr_reset_sync|resync_chains[0].synchronizer_nocut|*|clrn}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3324
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Warning (332049): Ignored set_max_skew at dcp_bbs.sdc(3324): Argument -to with value [get_pins {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4*_mem_if|ddr_reset_sync|resync_chains[0].synchronizer_nocut|*|clrn}] contains zero elements File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3324
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Warning (332049): Ignored set_max_skew at dcp_bbs.sdc(3325): Argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|SoftReset_mem}] contains zero elements File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3325
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Info (332050): set_max_skew -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|SoftReset_mem}] -to [get_pins {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4*_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|wraclr|*|clrn}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3325
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Warning (332049): Ignored set_max_skew at dcp_bbs.sdc(3325): Argument -to with value [get_pins {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4*_mem_if|afu_res_fifo|fifo_0|dcfifo_component|auto_generated|wraclr|*|clrn}] contains zero elements File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3325
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Warning (332049): Ignored set_max_skew at dcp_bbs.sdc(3326): Argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|SoftReset_mem}] contains zero elements File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3326
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Info (332050): set_max_skew -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|SoftReset_mem}] -to [get_pins {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4*_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|rdaclr|*|clrn}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3326
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Warning (332049): Ignored set_max_skew at dcp_bbs.sdc(3326): Argument -to with value [get_pins {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|inst_local_mem|ddr4*_mem_if|afu_cmd_fifo|fifo_0|dcfifo_component|auto_generated|rdaclr|*|clrn}] contains zero elements File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3326
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Warning (332049): Ignored set_max_skew at dcp_bbs.sdc(3327): Argument -from with value [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|inst_green_ccip_interface_reg|pck_cp2af_softReset_T0_q}] contains zero elements File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3327
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Info (332050): set_max_skew -from [get_keepers {fpga_top|inst_green_bs|inst_ccip_std_afu|inst_green_ccip_interface_reg|pck_cp2af_softReset_T0_q}] -to [get_pins {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|Clk_100_reset_sync|resync_chains[0].synchronizer_nocut|*|clrn}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3327
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Warning (332049): Ignored set_max_skew at dcp_bbs.sdc(3327): Argument -to with value [get_pins {fpga_top|inst_green_bs|inst_ccip_std_afu|nlb_lpbk|Clk_100_reset_sync|resync_chains[0].synchronizer_nocut|*|clrn}] contains zero elements File: /nethome/lcooper43/vortex-dev/hw/syn/opae/build_fpga_16c/build/dcp_bbs.sdc Line: 3327
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Info (332104): Reading SDC File: 'platform/green_bs.sdc'
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Info (332104): Reading SDC File: 'dcp_user_clocks.sdc'
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Info: Target user clock high: computed 167
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|
Info: Target user clock low: computed 83.5
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|
Warning (332043): Overwriting existing clock: fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk0
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Warning (332043): Overwriting existing clock: fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk1
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|
Critical Warning (19294): Synopsys Design Constraints File file not found for instance '': '/nfs/site/disks/pac_build_1/psgpacbuild/SC/adapt/nightly/19.1/367/l64/work/platform/dcp_1.0-rc/build/qdb/_compiler/dcp/_flat/19.2.0/partitioned/1/.temp/sld_fabrics/ipgen/alt_sld_fab_0/alt_sld_fab_0/altera_avalon_dc_fifo_191/synth/alt_sld_fab_0_altera_avalon_dc_fifo_191_27jzy3q.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
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Critical Warning (19294): Synopsys Design Constraints File file not found for instance '': '/nfs/site/disks/pac_build_1/psgpacbuild/SC/adapt/nightly/19.1/367/l64/work/platform/dcp_1.0-rc/build/qdb/_compiler/dcp/_flat/19.2.0/partitioned/1/.temp/sld_fabrics/ipgen/alt_sld_fab_0/alt_sld_fab_0/altera_jtag_dc_streaming_191/synth/altera_avalon_st_jtag_interface.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
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Critical Warning (19294): Synopsys Design Constraints File file not found for instance '': '/nfs/site/disks/pac_build_1/psgpacbuild/SC/adapt/nightly/19.1/367/l64/work/platform/dcp_1.0-rc/build/qdb/_compiler/dcp/_flat/19.2.0/partitioned/1/.temp/sld_fabrics/ipgen/alt_sld_fab_0/alt_sld_fab_0/altera_reset_controller_191/synth/altera_reset_controller.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
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Critical Warning (19294): Synopsys Design Constraints File file not found for instance '': '/p/psg/swip/releases/acds/19.2/57/linux64/ip/altera/sld/jtag/altera_jtag_wys_atom/default_jtag.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
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Info (19449): Reading SDC files elapsed 00:00:11.
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Info (332097): The following timing edges are non-unate. The Timing Analyzer will assume pos-unate behavior for these edges in the clock network.
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Info (332098): Cell: mem|ddr4a|ddr4a|arch|arch_inst|bufs_inst|gen_mem_dqs.inst[0].b|cal_oct.obuf from: oe to: o
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Info (332098): Cell: mem|ddr4a|ddr4a|arch|arch_inst|bufs_inst|gen_mem_dqs.inst[1].b|cal_oct.obuf from: oe to: o
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Info (332098): Cell: mem|ddr4a|ddr4a|arch|arch_inst|bufs_inst|gen_mem_dqs.inst[2].b|cal_oct.obuf from: oe to: o
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Info (332098): Cell: mem|ddr4a|ddr4a|arch|arch_inst|bufs_inst|gen_mem_dqs.inst[3].b|cal_oct.obuf from: oe to: o
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Info (332098): Cell: mem|ddr4a|ddr4a|arch|arch_inst|bufs_inst|gen_mem_dqs.inst[4].b|cal_oct.obuf from: oe to: o
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Info (332098): Cell: mem|ddr4a|ddr4a|arch|arch_inst|bufs_inst|gen_mem_dqs.inst[5].b|cal_oct.obuf from: oe to: o
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Info (332098): Cell: mem|ddr4a|ddr4a|arch|arch_inst|bufs_inst|gen_mem_dqs.inst[6].b|cal_oct.obuf from: oe to: o
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Info (332098): Cell: mem|ddr4a|ddr4a|arch|arch_inst|bufs_inst|gen_mem_dqs.inst[7].b|cal_oct.obuf from: oe to: o
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Info (332098): Cell: mem|ddr4b|ddr4b|arch|arch_inst|bufs_inst|gen_mem_dqs.inst[0].b|cal_oct.obuf from: oe to: o
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Info (332098): Cell: mem|ddr4b|ddr4b|arch|arch_inst|bufs_inst|gen_mem_dqs.inst[1].b|cal_oct.obuf from: oe to: o
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Info (332098): Cell: mem|ddr4b|ddr4b|arch|arch_inst|bufs_inst|gen_mem_dqs.inst[2].b|cal_oct.obuf from: oe to: o
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Info (332098): Cell: mem|ddr4b|ddr4b|arch|arch_inst|bufs_inst|gen_mem_dqs.inst[3].b|cal_oct.obuf from: oe to: o
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Info (332098): Cell: mem|ddr4b|ddr4b|arch|arch_inst|bufs_inst|gen_mem_dqs.inst[4].b|cal_oct.obuf from: oe to: o
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Info (332098): Cell: mem|ddr4b|ddr4b|arch|arch_inst|bufs_inst|gen_mem_dqs.inst[5].b|cal_oct.obuf from: oe to: o
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Info (332098): Cell: mem|ddr4b|ddr4b|arch|arch_inst|bufs_inst|gen_mem_dqs.inst[6].b|cal_oct.obuf from: oe to: o
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Info (332098): Cell: mem|ddr4b|ddr4b|arch|arch_inst|bufs_inst|gen_mem_dqs.inst[7].b|cal_oct.obuf from: oe to: o
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Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties.
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Info (332152): The following assignments are ignored by the derive_clock_uncertainty command
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Warning (332056): PLL cross checking found inconsistent PLL clock settings:
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Warning (332056): Clock: fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk0 was found on node: fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|fpll_inst|outclk[0] with settings that do not match the following PLL specifications:
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Warning (332056): -multiply_by (expected: 25, found: 835), -divide_by (expected: 16, found: 1000)
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Warning (332056): Clock: fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|outclk1 was found on node: fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_cvl_top|inst_user_clk|qph_user_clk_fpll_u0|xcvr_fpll_a10_0|fpll_inst|outclk[1] with settings that do not match the following PLL specifications:
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Warning (332056): -multiply_by (expected: 25, found: 1670), -divide_by (expected: 8, found: 1000)
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Warning (332056): Clock: hssi_pll_t_outclk0 with period: 3.200 found on PLL node: fpga_top|inst_fiu_top|inst_hssi_ctrl|pll_t|xcvr_fpll_a10_0|fpll_inst|outclk[0] does not match the period requirement: 6.400
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Warning (332056): Clock: hssi_pll_t_outclk1 with period: 3.800 found on PLL node: fpga_top|inst_fiu_top|inst_hssi_ctrl|pll_t|xcvr_fpll_a10_0|fpll_inst|outclk[1] does not match the period requirement: 6.400
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Warning (332056): Clock: hssi_pll_r_0_outclk0 with period: 3.200 found on PLL node: fpga_top|inst_fiu_top|inst_hssi_ctrl|pll_r_0|xcvr_fpll_a10_0|fpll_inst|outclk[0] does not match the period requirement: 6.400
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Warning (332056): Clock: hssi_pll_r_0_outclk1 with period: 3.800 found on PLL node: fpga_top|inst_fiu_top|inst_hssi_ctrl|pll_r_0|xcvr_fpll_a10_0|fpll_inst|outclk[1] does not match the period requirement: 6.400
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Info (332171): The following clock uncertainty values are less than the recommended values that would be applied by the derive_clock_uncertainty command
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Info (332172): Setup clock transfer from mem|ddr4b|ddr4b_phy_clk_0 (Rise) to mem|ddr4a|ddr4a_core_usr_clk (Rise) has uncertainty 0.268 that is less than the recommended uncertainty 0.360
|
|
Info (332172): Hold clock transfer from mem|ddr4b|ddr4b_phy_clk_0 (Rise) to mem|ddr4a|ddr4a_core_usr_clk (Rise) has uncertainty 0.272 that is less than the recommended uncertainty 0.360
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Info (332172): Setup clock transfer from mem|ddr4b|ddr4b_phy_clk_l_0 (Rise) to mem|ddr4a|ddr4a_core_usr_clk (Rise) has uncertainty 0.268 that is less than the recommended uncertainty 0.360
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|
Info (332172): Hold clock transfer from mem|ddr4b|ddr4b_phy_clk_l_0 (Rise) to mem|ddr4a|ddr4a_core_usr_clk (Rise) has uncertainty 0.272 that is less than the recommended uncertainty 0.360
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Info (332172): Setup clock transfer from mem|ddr4b|ddr4b_phy_clk_l_1 (Rise) to mem|ddr4a|ddr4a_core_usr_clk (Rise) has uncertainty 0.268 that is less than the recommended uncertainty 0.360
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Info (332172): Hold clock transfer from mem|ddr4b|ddr4b_phy_clk_l_1 (Rise) to mem|ddr4a|ddr4a_core_usr_clk (Rise) has uncertainty 0.272 that is less than the recommended uncertainty 0.360
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Info (332172): Setup clock transfer from mem|ddr4b|ddr4b_phy_clk_l_2 (Rise) to mem|ddr4a|ddr4a_core_usr_clk (Rise) has uncertainty 0.268 that is less than the recommended uncertainty 0.360
|
|
Info (332172): Hold clock transfer from mem|ddr4b|ddr4b_phy_clk_l_2 (Rise) to mem|ddr4a|ddr4a_core_usr_clk (Rise) has uncertainty 0.272 that is less than the recommended uncertainty 0.360
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|
Info (332172): Setup clock transfer from mem|ddr4a|ddr4a_phy_clk_l_1 (Rise) to mem|ddr4a|ddr4a_core_usr_clk (Rise) has uncertainty 0.268 that is less than the recommended uncertainty 0.360
|
|
Info (332172): Hold clock transfer from mem|ddr4a|ddr4a_phy_clk_l_1 (Rise) to mem|ddr4a|ddr4a_core_usr_clk (Rise) has uncertainty 0.272 that is less than the recommended uncertainty 0.360
|
|
Info (332172): Setup clock transfer from mem|ddr4a|ddr4a_phy_clk_l_2 (Rise) to mem|ddr4a|ddr4a_core_usr_clk (Rise) has uncertainty 0.268 that is less than the recommended uncertainty 0.360
|
|
Info (332172): Hold clock transfer from mem|ddr4a|ddr4a_phy_clk_l_2 (Rise) to mem|ddr4a|ddr4a_core_usr_clk (Rise) has uncertainty 0.272 that is less than the recommended uncertainty 0.360
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Info (332172): Setup clock transfer from mem|ddr4a|ddr4a_core_usr_clk (Rise) to mem|ddr4b|ddr4b_phy_clk_l_0 (Rise) has uncertainty 0.289 that is less than the recommended uncertainty 0.360
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Info (332172): Hold clock transfer from mem|ddr4a|ddr4a_core_usr_clk (Rise) to mem|ddr4b|ddr4b_phy_clk_l_0 (Rise) has uncertainty 0.320 that is less than the recommended uncertainty 0.360
|
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Info (332172): Setup clock transfer from mem|ddr4a|ddr4a_core_usr_clk (Rise) to mem|ddr4b|ddr4b_phy_clk_l_1 (Rise) has uncertainty 0.289 that is less than the recommended uncertainty 0.360
|
|
Info (332172): Hold clock transfer from mem|ddr4a|ddr4a_core_usr_clk (Rise) to mem|ddr4b|ddr4b_phy_clk_l_1 (Rise) has uncertainty 0.320 that is less than the recommended uncertainty 0.360
|
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Info (332172): Setup clock transfer from mem|ddr4a|ddr4a_core_usr_clk (Rise) to mem|ddr4b|ddr4b_phy_clk_l_2 (Rise) has uncertainty 0.289 that is less than the recommended uncertainty 0.360
|
|
Info (332172): Hold clock transfer from mem|ddr4a|ddr4a_core_usr_clk (Rise) to mem|ddr4b|ddr4b_phy_clk_l_2 (Rise) has uncertainty 0.320 that is less than the recommended uncertainty 0.360
|
|
Info (332172): Setup clock transfer from mem|ddr4a|ddr4a_core_usr_clk (Rise) to mem|ddr4a|ddr4a_phy_clk_l_1 (Rise) has uncertainty 0.289 that is less than the recommended uncertainty 0.360
|
|
Info (332172): Hold clock transfer from mem|ddr4a|ddr4a_core_usr_clk (Rise) to mem|ddr4a|ddr4a_phy_clk_l_1 (Rise) has uncertainty 0.320 that is less than the recommended uncertainty 0.360
|
|
Info (332172): Setup clock transfer from mem|ddr4a|ddr4a_core_usr_clk (Rise) to mem|ddr4a|ddr4a_phy_clk_l_2 (Rise) has uncertainty 0.289 that is less than the recommended uncertainty 0.360
|
|
Info (332172): Hold clock transfer from mem|ddr4a|ddr4a_core_usr_clk (Rise) to mem|ddr4a|ddr4a_phy_clk_l_2 (Rise) has uncertainty 0.320 that is less than the recommended uncertainty 0.360
|
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Warning (332088): No paths exist between clock target "fpga_top|inst_fiu_top|inst_ccip_fabric_top|inst_fme_top|inst_fme_csr|bmc|spi_bridge|spi_slave_to_avalon_mm_master_bridge_1|the_spislave_inst_for_spichain|the_SPIPhy|SPIPhy_MOSIctl|filtered_sclk_negedge|q" of clock "filtered_sclk_negedge" and its clock source. Assuming zero source clock latency.
|
|
Info (23030): Evaluation of Tcl script ./a10_partial_reconfig/report_timing.tcl was successful
|
|
Info: Quartus Prime Timing Analyzer was successful. 0 errors, 232 warnings
|
|
Info: Peak virtual memory: 24384 megabytes
|
|
Info: Processing ended: Sat Mar 6 09:00:50 2021
|
|
Info: Elapsed time: 00:03:14
|
|
Info (19538): Reading SDC files took 00:00:11 cumulatively in this process.
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Wrote vortex_afu.gbs
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===========================================================================
|
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PR AFU compilation complete
|
|
AFU gbs file is 'vortex_afu.gbs'
|
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Design meets timing
|
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===========================================================================
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