172 lines
5.9 KiB
Verilog
172 lines
5.9 KiB
Verilog
`include "VX_platform.vh"
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`TRACING_OFF
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module VX_dp_ram #(
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parameter DATAW = 1,
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parameter SIZE = 1,
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parameter BYTEENW = 1,
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parameter BUFFERED = 0,
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parameter RWCHECK = 1,
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parameter ADDRW = $clog2(SIZE),
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parameter SIZEW = $clog2(SIZE+1),
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parameter FASTRAM = 0
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) (
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input wire clk,
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input wire [ADDRW-1:0] waddr,
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input wire [ADDRW-1:0] raddr,
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input wire wren,
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input wire [BYTEENW-1:0] byteen,
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input wire rden,
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input wire [DATAW-1:0] din,
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output wire [DATAW-1:0] dout
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);
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`STATIC_ASSERT((1 == BYTEENW) || ((BYTEENW > 1) && 0 == (BYTEENW % 4)), ("invalid parameter"))
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localparam DATA32W = DATAW / 32;
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localparam BYTEEN32W = BYTEENW / 4;
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if (FASTRAM) begin
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if (BUFFERED) begin
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reg [DATAW-1:0] dout_r;
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if (BYTEENW > 1) begin
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`USE_FAST_BRAM reg [DATA32W-1:0][3:0][7:0] mem [SIZE-1:0];
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always @(posedge clk) begin
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if (wren) begin
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for (integer j = 0; j < BYTEEN32W; j++) begin
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for (integer i = 0; i < 4; i++) begin
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if (byteen[j * 4 + i])
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mem[waddr][j][i] <= din[j * 32 + i * 8 +: 8];
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end
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end
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end
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if (rden)
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dout_r <= mem[raddr];
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end
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end else begin
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`USE_FAST_BRAM reg [DATAW-1:0] mem [SIZE-1:0];
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always @(posedge clk) begin
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if (wren && byteen)
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mem[waddr] <= din;
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if (rden)
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dout_r <= mem[raddr];
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end
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end
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assign dout = dout_r;
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end else begin
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`UNUSED_VAR (rden)
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if (BYTEENW > 1) begin
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`USE_FAST_BRAM reg [DATA32W-1:0][3:0][7:0] mem [SIZE-1:0];
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always @(posedge clk) begin
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if (wren) begin
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for (integer j = 0; j < BYTEEN32W; j++) begin
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for (integer i = 0; i < 4; i++) begin
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if (byteen[j * 4 + i])
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mem[waddr][j][i] <= din[j * 32 + i * 8 +: 8];
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end
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end
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end
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end
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assign dout = mem[raddr];
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end else begin
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`USE_FAST_BRAM reg [DATAW-1:0] mem [SIZE-1:0];
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always @(posedge clk) begin
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if (wren && byteen)
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mem[waddr] <= din;
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end
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assign dout = mem[raddr];
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end
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end
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end else begin
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if (BUFFERED) begin
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reg [DATAW-1:0] dout_r;
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if (BYTEENW > 1) begin
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reg [DATA32W-1:0][3:0][7:0] mem [SIZE-1:0];
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always @(posedge clk) begin
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if (wren) begin
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for (integer j = 0; j < BYTEEN32W; j++) begin
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for (integer i = 0; i < 4; i++) begin
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if (byteen[j * 4 + i])
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mem[waddr][j][i] <= din[j * 32 + i * 8 +: 8];
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end
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end
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end
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if (rden)
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dout_r <= mem[raddr];
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end
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end else begin
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reg [DATAW-1:0] mem [SIZE-1:0];
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always @(posedge clk) begin
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if (wren && byteen)
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mem[waddr] <= din;
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if (rden)
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dout_r <= mem[raddr];
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end
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end
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assign dout = dout_r;
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end else begin
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`UNUSED_VAR (rden)
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if (RWCHECK) begin
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if (BYTEENW > 1) begin
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reg [DATA32W-1:0][3:0][7:0] mem [SIZE-1:0];
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always @(posedge clk) begin
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if (wren) begin
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for (integer j = 0; j < BYTEEN32W; j++) begin
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for (integer i = 0; i < 4; i++) begin
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if (byteen[j * 4 + i])
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mem[waddr][j][i] <= din[j * 32 + i * 8 +: 8];
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end
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end
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end
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end
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assign dout = mem[raddr];
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end else begin
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reg [DATAW-1:0] mem [SIZE-1:0];
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always @(posedge clk) begin
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if (wren && byteen)
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mem[waddr] <= din;
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end
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assign dout = mem[raddr];
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end
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end else begin
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if (BYTEENW > 1) begin
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`NO_RW_RAM_CHECK reg [DATA32W-1:0][3:0][7:0] mem [SIZE-1:0];
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always @(posedge clk) begin
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if (wren) begin
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for (integer j = 0; j < BYTEEN32W; j++) begin
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for (integer i = 0; i < 4; i++) begin
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if (byteen[j * 4 + i])
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mem[waddr][j][i] <= din[j * 32 + i * 8 +: 8];
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end
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end
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end
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end
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assign dout = mem[raddr];
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end else begin
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`NO_RW_RAM_CHECK reg [DATAW-1:0] mem [SIZE-1:0];
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always @(posedge clk) begin
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if (wren && byteen)
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mem[waddr] <= din;
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end
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assign dout = mem[raddr];
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end
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end
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end
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end
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endmodule
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`TRACING_ON |