327 lines
12 KiB
C++
327 lines
12 KiB
C++
#include <iostream>
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#include <string>
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#include <stdlib.h>
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#include <string.h>
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#include <iomanip>
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#include <vector>
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#include <unordered_map>
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#include "debug.h"
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#include "types.h"
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#include "util.h"
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#include "decode.h"
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#include "archdef.h"
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#include "instr.h"
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#include "trace.h"
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using namespace vortex;
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struct InstTableEntry_t {
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const char *opString;
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bool controlFlow;
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InstType iType;
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};
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static const std::unordered_map<int, struct InstTableEntry_t> sc_instTable = {
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{Opcode::NOP, {"nop" , false, InstType::N_TYPE}},
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{Opcode::R_INST, {"r_type", false, InstType::R_TYPE}},
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{Opcode::L_INST, {"load" , false, InstType::I_TYPE}},
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{Opcode::I_INST, {"i_type", false, InstType::I_TYPE}},
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{Opcode::S_INST, {"store" , false, InstType::S_TYPE}},
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{Opcode::B_INST, {"branch", true , InstType::B_TYPE}},
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{Opcode::LUI_INST, {"lui" , false, InstType::U_TYPE}},
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{Opcode::AUIPC_INST, {"auipc" , false, InstType::U_TYPE}},
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{Opcode::JAL_INST, {"jal" , true , InstType::J_TYPE}},
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{Opcode::JALR_INST, {"jalr" , true , InstType::I_TYPE}},
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{Opcode::SYS_INST, {"SYS" , true , InstType::I_TYPE}},
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{Opcode::FENCE, {"fence" , true , InstType::I_TYPE}},
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{Opcode::PJ_INST, {"pred j", true , InstType::R_TYPE}},
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{Opcode::GPGPU, {"gpgpu" , false, InstType::R_TYPE}},
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{Opcode::VSET_ARITH, {"vsetvl", false, InstType::V_TYPE}},
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{Opcode::VL, {"vl" , false, InstType::V_TYPE}},
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{Opcode::VS, {"vs" , false, InstType::V_TYPE}},
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{Opcode::FL, {"fl" , false, InstType::I_TYPE }},
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{Opcode::FS, {"fs" , false, InstType::S_TYPE }},
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{Opcode::FCI, {"fci" , false, InstType::R_TYPE }},
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{Opcode::FMADD, {"fma" , false, InstType::R4_TYPE }},
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{Opcode::FMSUB, {"fms" , false, InstType::R4_TYPE }},
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{Opcode::FMNMADD, {"fmnma" , false, InstType::R4_TYPE }},
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{Opcode::FMNMSUB, {"fmnms" , false, InstType::R4_TYPE }}
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};
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std::ostream &vortex::operator<<(std::ostream &os, Instr &instr) {
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os << std::dec << sc_instTable.at(instr.opcode_).opString;
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return os;
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}
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Decoder::Decoder(const ArchDef &arch) {
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inst_s_ = arch.getWordSize() * 8;
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opcode_s_ = 7;
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reg_s_ = 5;
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func2_s_ = 2;
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func3_s_ = 3;
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mop_s_ = 3;
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vmask_s_ = 1;
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shift_opcode_ = 0;
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shift_rd_ = opcode_s_;
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shift_func3_ = opcode_s_ + reg_s_;
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shift_rs1_ = opcode_s_ + reg_s_ + func3_s_;
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shift_rs2_ = opcode_s_ + reg_s_ + func3_s_ + reg_s_;
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shift_func7_ = opcode_s_ + reg_s_ + func3_s_ + reg_s_ + reg_s_;
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shift_func2_ = opcode_s_ + reg_s_ + func3_s_ + reg_s_ + reg_s_;
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shift_rs3_ = opcode_s_ + reg_s_ + func3_s_ + reg_s_ + reg_s_ + func2_s_;
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shift_j_u_immed_ = opcode_s_ + reg_s_;
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shift_s_b_immed_ = opcode_s_ + reg_s_ + func3_s_ + reg_s_ + reg_s_;
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shift_i_immed_ = opcode_s_ + reg_s_ + func3_s_ + reg_s_;
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shift_vset_immed_ = opcode_s_ + reg_s_ + func3_s_ + reg_s_;
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shift_vmask_ = opcode_s_ + reg_s_ + func3_s_ + reg_s_ + reg_s_;
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shift_vmop_ = opcode_s_ + reg_s_ + func3_s_ + reg_s_ + reg_s_ + vmask_s_;
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shift_vnf_ = opcode_s_ + reg_s_ + func3_s_ + reg_s_ + reg_s_ + vmask_s_ + mop_s_;
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shift_func6_ = opcode_s_ + reg_s_ + func3_s_ + reg_s_ + reg_s_ + 1;
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shift_vset_ = opcode_s_ + reg_s_ + func3_s_ + reg_s_ + reg_s_ + 6;
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reg_mask_ = 0x1f;
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func2_mask_ = 0x2;
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func3_mask_ = 0x7;
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func6_mask_ = 0x3f;
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func7_mask_ = 0x7f;
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opcode_mask_ = 0x7f;
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i_imm_mask_ = 0xfff;
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s_imm_mask_ = 0xfff;
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b_imm_mask_ = 0x1fff;
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u_imm_mask_ = 0xfffff;
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j_imm_mask_ = 0xfffff;
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v_imm_mask_ = 0x7ff;
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}
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std::shared_ptr<Instr> Decoder::decode(const std::vector<Byte> &v, Size &idx, trace_inst_t *trace_inst) {
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Word code(readWord(v, idx, inst_s_ / 8));
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// std::cout << "code: " << (int) code << " v: " << v << " indx: " << idx << "\n";
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auto instr = std::make_shared<Instr>();
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Opcode op = (Opcode)((code >> shift_opcode_) & opcode_mask_);
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// std::cout << "opcode: " << op << "\n";
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instr->setOpcode(op);
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Word imeed, dest_bits, imm_bits, bit_11, bits_4_1, bit_10_5,
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bit_12, bits_19_12, bits_10_1, bit_20, unordered, func3;
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InstType curInstType = sc_instTable.at(op).iType; // get current inst type
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if (op == Opcode::FL || op == Opcode::FS) { // need to find out whether it is vector or floating point inst
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Word width_bits = (code >> shift_func3_) & func3_mask_;
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if ((width_bits == 0x1) || (width_bits == 0x2)
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|| (width_bits == 0x3) || (width_bits == 0x4)) {
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curInstType = (op == Opcode::FL)? InstType::I_TYPE : InstType::S_TYPE;
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}
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}
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// std::cout << "op: " << std::hex << op << " what " << sc_instTable[op].iType << "\n";
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switch (curInstType) {
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case InstType::N_TYPE:
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break;
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case InstType::R_TYPE:
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instr->setDestReg((code >> shift_rd_) & reg_mask_);
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instr->setSrcReg((code >> shift_rs1_) & reg_mask_);
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instr->setSrcReg((code >> shift_rs2_) & reg_mask_);
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instr->setFunc3((code >> shift_func3_) & func3_mask_);
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instr->setFunc7((code >> shift_func7_) & func7_mask_);
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trace_inst->valid_inst = true;
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trace_inst->rs1 = ((code >> shift_rs1_) & reg_mask_);
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trace_inst->rs2 = ((code >> shift_rs2_) & reg_mask_);
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trace_inst->rd = ((code >> shift_rd_) & reg_mask_);
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break;
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case InstType::I_TYPE:
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instr->setDestReg((code >> shift_rd_) & reg_mask_);
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instr->setSrcReg((code >> shift_rs1_) & reg_mask_);
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instr->setFunc7((code >> shift_func7_) & func7_mask_);
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func3 = (code >> shift_func3_) & func3_mask_;
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instr->setFunc3(func3);
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if ((func3 == 5) && (op != L_INST) && (op != FL)) {
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// std::cout << "func7: " << func7 << "\n";
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instr->setSrcImm(signExt(((code >> shift_rs2_) & reg_mask_), 5, reg_mask_));
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} else {
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instr->setSrcImm(signExt(code >> shift_i_immed_, 12, i_imm_mask_));
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}
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trace_inst->valid_inst = true;
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trace_inst->rs1 = ((code >> shift_rs1_) & reg_mask_);
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trace_inst->rd = ((code >> shift_rd_) & reg_mask_);
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break;
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case InstType::S_TYPE:
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// std::cout << "************STORE\n";
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instr->setSrcReg((code >> shift_rs1_) & reg_mask_);
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instr->setSrcReg((code >> shift_rs2_) & reg_mask_);
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instr->setFunc3((code >> shift_func3_) & func3_mask_);
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dest_bits = (code >> shift_rd_) & reg_mask_;
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imm_bits = (code >> shift_s_b_immed_ & func7_mask_);
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imeed = (imm_bits << reg_s_) | dest_bits;
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// std::cout << "ENC: store imeed: " << imeed << "\n";
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instr->setSrcImm(signExt(imeed, 12, s_imm_mask_));
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trace_inst->valid_inst = true;
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trace_inst->rs1 = ((code >> shift_rs1_) & reg_mask_);
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trace_inst->rs2 = ((code >> shift_rs2_) & reg_mask_);
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break;
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case InstType::B_TYPE:
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instr->setSrcReg((code >> shift_rs1_) & reg_mask_);
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instr->setSrcReg((code >> shift_rs2_) & reg_mask_);
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instr->setFunc3((code >> shift_func3_) & func3_mask_);
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dest_bits = (code >> shift_rd_) & reg_mask_;
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imm_bits = (code >> shift_s_b_immed_ & func7_mask_);
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bit_11 = dest_bits & 0x1;
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bits_4_1 = dest_bits >> 1;
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bit_10_5 = imm_bits & 0x3f;
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bit_12 = imm_bits >> 6;
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imeed = 0 | (bits_4_1 << 1) | (bit_10_5 << 5) | (bit_11 << 11) | (bit_12 << 12);
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instr->setSrcImm(signExt(imeed, 13, b_imm_mask_));
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trace_inst->valid_inst = true;
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trace_inst->rs1 = ((code >> shift_rs1_) & reg_mask_);
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trace_inst->rs2 = ((code >> shift_rs2_) & reg_mask_);
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break;
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case InstType::U_TYPE:
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instr->setDestReg((code >> shift_rd_) & reg_mask_);
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instr->setSrcImm(signExt(code >> shift_j_u_immed_, 20, u_imm_mask_));
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trace_inst->valid_inst = true;
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trace_inst->rd = ((code >> shift_rd_) & reg_mask_);
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break;
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case InstType::J_TYPE:
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instr->setDestReg((code >> shift_rd_) & reg_mask_);
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// [20 | 10:1 | 11 | 19:12]
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unordered = code >> shift_j_u_immed_;
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bits_19_12 = unordered & 0xff;
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bit_11 = (unordered >> 8) & 0x1;
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bits_10_1 = (unordered >> 9) & 0x3ff;
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bit_20 = (unordered >> 19) & 0x1;
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imeed = 0 | (bits_10_1 << 1) | (bit_11 << 11) | (bits_19_12 << 12) | (bit_20 << 20);
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if (bit_20) {
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imeed |= ~j_imm_mask_;
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}
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instr->setSrcImm(imeed);
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trace_inst->valid_inst = true;
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trace_inst->rd = ((code >> shift_rd_) & reg_mask_);
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break;
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case InstType::V_TYPE:
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D(3, "Entered here: instr type = vector" << op);
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switch (op) {
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case Opcode::VSET_ARITH: //TODO: arithmetic ops
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instr->setDestReg((code >> shift_rd_) & reg_mask_);
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instr->setSrcReg((code >> shift_rs1_) & reg_mask_);
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func3 = (code >> shift_func3_) & func3_mask_;
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instr->setFunc3(func3);
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D(3, "Entered here: instr type = vector");
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if (func3 == 7) {
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D(3, "Entered here: imm instr");
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instr->setVsetImm(!(code >> shift_vset_));
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if (instr->getVsetImm()) {
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Word immed = (code >> shift_rs2_) & v_imm_mask_;
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D(3, "immed" << immed);
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instr->setSrcImm(immed); //TODO
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instr->setVlmul(immed & 0x3);
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D(3, "lmul " << (immed & 0x3));
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instr->setVediv((immed >> 4) & 0x3);
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D(3, "ediv " << ((immed >> 4) & 0x3));
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instr->setVsew((immed >> 2) & 0x3);
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D(3, "sew " << ((immed >> 2) & 0x3));
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} else {
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instr->setSrcReg((code >> shift_rs2_) & reg_mask_);
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trace_inst->rs2 = ((code >> shift_rs2_) & reg_mask_);
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}
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trace_inst->valid_inst = true;
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trace_inst->rs1 = ((code >> shift_rs1_) & reg_mask_);
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trace_inst->rd = ((code >> shift_rd_) & reg_mask_);
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} else {
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instr->setSrcReg((code >> shift_rs2_) & reg_mask_);
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instr->setVmask((code >> shift_vmask_) & 0x1);
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instr->setFunc6((code >> shift_func6_) & func6_mask_);
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trace_inst->valid_inst = true;
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trace_inst->rs1 = ((code >> shift_rs1_) & reg_mask_);
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trace_inst->rs2 = ((code >> shift_rs2_) & reg_mask_);
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trace_inst->rd = ((code >> shift_rd_) & reg_mask_);
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}
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break;
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case Opcode::VL:
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D(3, "vector load instr");
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instr->setDestReg((code >> shift_rd_) & reg_mask_);
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instr->setSrcReg((code >> shift_rs1_) & reg_mask_);
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instr->setVlsWidth((code >> shift_func3_) & func3_mask_);
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instr->setSrcReg((code >> shift_rs2_) & reg_mask_);
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instr->setVmask((code >> shift_vmask_));
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instr->setVmop((code >> shift_vmop_) & func3_mask_);
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instr->setVnf((code >> shift_vnf_) & func3_mask_);
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trace_inst->valid_inst = true;
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trace_inst->rs1 = ((code >> shift_rs1_) & reg_mask_);
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trace_inst->vd = ((code >> shift_rd_) & reg_mask_);
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//trace_inst->vs2 = ((code>>shift_rs2_) & reg_mask_);
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break;
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case Opcode::VS:
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instr->setVs3((code >> shift_rd_) & reg_mask_);
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instr->setSrcReg((code >> shift_rs1_) & reg_mask_);
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instr->setVlsWidth((code >> shift_func3_) & func3_mask_);
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instr->setSrcReg((code >> shift_rs2_) & reg_mask_);
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instr->setVmask((code >> shift_vmask_));
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instr->setVmop((code >> shift_vmop_) & func3_mask_);
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instr->setVnf((code >> shift_vnf_) & func3_mask_);
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trace_inst->valid_inst = true;
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trace_inst->rs1 = ((code >> shift_rs1_) & reg_mask_);
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//trace_inst->vd = ((code>>shift_rd_) & reg_mask_);
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trace_inst->vs1 = ((code >> shift_rd_) & reg_mask_); //vs3
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break;
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default:
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std::cout << "Inavlid opcode.\n";
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std::abort();
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}
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break;
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case R4_TYPE:
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// RT: add R4_TYPE decoder
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instr->setDestReg((code >> shift_rd_) & reg_mask_);
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instr->setSrcReg((code >> shift_rs1_) & reg_mask_);
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instr->setSrcReg((code >> shift_rs2_) & reg_mask_);
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instr->setSrcReg((code >> shift_rs3_) & reg_mask_);
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instr->setFunc3((code >> shift_func3_) & func3_mask_);
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trace_inst->valid_inst = true;
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trace_inst->rs1 = ((code >> shift_rs1_) & reg_mask_);
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trace_inst->rs2 = ((code >> shift_rs2_) & reg_mask_);
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trace_inst->rs3 = ((code >> shift_rs3_) & reg_mask_);
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trace_inst->rd = ((code >> shift_rd_) & reg_mask_);
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break;
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default:
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std::cout << "Unrecognized argument class in word decoder.\n";
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std::abort();
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}
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D(2, "Decoded instr 0x" << std::hex << code << " into: " << instr << std::flush);
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return instr;
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}
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