Lingjun Zhu 50d567d70c Removed unnessary Verilog files, linked memory tech files, having problem with memory instatiation

2019-10-28 14:49:55 -04:00

..

191017.log

added log file

2019-10-17 14:00:22 -04:00

cshrc.dc

Added fsyn for my synthesis

2019-10-27 22:16:57 -04:00

dc_noOpt.log

Finished synthesis with no optimization, cell count increasts to 100k

2019-10-21 17:53:51 -04:00

dc.log

Removed unnessary Verilog files, linked memory tech files, having problem with memory instatiation

2019-10-28 14:49:55 -04:00

fsyn.tcl

Updated files list

2019-10-28 14:29:07 -04:00

Makefile

Synthesis Cleanup 1

2019-10-28 13:43:12 -04:00

NanGate_15nm_OCL.db

Added fsyn for my synthesis

2019-10-27 22:16:57 -04:00

syn.tcl

Removed unnessary Verilog files, linked memory tech files, having problem with memory instatiation

2019-10-28 14:49:55 -04:00

vortex_syn.log

Sucess Synthesis - Finding db

2019-10-28 13:52:49 -04:00