84 lines
2.8 KiB
Verilog
84 lines
2.8 KiB
Verilog
`include "VX_define.vh"
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module VX_smem_arb (
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input wire clk,
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input wire reset,
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// input request
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VX_dcache_core_req_if core_req_if,
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// output requests
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VX_dcache_core_req_if cache_req_if,
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VX_dcache_core_req_if smem_req_if,
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// input responses
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VX_dcache_core_rsp_if cache_rsp_if,
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VX_dcache_core_rsp_if smem_rsp_if,
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// output response
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VX_dcache_core_rsp_if core_rsp_if
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);
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localparam REQ_DATAW = `DCORE_ADDR_WIDTH + 1 + `DWORD_SIZE + (`DWORD_SIZE*8) + (`DCORE_TAG_WIDTH-1);
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localparam RSP_DATAW = `NUM_THREADS + `NUM_THREADS * (`DWORD_SIZE*8) + `DCORE_TAG_WIDTH;
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//
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// handle requests
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//
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for (genvar i = 0; i < `NUM_THREADS; ++i) begin
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wire [1:0][REQ_DATAW-1:0] req_data_out;
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VX_stream_demux #(
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.NUM_REQS (2),
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.DATAW (REQ_DATAW),
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.BUFFERED (1)
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) req_demux (
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.clk (clk),
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.reset (reset),
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.sel (core_req_if.tag[i][0]),
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.valid_in (core_req_if.valid[i]),
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.data_in ({core_req_if.addr[i], core_req_if.rw[i], core_req_if.byteen[i], core_req_if.data[i], core_req_if.tag[i][`DCORE_TAG_WIDTH-1:1]}),
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.ready_in (core_req_if.ready[i]),
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.valid_out ({smem_req_if.valid[i], cache_req_if.valid[i]}),
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.data_out (req_data_out),
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.ready_out ({smem_req_if.ready[i], cache_req_if.ready[i]})
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);
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assign {cache_req_if.addr[i], cache_req_if.rw[i], cache_req_if.byteen[i], cache_req_if.data[i], cache_req_if.tag[i]} = req_data_out[0];
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assign {smem_req_if.addr[i], smem_req_if.rw[i], smem_req_if.byteen[i], smem_req_if.data[i], smem_req_if.tag[i]} = req_data_out[1];
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end
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//
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// handle responses
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//
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wire [1:0] rsp_valid_in;
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wire [1:0][RSP_DATAW-1:0] rsp_data_in;
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wire [`NUM_THREADS-1:0] core_rsp_tmask;
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wire core_rsp_valid;
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assign rsp_valid_in[0] = (| cache_rsp_if.valid);
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assign rsp_valid_in[1] = (| smem_rsp_if.valid);
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assign rsp_data_in[0] = {cache_rsp_if.valid, cache_rsp_if.data, {cache_rsp_if.tag, 1'b0}};
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assign rsp_data_in[1] = {smem_rsp_if.valid, smem_rsp_if.data, {smem_rsp_if.tag, 1'b1}};
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VX_stream_arbiter #(
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.NUM_REQS (2),
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.DATAW (RSP_DATAW),
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.BUFFERED (1)
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) rsp_arb (
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.clk (clk),
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.reset (reset),
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.valid_in (rsp_valid_in),
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.data_in (rsp_data_in),
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.ready_in ({smem_rsp_if.ready, cache_rsp_if.ready}),
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.valid_out (core_rsp_valid),
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.data_out ({core_rsp_tmask, core_rsp_if.data, core_rsp_if.tag}),
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.ready_out (core_rsp_if.ready)
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);
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assign core_rsp_if.valid = {`NUM_THREADS{core_rsp_valid}} & core_rsp_tmask;
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endmodule |