44 lines
793 B
Systemverilog
44 lines
793 B
Systemverilog
`ifndef VX_TEX_RSP_IF
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`define VX_TEX_RSP_IF
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`include "VX_define.vh"
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interface VX_tex_rsp_if ();
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wire valid;
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wire [`NW_BITS-1:0] wid;
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wire [`NUM_THREADS-1:0] tmask;
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wire [31:0] PC;
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wire [`NR_BITS-1:0] rd;
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wire wb;
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wire [`NUM_THREADS-1:0][31:0] data;
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wire ready;
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modport master (
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output valid,
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output wid,
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output tmask,
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output PC,
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output rd,
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output wb,
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output data,
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input ready
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);
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modport slave (
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input valid,
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input wid,
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input tmask,
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input PC,
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input rd,
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input wb,
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input data,
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output ready
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);
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endinterface
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`endif
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