204 lines
8.6 KiB
Verilog
204 lines
8.6 KiB
Verilog
`include "VX_define.vh"
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module VX_lsu_unit #(
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parameter CORE_ID = 0
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) (
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`SCOPE_SIGNALS_LSU_IO
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input wire clk,
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input wire reset,
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// Dcache interface
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VX_cache_core_req_if dcache_req_if,
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VX_cache_core_rsp_if dcache_rsp_if,
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// inputs
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VX_lsu_req_if lsu_req_if,
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// outputs
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VX_exu_to_cmt_if lsu_commit_if
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);
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wire use_valid;
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wire [`NUM_THREADS-1:0] use_thread_mask;
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wire use_req_rw;
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wire [`NUM_THREADS-1:0][29:0] use_req_addr;
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wire [`NUM_THREADS-1:0][1:0] use_req_offset;
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wire [`NUM_THREADS-1:0][3:0] use_req_byteen;
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wire [`NUM_THREADS-1:0][31:0] use_req_data;
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wire [1:0] use_req_sext;
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wire [`NR_BITS-1:0] use_rd;
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wire [`NW_BITS-1:0] use_warp_num;
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wire [`ISTAG_BITS-1:0] use_issue_tag;
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wire use_wb;
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wire [31:0] use_pc;
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genvar i;
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wire [`NUM_THREADS-1:0][31:0] full_address;
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for (i = 0; i < `NUM_THREADS; i++) begin
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assign full_address[i] = lsu_req_if.base_addr[i] + lsu_req_if.offset;
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end
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reg [1:0] mem_req_sext;
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always @(*) begin
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case (lsu_req_if.byteen)
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`BYTEEN_SB: mem_req_sext = 2'h1;
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`BYTEEN_SH: mem_req_sext = 2'h2;
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default: mem_req_sext = 2'h0;
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endcase
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end
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wire [`NUM_THREADS-1:0][29:0] mem_req_addr;
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wire [`NUM_THREADS-1:0][1:0] mem_req_offset;
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wire [`NUM_THREADS-1:0][3:0] mem_req_byteen;
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wire [`NUM_THREADS-1:0][31:0] mem_req_data;
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reg [3:0] wmask;
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always @(*) begin
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case (`BYTEEN_TYPE(lsu_req_if.byteen))
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0: wmask = 4'b0001;
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1: wmask = 4'b0011;
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default: wmask = 4'b1111;
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endcase
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end
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for (i = 0; i < `NUM_THREADS; i++) begin
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assign mem_req_addr[i] = full_address[i][31:2];
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assign mem_req_offset[i] = full_address[i][1:0];
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assign mem_req_byteen[i] = wmask << full_address[i][1:0];
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assign mem_req_data[i] = lsu_req_if.store_data[i] << {mem_req_offset[i], 3'b0};
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end
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wire stall_in = ~dcache_req_if.ready && use_valid;
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// Can accept new request?
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assign lsu_req_if.ready = ~stall_in;
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`IGNORE_WARNINGS_BEGIN
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wire [`NUM_THREADS-1:0][31:0] use_address;
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`IGNORE_WARNINGS_END
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VX_generic_register #(
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.N(1 + `NW_BITS + `NUM_THREADS + `ISTAG_BITS + (`NUM_THREADS * 32) + 2 + 1 + (`NUM_THREADS * (30 + 2 + 4 + 32)) + `NR_BITS + 1 + 32)
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) lsu_req_reg (
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.clk (clk),
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.reset (reset),
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.stall (stall_in),
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.flush (0),
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.in ({lsu_req_if.valid, lsu_req_if.warp_num, lsu_req_if.thread_mask, lsu_req_if.issue_tag, full_address, mem_req_sext, lsu_req_if.rw, mem_req_addr, mem_req_offset, mem_req_byteen, mem_req_data, lsu_req_if.rd, lsu_req_if.wb, lsu_req_if.curr_PC}),
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.out ({use_valid, use_warp_num, use_thread_mask, use_issue_tag, use_address, use_req_sext, use_req_rw, use_req_addr, use_req_offset, use_req_byteen, use_req_data, use_rd, use_wb, use_pc})
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);
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reg [`NUM_THREADS-1:0] mem_rsp_mask_buf [`ISSUEQ_SIZE-1:0];
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reg [`NUM_THREADS-1:0][1:0] mem_rsp_offset_buf [`ISSUEQ_SIZE-1:0];
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reg [1:0] mem_rsp_sext_buf [`ISSUEQ_SIZE-1:0];
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reg [`NUM_THREADS-1:0][31:0] mem_rsp_data_all_buf [`ISSUEQ_SIZE-1:0];
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reg [`NW_BITS-1:0] mem_rsp_warp_num_buf [`ISSUEQ_SIZE-1:0];
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reg [31:0] mem_rsp_curr_PC_buf [`ISSUEQ_SIZE-1:0];
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reg [`NR_BITS-1:0] mem_rsp_rd_buf [`ISSUEQ_SIZE-1:0];
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reg [`NUM_THREADS-1:0][31:0] mem_rsp_data_curr;
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wire [`ISTAG_BITS-1:0] rsp_issue_tag = dcache_rsp_if.tag[0][`ISTAG_BITS-1:0];
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wire [`NUM_THREADS-1:0] mem_rsp_mask = mem_rsp_mask_buf [rsp_issue_tag];
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wire [`NUM_THREADS-1:0][1:0] mem_rsp_offset = mem_rsp_offset_buf [rsp_issue_tag];
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wire [1:0] mem_rsp_sext = mem_rsp_sext_buf [rsp_issue_tag];
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wire [`NUM_THREADS-1:0][31:0] mem_rsp_data_all = mem_rsp_data_all_buf [rsp_issue_tag];
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wire [`NW_BITS-1:0] mem_rsp_warp_num = mem_rsp_warp_num_buf [rsp_issue_tag];
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wire [31:0] mem_rsp_curr_PC = mem_rsp_curr_PC_buf [rsp_issue_tag];
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wire [`NR_BITS-1:0] mem_rsp_rd = mem_rsp_rd_buf [rsp_issue_tag];
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wire [`NUM_THREADS-1:0] mem_rsp_mask_n = mem_rsp_mask & ~dcache_rsp_if.valid;
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wire dcache_req_fire = (| dcache_req_if.valid) && dcache_req_if.ready;
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wire dcache_rsp_fire = (| dcache_rsp_if.valid) && dcache_rsp_if.ready;
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always @(posedge clk) begin
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if (dcache_req_fire && (0 == use_req_rw)) begin
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mem_rsp_mask_buf [use_issue_tag] <= use_thread_mask;
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mem_rsp_offset_buf [use_issue_tag] <= use_req_offset;
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mem_rsp_sext_buf [use_issue_tag] <= use_req_sext;
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mem_rsp_data_all_buf [use_issue_tag] <= 0;
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mem_rsp_warp_num_buf [use_issue_tag] <= use_warp_num;
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mem_rsp_curr_PC_buf [use_issue_tag] <= use_pc;
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mem_rsp_rd_buf [use_issue_tag] <= use_rd;
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end
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if (dcache_rsp_fire) begin
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mem_rsp_mask_buf [rsp_issue_tag] <= mem_rsp_mask_n;
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mem_rsp_data_all_buf [rsp_issue_tag] <= mem_rsp_data_all | mem_rsp_data_curr;
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end
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end
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// Core Request
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assign dcache_req_if.valid = {`NUM_THREADS{use_valid}} & use_thread_mask;
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assign dcache_req_if.rw = {`NUM_THREADS{use_req_rw}};
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assign dcache_req_if.byteen = use_req_byteen;
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assign dcache_req_if.addr = use_req_addr;
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assign dcache_req_if.data = use_req_data;
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`ifdef DBG_CORE_REQ_INFO
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assign dcache_req_if.tag = {use_pc, use_wb, use_rd, use_warp_num, use_issue_tag};
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`else
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assign dcache_req_if.tag = use_issue_tag;
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`endif
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// Core Response
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for (i = 0; i < `NUM_THREADS; i++) begin
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wire [31:0] rsp_data_shifted = dcache_rsp_if.data[i] >> {mem_rsp_offset[i], 3'b0};
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always @(*) begin
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case (mem_rsp_sext)
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1: mem_rsp_data_curr[i] = {{24{rsp_data_shifted[7]}}, rsp_data_shifted[7:0]};
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2: mem_rsp_data_curr[i] = {{16{rsp_data_shifted[15]}}, rsp_data_shifted[15:0]};
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default: mem_rsp_data_curr[i] = rsp_data_shifted;
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endcase
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end
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end
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wire is_store_rsp = dcache_req_fire && use_req_rw;
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wire is_load_rsp = (| dcache_rsp_if.valid) && (0 == mem_rsp_mask_n);
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assign lsu_commit_if.valid = is_load_rsp || is_store_rsp;
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assign lsu_commit_if.issue_tag = is_store_rsp ? use_issue_tag : rsp_issue_tag;
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assign lsu_commit_if.data = mem_rsp_data_curr | mem_rsp_data_all;
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// Can accept new cache response?
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assign dcache_rsp_if.ready = lsu_commit_if.ready && ~is_store_rsp; // STORE has priority
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// scope registration
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`SCOPE_ASSIGN (scope_dcache_req_valid, dcache_req_if.valid);
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`SCOPE_ASSIGN (scope_dcache_req_addr, use_address);
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`SCOPE_ASSIGN (scope_dcache_req_rw, dcache_req_if.rw );
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`SCOPE_ASSIGN (scope_dcache_req_byteen,dcache_req_if.byteen);
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`SCOPE_ASSIGN (scope_dcache_req_data, dcache_req_if.data);
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`SCOPE_ASSIGN (scope_dcache_req_tag, dcache_req_if.tag);
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`SCOPE_ASSIGN (scope_dcache_req_ready, dcache_req_if.ready);
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`SCOPE_ASSIGN (scope_dcache_req_warp_num, use_warp_num);
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`SCOPE_ASSIGN (scope_dcache_req_curr_PC, use_pc);
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`SCOPE_ASSIGN (scope_dcache_rsp_valid, dcache_rsp_if.valid);
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`SCOPE_ASSIGN (scope_dcache_rsp_data, dcache_rsp_if.data);
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`SCOPE_ASSIGN (scope_dcache_rsp_tag, dcache_rsp_if.tag);
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`SCOPE_ASSIGN (scope_dcache_rsp_ready, dcache_rsp_if.ready);
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`UNUSED_VAR (mem_rsp_warp_num)
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`UNUSED_VAR (mem_rsp_curr_PC)
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`UNUSED_VAR (mem_rsp_rd)
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`UNUSED_VAR (use_wb)
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`ifdef DBG_PRINT_CORE_DCACHE
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always @(posedge clk) begin
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if ((| dcache_req_if.valid) && dcache_req_if.ready) begin
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$display("%t: D$%0d req: warp=%0d, PC=%0h, tmask=%b, addr=%0h, tag=%0h, rd=%0d, rw=%0b, byteen=%0h, data=%0h",
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$time, CORE_ID, use_warp_num, use_pc, dcache_req_if.valid, use_address, dcache_req_if.tag, use_rd, dcache_req_if.rw, dcache_req_if.byteen, dcache_req_if.data);
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end
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if ((| dcache_rsp_if.valid) && dcache_rsp_if.ready) begin
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$display("%t: D$%0d rsp: valid=%b, warp=%0d, PC=%0h, tag=%0h, rd=%0d, data=%0h",
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$time, CORE_ID, dcache_rsp_if.valid, mem_rsp_warp_num, mem_rsp_curr_PC, dcache_rsp_if.tag, mem_rsp_rd, dcache_rsp_if.data);
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end
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end
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`endif
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endmodule
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