d47cccc157
+ Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes
58 lines
1.7 KiB
Systemverilog
58 lines
1.7 KiB
Systemverilog
// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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`include "VX_define.vh"
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`include "VX_trace.vh"
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module VX_dcr_data import VX_gpu_pkg::*; (
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input wire clk,
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input wire reset,
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// Inputs
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VX_dcr_bus_if.slave dcr_bus_if,
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// Outputs
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output base_dcrs_t base_dcrs
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);
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`UNUSED_VAR (reset)
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base_dcrs_t dcrs;
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always @(posedge clk) begin
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if (dcr_bus_if.write_valid) begin
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case (dcr_bus_if.write_addr)
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`VX_DCR_BASE_STARTUP_ADDR0 : dcrs.startup_addr[31:0] <= dcr_bus_if.write_data;
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`ifdef XLEN_64
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`VX_DCR_BASE_STARTUP_ADDR1 : dcrs.startup_addr[63:32] <= dcr_bus_if.write_data;
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`endif
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`VX_DCR_BASE_MPM_CLASS : dcrs.mpm_class <= dcr_bus_if.write_data[7:0];
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default:;
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endcase
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end
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end
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assign base_dcrs = dcrs;
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`ifdef DBG_TRACE_CORE_PIPELINE
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always @(posedge clk) begin
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if (dcr_bus_if.write_valid) begin
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`TRACE(1, ("%d: base-dcr: state=", $time));
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trace_base_dcr(1, dcr_bus_if.write_addr);
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`TRACE(1, (", data=0x%0h\n", dcr_bus_if.write_data));
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end
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end
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`endif
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endmodule
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