914b680aed
minor updates minor updates minor update operands optimization minor updates minor updates
130 lines
4.7 KiB
Systemverilog
130 lines
4.7 KiB
Systemverilog
// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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`include "VX_define.vh"
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module VX_gather_unit import VX_gpu_pkg::*; #(
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parameter BLOCK_SIZE = 1,
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parameter NUM_LANES = 1,
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parameter OUT_REG = 0
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) (
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input wire clk,
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input wire reset,
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// inputs
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VX_commit_if.slave commit_in_if [BLOCK_SIZE],
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// outputs
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VX_commit_if.master commit_out_if [`ISSUE_WIDTH]
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);
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localparam BLOCK_SIZE_W = `LOG2UP(BLOCK_SIZE);
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localparam PID_BITS = `CLOG2(`NUM_THREADS / NUM_LANES);
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localparam PID_WIDTH = `UP(PID_BITS);
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localparam DATAW = `UUID_WIDTH + `NW_WIDTH + NUM_LANES + `XLEN + 1 + `NR_BITS + NUM_LANES * `XLEN + PID_WIDTH + 1 + 1;
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localparam DATA_WIS_OFF = DATAW - (`UUID_WIDTH + `NW_WIDTH);
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wire [BLOCK_SIZE-1:0] commit_in_valid;
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wire [BLOCK_SIZE-1:0][DATAW-1:0] commit_in_data;
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wire [BLOCK_SIZE-1:0] commit_in_ready;
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wire [BLOCK_SIZE-1:0][ISSUE_ISW_W-1:0] commit_in_isw;
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for (genvar i = 0; i < BLOCK_SIZE; ++i) begin
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assign commit_in_valid[i] = commit_in_if[i].valid;
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assign commit_in_data[i] = commit_in_if[i].data;
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assign commit_in_if[i].ready = commit_in_ready[i];
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if (BLOCK_SIZE != `ISSUE_WIDTH) begin
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if (BLOCK_SIZE != 1) begin
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assign commit_in_isw[i] = {commit_in_data[i][DATA_WIS_OFF+BLOCK_SIZE_W +: (ISSUE_ISW_W-BLOCK_SIZE_W)], BLOCK_SIZE_W'(i)};
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end else begin
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assign commit_in_isw[i] = commit_in_data[i][DATA_WIS_OFF +: ISSUE_ISW_W];
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end
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end else begin
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assign commit_in_isw[i] = BLOCK_SIZE_W'(i);
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end
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end
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reg [`ISSUE_WIDTH-1:0] commit_out_valid;
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reg [`ISSUE_WIDTH-1:0][DATAW-1:0] commit_out_data;
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wire [`ISSUE_WIDTH-1:0] commit_out_ready;
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always @(*) begin
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commit_out_valid = '0;
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for (integer i = 0; i < `ISSUE_WIDTH; ++i) begin
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commit_out_data[i] = 'x;
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end
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for (integer i = 0; i < BLOCK_SIZE; ++i) begin
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commit_out_valid[commit_in_isw[i]] = commit_in_valid[i];
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commit_out_data[commit_in_isw[i]] = commit_in_data[i];
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end
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end
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for (genvar i = 0; i < BLOCK_SIZE; ++i) begin
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assign commit_in_ready[i] = commit_out_ready[commit_in_isw[i]];
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end
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for (genvar i = 0; i < `ISSUE_WIDTH; ++i) begin
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VX_commit_if #(
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.NUM_LANES (NUM_LANES)
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) commit_tmp_if();
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`RESET_RELAY(commit_out_reset, reset);
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VX_elastic_buffer #(
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.DATAW (DATAW),
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.SIZE (`OUT_REG_TO_EB_SIZE(OUT_REG)),
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.OUT_REG (`OUT_REG_TO_EB_REG(OUT_REG))
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) out_buf (
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.clk (clk),
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.reset (commit_out_reset),
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.valid_in (commit_out_valid[i]),
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.ready_in (commit_out_ready[i]),
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.data_in (commit_out_data[i]),
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.data_out (commit_tmp_if.data),
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.valid_out (commit_tmp_if.valid),
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.ready_out (commit_tmp_if.ready)
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);
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logic [`NUM_THREADS-1:0] commit_tmask_r;
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logic [`NUM_THREADS-1:0][`XLEN-1:0] commit_data_r;
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if (PID_BITS != 0) begin
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always @(*) begin
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commit_tmask_r = '0;
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commit_data_r = 'x;
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for (integer j = 0; j < NUM_LANES; ++j) begin
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commit_tmask_r[commit_tmp_if.data.pid * NUM_LANES + j] = commit_tmp_if.data.tmask[j];
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commit_data_r[commit_tmp_if.data.pid * NUM_LANES + j] = commit_tmp_if.data.data[j];
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end
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end
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end else begin
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assign commit_tmask_r = commit_tmp_if.data.tmask;
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assign commit_data_r = commit_tmp_if.data.data;
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end
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assign commit_out_if[i].valid = commit_tmp_if.valid;
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assign commit_out_if[i].data = {
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commit_tmp_if.data.uuid,
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commit_tmp_if.data.wid,
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commit_tmask_r,
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commit_tmp_if.data.PC,
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commit_tmp_if.data.wb,
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commit_tmp_if.data.rd,
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commit_data_r,
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1'b0, // PID
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commit_tmp_if.data.sop,
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commit_tmp_if.data.eop
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};
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assign commit_tmp_if.ready = commit_out_if[i].ready;
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end
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endmodule
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