d47cccc157
+ Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes
80 lines
2.6 KiB
Systemverilog
80 lines
2.6 KiB
Systemverilog
// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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`include "VX_define.vh"
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module VX_pending_instr #(
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parameter CTR_WIDTH = 12,
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parameter ALM_EMPTY = 1,
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parameter DECR_COUNT = 1
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) (
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input wire clk,
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input wire reset,
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input wire incr,
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input wire [`NW_WIDTH-1:0] incr_wid,
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input wire [DECR_COUNT-1:0] decr,
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input wire [DECR_COUNT-1:0][`NW_WIDTH-1:0] decr_wid,
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input wire [`NW_WIDTH-1:0] alm_empty_wid,
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output wire empty,
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output wire alm_empty
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);
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localparam COUNTW = `CLOG2(DECR_COUNT+1);
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reg [`NUM_WARPS-1:0][CTR_WIDTH-1:0] pending_instrs;
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reg [`NUM_WARPS-1:0][COUNTW-1:0] decr_cnt;
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reg [`NUM_WARPS-1:0][DECR_COUNT-1:0] decr_mask;
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reg [`NUM_WARPS-1:0] incr_cnt, incr_cnt_n;
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reg [`NUM_WARPS-1:0] alm_empty_r, empty_r;
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always @(*) begin
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incr_cnt_n = 0;
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decr_mask = 0;
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if (incr) begin
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incr_cnt_n[incr_wid] = 1;
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end
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for (integer i = 0; i < DECR_COUNT; ++i) begin
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if (decr[i]) begin
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decr_mask[decr_wid[i]][i] = 1;
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end
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end
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end
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for (genvar i = 0; i < `NUM_WARPS; ++i) begin
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wire [COUNTW-1:0] decr_cnt_n;
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`POP_COUNT(decr_cnt_n, decr_mask[i]);
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wire [CTR_WIDTH-1:0] pending_instrs_n = pending_instrs[i] + CTR_WIDTH'(incr_cnt[i]) - CTR_WIDTH'(decr_cnt[i]);
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always @(posedge clk) begin
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if (reset) begin
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incr_cnt[i] <= '0;
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decr_cnt[i] <= '0;
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pending_instrs[i] <= '0;
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alm_empty_r[i] <= 0;
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empty_r[i] <= 1;
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end else begin
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incr_cnt[i] <= incr_cnt_n[i];
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decr_cnt[i] <= decr_cnt_n;
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pending_instrs[i] <= pending_instrs_n;
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alm_empty_r[i] <= (pending_instrs_n == ALM_EMPTY);
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empty_r[i] <= (pending_instrs_n == 0);
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end
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end
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end
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assign alm_empty = alm_empty_r[alm_empty_wid];
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assign empty = (& empty_r);
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endmodule
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