125 lines
4.5 KiB
Systemverilog
125 lines
4.5 KiB
Systemverilog
// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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`include "VX_define.vh"
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module VX_smem_unit import VX_gpu_pkg::*; #(
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parameter CORE_ID = 0
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) (
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input wire clk,
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input wire reset,
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`ifdef PERF_ENABLE
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output cache_perf_t cache_perf,
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`endif
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VX_mem_bus_if.slave dcache_bus_in_if [DCACHE_NUM_REQS],
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VX_mem_bus_if.master dcache_bus_out_if [DCACHE_NUM_REQS]
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);
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`UNUSED_PARAM (CORE_ID)
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localparam SMEM_ADDR_WIDTH = `SMEM_LOG_SIZE - `CLOG2(DCACHE_WORD_SIZE);
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wire [DCACHE_NUM_REQS-1:0] smem_req_valid;
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wire [DCACHE_NUM_REQS-1:0] smem_req_rw;
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wire [DCACHE_NUM_REQS-1:0][SMEM_ADDR_WIDTH-1:0] smem_req_addr;
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wire [DCACHE_NUM_REQS-1:0][DCACHE_WORD_SIZE-1:0] smem_req_byteen;
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wire [DCACHE_NUM_REQS-1:0][DCACHE_WORD_SIZE*8-1:0] smem_req_data;
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wire [DCACHE_NUM_REQS-1:0][DCACHE_NOSM_TAG_WIDTH-1:0] smem_req_tag;
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wire [DCACHE_NUM_REQS-1:0] smem_req_ready;
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wire [DCACHE_NUM_REQS-1:0] smem_rsp_valid;
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wire [DCACHE_NUM_REQS-1:0][DCACHE_WORD_SIZE*8-1:0] smem_rsp_data;
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wire [DCACHE_NUM_REQS-1:0][DCACHE_NOSM_TAG_WIDTH-1:0] smem_rsp_tag;
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wire [DCACHE_NUM_REQS-1:0] smem_rsp_ready;
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`RESET_RELAY (smem_reset, reset);
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VX_shared_mem #(
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.INSTANCE_ID($sformatf("core%0d-smem", CORE_ID)),
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.SIZE (1 << `SMEM_LOG_SIZE),
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.NUM_REQS (DCACHE_NUM_REQS),
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.NUM_BANKS (`SMEM_NUM_BANKS),
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.WORD_SIZE (DCACHE_WORD_SIZE),
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.ADDR_WIDTH (SMEM_ADDR_WIDTH),
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.UUID_WIDTH (`UUID_WIDTH),
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.TAG_WIDTH (DCACHE_NOSM_TAG_WIDTH)
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) shared_mem (
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.clk (clk),
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.reset (smem_reset),
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`ifdef PERF_ENABLE
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.cache_perf (cache_perf),
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`endif
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// Core request
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.req_valid (smem_req_valid),
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.req_rw (smem_req_rw),
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.req_byteen (smem_req_byteen),
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.req_addr (smem_req_addr),
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.req_data (smem_req_data),
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.req_tag (smem_req_tag),
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.req_ready (smem_req_ready),
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// Core response
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.rsp_valid (smem_rsp_valid),
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.rsp_data (smem_rsp_data),
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.rsp_tag (smem_rsp_tag),
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.rsp_ready (smem_rsp_ready)
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);
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VX_mem_bus_if #(
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.DATA_SIZE (DCACHE_WORD_SIZE),
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.TAG_WIDTH (DCACHE_NOSM_TAG_WIDTH)
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) switch_out_bus_if[2 * DCACHE_NUM_REQS]();
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`RESET_RELAY (switch_reset, reset);
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for (genvar i = 0; i < DCACHE_NUM_REQS; ++i) begin
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assign smem_req_valid[i] = switch_out_bus_if[i * 2 + 1].req_valid;
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assign smem_req_rw[i] = switch_out_bus_if[i * 2 + 1].req_data.rw;
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assign smem_req_byteen[i] = switch_out_bus_if[i * 2 + 1].req_data.byteen;
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assign smem_req_data[i] = switch_out_bus_if[i * 2 + 1].req_data.data;
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assign smem_req_tag[i] = switch_out_bus_if[i * 2 + 1].req_data.tag;
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assign switch_out_bus_if[i * 2 + 1].req_ready = smem_req_ready[i];
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assign switch_out_bus_if[i * 2 + 1].rsp_valid = smem_rsp_valid[i];
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assign switch_out_bus_if[i * 2 + 1].rsp_data.data = smem_rsp_data[i];
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assign switch_out_bus_if[i * 2 + 1].rsp_data.tag = smem_rsp_tag[i];
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assign smem_rsp_ready[i] = switch_out_bus_if[i * 2 + 1].rsp_ready;
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assign smem_req_addr[i] = switch_out_bus_if[i * 2 + 1].req_data.addr[SMEM_ADDR_WIDTH-1:0];
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VX_smem_switch #(
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.NUM_REQS (2),
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.DATA_SIZE (DCACHE_WORD_SIZE),
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.TAG_WIDTH (DCACHE_TAG_WIDTH),
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.TAG_SEL_IDX (0),
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.ARBITER ("P"),
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.OUT_REG_REQ (2),
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.OUT_REG_RSP (2)
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) smem_switch (
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.clk (clk),
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.reset (switch_reset),
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.bus_in_if (dcache_bus_in_if[i]),
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.bus_out_if (switch_out_bus_if[i * 2 +: 2])
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);
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end
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// this bus goes to the dcache
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for (genvar i = 0; i < DCACHE_NUM_REQS; ++i) begin
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`ASSIGN_VX_MEM_BUS_IF (dcache_bus_out_if[i], switch_out_bus_if[i * 2]);
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end
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endmodule
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