d47cccc157
+ Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes
46 lines
1.5 KiB
Systemverilog
46 lines
1.5 KiB
Systemverilog
// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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`include "VX_fpu_define.vh"
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`ifdef FPU_DSP
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module VX_fpu_class import VX_fpu_pkg::*; #(
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parameter MAN_BITS = 23,
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parameter EXP_BITS = 8
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) (
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input [EXP_BITS-1:0] exp_i,
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input [MAN_BITS-1:0] man_i,
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output fclass_t clss_o
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);
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wire is_normal = (exp_i != '0) && (exp_i != '1);
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wire is_zero = (exp_i == '0) && (man_i == '0);
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wire is_subnormal = (exp_i == '0) && (man_i != '0);
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wire is_inf = (exp_i == '1) && (man_i == '0);
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wire is_nan = (exp_i == '1) && (man_i != '0);
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wire is_signaling = is_nan && ~man_i[MAN_BITS-1];
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wire is_quiet = is_nan && ~is_signaling;
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assign clss_o.is_normal = is_normal;
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assign clss_o.is_zero = is_zero;
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assign clss_o.is_subnormal = is_subnormal;
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assign clss_o.is_inf = is_inf;
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assign clss_o.is_nan = is_nan;
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assign clss_o.is_quiet = is_quiet;
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assign clss_o.is_signaling = is_signaling;
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endmodule
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`endif
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