43 lines
1.3 KiB
Systemverilog
43 lines
1.3 KiB
Systemverilog
// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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`ifndef VX_FPU_DEFINE_VH
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`define VX_FPU_DEFINE_VH
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`include "VX_define.vh"
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`ifdef SV_DPI
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`include "float_dpi.vh"
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`endif
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`define FPU_MERGE_FFLAGS(out, in, mask, lanes) \
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fflags_t __``out; \
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always @(*) begin \
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__``out = '0; \
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for (integer __i = 0; __i < lanes; ++__i) begin \
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if (mask[__i]) begin \
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__``out.NX |= in[__i].NX; \
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__``out.UF |= in[__i].UF; \
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__``out.OF |= in[__i].OF; \
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__``out.DZ |= in[__i].DZ; \
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__``out.NV |= in[__i].NV; \
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end \
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end \
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end \
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assign out = __``out
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`define FP_CLASS_BITS $bits(VX_fpu_pkg::fclass_t)
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`define FP_FLAGS_BITS $bits(VX_fpu_pkg::fflags_t)
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`endif // VX_FPU_DEFINE_VH
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