d47cccc157
+ Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes
287 lines
9.8 KiB
Systemverilog
287 lines
9.8 KiB
Systemverilog
// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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`include "VX_fpu_define.vh"
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`ifdef FPU_FPNEW
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module VX_fpu_fpnew
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import VX_fpu_pkg::*;
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import fpnew_pkg::*;
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import cf_math_pkg::*;
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import defs_div_sqrt_mvp::*;
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#(
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parameter NUM_LANES = 1,
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parameter TAGW = 1,
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parameter OUT_REG = 0
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) (
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input wire clk,
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input wire reset,
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input wire valid_in,
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output wire ready_in,
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input wire [NUM_LANES-1:0] lane_mask,
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input wire [TAGW-1:0] tag_in,
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input wire [`INST_FPU_BITS-1:0] op_type,
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input wire [`INST_FMT_BITS-1:0] fmt,
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input wire [`INST_FRM_BITS-1:0] frm,
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input wire [NUM_LANES-1:0][`XLEN-1:0] dataa,
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input wire [NUM_LANES-1:0][`XLEN-1:0] datab,
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input wire [NUM_LANES-1:0][`XLEN-1:0] datac,
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output wire [NUM_LANES-1:0][`XLEN-1:0] result,
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output wire has_fflags,
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output wire [`FP_FLAGS_BITS-1:0] fflags,
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output wire [TAGW-1:0] tag_out,
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input wire ready_out,
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output wire valid_out
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);
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localparam LATENCY_FDIVSQRT = `MAX(`LATENCY_FDIV, `LATENCY_FSQRT);
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localparam RSP_DATAW = (NUM_LANES * `XLEN) + 1 + $bits(fflags_t) + TAGW;
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`ifdef XLEN_64
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// use scalar configuration for mixed formats
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localparam fpnew_pkg::fpu_features_t FPU_FEATURES = '{
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Width: unsigned'(`XLEN),
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EnableVectors: 1'b0,
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EnableNanBox: 1'b1,
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`ifdef FLEN_64
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FpFmtMask: 5'b11000,
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`else
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FpFmtMask: 5'b11000, // TODO: added FP64 to fix CVT bug in FpNew
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`endif
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IntFmtMask: 4'b0011
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};
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`else
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localparam fpnew_pkg::fpu_features_t FPU_FEATURES = '{
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Width: unsigned'(`XLEN * NUM_LANES),
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EnableVectors: 1'b1,
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EnableNanBox: 1'b0,
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FpFmtMask: 5'b10000,
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IntFmtMask: 4'b0010
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};
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`endif
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localparam fpnew_pkg::fpu_implementation_t FPU_IMPLEMENTATION = '{
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PipeRegs:'{'{`LATENCY_FMA, 0, 0, 0, 0}, // ADDMUL
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'{default: unsigned'(LATENCY_FDIVSQRT)}, // DIVSQRT
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'{default: `LATENCY_FNCP}, // NONCOMP
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'{default: `LATENCY_FCVT}}, // CONV
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UnitTypes:'{'{default: fpnew_pkg::PARALLEL}, // ADDMUL
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'{default: fpnew_pkg::MERGED}, // DIVSQRT
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'{default: fpnew_pkg::PARALLEL}, // NONCOMP
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'{default: fpnew_pkg::MERGED}}, // CONV
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PipeConfig: fpnew_pkg::DISTRIBUTED
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};
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wire fpu_ready_in, fpu_valid_in;
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wire fpu_ready_out, fpu_valid_out;
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reg [TAGW-1:0] fpu_tag_in, fpu_tag_out;
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reg [2:0][NUM_LANES-1:0][`XLEN-1:0] fpu_operands;
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wire [NUM_LANES-1:0][`XLEN-1:0] fpu_result;
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fpnew_pkg::status_t fpu_status;
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fpnew_pkg::operation_e fpu_op;
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reg [`INST_FRM_BITS-1:0] fpu_rnd;
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reg fpu_op_mod;
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reg fpu_has_fflags, fpu_has_fflags_out;
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fpnew_pkg::fp_format_e fpu_src_fmt, fpu_dst_fmt;
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fpnew_pkg::int_format_e fpu_int_fmt;
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`UNUSED_VAR (fmt)
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always @(*) begin
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fpu_op = 'x;
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fpu_rnd = frm;
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fpu_op_mod = 0;
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fpu_has_fflags = 1;
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fpu_operands[0] = dataa;
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fpu_operands[1] = datab;
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fpu_operands[2] = datac;
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fpu_dst_fmt = fpnew_pkg::FP32;
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fpu_int_fmt = fpnew_pkg::INT32;
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`ifdef FLEN_64
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if (fmt[0]) begin
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fpu_dst_fmt = fpnew_pkg::FP64;
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end
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`endif
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`ifdef XLEN_64
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if (fmt[1]) begin
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fpu_int_fmt = fpnew_pkg::INT64;
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end
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`endif
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fpu_src_fmt = fpu_dst_fmt;
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case (op_type)
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`INST_FPU_ADD: begin
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fpu_op = fpnew_pkg::ADD;
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fpu_operands[1] = dataa;
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fpu_operands[2] = datab;
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end
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`INST_FPU_SUB: begin
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fpu_op = fpnew_pkg::ADD;
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fpu_operands[1] = dataa;
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fpu_operands[2] = datab;
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fpu_op_mod = 1;
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end
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`INST_FPU_MUL: begin fpu_op = fpnew_pkg::MUL; end
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`INST_FPU_DIV: begin fpu_op = fpnew_pkg::DIV; end
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`INST_FPU_SQRT: begin fpu_op = fpnew_pkg::SQRT; end
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`INST_FPU_MADD: begin fpu_op = fpnew_pkg::FMADD; end
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`INST_FPU_MSUB: begin fpu_op = fpnew_pkg::FMADD; fpu_op_mod = 1; end
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`INST_FPU_NMADD: begin fpu_op = fpnew_pkg::FNMSUB; fpu_op_mod = 1; end
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`INST_FPU_NMSUB: begin fpu_op = fpnew_pkg::FNMSUB; end
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`ifdef FLEN_64
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`INST_FPU_F2F: begin fpu_op = fpnew_pkg::F2F; fpu_src_fmt = fmt[0] ? fpnew_pkg::FP32 : fpnew_pkg::FP64; end
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`endif
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`INST_FPU_F2I,
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`INST_FPU_F2U: begin fpu_op = fpnew_pkg::F2I; fpu_op_mod = op_type[0]; end
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`INST_FPU_I2F,
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`INST_FPU_U2F: begin fpu_op = fpnew_pkg::I2F; fpu_op_mod = op_type[0]; end
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`INST_FPU_CMP: begin fpu_op = fpnew_pkg::CMP; end
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`INST_FPU_MISC:begin
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case (frm)
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0,1,2: begin fpu_op = fpnew_pkg::SGNJ; fpu_rnd = {1'b0, frm[1:0]}; fpu_has_fflags = 0; end // FSGNJ
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3: begin fpu_op = fpnew_pkg::CLASSIFY; fpu_has_fflags = 0; end // CLASS
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4,5: begin fpu_op = fpnew_pkg::SGNJ; fpu_rnd = 3'b011; fpu_op_mod = ~frm[0]; fpu_has_fflags = 0; end // FMV.X.W, FMV.W.X
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6,7: begin fpu_op = fpnew_pkg::MINMAX; fpu_rnd = {2'b00, frm[0]}; end // MIN, MAX
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endcase
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end
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default:;
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endcase
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`ifdef FPU_RV64F
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// apply nan-boxing to floating-point operands
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for (integer i = 0; i < NUM_LANES; ++i) begin
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if (op_type != `INST_FPU_I2F && op_type != `INST_FPU_U2F) begin
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fpu_operands[0][i] |= 64'hffffffff00000000;
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end
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fpu_operands[1][i] |= 64'hffffffff00000000;
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fpu_operands[2][i] |= 64'hffffffff00000000;
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end
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`endif
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end
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`ifdef XLEN_64
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`UNUSED_VAR (lane_mask)
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for (genvar i = 0; i < NUM_LANES; ++i) begin
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wire [(TAGW+1)-1:0] fpu_tag;
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wire fpu_valid_out_uq;
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wire fpu_ready_in_uq;
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fpnew_pkg::status_t fpu_status_uq;
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`UNUSED_VAR (fpu_tag)
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`UNUSED_VAR (fpu_valid_out_uq)
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`UNUSED_VAR (fpu_ready_in_uq)
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`UNUSED_VAR (fpu_status_uq)
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fpnew_top #(
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.Features (FPU_FEATURES),
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.Implementation (FPU_IMPLEMENTATION),
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.TagType (logic[(TAGW+1)-1:0])
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) fpnew_core (
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.clk_i (clk),
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.rst_ni (~reset),
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.operands_i ({fpu_operands[2][i], fpu_operands[1][i], fpu_operands[0][i]}),
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.rnd_mode_i (fpnew_pkg::roundmode_e'(fpu_rnd)),
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.op_i (fpu_op),
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.op_mod_i (fpu_op_mod),
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.src_fmt_i (fpu_src_fmt),
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.dst_fmt_i (fpu_dst_fmt),
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.int_fmt_i (fpu_int_fmt),
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`UNUSED_PIN (vectorial_op_i),
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`UNUSED_PIN (simd_mask_i),
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.tag_i ({fpu_tag_in, fpu_has_fflags}),
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.in_valid_i (fpu_valid_in),
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.in_ready_o (fpu_ready_in_uq),
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.flush_i (reset),
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.result_o (fpu_result[i]),
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.status_o (fpu_status_uq),
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.tag_o (fpu_tag),
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.out_valid_o (fpu_valid_out_uq),
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.out_ready_i (fpu_ready_out),
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`UNUSED_PIN (busy_o)
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);
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if (i == 0) begin
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assign {fpu_tag_out, fpu_has_fflags_out} = fpu_tag;
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assign fpu_valid_out = fpu_valid_out_uq;
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assign fpu_ready_in = fpu_ready_in_uq;
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assign fpu_status = fpu_status_uq;
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end
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end
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`else
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fpnew_top #(
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.Features (FPU_FEATURES),
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.Implementation (FPU_IMPLEMENTATION),
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.TagType (logic[(TAGW+1)-1:0]),
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.TrueSIMDClass (1),
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.EnableSIMDMask (1)
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) fpnew_core (
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.clk_i (clk),
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.rst_ni (~reset),
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.operands_i (fpu_operands),
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.rnd_mode_i (fpnew_pkg::roundmode_e'(fpu_rnd)),
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.op_i (fpu_op),
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.op_mod_i (fpu_op_mod),
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.src_fmt_i (fpu_src_fmt),
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.dst_fmt_i (fpu_dst_fmt),
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.int_fmt_i (fpu_int_fmt),
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.vectorial_op_i (1'b1),
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.simd_mask_i (lane_mask),
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.tag_i ({fpu_tag_in, fpu_has_fflags}),
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.in_valid_i (fpu_valid_in),
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.in_ready_o (fpu_ready_in),
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.flush_i (reset),
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.result_o (fpu_result),
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.status_o (fpu_status),
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.tag_o ({fpu_tag_out, fpu_has_fflags_out}),
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.out_valid_o (fpu_valid_out),
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.out_ready_i (fpu_ready_out),
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`UNUSED_PIN (busy_o)
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);
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`endif
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assign fpu_valid_in = valid_in;
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assign ready_in = fpu_ready_in;
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assign fpu_tag_in = tag_in;
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VX_elastic_buffer #(
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.DATAW (RSP_DATAW),
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.SIZE (`OUT_REG_TO_EB_SIZE(OUT_REG)),
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.OUT_REG (`OUT_REG_TO_EB_REG(OUT_REG))
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) rsp_buf (
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.clk (clk),
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.reset (reset),
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.valid_in (fpu_valid_out),
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.ready_in (fpu_ready_out),
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.data_in ({fpu_result, fpu_has_fflags_out, fpu_status, fpu_tag_out}),
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.data_out ({result, has_fflags, fflags, tag_out}),
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.valid_out (valid_out),
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.ready_out (ready_out)
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);
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endmodule
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`endif
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