d47cccc157
+ Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes
42 lines
1.0 KiB
Systemverilog
42 lines
1.0 KiB
Systemverilog
// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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`ifndef VX_FPU_PKG_VH
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`define VX_FPU_PKG_VH
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`include "VX_define.vh"
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package VX_fpu_pkg;
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typedef struct packed {
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logic is_normal;
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logic is_zero;
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logic is_subnormal;
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logic is_inf;
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logic is_nan;
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logic is_quiet;
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logic is_signaling;
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} fclass_t;
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typedef struct packed {
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logic NV; // 4-Invalid
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logic DZ; // 3-Divide by zero
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logic OF; // 2-Overflow
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logic UF; // 1-Underflow
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logic NX; // 0-Inexact
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} fflags_t;
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endpackage
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`endif // VX_FPU_PKG_VH
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