d47cccc157
+ Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes
135 lines
3.3 KiB
Systemverilog
135 lines
3.3 KiB
Systemverilog
// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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`include "VX_fpu_define.vh"
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`ifdef FPU_DSP
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module VX_fpu_sqrt import VX_fpu_pkg::*; #(
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parameter NUM_LANES = 1,
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parameter TAGW = 1
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) (
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input wire clk,
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input wire reset,
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output wire ready_in,
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input wire valid_in,
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input wire [NUM_LANES-1:0] lane_mask,
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input wire [TAGW-1:0] tag_in,
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input wire [`INST_FRM_BITS-1:0] frm,
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input wire [NUM_LANES-1:0][31:0] dataa,
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output wire [NUM_LANES-1:0][31:0] result,
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output wire has_fflags,
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output wire [`FP_FLAGS_BITS-1:0] fflags,
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output wire [TAGW-1:0] tag_out,
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input wire ready_out,
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output wire valid_out
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);
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`UNUSED_VAR (frm)
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wire stall = ~ready_out && valid_out;
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wire enable = ~stall;
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fflags_t [NUM_LANES-1:0] per_lane_fflags;
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wire [NUM_LANES-1:0] lane_mask_out;
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VX_shift_register #(
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.DATAW (1 + NUM_LANES + TAGW),
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.DEPTH (`LATENCY_FSQRT),
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.RESETW (1)
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) shift_reg (
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.clk(clk),
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.reset (reset),
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.enable (enable),
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.data_in ({valid_in, lane_mask, tag_in}),
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.data_out ({valid_out, lane_mask_out, tag_out})
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);
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assign ready_in = enable;
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`ifdef QUARTUS
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for (genvar i = 0; i < NUM_LANES; ++i) begin
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acl_fsqrt fsqrt (
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.clk (clk),
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.areset (1'b0),
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.en (enable),
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.a (dataa[i]),
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.q (result[i])
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);
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end
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assign has_fflags = 0;
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assign per_lane_fflags = 'x;
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`elsif VIVADO
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for (genvar i = 0; i < NUM_LANES; ++i) begin
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wire tuser;
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xil_fsqrt fsqrt (
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.aclk (clk),
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.aclken (enable),
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.s_axis_a_tvalid (1'b1),
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.s_axis_a_tdata (dataa[i][31:0]),
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`UNUSED_PIN (m_axis_result_tvalid),
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.m_axis_result_tdata (result[i][31:0]),
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.m_axis_result_tuser (tuser)
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);
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// NV, DZ, OF, UF, NX
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assign per_lane_fflags[i] = {tuser, 1'b0, 1'b0, 1'b0, 1'b0};
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end
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assign has_fflags = 1;
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`else
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for (genvar i = 0; i < NUM_LANES; ++i) begin
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reg [63:0] r;
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`UNUSED_VAR (r)
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fflags_t f;
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always @(*) begin
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dpi_fsqrt (enable && valid_in, int'(0), {32'hffffffff, dataa[i]}, frm, r, f);
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end
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VX_shift_register #(
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.DATAW (32 + $bits(fflags_t)),
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.DEPTH (`LATENCY_FSQRT)
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) shift_req_dpi (
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.clk (clk),
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`UNUSED_PIN (reset),
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.enable (enable),
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.data_in ({r[31:0], f}),
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.data_out ({result[i], per_lane_fflags[i]})
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);
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end
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assign has_fflags = 1;
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`endif
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`FPU_MERGE_FFLAGS(fflags, per_lane_fflags, lane_mask_out, NUM_LANES);
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endmodule
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`endif
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