c1e168fdbe
+ Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes minor update minor update minor update minor update minor update minor update cleanup cleanup cache bindings and memory perf refactory minor update minor update hw unit tests fixes minor update minor update minor update minor update minor update minor udpate minor update minor update minor update minor update minor update minor update minor update minor updates minor updates minor update minor update minor update minor update minor update minor update minor updates minor updates minor updates minor updates minor update minor update
272 lines
10 KiB
Systemverilog
272 lines
10 KiB
Systemverilog
// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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`include "VX_cache_define.vh"
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// this is an implementation of a pipelined multi-banked cache
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// we allocate a free slot from the MSHR before processing a core request
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// and release the slot when we get a cache hit.
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// during a memory fill response we initiate the replay sequence
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// and dequeue all associated pending entries.
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// Warning: This MSHR implementation is strongly coupled with the bank pipeline
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// and as such changes to either module requires careful evaluation.
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// This implementation makes the following assumptions:
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// (1) two-cycle pipeline: st0 and st1.
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// (2) core request flow: st0: allocate / lookup, st1: finalize.
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// (3) the first dequeue after the fill should happen in st0, when the fill is in st1
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// this is enforced inside the bank by "rdw_hazard_st0".
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module VX_cache_mshr #(
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parameter `STRING INSTANCE_ID= "",
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parameter BANK_ID = 0,
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// Size of line inside a bank in bytes
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parameter LINE_SIZE = 16,
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// Number of banks
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parameter NUM_BANKS = 1,
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// Miss Reserv Queue Knob
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parameter MSHR_SIZE = 4,
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// Request debug identifier
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parameter UUID_WIDTH = 0,
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// MSHR parameters
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parameter DATA_WIDTH = 1,
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parameter MSHR_ADDR_WIDTH = `LOG2UP(MSHR_SIZE)
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) (
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input wire clk,
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input wire reset,
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`IGNORE_UNUSED_BEGIN
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input wire[`UP(UUID_WIDTH)-1:0] deq_req_uuid,
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input wire[`UP(UUID_WIDTH)-1:0] lkp_req_uuid,
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input wire[`UP(UUID_WIDTH)-1:0] fin_req_uuid,
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`IGNORE_UNUSED_END
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// allocate
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input wire allocate_valid,
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input wire [`CS_LINE_ADDR_WIDTH-1:0] allocate_addr,
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input wire allocate_rw,
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input wire [DATA_WIDTH-1:0] allocate_data,
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output wire [MSHR_ADDR_WIDTH-1:0] allocate_id,
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output wire [MSHR_ADDR_WIDTH-1:0] allocate_tail,
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output wire allocate_ready,
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// lookup
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input wire lookup_valid,
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input wire [`CS_LINE_ADDR_WIDTH-1:0] lookup_addr,
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output wire [MSHR_SIZE-1:0] lookup_matches,
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// memory fill
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input wire fill_valid,
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input wire [MSHR_ADDR_WIDTH-1:0] fill_id,
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output wire [`CS_LINE_ADDR_WIDTH-1:0] fill_addr,
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// dequeue
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output wire dequeue_valid,
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output wire [`CS_LINE_ADDR_WIDTH-1:0] dequeue_addr,
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output wire dequeue_rw,
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output wire [DATA_WIDTH-1:0] dequeue_data,
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output wire [MSHR_ADDR_WIDTH-1:0] dequeue_id,
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input wire dequeue_ready,
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// finalize
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input wire finalize_valid,
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input wire finalize_release,
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input wire finalize_pending,
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input wire [MSHR_ADDR_WIDTH-1:0] finalize_id,
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input wire [MSHR_ADDR_WIDTH-1:0] finalize_tail
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);
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`UNUSED_PARAM (BANK_ID)
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reg [`CS_LINE_ADDR_WIDTH-1:0] addr_table [MSHR_SIZE-1:0];
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reg [MSHR_ADDR_WIDTH-1:0] next_index [MSHR_SIZE-1:0];
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reg [MSHR_SIZE-1:0] valid_table, valid_table_n;
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reg [MSHR_SIZE-1:0] next_table, next_table_x, next_table_n;
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reg [MSHR_SIZE-1:0] write_table;
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reg allocate_rdy, allocate_rdy_n;
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reg [MSHR_ADDR_WIDTH-1:0] allocate_id_r, allocate_id_n;
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reg dequeue_val, dequeue_val_n;
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reg [MSHR_ADDR_WIDTH-1:0] dequeue_id_r, dequeue_id_n;
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wire [MSHR_ADDR_WIDTH-1:0] tail_idx;
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wire allocate_fire = allocate_valid && allocate_ready;
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wire dequeue_fire = dequeue_valid && dequeue_ready;
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wire [MSHR_SIZE-1:0] addr_matches;
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for (genvar i = 0; i < MSHR_SIZE; ++i) begin
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assign addr_matches[i] = valid_table[i] && (addr_table[i] == lookup_addr);
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end
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VX_lzc #(
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.N (MSHR_SIZE),
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.REVERSE (1)
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) allocate_sel (
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.data_in (~valid_table_n),
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.data_out (allocate_id_n),
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.valid_out (allocate_rdy_n)
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);
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VX_onehot_encoder #(
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.N (MSHR_SIZE)
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) tail_sel (
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.data_in (addr_matches & ~next_table_x),
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.data_out (tail_idx),
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`UNUSED_PIN (valid_out)
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);
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always @(*) begin
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valid_table_n = valid_table;
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next_table_x = next_table;
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dequeue_val_n = dequeue_val;
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dequeue_id_n = dequeue_id;
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if (fill_valid) begin
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dequeue_val_n = 1;
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dequeue_id_n = fill_id;
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end
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if (dequeue_fire) begin
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valid_table_n[dequeue_id] = 0;
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if (next_table[dequeue_id]) begin
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dequeue_id_n = next_index[dequeue_id];
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end else begin
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dequeue_val_n = 0;
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end
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end
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if (finalize_valid) begin
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if (finalize_release) begin
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valid_table_n[finalize_id] = 0;
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end
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if (finalize_pending) begin
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next_table_x[finalize_tail] = 1;
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end
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end
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next_table_n = next_table_x;
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if (allocate_fire) begin
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valid_table_n[allocate_id] = 1;
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next_table_n[allocate_id] = 0;
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end
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end
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always @(posedge clk) begin
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if (reset) begin
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valid_table <= '0;
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allocate_rdy <= 0;
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dequeue_val <= 0;
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end else begin
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valid_table <= valid_table_n;
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allocate_rdy <= allocate_rdy_n;
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dequeue_val <= dequeue_val_n;
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end
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if (allocate_fire) begin
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addr_table[allocate_id] <= allocate_addr;
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write_table[allocate_id] <= allocate_rw;
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end
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if (finalize_valid && finalize_pending) begin
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next_index[finalize_tail] <= finalize_id;
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end
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dequeue_id_r <= dequeue_id_n;
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allocate_id_r <= allocate_id_n;
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next_table <= next_table_n;
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end
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`RUNTIME_ASSERT((~allocate_fire || ~valid_table[allocate_id_r]), ("%t: *** %s-bank%0d inuse allocation: addr=0x%0h, id=%0d (#%0d)", $time, INSTANCE_ID, BANK_ID,
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`CS_LINE_TO_FULL_ADDR(allocate_addr, BANK_ID), allocate_id_r, lkp_req_uuid))
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`RUNTIME_ASSERT((~finalize_valid || valid_table[finalize_id]), ("%t: *** %s-bank%0d invalid release: addr=0x%0h, id=%0d (#%0d)", $time, INSTANCE_ID, BANK_ID,
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`CS_LINE_TO_FULL_ADDR(addr_table[finalize_id], BANK_ID), finalize_id, fin_req_uuid))
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`RUNTIME_ASSERT((~fill_valid || valid_table[fill_id]), ("%t: *** %s-bank%0d invalid fill: addr=0x%0h, id=%0d", $time, INSTANCE_ID, BANK_ID,
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`CS_LINE_TO_FULL_ADDR(addr_table[fill_id], BANK_ID), fill_id))
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VX_dp_ram #(
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.DATAW (DATA_WIDTH),
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.SIZE (MSHR_SIZE),
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.LUTRAM (1)
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) entries (
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.clk (clk),
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.read (1'b1),
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.write (allocate_valid),
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`UNUSED_PIN (wren),
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.waddr (allocate_id_r),
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.wdata (allocate_data),
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.raddr (dequeue_id_r),
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.rdata (dequeue_data)
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);
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assign fill_addr = addr_table[fill_id];
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assign allocate_ready = allocate_rdy;
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assign allocate_id = allocate_id_r;
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assign allocate_tail = tail_idx;
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assign dequeue_valid = dequeue_val;
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assign dequeue_addr = addr_table[dequeue_id_r];
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assign dequeue_rw = write_table[dequeue_id_r];
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assign dequeue_id = dequeue_id_r;
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assign lookup_matches = addr_matches & ~write_table;
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`UNUSED_VAR (lookup_valid)
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`ifdef DBG_TRACE_CACHE_MSHR
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reg show_table;
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always @(posedge clk) begin
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if (reset) begin
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show_table <= 0;
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end else begin
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show_table <= allocate_fire || lookup_valid || finalize_valid || fill_valid || dequeue_fire;
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end
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if (allocate_fire)
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`TRACE(3, ("%d: %s-bank%0d mshr-allocate: addr=0x%0h, tail=%0d, id=%0d (#%0d)\n", $time, INSTANCE_ID, BANK_ID,
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`CS_LINE_TO_FULL_ADDR(allocate_addr, BANK_ID), allocate_tail, allocate_id, lkp_req_uuid));
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if (lookup_valid)
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`TRACE(3, ("%d: %s-bank%0d mshr-lookup: addr=0x%0h, matches=%b (#%0d)\n", $time, INSTANCE_ID, BANK_ID,
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`CS_LINE_TO_FULL_ADDR(lookup_addr, BANK_ID), lookup_matches, lkp_req_uuid));
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if (finalize_valid)
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`TRACE(3, ("%d: %s-bank%0d mshr-finalize release=%b, pending=%b, tail=%0d, id=%0d (#%0d)\n", $time, INSTANCE_ID, BANK_ID,
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finalize_release, finalize_pending, finalize_tail, finalize_id, fin_req_uuid));
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if (fill_valid)
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`TRACE(3, ("%d: %s-bank%0d mshr-fill: addr=0x%0h, addr=0x%0h, id=%0d\n", $time, INSTANCE_ID, BANK_ID,
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`CS_LINE_TO_FULL_ADDR(addr_table[fill_id], BANK_ID), `CS_LINE_TO_FULL_ADDR(fill_addr, BANK_ID), fill_id));
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if (dequeue_fire)
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`TRACE(3, ("%d: %s-bank%0d mshr-dequeue: addr=0x%0h, id=%0d (#%0d)\n", $time, INSTANCE_ID, BANK_ID,
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`CS_LINE_TO_FULL_ADDR(dequeue_addr, BANK_ID), dequeue_id_r, deq_req_uuid));
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if (show_table) begin
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`TRACE(3, ("%d: %s-bank%0d mshr-table", $time, INSTANCE_ID, BANK_ID));
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for (integer i = 0; i < MSHR_SIZE; ++i) begin
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if (valid_table[i]) begin
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`TRACE(3, (" %0d=0x%0h", i, `CS_LINE_TO_FULL_ADDR(addr_table[i], BANK_ID)));
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if (write_table[i])
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`TRACE(3, ("(w)"));
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else
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`TRACE(3, ("(r)"));
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if (next_table[i])
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`TRACE(3, ("->%0d", next_index[i]));
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end
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end
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`TRACE(3, ("\n"));
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end
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end
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`endif
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endmodule
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