27 lines
279 B
Verilog
27 lines
279 B
Verilog
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`include "VX_define.v"
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`ifndef VX_ICACHE_REQ
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`define VX_ICACHE_REQ
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interface VX_icache_request_inter ();
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wire[31:0] pc_address;
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// source-side view
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modport snk (
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input pc_address
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);
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// source-side view
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modport src (
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output pc_address
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);
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endinterface
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`endif |