139 lines
5.0 KiB
Verilog
139 lines
5.0 KiB
Verilog
`include "VX_cache_config.vh"
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module VX_data_access #(
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parameter CACHE_ID = 0,
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parameter BANK_ID = 0,
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// Size of cache in bytes
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parameter CACHE_SIZE = 1,
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// Size of line inside a bank in bytes
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parameter CACHE_LINE_SIZE = 1,
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// Number of banks
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parameter NUM_BANKS = 1,
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// Size of a word in bytes
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parameter WORD_SIZE = 1,
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// Enable dram update
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parameter DRAM_ENABLE = 1,
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// Enable cache writeable
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parameter WRITE_ENABLE = 1,
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// Enable write-through
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parameter WRITE_THROUGH = 1,
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// size of tag id in core request tag
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parameter CORE_TAG_ID_BITS = 0
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) (
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input wire clk,
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input wire reset,
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`ifdef DBG_CACHE_REQ_INFO
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`IGNORE_WARNINGS_BEGIN
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input wire[31:0] rdebug_pc,
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input wire[`NW_BITS-1:0] rdebug_wid,
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input wire[31:0] wdebug_pc,
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input wire[`NW_BITS-1:0] wdebug_wid,
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`IGNORE_WARNINGS_END
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`endif
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input wire stall,
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// reading
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input wire readen_in,
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`IGNORE_WARNINGS_BEGIN
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input wire[`LINE_ADDR_WIDTH-1:0] raddr_in,
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`IGNORE_WARNINGS_END
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output wire [`CACHE_LINE_WIDTH-1:0] readdata_out,
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output wire [CACHE_LINE_SIZE-1:0] dirtyb_out,
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// writing
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input wire writeen_in,
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`IGNORE_WARNINGS_BEGIN
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input wire[`LINE_ADDR_WIDTH-1:0] waddr_in,
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`IGNORE_WARNINGS_END
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input wire [`UP(`WORD_SELECT_BITS)-1:0] wwsel_in,
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input wire [WORD_SIZE-1:0] wbyteen_in,
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input wire wfill_in,
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input wire [`WORD_WIDTH-1:0] writeword_in,
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input wire [`CACHE_LINE_WIDTH-1:0] readdata_in,
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input wire [`CACHE_LINE_WIDTH-1:0] filldata_in
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);
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wire [CACHE_LINE_SIZE-1:0] read_dirtyb;
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wire [`CACHE_LINE_WIDTH-1:0] read_data;
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wire [CACHE_LINE_SIZE-1:0] byte_enable;
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wire [`CACHE_LINE_WIDTH-1:0] write_data;
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wire write_enable;
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wire [`LINE_SELECT_BITS-1:0] raddr = raddr_in[`LINE_SELECT_BITS-1:0];
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wire [`LINE_SELECT_BITS-1:0] waddr = waddr_in[`LINE_SELECT_BITS-1:0];
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`UNUSED_VAR (readen_in)
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VX_data_store #(
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.CACHE_SIZE (CACHE_SIZE),
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.CACHE_LINE_SIZE (CACHE_LINE_SIZE),
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.NUM_BANKS (NUM_BANKS),
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.WORD_SIZE (WORD_SIZE),
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.WRITE_ENABLE (WRITE_ENABLE)
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) data_store (
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.clk (clk),
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.reset (reset),
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.read_addr (raddr),
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.read_data (read_data),
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.read_dirtyb (read_dirtyb),
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.write_enable(write_enable),
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.write_fill (wfill_in),
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.write_addr (waddr),
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.byte_enable (byte_enable),
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.write_data (write_data)
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);
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wire [`WORDS_PER_LINE-1:0][WORD_SIZE-1:0] wbyteen_qual;
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wire [`WORDS_PER_LINE-1:0][`WORD_WIDTH-1:0] writedata_qual;
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if (`WORD_SELECT_BITS != 0) begin
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for (genvar i = 0; i < `WORDS_PER_LINE; i++) begin
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assign wbyteen_qual[i] = (wwsel_in == `WORD_SELECT_BITS'(i)) ? wbyteen_in : {WORD_SIZE{1'b0}};
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assign writedata_qual[i] = (wwsel_in == `WORD_SELECT_BITS'(i)) ? writeword_in : readdata_in[i * `WORD_WIDTH +: `WORD_WIDTH];
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end
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end else begin
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`UNUSED_VAR (wwsel_in)
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`UNUSED_VAR (readdata_in)
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assign wbyteen_qual = wbyteen_in;
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assign writedata_qual = writeword_in;
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end
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assign byte_enable = wfill_in ? {CACHE_LINE_SIZE{1'b1}} : wbyteen_qual;
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assign write_data = wfill_in ? filldata_in : writedata_qual;
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assign write_enable = writeen_in && !stall;
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wire rw_hazard = DRAM_ENABLE && (raddr == waddr) && writeen_in;
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for (genvar i = 0; i < CACHE_LINE_SIZE; i++) begin
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assign dirtyb_out[i] = rw_hazard ? byte_enable[i] : read_dirtyb[i];
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assign readdata_out[i * 8 +: 8] = (rw_hazard && byte_enable[i]) ? write_data[i * 8 +: 8] : read_data[i * 8 +: 8];
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end
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`ifdef DBG_PRINT_CACHE_DATA
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always @(posedge clk) begin
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if (!stall) begin
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if (writeen_in) begin
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if (wfill_in) begin
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$display("%t: cache%0d:%0d data-fill: addr=%0h, dirty=%b, blk_addr=%0d, data=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(waddr_in, BANK_ID), dirtyb_out, waddr, write_data);
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end else begin
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$display("%t: cache%0d:%0d data-write: addr=%0h, wid=%0d, PC=%0h, byteen=%b, dirty=%b, blk_addr=%0d, wsel=%0d, data=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(waddr_in, BANK_ID), rdebug_wid, rdebug_pc, byte_enable, dirtyb_out, waddr, wwsel_in, writeword_in);
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end
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end
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if (readen_in) begin
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$display("%t: cache%0d:%0d data-read: addr=%0h, wid=%0d, PC=%0h, dirty=%b, blk_addr=%0d, data=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(raddr_in, BANK_ID), rdebug_wid, rdebug_pc, dirtyb_out, raddr, read_data);
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end
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end
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end
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`endif
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endmodule |