143 lines
4.0 KiB
Verilog
143 lines
4.0 KiB
Verilog
`include "VX_define.vh"
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module VX_execute #(
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parameter CORE_ID = 0
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) (
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`SCOPE_IO_VX_execute
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input wire clk,
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input wire reset,
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// Dcache interface
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VX_dcache_core_req_if dcache_req_if,
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VX_dcache_core_rsp_if dcache_rsp_if,
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// commit status
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VX_cmt_to_csr_if cmt_to_csr_if,
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`ifdef PERF_ENABLE
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VX_perf_memsys_if perf_memsys_if,
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VX_perf_pipeline_if perf_pipeline_if,
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`endif
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// inputs
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VX_alu_req_if alu_req_if,
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VX_lsu_req_if lsu_req_if,
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VX_csr_req_if csr_req_if,
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VX_fpu_req_if fpu_req_if,
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VX_gpu_req_if gpu_req_if,
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// outputs
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VX_branch_ctl_if branch_ctl_if,
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VX_warp_ctl_if warp_ctl_if,
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VX_commit_if alu_commit_if,
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VX_commit_if ld_commit_if,
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VX_commit_if st_commit_if,
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VX_commit_if csr_commit_if,
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VX_commit_if fpu_commit_if,
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VX_commit_if gpu_commit_if,
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input wire busy
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);
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VX_fpu_to_csr_if fpu_to_csr_if();
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wire[`NUM_WARPS-1:0] csr_pending;
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wire[`NUM_WARPS-1:0] fpu_pending;
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`RESET_RELAY (alu_reset);
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`RESET_RELAY (lsu_reset);
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`RESET_RELAY (csr_reset);
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`RESET_RELAY (gpu_reset);
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VX_alu_unit #(
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.CORE_ID (CORE_ID)
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) alu_unit (
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.clk (clk),
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.reset (alu_reset),
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.alu_req_if (alu_req_if),
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.branch_ctl_if (branch_ctl_if),
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.alu_commit_if (alu_commit_if)
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);
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VX_lsu_unit #(
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.CORE_ID (CORE_ID)
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) lsu_unit (
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`SCOPE_BIND_VX_execute_lsu_unit
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.clk (clk),
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.reset (lsu_reset),
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.dcache_req_if (dcache_req_if),
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.dcache_rsp_if (dcache_rsp_if),
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.lsu_req_if (lsu_req_if),
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.ld_commit_if (ld_commit_if),
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.st_commit_if (st_commit_if)
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);
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VX_csr_unit #(
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.CORE_ID (CORE_ID)
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) csr_unit (
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.clk (clk),
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.reset (csr_reset),
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`ifdef PERF_ENABLE
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.perf_memsys_if (perf_memsys_if),
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.perf_pipeline_if (perf_pipeline_if),
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`endif
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.cmt_to_csr_if (cmt_to_csr_if),
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.fpu_to_csr_if (fpu_to_csr_if),
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.csr_req_if (csr_req_if),
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.csr_commit_if (csr_commit_if),
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.fpu_pending (fpu_pending),
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.pending (csr_pending),
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.busy (busy)
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);
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`ifdef EXT_F_ENABLE
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`RESET_RELAY (fpu_reset);
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VX_fpu_unit #(
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.CORE_ID (CORE_ID)
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) fpu_unit (
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.clk (clk),
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.reset (fpu_reset),
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.fpu_req_if (fpu_req_if),
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.fpu_to_csr_if (fpu_to_csr_if),
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.fpu_commit_if (fpu_commit_if),
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.csr_pending (csr_pending),
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.pending (fpu_pending)
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);
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`else
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`UNUSED_VAR (csr_pending)
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`UNUSED_VAR (fpu_to_csr_if.read_frm)
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assign fpu_req_if.ready = 0;
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assign fpu_commit_if.valid = 0;
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assign fpu_commit_if.wid = 0;
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assign fpu_commit_if.PC = 0;
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assign fpu_commit_if.tmask = 0;
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assign fpu_commit_if.wb = 0;
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assign fpu_commit_if.rd = 0;
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assign fpu_commit_if.data = 0;
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assign fpu_to_csr_if.write_enable = 0;
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assign fpu_to_csr_if.write_wid = 0;
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assign fpu_to_csr_if.write_fflags = 0;
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assign fpu_to_csr_if.read_wid = 0;
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assign fpu_pending = 0;
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`endif
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VX_gpu_unit #(
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.CORE_ID (CORE_ID)
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) gpu_unit (
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`SCOPE_BIND_VX_execute_gpu_unit
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.clk (clk),
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.reset (gpu_reset),
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.gpu_req_if (gpu_req_if),
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.warp_ctl_if (warp_ctl_if),
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.gpu_commit_if (gpu_commit_if)
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);
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// special workaround to get RISC-V tests Pass/Fail status
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wire ebreak /* verilator public */;
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assign ebreak = alu_req_if.valid && alu_req_if.ready
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&& `ALU_IS_BR(alu_req_if.op_mod)
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&& (`BR_OP(alu_req_if.op_type) == `BR_EBREAK
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|| `BR_OP(alu_req_if.op_type) == `BR_ECALL);
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endmodule
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