88 lines
2.8 KiB
Verilog
88 lines
2.8 KiB
Verilog
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`include "VX_define.v"
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module VX_writeback (
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input wire clk,
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input wire reset,
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// Mem WB info
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VX_inst_mem_wb_inter VX_mem_wb,
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// EXEC Unit WB info
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VX_inst_exec_wb_inter VX_inst_exec_wb,
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// CSR Unit WB info
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VX_csr_wb_inter VX_csr_wb,
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// Actual WB to GPR
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VX_wb_inter VX_writeback_inter,
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output wire no_slot_mem,
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output wire no_slot_exec
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);
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VX_wb_inter VX_writeback_tempp();
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wire exec_wb = (VX_inst_exec_wb.wb != 0) && (|VX_inst_exec_wb.wb_valid);
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wire mem_wb = (VX_mem_wb.wb != 0) && (|VX_mem_wb.wb_valid);
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wire csr_wb = (VX_csr_wb.wb != 0) && (|VX_csr_wb.valid);
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assign no_slot_mem = mem_wb && (exec_wb || csr_wb);
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assign no_slot_exec = exec_wb && (csr_wb);
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assign VX_writeback_tempp.write_data = csr_wb ? VX_csr_wb.csr_result :
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exec_wb ? VX_inst_exec_wb.alu_result :
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mem_wb ? VX_mem_wb.loaded_data :
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0;
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assign VX_writeback_tempp.wb_valid = csr_wb ? VX_csr_wb.valid :
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exec_wb ? VX_inst_exec_wb.wb_valid :
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mem_wb ? VX_mem_wb.wb_valid :
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0;
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assign VX_writeback_tempp.rd = csr_wb ? VX_csr_wb.rd :
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exec_wb ? VX_inst_exec_wb.rd :
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mem_wb ? VX_mem_wb.rd :
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0;
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assign VX_writeback_tempp.wb = csr_wb ? VX_csr_wb.wb :
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exec_wb ? VX_inst_exec_wb.wb :
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mem_wb ? VX_mem_wb.wb :
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0;
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assign VX_writeback_tempp.wb_warp_num = csr_wb ? VX_csr_wb.warp_num :
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exec_wb ? VX_inst_exec_wb.wb_warp_num :
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mem_wb ? VX_mem_wb.wb_warp_num :
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0;
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assign VX_writeback_tempp.wb_pc = csr_wb ? 32'hdeadbeef :
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exec_wb ? VX_inst_exec_wb.exec_wb_pc :
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mem_wb ? VX_mem_wb.mem_wb_pc :
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32'hdeadbeef;
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wire zero = 0;
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wire[`NT-1:0][31:0] use_wb_data;
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VX_generic_register #(.N(39 + `NW_M1 + 1 + `NT*33)) wb_register(
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.clk (clk),
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.reset(reset),
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.stall(zero),
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.flush(zero),
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.in ({VX_writeback_tempp.write_data, VX_writeback_tempp.wb_valid, VX_writeback_tempp.rd, VX_writeback_tempp.wb, VX_writeback_tempp.wb_warp_num, VX_writeback_tempp.wb_pc}),
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.out ({use_wb_data , VX_writeback_inter.wb_valid, VX_writeback_inter.rd, VX_writeback_inter.wb, VX_writeback_inter.wb_warp_num, VX_writeback_inter.wb_pc})
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);
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assign VX_writeback_inter.write_data = use_wb_data;
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endmodule : VX_writeback // VX_writeback
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