62 lines
1.7 KiB
Systemverilog
62 lines
1.7 KiB
Systemverilog
// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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`include "VX_define.vh"
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interface VX_decode_if ();
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typedef struct packed {
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logic [`UUID_WIDTH-1:0] uuid;
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logic [`NW_WIDTH-1:0] wid;
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logic [`NUM_THREADS-1:0] tmask;
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logic [`EX_BITS-1:0] ex_type;
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logic [`INST_OP_BITS-1:0] op_type;
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logic [`INST_MOD_BITS-1:0] op_mod;
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logic wb;
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logic use_PC;
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logic use_imm;
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logic [`XLEN-1:0] PC;
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logic [`XLEN-1:0] imm;
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logic [`NR_BITS-1:0] rd;
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logic [`NR_BITS-1:0] rs1;
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logic [`NR_BITS-1:0] rs2;
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logic [`NR_BITS-1:0] rs3;
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} data_t;
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logic valid;
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data_t data;
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logic ready;
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`ifndef L1_ENABLE
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logic [`ISSUE_WIDTH-1:0] ibuf_pop;
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`endif
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modport master (
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output valid,
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output data,
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input ready
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`ifndef L1_ENABLE
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, input ibuf_pop
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`endif
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);
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modport slave (
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input valid,
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input data,
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output ready
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`ifndef L1_ENABLE
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, output ibuf_pop
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`endif
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);
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endinterface
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