Blaise Tine f6f95e0c46 mutiple fixes: parallel printf, fixed cycle in cache, opencl refactored vecadd and sgemm, regen opencl kernels with hard-float, fixed vortex io bus interface, fixed dpi floats APi to support multicore mode, make vlsim multicore default, make rtlsim multi-core default, removed POCL binaries from repository, updated Makefiles to use external POCL

2020-09-19 14:45:42 -04:00

..

.gitignore

minor update

2020-06-20 18:13:15 -04:00

Makefile

mutiple fixes: parallel printf, fixed cycle in cache, opencl refactored vecadd and sgemm, regen opencl kernels with hard-float, fixed vortex io bus interface, fixed dpi floats APi to support multicore mode, make vlsim multicore default, make rtlsim multi-core default, removed POCL binaries from repository, updated Makefiles to use external POCL

2020-09-19 14:45:42 -04:00

ram.h

pipeline refactoring

2020-07-21 05:22:47 -04:00

simulator.cpp

mutiple fixes: parallel printf, fixed cycle in cache, opencl refactored vecadd and sgemm, regen opencl kernels with hard-float, fixed vortex io bus interface, fixed dpi floats APi to support multicore mode, make vlsim multicore default, make rtlsim multi-core default, removed POCL binaries from repository, updated Makefiles to use external POCL

2020-09-19 14:45:42 -04:00

simulator.h

mutiple fixes: parallel printf, fixed cycle in cache, opencl refactored vecadd and sgemm, regen opencl kernels with hard-float, fixed vortex io bus interface, fixed dpi floats APi to support multicore mode, make vlsim multicore default, make rtlsim multi-core default, removed POCL binaries from repository, updated Makefiles to use external POCL

2020-09-19 14:45:42 -04:00

testbench.cpp

updated Makefile of riscv_tests/isa

2020-08-11 13:55:36 -04:00

verilator.vlt

floating point support fixes

2020-07-28 04:19:46 -04:00