242 lines
7.8 KiB
C++
242 lines
7.8 KiB
C++
#define RISCV_CUSTOM3 0x7B
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#include <vx_spawn.h>
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#include <vx_intrinsics.h>
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#include <stdio.h>
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#include <vx_print.h>
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constexpr int DIM_M = 8;
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constexpr int DIM_N = 8;
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constexpr int DIM_K = 8;
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// #include "test_data.h"
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const float *A = reinterpret_cast<const float *>(0xa0000000UL);
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const float *B = reinterpret_cast<const float *>(0xa1000000UL);
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// FIXME: C region is uninitialized
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const float *C = reinterpret_cast<const float *>(0xa2000000UL);
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// single "substep" wmma instruction
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// use accum buffer 0 (f16-f23)
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inline void vx_wmma_acc0() {
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asm volatile (".insn r %0, 0, 0, x0, x0, x0" :: "i"(RISCV_CUSTOM3));
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}
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// single "substep" wmma instruction
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// use accum buffer 1 (f24-f31)
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inline void vx_wmma_acc1() {
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asm volatile (".insn r %0, 0, 0, x1, x0, x0" :: "i"(RISCV_CUSTOM3));
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}
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inline constexpr void map_operand_32lanes(const int tid, int &row, int &col) {
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const int tg = tid / 4;
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// A (row major)
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// Figure 7(a) in paper
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// row 0~ 3: threadgroups 0 and 2
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// row 4~ 7: threadgroups 4 and 6
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// row 8~11: threadgroups 1 and 3
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// row 12~15: threadgroups 5 and 7
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row = tid % 4;
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row += (tg * 8) % 16;
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row += (tg / 4) * 4;
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// B (column major)
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// NOTE: Matrix B mapping in Figure 7(a) is incorrect; below is the
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// corrected mapping:
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// col 0~ 3: threadgroups 0 and 1
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// col 4~ 7: threadgroups 4 and 5
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// col 8~11: threadgroups 2 and 3
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// col 12~15: threadgroups 6 and 7
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col = tid % 4;
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col += ((tg % 4) / 2) * 8;
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col += (tg / 4) * 4;
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}
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inline constexpr void map_operand_8lanes(const int tid, int &row, int &col) {
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const int tg = tid / 4;
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// A (row major)
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// row 0~ 3: threadgroup 0
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// row 4~ 7: threadgroup 1
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row = tid % 4;
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row += tg * 4;
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// B (column major)
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// col 0~ 3: threadgroup 0
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// col 4~ 7: threadgroup 1
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col = tid % 4;
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col += tg * 4;
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}
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inline constexpr void map_c_32lanes(const int tid, int &row, int &col) {
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const int tg = tid / 4;
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// C
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// Figure 7(b), left
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col = ((tg % 4) / 2) * 8;
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row = (tg * 8) % 16;
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row += (tg / 4) * 4;
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// Figure 7(b), right
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row += (tid % 4) % 2;
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col += ((tid % 4) / 2) * 2;
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}
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inline constexpr void map_c_8lanes(const int tid, int &row, int &col) {
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const int tg = tid / 4;
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// C
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col = 0;
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row = tg * 4;
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// Figure 7(b), right
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row += (tid % 4) % 2;
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col += ((tid % 4) / 2) * 2;
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}
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void vx_wmma_load() {
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int tid = vx_thread_id();
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int tg = tid / 4;
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int row = 0;
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int col = 0;
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map_operand_8lanes(tid, row, col);
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// load A
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// A is stored row-major in the memory,
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// loaded row-major into the RF.
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//
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// For 32 lanes config, each operand element is read twice by two
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// threadgroups (Sec. III-B); i.e. 8 regs * 32 lanes = 256 fp32 elements = 2
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// * (16 * 8) elements
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asm volatile("flw f0, %0" ::"m"(A[DIM_K * row + 0]));
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asm volatile("flw f1, %0" ::"m"(A[DIM_K * row + 1]));
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asm volatile("flw f2, %0" ::"m"(A[DIM_K * row + 2]));
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asm volatile("flw f3, %0" ::"m"(A[DIM_K * row + 3]));
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asm volatile("flw f4, %0" ::"m"(A[DIM_K * row + 4]));
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asm volatile("flw f5, %0" ::"m"(A[DIM_K * row + 5]));
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asm volatile("flw f6, %0" ::"m"(A[DIM_K * row + 6]));
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asm volatile("flw f7, %0" ::"m"(A[DIM_K * row + 7]));
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// load B
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// B is stored row-major in the memory,
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// loaded column-major into the RF.
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// asm volatile("flw f8 , %0" ::"m"(B[DIM_N * 0 + col]));
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// asm volatile("flw f9 , %0" ::"m"(B[DIM_N * 1 + col]));
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// asm volatile("flw f10, %0" ::"m"(B[DIM_N * 2 + col]));
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// asm volatile("flw f11, %0" ::"m"(B[DIM_N * 3 + col]));
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// asm volatile("flw f12, %0" ::"m"(B[DIM_N * 4 + col]));
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// asm volatile("flw f13, %0" ::"m"(B[DIM_N * 5 + col]));
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// asm volatile("flw f14, %0" ::"m"(B[DIM_N * 6 + col]));
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// asm volatile("flw f15, %0" ::"m"(B[DIM_N * 7 + col]));
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// B is stored column-major in the memory,
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// loaded column-major into the RF.
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asm volatile("flw f8 , %0" ::"m"(B[DIM_K * row + 0]));
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asm volatile("flw f9 , %0" ::"m"(B[DIM_K * row + 1]));
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asm volatile("flw f10, %0" ::"m"(B[DIM_K * row + 2]));
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asm volatile("flw f11, %0" ::"m"(B[DIM_K * row + 3]));
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asm volatile("flw f12, %0" ::"m"(B[DIM_K * row + 4]));
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asm volatile("flw f13, %0" ::"m"(B[DIM_K * row + 5]));
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asm volatile("flw f14, %0" ::"m"(B[DIM_K * row + 6]));
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asm volatile("flw f15, %0" ::"m"(B[DIM_K * row + 7]));
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map_c_8lanes(tid, row, col);
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// load C
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// accum buffer 0
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asm volatile("flw f16, %0" ::"m"(C[DIM_N * (row + 0) + col + 0]));
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asm volatile("flw f17, %0" ::"m"(C[DIM_N * (row + 0) + col + 1]));
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asm volatile("flw f18, %0" ::"m"(C[DIM_N * (row + 2) + col + 0]));
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asm volatile("flw f19, %0" ::"m"(C[DIM_N * (row + 2) + col + 1]));
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asm volatile("flw f20, %0" ::"m"(C[DIM_N * (row + 0) + col + 4]));
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asm volatile("flw f21, %0" ::"m"(C[DIM_N * (row + 0) + col + 5]));
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asm volatile("flw f22, %0" ::"m"(C[DIM_N * (row + 2) + col + 4]));
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asm volatile("flw f23, %0" ::"m"(C[DIM_N * (row + 2) + col + 5]));
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// accum buffer 1
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asm volatile("flw f24, %0" ::"m"(C[DIM_N * (row + 0) + col + 0]));
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asm volatile("flw f25, %0" ::"m"(C[DIM_N * (row + 0) + col + 1]));
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asm volatile("flw f26, %0" ::"m"(C[DIM_N * (row + 2) + col + 0]));
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asm volatile("flw f27, %0" ::"m"(C[DIM_N * (row + 2) + col + 1]));
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asm volatile("flw f28, %0" ::"m"(C[DIM_N * (row + 0) + col + 4]));
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asm volatile("flw f29, %0" ::"m"(C[DIM_N * (row + 0) + col + 5]));
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asm volatile("flw f30, %0" ::"m"(C[DIM_N * (row + 2) + col + 4]));
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asm volatile("flw f31, %0" ::"m"(C[DIM_N * (row + 2) + col + 5]));
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}
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// hardcoded device address for result
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float *const results = reinterpret_cast<float *>(0xc0000000UL);
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void store_wmma_result() {
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int wid = vx_warp_id();
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int tid = vx_thread_id();
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int tg = tid / 4;
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int row = 0;
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int col = 0;
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map_c_8lanes(tid, row, col);
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// store C
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float *const results_wid = results + (DIM_M * DIM_M * wid);
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// uncomment to have two accum buffers in rf
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// asm volatile("fsw f16, %0" ::"m"(results_wid[DIM_M * (row + 0) + (col + 0)]));
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// asm volatile("fsw f17, %0" ::"m"(results_wid[DIM_M * (row + 0) + (col + 1)]));
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// asm volatile("fsw f18, %0" ::"m"(results_wid[DIM_M * (row + 2) + (col + 0)]));
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// asm volatile("fsw f19, %0" ::"m"(results_wid[DIM_M * (row + 2) + (col + 1)]));
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// asm volatile("fsw f20, %0" ::"m"(results_wid[DIM_M * (row + 0) + (col + 4)]));
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// asm volatile("fsw f21, %0" ::"m"(results_wid[DIM_M * (row + 0) + (col + 5)]));
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// asm volatile("fsw f22, %0" ::"m"(results_wid[DIM_M * (row + 2) + (col + 4)]));
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// asm volatile("fsw f23, %0" ::"m"(results_wid[DIM_M * (row + 2) + (col + 5)]));
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asm volatile("fsw f24, %0" ::"m"(results_wid[DIM_M * (row + 0) + (col + 0)]));
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asm volatile("fsw f25, %0" ::"m"(results_wid[DIM_M * (row + 0) + (col + 1)]));
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asm volatile("fsw f26, %0" ::"m"(results_wid[DIM_M * (row + 2) + (col + 0)]));
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asm volatile("fsw f27, %0" ::"m"(results_wid[DIM_M * (row + 2) + (col + 1)]));
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asm volatile("fsw f28, %0" ::"m"(results_wid[DIM_M * (row + 0) + (col + 4)]));
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asm volatile("fsw f29, %0" ::"m"(results_wid[DIM_M * (row + 0) + (col + 5)]));
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asm volatile("fsw f30, %0" ::"m"(results_wid[DIM_M * (row + 2) + (col + 4)]));
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asm volatile("fsw f31, %0" ::"m"(results_wid[DIM_M * (row + 2) + (col + 5)]));
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}
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void print_wmma_result() {
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const int num_threads = vx_num_threads();
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for (int tid = 0; tid < num_threads; tid += 1) {
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for (int reg = 0; reg < 8; reg += 1) {
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vx_printf("thread %d, f%d: %x\n", tid, 16 + reg,
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*((int *)&results[tid * 8 + reg]));
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}
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}
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}
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void wmma() {
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vx_tmc(-1);
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// if (vx_warp_id() == 1) {
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// for (int i = 0; i < 100; i++) {
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// asm volatile ("nop");
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// }
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// }
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vx_wmma_load();
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// #pragma GCC unroll 100
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// for (int i = 0; i < 100; i++) {
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// vx_wmma_acc0();
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// }
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vx_wmma_acc1();
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store_wmma_result();
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// print_wmma_result();
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vx_tmc(1);
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}
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int main() {
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const int num_warps = vx_num_warps();
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// vx_wspawn(num_warps, wmma);
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wmma();
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// vx_wspawn_wait();
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return 0;
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}
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