868 lines
27 KiB
Systemverilog
868 lines
27 KiB
Systemverilog
`ifndef NOPAE
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`include "platform_if.vh"
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import local_mem_cfg_pkg::*;
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`include "afu_json_info.vh"
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`include "VX_define.vh"
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`else
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`include "vortex_afu.vh"
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/* verilator lint_off IMPORTSTAR */
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import ccip_if_pkg::*;
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import local_mem_cfg_pkg::*;
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/* verilator lint_on IMPORTSTAR */
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`endif
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`include "VX_define.vh"
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`define VX_TO_DRAM_ADDR(x) x[`VX_DRAM_ADDR_WIDTH-1:(`VX_DRAM_ADDR_WIDTH-DRAM_ADDR_WIDTH)]
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module vortex_afu #(
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parameter NUM_LOCAL_MEM_BANKS = 2
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) (
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// global signals
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input clk,
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input SoftReset,
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// IF signals between CCI and AFU
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input t_if_ccip_Rx cp2af_sRxPort,
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output t_if_ccip_Tx af2cp_sTxPort,
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// Avalon signals for local memory access
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output t_local_mem_data avs_writedata,
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input t_local_mem_data avs_readdata,
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output t_local_mem_addr avs_address,
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input logic avs_waitrequest,
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output logic avs_write,
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output logic avs_read,
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output t_local_mem_byte_mask avs_byteenable,
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output t_local_mem_burst_cnt avs_burstcount,
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input avs_readdatavalid,
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output logic [$clog2(NUM_LOCAL_MEM_BANKS)-1:0] mem_bank_select
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);
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localparam DRAM_ADDR_WIDTH = $bits(t_local_mem_addr);
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localparam DRAM_LINE_WIDTH = $bits(t_local_mem_data);
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localparam DRAM_LINE_LW = $clog2(DRAM_LINE_WIDTH);
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localparam VX_DRAM_LINE_LW = $clog2(`VX_DRAM_LINE_WIDTH);
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localparam AVS_RD_QUEUE_SIZE = 16;
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localparam CCI_RD_WINDOW_SIZE = 8;
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localparam CCI_RD_QUEUE_SIZE = 2 * CCI_RD_WINDOW_SIZE;
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localparam CCI_RW_QUEUE_SIZE = 1024;
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localparam AFU_ID_L = 16'h0002; // AFU ID Lower
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localparam AFU_ID_H = 16'h0004; // AFU ID Higher
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localparam CMD_TYPE_READ = `AFU_IMAGE_CMD_TYPE_READ;
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localparam CMD_TYPE_WRITE = `AFU_IMAGE_CMD_TYPE_WRITE;
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localparam CMD_TYPE_RUN = `AFU_IMAGE_CMD_TYPE_RUN;
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localparam CMD_TYPE_CLFLUSH = `AFU_IMAGE_CMD_TYPE_CLFLUSH;
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localparam MMIO_CSR_CMD = `AFU_IMAGE_MMIO_CSR_CMD;
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localparam MMIO_CSR_IO_ADDR = `AFU_IMAGE_MMIO_CSR_IO_ADDR;
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localparam MMIO_CSR_MEM_ADDR = `AFU_IMAGE_MMIO_CSR_MEM_ADDR;
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localparam MMIO_CSR_DATA_SIZE = `AFU_IMAGE_MMIO_CSR_DATA_SIZE;
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localparam MMIO_CSR_STATUS = `AFU_IMAGE_MMIO_CSR_STATUS;
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localparam MMIO_CSR_SCOPE_DELAY = `AFU_IMAGE_MMIO_CSR_SCOPE_DELAY;
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localparam MMIO_CSR_SCOPE_DATA = `AFU_IMAGE_MMIO_CSR_SCOPE_DATA;
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logic [127:0] afu_id = `AFU_ACCEL_UUID;
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typedef enum logic[3:0] {
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STATE_IDLE,
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STATE_READ,
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STATE_WRITE,
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STATE_START,
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STATE_RUN,
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STATE_CLFLUSH
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} state_t;
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typedef logic [$clog2(CCI_RD_WINDOW_SIZE)-1:0] t_cci_rdq_tag;
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typedef logic [$bits(t_ccip_clData) + $bits(t_cci_rdq_tag)-1:0] t_cci_rdq_data;
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state_t state;
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// Vortex ports ///////////////////////////////////////////////////////////////
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logic vx_dram_req_valid;
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logic vx_dram_req_rw;
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logic [`VX_DRAM_BYTEEN_WIDTH-1:0] vx_dram_req_byteen;
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logic [`VX_DRAM_ADDR_WIDTH-1:0] vx_dram_req_addr;
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logic [`VX_DRAM_LINE_WIDTH-1:0] vx_dram_req_data;
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logic [`VX_DRAM_TAG_WIDTH-1:0] vx_dram_req_tag;
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logic vx_dram_req_ready;
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logic vx_dram_rsp_valid;
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logic [`VX_DRAM_LINE_WIDTH-1:0] vx_dram_rsp_data;
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logic [`VX_DRAM_TAG_WIDTH-1:0] vx_dram_rsp_tag;
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logic vx_dram_rsp_ready;
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logic vx_snp_req_valid;
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logic [`VX_DRAM_ADDR_WIDTH-1:0] vx_snp_req_addr;
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logic [`VX_SNP_TAG_WIDTH-1:0] vx_snp_req_tag;
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logic vx_snp_req_ready;
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logic vx_snp_rsp_valid;
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`DEBUG_BEGIN
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logic [`VX_SNP_TAG_WIDTH-1:0] vx_snp_rsp_tag;
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`DEBUG_END
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logic vx_snp_rsp_ready;
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logic vx_reset;
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logic vx_busy;
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// AVS Queues /////////////////////////////////////////////////////////////////
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logic avs_rtq_push;
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logic avs_rtq_pop;
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`DEBUG_BEGIN
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logic avs_rtq_empty;
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logic avs_rtq_full;
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`DEBUG_BEGIN
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logic avs_rdq_push;
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logic avs_rdq_pop;
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t_local_mem_data avs_rdq_dout;
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logic avs_rdq_empty;
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`DEBUG_BEGIN
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logic avs_rdq_full;
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`DEBUG_END
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// CSR variables //////////////////////////////////////////////////////////////
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logic [2:0] csr_cmd;
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t_ccip_clAddr csr_io_addr;
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logic[DRAM_ADDR_WIDTH-1:0] csr_mem_addr;
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logic[DRAM_ADDR_WIDTH-1:0] csr_data_size;
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logic [63:0] csr_scope_delay;
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logic [63:0] csr_scope_data;
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logic csr_scope_read;
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logic csr_scope_write;
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// MMIO controller ////////////////////////////////////////////////////////////
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`IGNORE_WARNINGS_BEGIN
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t_ccip_c0_ReqMmioHdr mmio_hdr;
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`IGNORE_WARNINGS_END
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assign mmio_hdr = t_ccip_c0_ReqMmioHdr'(cp2af_sRxPort.c0.hdr);
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t_if_ccip_c2_Tx mmio_tx;
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assign af2cp_sTxPort.c2 = mmio_tx;
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assign csr_scope_delay = 64'(cp2af_sRxPort.c0.data);
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assign csr_scope_write = cp2af_sRxPort.c0.mmioWrValid && (MMIO_CSR_SCOPE_DELAY == mmio_hdr.address);
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assign csr_scope_read = cp2af_sRxPort.c0.mmioRdValid && (MMIO_CSR_SCOPE_DATA == mmio_hdr.address);
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always_ff @(posedge clk)
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begin
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if (SoftReset) begin
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mmio_tx.hdr <= 0;
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mmio_tx.data <= 0;
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mmio_tx.mmioRdValid <= 0;
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csr_cmd <= 0;
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csr_io_addr <= 0;
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csr_mem_addr <= 0;
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csr_data_size <= 0;
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end
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else begin
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csr_cmd <= 0;
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mmio_tx.mmioRdValid <= 0;
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// serve MMIO write request
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if (cp2af_sRxPort.c0.mmioWrValid)
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begin
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case (mmio_hdr.address)
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MMIO_CSR_IO_ADDR: begin
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csr_io_addr <= t_ccip_clAddr'(cp2af_sRxPort.c0.data);
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`ifdef DBG_PRINT_OPAE
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$display("%t: CSR_IO_ADDR: 0x%0h", $time, t_ccip_clAddr'(cp2af_sRxPort.c0.data));
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`endif
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end
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MMIO_CSR_MEM_ADDR: begin
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csr_mem_addr <= t_local_mem_addr'(cp2af_sRxPort.c0.data);
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`ifdef DBG_PRINT_OPAE
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$display("%t: CSR_MEM_ADDR: 0x%0h", $time, t_local_mem_addr'(cp2af_sRxPort.c0.data));
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`endif
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end
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MMIO_CSR_DATA_SIZE: begin
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csr_data_size <= $bits(csr_data_size)'(cp2af_sRxPort.c0.data);
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`ifdef DBG_PRINT_OPAE
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$display("%t: CSR_DATA_SIZE: %0d", $time, $bits(csr_data_size)'(cp2af_sRxPort.c0.data));
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`endif
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end
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MMIO_CSR_CMD: begin
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csr_cmd <= $bits(csr_cmd)'(cp2af_sRxPort.c0.data);
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`ifdef DBG_PRINT_OPAE
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$display("%t: CSR_CMD: %0d", $time, $bits(csr_cmd)'(cp2af_sRxPort.c0.data));
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`endif
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end
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default: begin
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// user-defined CSRs
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//if (mmio_hdr.addres >= MMIO_CSR_USER) begin
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// write Vortex CRS
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//end
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end
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endcase
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end
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// serve MMIO read requests
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if (cp2af_sRxPort.c0.mmioRdValid) begin
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mmio_tx.hdr.tid <= mmio_hdr.tid; // copy TID
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case (mmio_hdr.address)
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// AFU header
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16'h0000: mmio_tx.data <= {
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4'b0001, // Feature type = AFU
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8'b0, // reserved
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4'b0, // afu minor revision = 0
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7'b0, // reserved
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1'b1, // end of DFH list = 1
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24'b0, // next DFH offset = 0
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4'b0, // afu major revision = 0
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12'b0 // feature ID = 0
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};
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AFU_ID_L: mmio_tx.data <= afu_id[63:0]; // afu id low
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AFU_ID_H: mmio_tx.data <= afu_id[127:64]; // afu id hi
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16'h0006: mmio_tx.data <= 64'h0; // next AFU
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16'h0008: mmio_tx.data <= 64'h0; // reserved
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MMIO_CSR_STATUS: begin
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`ifdef DBG_PRINT_OPAE
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if (state != mmio_tx.data) begin
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$display("%t: STATUS: state=%0d", $time, state);
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end
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`endif
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mmio_tx.data <= 64'(state);
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end
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MMIO_CSR_SCOPE_DATA: begin
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mmio_tx.data <= csr_scope_data;
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`ifdef DBG_PRINT_OPAE
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$display("%t: scope: data=%0d", $time, csr_scope_data);
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`endif
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end
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default: mmio_tx.data <= 64'h0;
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endcase
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mmio_tx.mmioRdValid <= 1; // post response
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end
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end
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end
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// COMMAND FSM ////////////////////////////////////////////////////////////////
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logic cmd_read_done;
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logic cmd_write_done;
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logic cmd_clflush_done;
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logic cmd_run_done;
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always_ff @(posedge clk)
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begin
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if (SoftReset) begin
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state <= STATE_IDLE;
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vx_reset <= 0;
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end
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else begin
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vx_reset <= 0;
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case (state)
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STATE_IDLE: begin
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case (csr_cmd)
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CMD_TYPE_READ: begin
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`ifdef DBG_PRINT_OPAE
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$display("%t: STATE READ: ia=%0h da=%0h sz=%0d", $time, csr_io_addr, csr_mem_addr, csr_data_size);
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`endif
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state <= STATE_READ;
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end
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CMD_TYPE_WRITE: begin
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`ifdef DBG_PRINT_OPAE
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$display("%t: STATE WRITE: ia=%0h da=%0h sz=%0d", $time, csr_io_addr, csr_mem_addr, csr_data_size);
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`endif
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state <= STATE_WRITE;
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end
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CMD_TYPE_RUN: begin
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`ifdef DBG_PRINT_OPAE
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$display("%t: STATE START", $time);
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`endif
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vx_reset <= 1;
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state <= STATE_START;
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end
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CMD_TYPE_CLFLUSH: begin
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`ifdef DBG_PRINT_OPAE
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$display("%t: STATE CFLUSH: da=%0h sz=%0d", $time, csr_mem_addr, csr_data_size);
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`endif
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state <= STATE_CLFLUSH;
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end
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default: begin
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state <= state;
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end
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endcase
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end
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STATE_READ: begin
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if (cmd_read_done) begin
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state <= STATE_IDLE;
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end
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end
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STATE_WRITE: begin
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if (cmd_write_done) begin
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state <= STATE_IDLE;
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end
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end
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STATE_START: begin // vortex reset cycle
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state <= STATE_RUN;
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end
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STATE_RUN: begin
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if (cmd_run_done) begin
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state <= STATE_IDLE;
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end
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end
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STATE_CLFLUSH: begin
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if (cmd_clflush_done) begin
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state <= STATE_IDLE;
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end
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end
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default: begin
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state <= state;
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end
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endcase
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end
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end
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// AVS Controller /////////////////////////////////////////////////////////////
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logic vortex_enabled;
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logic cci_rdq_empty;
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t_cci_rdq_data cci_rdq_dout;
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logic cci_dram_rd_req_fire;
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logic cci_dram_wr_req_fire;
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logic vx_dram_rd_req_fire;
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`DEBUG_BEGIN
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logic vx_dram_wr_req_fire;
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`DEBUG_END
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logic vx_dram_rd_rsp_fire;
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t_local_mem_byte_mask vx_dram_req_byteen_;
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logic [$clog2(AVS_RD_QUEUE_SIZE+1)-1:0] avs_pending_reads, avs_pending_reads_next;
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logic [DRAM_LINE_LW-1:0] vx_dram_req_offset, vx_dram_rsp_offset;
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logic [DRAM_ADDR_WIDTH-1:0] cci_dram_rd_req_addr, cci_dram_wr_req_addr;
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logic cci_dram_rd_req_enable, cci_dram_wr_req_enable;
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logic vx_dram_req_enable, vx_dram_rd_req_enable, vx_dram_wr_req_enable;
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logic [DRAM_ADDR_WIDTH-1:0] cci_dram_rd_req_ctr, cci_dram_wr_req_ctr;
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assign vortex_enabled = (STATE_RUN == state) || (STATE_CLFLUSH == state);
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assign cci_dram_rd_req_enable = (state == STATE_READ)
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&& (avs_pending_reads < AVS_RD_QUEUE_SIZE)
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&& (cci_dram_rd_req_ctr != 0);
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assign cci_dram_wr_req_enable = (state == STATE_WRITE)
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&& !cci_rdq_empty
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&& (cci_dram_wr_req_ctr < csr_data_size);
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assign vx_dram_req_enable = vortex_enabled && (avs_pending_reads < AVS_RD_QUEUE_SIZE);
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assign vx_dram_rd_req_enable = vx_dram_req_enable && vx_dram_req_valid && ~vx_dram_req_rw;
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assign vx_dram_wr_req_enable = vx_dram_req_enable && vx_dram_req_valid && vx_dram_req_rw;
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assign cci_dram_rd_req_fire = cci_dram_rd_req_enable && ~avs_waitrequest;
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assign cci_dram_wr_req_fire = cci_dram_wr_req_enable && ~avs_waitrequest;
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assign vx_dram_rd_req_fire = vx_dram_rd_req_enable && ~avs_waitrequest;
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assign vx_dram_wr_req_fire = vx_dram_wr_req_enable && ~avs_waitrequest;
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assign vx_dram_rd_rsp_fire = vx_dram_rsp_valid && vx_dram_rsp_ready;
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assign avs_pending_reads_next = avs_pending_reads
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+ (((cci_dram_rd_req_fire || vx_dram_rd_req_fire) && ~avs_rdq_pop) ? 1 :
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(~(cci_dram_rd_req_fire || vx_dram_rd_req_fire) && avs_rdq_pop) ? -1 : 0);
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if (`VX_DRAM_LINE_WIDTH != DRAM_LINE_WIDTH) begin
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assign vx_dram_req_offset = ((DRAM_LINE_LW)'(vx_dram_req_addr[(DRAM_LINE_LW-VX_DRAM_LINE_LW)-1:0])) << VX_DRAM_LINE_LW;
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assign vx_dram_req_byteen_ = 64'(vx_dram_req_byteen) << (6'(vx_dram_req_addr[(DRAM_LINE_LW-VX_DRAM_LINE_LW)-1:0]) << (VX_DRAM_LINE_LW - 3));
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end else begin
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assign vx_dram_req_offset = 0;
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assign vx_dram_req_byteen_ = vx_dram_req_byteen;
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end
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always_comb
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begin
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case (state)
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CMD_TYPE_READ: avs_address = cci_dram_rd_req_addr;
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CMD_TYPE_WRITE: avs_address = cci_dram_wr_req_addr + ((DRAM_ADDR_WIDTH)'(t_cci_rdq_tag'(cci_rdq_dout)));
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default: avs_address = `VX_TO_DRAM_ADDR(vx_dram_req_addr);
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endcase
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case (state)
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CMD_TYPE_READ: avs_byteenable = 64'hffffffffffffffff;
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CMD_TYPE_WRITE: avs_byteenable = 64'hffffffffffffffff;
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default: avs_byteenable = vx_dram_req_byteen_;
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endcase
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case (state)
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CMD_TYPE_WRITE: avs_writedata = cci_rdq_dout[$bits(t_ccip_clData) + $bits(t_cci_rdq_tag)-1:$bits(t_cci_rdq_tag)];
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default: avs_writedata = (DRAM_LINE_WIDTH)'(vx_dram_req_data) << vx_dram_req_offset;
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endcase
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end
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assign avs_read = cci_dram_rd_req_enable || vx_dram_rd_req_enable;
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assign avs_write = cci_dram_wr_req_enable || vx_dram_wr_req_enable;
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assign cmd_write_done = (cci_dram_wr_req_ctr >= csr_data_size);
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always_ff @(posedge clk)
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begin
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if (SoftReset)
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begin
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mem_bank_select <= 0;
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avs_burstcount <= 1;
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cci_dram_rd_req_addr <= 0;
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cci_dram_wr_req_addr <= 0;
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cci_dram_rd_req_ctr <= 0;
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cci_dram_wr_req_ctr <= 0;
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avs_pending_reads <= 0;
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end
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else begin
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if (state == STATE_IDLE) begin
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if (CMD_TYPE_READ == csr_cmd) begin
|
|
cci_dram_rd_req_addr <= csr_mem_addr;
|
|
cci_dram_rd_req_ctr <= csr_data_size;
|
|
end
|
|
else if (CMD_TYPE_WRITE == csr_cmd) begin
|
|
cci_dram_wr_req_addr <= csr_mem_addr;
|
|
cci_dram_wr_req_ctr <= 0;
|
|
end
|
|
end
|
|
|
|
if (cci_dram_rd_req_fire) begin
|
|
cci_dram_rd_req_addr <= cci_dram_rd_req_addr + 1;
|
|
cci_dram_rd_req_ctr <= cci_dram_rd_req_ctr - 1;
|
|
`ifdef DBG_PRINT_OPAE
|
|
$display("%t: AVS Rd Req: addr=%0h, rem=%0d, pending=%0d", $time, `DRAM_TO_BYTE_ADDR(avs_address), (cci_dram_rd_req_ctr - 1), avs_pending_reads_next);
|
|
`endif
|
|
end
|
|
|
|
if (cci_dram_wr_req_fire) begin
|
|
cci_dram_wr_req_addr <= cci_dram_wr_req_addr + ((t_cci_rdq_tag'(cci_dram_wr_req_ctr) == t_cci_rdq_tag'(CCI_RD_WINDOW_SIZE-1)) ? (DRAM_ADDR_WIDTH)'(CCI_RD_WINDOW_SIZE) : 0);
|
|
cci_dram_wr_req_ctr <= cci_dram_wr_req_ctr + 1;
|
|
`ifdef DBG_PRINT_OPAE
|
|
$display("%t: AVS Wr Req: addr=%0h, data=%0h, rem=%0d", $time, `DRAM_TO_BYTE_ADDR(avs_address), avs_writedata, (cci_dram_wr_req_ctr + 1));
|
|
`endif
|
|
end
|
|
|
|
`ifdef DBG_PRINT_OPAE
|
|
if (vx_dram_rd_req_fire) begin
|
|
$display("%t: AVS Rd Req: addr=%0h, byteen=%0h, tag=%0h, pending=%0d", $time, `DRAM_TO_BYTE_ADDR(avs_address), avs_byteenable, vx_dram_req_tag, avs_pending_reads_next);
|
|
end
|
|
|
|
if (vx_dram_wr_req_fire) begin
|
|
$display("%t: AVS Wr Req: addr=%0h, byteen=%0h, tag=%0h, data=%0h", $time, `DRAM_TO_BYTE_ADDR(avs_address), avs_byteenable, vx_dram_req_tag, avs_writedata);
|
|
end
|
|
|
|
if (avs_readdatavalid) begin
|
|
$display("%t: AVS Rd Rsp: data=%0h, pending=%0d", $time, avs_readdata, avs_pending_reads_next);
|
|
end
|
|
`endif
|
|
|
|
avs_pending_reads <= avs_pending_reads_next;
|
|
end
|
|
end
|
|
|
|
// Vortex DRAM requests
|
|
|
|
assign vx_dram_req_ready = vx_dram_req_enable && !avs_waitrequest;
|
|
|
|
// Vortex DRAM fill response
|
|
|
|
assign vx_dram_rsp_valid = vortex_enabled && !avs_rdq_empty;
|
|
if (`VX_DRAM_LINE_WIDTH != DRAM_LINE_WIDTH) begin
|
|
assign vx_dram_rsp_data = (`VX_DRAM_LINE_WIDTH)'(avs_rdq_dout >> vx_dram_rsp_offset);
|
|
end else begin
|
|
assign vx_dram_rsp_data = avs_rdq_dout;
|
|
end
|
|
|
|
// AVS address read request queue /////////////////////////////////////////////
|
|
|
|
assign avs_rtq_push = vx_dram_rd_req_fire;
|
|
assign avs_rtq_pop = vx_dram_rd_rsp_fire;
|
|
|
|
VX_generic_queue #(
|
|
.DATAW(`VX_DRAM_TAG_WIDTH + DRAM_LINE_LW),
|
|
.SIZE(AVS_RD_QUEUE_SIZE)
|
|
) avs_rd_req_queue (
|
|
.clk (clk),
|
|
.reset (SoftReset),
|
|
.push (avs_rtq_push),
|
|
.data_in ({vx_dram_req_tag, vx_dram_req_offset}),
|
|
.pop (avs_rtq_pop),
|
|
.data_out ({vx_dram_rsp_tag, vx_dram_rsp_offset}),
|
|
.empty (avs_rtq_empty),
|
|
.full (avs_rtq_full),
|
|
`UNUSED_PIN (size)
|
|
);
|
|
|
|
// AVS data read response queue ///////////////////////////////////////////////
|
|
|
|
logic cci_wr_req_fire;
|
|
|
|
assign avs_rdq_push = avs_readdatavalid;
|
|
assign avs_rdq_pop = vx_dram_rd_rsp_fire || cci_wr_req_fire;
|
|
|
|
VX_generic_queue #(
|
|
.DATAW(DRAM_LINE_WIDTH),
|
|
.SIZE(AVS_RD_QUEUE_SIZE)
|
|
) avs_rd_rsp_queue (
|
|
.clk (clk),
|
|
.reset (SoftReset),
|
|
.push (avs_rdq_push),
|
|
.data_in (avs_readdata),
|
|
.pop (avs_rdq_pop),
|
|
.data_out (avs_rdq_dout),
|
|
.empty (avs_rdq_empty),
|
|
.full (avs_rdq_full),
|
|
`UNUSED_PIN (size)
|
|
);
|
|
|
|
// CCI-P Read Request ///////////////////////////////////////////////////////////
|
|
|
|
logic [$clog2(CCI_RD_QUEUE_SIZE+1)-1:0] cci_pending_reads, cci_pending_reads_next;
|
|
logic [DRAM_ADDR_WIDTH-1:0] cci_rd_req_ctr, cci_rd_req_ctr_next;
|
|
t_ccip_clAddr cci_rd_req_addr;
|
|
t_cci_rdq_tag cci_rd_rsp_ctr;
|
|
|
|
logic cci_rd_req_fire, cci_rd_rsp_fire;
|
|
logic cci_rd_req_enable, cci_rd_req_wait;
|
|
|
|
logic cci_rdq_push, cci_rdq_pop;
|
|
t_cci_rdq_data cci_rdq_din;
|
|
|
|
always_comb begin
|
|
af2cp_sTxPort.c0.hdr = t_ccip_c0_ReqMemHdr'(0);
|
|
af2cp_sTxPort.c0.hdr.address = cci_rd_req_addr;
|
|
af2cp_sTxPort.c0.hdr.mdata = t_ccip_mdata'(t_cci_rdq_tag'(cci_rd_req_ctr));
|
|
end
|
|
|
|
assign cci_rd_req_fire = af2cp_sTxPort.c0.valid && !cp2af_sRxPort.c0TxAlmFull;
|
|
assign cci_rd_rsp_fire = (STATE_WRITE == state) && cp2af_sRxPort.c0.rspValid;
|
|
|
|
assign cci_rd_req_ctr_next = cci_rd_req_ctr + (cci_rd_req_fire ? 1 : 0);
|
|
|
|
assign cci_rdq_pop = cci_dram_wr_req_fire;
|
|
assign cci_rdq_push = cci_rd_rsp_fire;
|
|
assign cci_rdq_din = {cp2af_sRxPort.c0.data, t_cci_rdq_tag'(cp2af_sRxPort.c0.hdr.mdata)};
|
|
|
|
assign cci_pending_reads_next = cci_pending_reads
|
|
+ ((cci_rd_req_fire && ~cci_rdq_pop) ? 1 :
|
|
(~cci_rd_req_fire && cci_rdq_pop) ? -1 : 0);
|
|
|
|
assign af2cp_sTxPort.c0.valid = cci_rd_req_enable && ~cci_rd_req_wait;
|
|
|
|
// Send read requests to CCI
|
|
always_ff @(posedge clk)
|
|
begin
|
|
if (SoftReset) begin
|
|
cci_rd_req_addr <= 0;
|
|
cci_rd_req_ctr <= 0;
|
|
cci_rd_rsp_ctr <= 0;
|
|
cci_pending_reads <= 0;
|
|
cci_rd_req_enable <= 0;
|
|
cci_rd_req_wait <= 0;
|
|
end
|
|
else begin
|
|
|
|
if ((STATE_IDLE == state)
|
|
&& (CMD_TYPE_WRITE == csr_cmd)) begin
|
|
cci_rd_req_addr <= csr_io_addr;
|
|
cci_rd_req_ctr <= 0;
|
|
cci_rd_rsp_ctr <= 0;
|
|
cci_pending_reads <= 0;
|
|
cci_rd_req_enable <= (csr_data_size != 0);
|
|
cci_rd_req_wait <= 0;
|
|
end
|
|
|
|
cci_rd_req_enable <= (STATE_WRITE == state)
|
|
&& (cci_rd_req_ctr_next < csr_data_size)
|
|
&& (cci_pending_reads_next < CCI_RD_QUEUE_SIZE);
|
|
|
|
if (cci_rd_req_fire) begin
|
|
cci_rd_req_addr <= cci_rd_req_addr + 1;
|
|
cci_rd_req_ctr <= cci_rd_req_ctr_next;
|
|
if (t_cci_rdq_tag'(cci_rd_req_ctr) == t_cci_rdq_tag'(CCI_RD_WINDOW_SIZE-1)) begin
|
|
cci_rd_req_wait <= 1; // end current request batch
|
|
end
|
|
`ifdef DBG_PRINT_OPAE
|
|
$display("%t: CCI Rd Req: addr=%0h, rem=%0d, pending=%0d", $time, cci_rd_req_addr, (csr_data_size - cci_rd_req_ctr_next), cci_pending_reads_next);
|
|
`endif
|
|
end
|
|
|
|
if (cci_rd_rsp_fire) begin
|
|
cci_rd_rsp_ctr <= cci_rd_rsp_ctr + 1;
|
|
if (cci_rd_rsp_ctr == t_cci_rdq_tag'(CCI_RD_WINDOW_SIZE-1)) begin
|
|
cci_rd_req_wait <= 0; // restart new request batch
|
|
end
|
|
`ifdef DBG_PRINT_OPAE
|
|
$display("%t: CCI Rd Rsp: idx=%0d, ctr=%0d", $time, t_cci_rdq_tag'(cp2af_sRxPort.c0.hdr.mdata), cci_rd_rsp_ctr);
|
|
`endif
|
|
end
|
|
|
|
if (cci_rdq_pop) begin
|
|
`ifdef DBG_PRINT_OPAE
|
|
$display("%t: CCI Rd Queue Pop: pending=%0d", $time, cci_pending_reads_next);
|
|
`endif
|
|
end
|
|
|
|
cci_pending_reads <= cci_pending_reads_next;
|
|
|
|
end
|
|
end
|
|
|
|
VX_generic_queue #(
|
|
.DATAW($bits(t_ccip_clData) + $bits(t_cci_rdq_tag)),
|
|
.SIZE(CCI_RD_QUEUE_SIZE)
|
|
) cci_rd_req_queue (
|
|
.clk (clk),
|
|
.reset (SoftReset),
|
|
.push (cci_rdq_push),
|
|
.data_in (cci_rdq_din),
|
|
.pop (cci_rdq_pop),
|
|
.data_out (cci_rdq_dout),
|
|
.empty (cci_rdq_empty),
|
|
`UNUSED_PIN (full),
|
|
`UNUSED_PIN (size)
|
|
);
|
|
|
|
// CCI-P Write Request //////////////////////////////////////////////////////////
|
|
|
|
logic [$clog2(CCI_RW_QUEUE_SIZE+1)-1:0] cci_pending_writes, cci_pending_writes_next;
|
|
logic [DRAM_ADDR_WIDTH-1:0] cci_wr_req_ctr;
|
|
t_ccip_clAddr cci_wr_req_addr;
|
|
logic cci_wr_req_enable, cci_wr_rsp_fire;
|
|
|
|
always_comb begin
|
|
af2cp_sTxPort.c1.hdr = t_ccip_c1_ReqMemHdr'(0);
|
|
af2cp_sTxPort.c1.hdr.address = cci_wr_req_addr;
|
|
af2cp_sTxPort.c1.hdr.sop = 1; // single line write mode
|
|
af2cp_sTxPort.c1.data = t_ccip_clData'(avs_rdq_dout);
|
|
end
|
|
|
|
assign cci_wr_req_fire = af2cp_sTxPort.c1.valid && !cp2af_sRxPort.c1TxAlmFull;
|
|
assign cci_wr_rsp_fire = (STATE_READ == state) && cp2af_sRxPort.c1.rspValid;
|
|
|
|
assign cci_pending_writes_next = cci_pending_writes
|
|
+ ((cci_wr_req_fire && ~cci_wr_rsp_fire) ? 1 :
|
|
(~cci_wr_req_fire && cci_wr_rsp_fire) ? -1 : 0);
|
|
|
|
assign cmd_read_done = (0 == cci_wr_req_ctr) && (0 == cci_pending_writes);
|
|
|
|
assign af2cp_sTxPort.c1.valid = cci_wr_req_enable && ~avs_rdq_empty;
|
|
|
|
// Send write requests to CCI
|
|
always_ff @(posedge clk)
|
|
begin
|
|
if (SoftReset) begin
|
|
cci_wr_req_addr <= 0;
|
|
cci_wr_req_ctr <= 0;
|
|
cci_wr_req_enable <= 0;
|
|
cci_pending_writes <= 0;
|
|
end
|
|
else begin
|
|
|
|
if ((STATE_IDLE == state)
|
|
&& (CMD_TYPE_READ == csr_cmd)) begin
|
|
cci_wr_req_addr <= csr_io_addr;
|
|
cci_wr_req_ctr <= csr_data_size;
|
|
cci_pending_writes <= 0;
|
|
end
|
|
|
|
cci_wr_req_enable <= (STATE_READ == state)
|
|
&& (cci_pending_writes_next < CCI_RW_QUEUE_SIZE);
|
|
|
|
if (cci_wr_req_fire) begin
|
|
assert(cci_wr_req_ctr != 0);
|
|
cci_wr_req_addr <= cci_wr_req_addr + 1;
|
|
cci_wr_req_ctr <= cci_wr_req_ctr - 1;
|
|
`ifdef DBG_PRINT_OPAE
|
|
$display("%t: CCI Wr Req: addr=%0h, rem=%0d, pending=%0d", $time, cci_wr_req_addr, (cci_wr_req_ctr - 1), cci_pending_writes_next);
|
|
`endif
|
|
end
|
|
|
|
`ifdef DBG_PRINT_OPAE
|
|
if (cci_wr_rsp_fire) begin
|
|
$display("%t: CCI Wr Rsp: pending=%0d", $time, cci_pending_writes_next);
|
|
end
|
|
`endif
|
|
|
|
cci_pending_writes <= cci_pending_writes_next;
|
|
end
|
|
end
|
|
|
|
// Vortex cache snooping //////////////////////////////////////////////////////
|
|
|
|
logic [`VX_DRAM_ADDR_WIDTH-1:0] snp_req_size;
|
|
logic [`VX_DRAM_ADDR_WIDTH-1:0] snp_req_baseaddr;
|
|
logic [`VX_DRAM_ADDR_WIDTH-1:0] snp_req_ctr, snp_req_ctr_next;
|
|
logic [`VX_DRAM_ADDR_WIDTH-1:0] snp_rsp_ctr, snp_rsp_ctr_next;
|
|
|
|
logic vx_snp_req_fire, vx_snp_rsp_fire;
|
|
|
|
if (`VX_DRAM_LINE_WIDTH != DRAM_LINE_WIDTH) begin
|
|
assign snp_req_baseaddr = {csr_mem_addr, (`VX_DRAM_ADDR_WIDTH - DRAM_ADDR_WIDTH)'(0)};
|
|
assign snp_req_size = {csr_data_size, (`VX_DRAM_ADDR_WIDTH - DRAM_ADDR_WIDTH)'(0)};
|
|
end else begin
|
|
assign snp_req_baseaddr = csr_mem_addr;
|
|
assign snp_req_size = csr_data_size;
|
|
end
|
|
|
|
assign vx_snp_req_fire = vx_snp_req_valid && vx_snp_req_ready;
|
|
assign vx_snp_rsp_fire = vx_snp_rsp_valid && vx_snp_rsp_ready;
|
|
|
|
assign snp_req_ctr_next = vx_snp_req_fire ? (snp_req_ctr + 1) : snp_req_ctr;
|
|
assign snp_rsp_ctr_next = vx_snp_rsp_fire ? (snp_rsp_ctr - 1) : snp_rsp_ctr;
|
|
|
|
assign cmd_clflush_done = (0 == snp_rsp_ctr);
|
|
|
|
always_ff @(posedge clk)
|
|
begin
|
|
if (SoftReset) begin
|
|
vx_snp_req_valid <= 0;
|
|
vx_snp_req_addr <= 0;
|
|
vx_snp_req_tag <= 0;
|
|
vx_snp_rsp_ready <= 0;
|
|
snp_req_ctr <= 0;
|
|
snp_rsp_ctr <= 0;
|
|
end
|
|
else begin
|
|
|
|
if ((STATE_IDLE == state)
|
|
&& (CMD_TYPE_CLFLUSH == csr_cmd)) begin
|
|
vx_snp_req_addr <= snp_req_baseaddr;
|
|
vx_snp_req_tag <= 0;
|
|
snp_req_ctr <= 0;
|
|
snp_rsp_ctr <= snp_req_size;
|
|
vx_snp_req_valid <= (snp_req_size != 0);
|
|
vx_snp_rsp_ready <= (snp_req_size != 0);
|
|
end
|
|
|
|
if ((STATE_CLFLUSH == state)
|
|
&& (snp_req_ctr_next >= snp_req_size)) begin
|
|
vx_snp_req_valid <= 0;
|
|
end
|
|
|
|
if ((STATE_CLFLUSH == state)
|
|
&& (0 == snp_rsp_ctr_next)) begin
|
|
vx_snp_rsp_ready <= 0;
|
|
end
|
|
|
|
if (vx_snp_req_fire)
|
|
begin
|
|
assert(snp_req_ctr < snp_req_size);
|
|
vx_snp_req_addr <= vx_snp_req_addr + 1;
|
|
vx_snp_req_tag <= (`VX_SNP_TAG_WIDTH)'(snp_req_ctr_next);
|
|
snp_req_ctr <= snp_req_ctr_next;
|
|
`ifdef DBG_PRINT_OPAE
|
|
$display("%t: AFU Snp Req: addr=%0h, tag=%0d, rem=%0d", $time, `DRAM_TO_BYTE_ADDR(vx_snp_req_addr), (`VX_SNP_TAG_WIDTH)'(snp_req_ctr_next), (snp_req_size - snp_req_ctr_next));
|
|
`endif
|
|
end
|
|
|
|
if ((STATE_CLFLUSH == state)
|
|
&& vx_snp_rsp_fire) begin
|
|
assert(snp_rsp_ctr != 0);
|
|
snp_rsp_ctr <= snp_rsp_ctr_next;
|
|
`ifdef DBG_PRINT_OPAE
|
|
$display("%t: AFU Snp Rsp: tag=%0d, rem=%0d", $time, vx_snp_rsp_tag, snp_rsp_ctr_next);
|
|
`endif
|
|
end
|
|
end
|
|
end
|
|
|
|
// SCOPE //////////////////////////////////////////////////////////////////////
|
|
|
|
`ifdef SCOPE
|
|
|
|
`SCOPE_SIGNALS_DECL()
|
|
|
|
VX_scope #(
|
|
.DATAW ($bits({`SCOPE_SIGNALS_LIST()})),
|
|
.BUSW (64),
|
|
.SIZE (1024)
|
|
) scope (
|
|
.clk (clk),
|
|
.reset (SoftReset),
|
|
.start (vx_reset),
|
|
.data_in ({`SCOPE_SIGNALS_LIST()}),
|
|
.bus_in (csr_scope_delay),
|
|
.bus_out (csr_scope_data),
|
|
.bus_read (csr_scope_read),
|
|
.bus_write(csr_scope_write)
|
|
);
|
|
|
|
`endif
|
|
|
|
// Vortex binding /////////////////////////////////////////////////////////////
|
|
|
|
assign cmd_run_done = !vx_busy;
|
|
|
|
Vortex_Socket #() vx_socket (
|
|
`SCOPE_SIGNALS_ATTACH(),
|
|
|
|
.clk (clk),
|
|
.reset (vx_reset),
|
|
|
|
// DRAM request
|
|
.dram_req_valid (vx_dram_req_valid),
|
|
.dram_req_rw (vx_dram_req_rw),
|
|
.dram_req_byteen (vx_dram_req_byteen),
|
|
.dram_req_addr (vx_dram_req_addr),
|
|
.dram_req_data (vx_dram_req_data),
|
|
.dram_req_tag (vx_dram_req_tag),
|
|
.dram_req_ready (vx_dram_req_ready),
|
|
|
|
// DRAM response
|
|
.dram_rsp_valid (vx_dram_rsp_valid),
|
|
.dram_rsp_data (vx_dram_rsp_data),
|
|
.dram_rsp_tag (vx_dram_rsp_tag),
|
|
.dram_rsp_ready (vx_dram_rsp_ready),
|
|
|
|
// Snoop request
|
|
.snp_req_valid (vx_snp_req_valid),
|
|
.snp_req_addr (vx_snp_req_addr),
|
|
.snp_req_tag (vx_snp_req_tag),
|
|
.snp_req_ready (vx_snp_req_ready),
|
|
|
|
// Snoop response
|
|
.snp_rsp_valid (vx_snp_rsp_valid),
|
|
.snp_rsp_tag (vx_snp_rsp_tag),
|
|
.snp_rsp_ready (vx_snp_rsp_ready),
|
|
|
|
// I/O request
|
|
`UNUSED_PIN (io_req_valid),
|
|
`UNUSED_PIN (io_req_rw),
|
|
`UNUSED_PIN (io_req_byteen),
|
|
`UNUSED_PIN (io_req_addr),
|
|
`UNUSED_PIN (io_req_data),
|
|
`UNUSED_PIN (io_req_tag),
|
|
.io_req_ready (1),
|
|
|
|
// I/O response
|
|
.io_rsp_valid (0),
|
|
.io_rsp_data (0),
|
|
.io_rsp_tag (0),
|
|
`UNUSED_PIN (io_rsp_ready),
|
|
|
|
// status
|
|
.busy (vx_busy),
|
|
`UNUSED_PIN (ebreak)
|
|
);
|
|
|
|
endmodule |