271 lines
10 KiB
Verilog
271 lines
10 KiB
Verilog
`include "VX_define.vh"
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module Vortex #(
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parameter CORE_ID = 0
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) (
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`SCOPE_SIGNALS_IO(),
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// Clock
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input wire clk,
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input wire reset,
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// DRAM Dcache request
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output wire D_dram_req_valid,
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output wire D_dram_req_rw,
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output wire [`DDRAM_BYTEEN_WIDTH-1:0] D_dram_req_byteen,
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output wire [`DDRAM_ADDR_WIDTH-1:0] D_dram_req_addr,
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output wire [`DDRAM_LINE_WIDTH-1:0] D_dram_req_data,
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output wire [`DDRAM_TAG_WIDTH-1:0] D_dram_req_tag,
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input wire D_dram_req_ready,
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// DRAM Dcache reponse
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input wire D_dram_rsp_valid,
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input wire [`DDRAM_LINE_WIDTH-1:0] D_dram_rsp_data,
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input wire [`DDRAM_TAG_WIDTH-1:0] D_dram_rsp_tag,
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output wire D_dram_rsp_ready,
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// DRAM Icache request
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output wire I_dram_req_valid,
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output wire I_dram_req_rw,
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output wire [`IDRAM_BYTEEN_WIDTH-1:0] I_dram_req_byteen,
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output wire [`IDRAM_ADDR_WIDTH-1:0] I_dram_req_addr,
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output wire [`IDRAM_LINE_WIDTH-1:0] I_dram_req_data,
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output wire [`IDRAM_TAG_WIDTH-1:0] I_dram_req_tag,
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input wire I_dram_req_ready,
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// DRAM Icache response
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input wire I_dram_rsp_valid,
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input wire [`IDRAM_LINE_WIDTH-1:0] I_dram_rsp_data,
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input wire [`IDRAM_TAG_WIDTH-1:0] I_dram_rsp_tag,
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output wire I_dram_rsp_ready,
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// Snoop request
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input wire snp_req_valid,
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input wire [`DDRAM_ADDR_WIDTH-1:0] snp_req_addr,
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input wire [`DSNP_TAG_WIDTH-1:0] snp_req_tag,
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output wire snp_req_ready,
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output wire snp_rsp_valid,
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output wire [`DSNP_TAG_WIDTH-1:0] snp_rsp_tag,
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input wire snp_rsp_ready,
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// I/O request
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output wire io_req_valid,
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output wire io_req_rw,
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output wire[3:0] io_req_byteen,
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output wire[29:0] io_req_addr,
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output wire[31:0] io_req_data,
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output wire[`DCORE_TAG_WIDTH-1:0] io_req_tag,
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input wire io_req_ready,
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// I/O response
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input wire io_rsp_valid,
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input wire[31:0] io_rsp_data,
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input wire[`DCORE_TAG_WIDTH-1:0] io_rsp_tag,
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output wire io_rsp_ready,
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// Status
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output wire busy,
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output wire ebreak
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);
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// Dcache Interfaces
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VX_cache_dram_req_if #(
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.DRAM_LINE_WIDTH(`DDRAM_LINE_WIDTH),
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.DRAM_ADDR_WIDTH(`DDRAM_ADDR_WIDTH),
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.DRAM_TAG_WIDTH(`DDRAM_TAG_WIDTH)
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) dcache_dram_req_if();
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VX_cache_dram_rsp_if #(
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.DRAM_LINE_WIDTH(`DDRAM_LINE_WIDTH),
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.DRAM_TAG_WIDTH(`DDRAM_TAG_WIDTH)
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) dcache_dram_rsp_if();
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assign D_dram_req_valid = dcache_dram_req_if.dram_req_valid;
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assign D_dram_req_rw = dcache_dram_req_if.dram_req_rw;
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assign D_dram_req_byteen= dcache_dram_req_if.dram_req_byteen;
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assign D_dram_req_addr = dcache_dram_req_if.dram_req_addr;
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assign D_dram_req_data = dcache_dram_req_if.dram_req_data;
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assign D_dram_req_tag = dcache_dram_req_if.dram_req_tag;
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assign dcache_dram_req_if.dram_req_ready = D_dram_req_ready;
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assign dcache_dram_rsp_if.dram_rsp_valid = D_dram_rsp_valid;
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assign dcache_dram_rsp_if.dram_rsp_data = D_dram_rsp_data;
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assign dcache_dram_rsp_if.dram_rsp_tag = D_dram_rsp_tag;
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assign D_dram_rsp_ready = dcache_dram_rsp_if.dram_rsp_ready;
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VX_cache_core_req_if #(
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.NUM_REQUESTS(`DNUM_REQUESTS),
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.WORD_SIZE(`DWORD_SIZE),
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.CORE_TAG_WIDTH(`DCORE_TAG_WIDTH),
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.CORE_TAG_ID_BITS(`DCORE_TAG_ID_BITS)
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) core_dcache_req_if(),arb_dcache_req_if(), arb_io_req_if();
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VX_cache_core_rsp_if #(
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.NUM_REQUESTS(`DNUM_REQUESTS),
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.WORD_SIZE(`DWORD_SIZE),
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.CORE_TAG_WIDTH(`DCORE_TAG_WIDTH),
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.CORE_TAG_ID_BITS(`DCORE_TAG_ID_BITS)
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) core_dcache_rsp_if(), arb_dcache_rsp_if(), arb_io_rsp_if();
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assign io_req_valid = arb_io_req_if.core_req_valid[0];
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assign io_req_rw = arb_io_req_if.core_req_rw[0];
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assign io_req_byteen = arb_io_req_if.core_req_byteen[0];
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assign io_req_addr = arb_io_req_if.core_req_addr[0];
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assign io_req_data = arb_io_req_if.core_req_data[0];
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assign io_req_tag = arb_io_req_if.core_req_tag[0];
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assign arb_io_req_if.core_req_ready = io_req_ready;
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assign arb_io_rsp_if.core_rsp_valid = {{(`NUM_THREADS-1){1'b0}}, io_rsp_valid};
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assign arb_io_rsp_if.core_rsp_data[0] = io_rsp_data;
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assign arb_io_rsp_if.core_rsp_tag = io_rsp_tag;
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assign io_rsp_ready = arb_io_rsp_if.core_rsp_ready;
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// Icache interfaces
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VX_cache_dram_req_if #(
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.DRAM_LINE_WIDTH(`IDRAM_LINE_WIDTH),
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.DRAM_ADDR_WIDTH(`IDRAM_ADDR_WIDTH),
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.DRAM_TAG_WIDTH(`IDRAM_TAG_WIDTH)
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) icache_dram_req_if();
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VX_cache_dram_rsp_if #(
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.DRAM_LINE_WIDTH(`IDRAM_LINE_WIDTH),
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.DRAM_TAG_WIDTH(`IDRAM_TAG_WIDTH)
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) icache_dram_rsp_if();
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assign I_dram_req_valid = icache_dram_req_if.dram_req_valid;
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assign I_dram_req_rw = icache_dram_req_if.dram_req_rw;
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assign I_dram_req_byteen= icache_dram_req_if.dram_req_byteen;
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assign I_dram_req_addr = icache_dram_req_if.dram_req_addr;
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assign I_dram_req_data = icache_dram_req_if.dram_req_data;
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assign I_dram_req_tag = icache_dram_req_if.dram_req_tag;
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assign icache_dram_req_if.dram_req_ready = I_dram_req_ready;
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assign icache_dram_rsp_if.dram_rsp_valid = I_dram_rsp_valid;
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assign icache_dram_rsp_if.dram_rsp_data = I_dram_rsp_data;
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assign icache_dram_rsp_if.dram_rsp_tag = I_dram_rsp_tag;
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assign I_dram_rsp_ready = icache_dram_rsp_if.dram_rsp_ready;
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VX_cache_core_req_if #(
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.NUM_REQUESTS(`INUM_REQUESTS),
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.WORD_SIZE(`IWORD_SIZE),
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.CORE_TAG_WIDTH(`DCORE_TAG_WIDTH),
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.CORE_TAG_ID_BITS(`DCORE_TAG_ID_BITS)
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) core_icache_req_if();
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VX_cache_core_rsp_if #(
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.NUM_REQUESTS(`INUM_REQUESTS),
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.WORD_SIZE(`IWORD_SIZE),
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.CORE_TAG_WIDTH(`DCORE_TAG_WIDTH),
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.CORE_TAG_ID_BITS(`DCORE_TAG_ID_BITS)
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) core_icache_rsp_if();
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// Vortex pipeline
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VX_pipeline #(
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.CORE_ID(CORE_ID)
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) pipeline (
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`SCOPE_SIGNALS_ATTACH(),
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.clk(clk),
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.reset(reset),
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// Dcache core request
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.dcache_req_valid (core_dcache_req_if.core_req_valid),
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.dcache_req_rw (core_dcache_req_if.core_req_rw),
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.dcache_req_byteen (core_dcache_req_if.core_req_byteen),
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.dcache_req_addr (core_dcache_req_if.core_req_addr),
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.dcache_req_data (core_dcache_req_if.core_req_data),
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.dcache_req_tag (core_dcache_req_if.core_req_tag),
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.dcache_req_ready (core_dcache_req_if.core_req_ready),
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// Dcache core reponse
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.dcache_rsp_valid (core_dcache_rsp_if.core_rsp_valid),
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.dcache_rsp_data (core_dcache_rsp_if.core_rsp_data),
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.dcache_rsp_tag (core_dcache_rsp_if.core_rsp_tag),
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.dcache_rsp_ready (core_dcache_rsp_if.core_rsp_ready),
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// Dcache core request
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.icache_req_valid (core_icache_req_if.core_req_valid),
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.icache_req_rw (core_icache_req_if.core_req_rw),
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.icache_req_byteen (core_icache_req_if.core_req_byteen),
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.icache_req_addr (core_icache_req_if.core_req_addr),
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.icache_req_data (core_icache_req_if.core_req_data),
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.icache_req_tag (core_icache_req_if.core_req_tag),
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.icache_req_ready (core_icache_req_if.core_req_ready),
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// Dcache core reponse
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.icache_rsp_valid (core_icache_rsp_if.core_rsp_valid),
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.icache_rsp_data (core_icache_rsp_if.core_rsp_data),
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.icache_rsp_tag (core_icache_rsp_if.core_rsp_tag),
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.icache_rsp_ready (core_icache_rsp_if.core_rsp_ready),
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// Status
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.busy(busy),
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.ebreak(ebreak)
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);
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// Cache snooping
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VX_cache_snp_req_if #(
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.DRAM_ADDR_WIDTH(`DDRAM_ADDR_WIDTH),
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.SNP_TAG_WIDTH(`DSNP_TAG_WIDTH)
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) dcache_snp_req_if();
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VX_cache_snp_rsp_if #(
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.SNP_TAG_WIDTH(`DSNP_TAG_WIDTH)
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) dcache_snp_rsp_if();
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assign dcache_snp_req_if.snp_req_valid = snp_req_valid;
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assign dcache_snp_req_if.snp_req_addr = snp_req_addr;
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assign dcache_snp_req_if.snp_req_tag = snp_req_tag;
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assign snp_req_ready = dcache_snp_req_if.snp_req_ready;
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assign snp_rsp_valid = dcache_snp_rsp_if.snp_rsp_valid;
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assign snp_rsp_tag = dcache_snp_rsp_if.snp_rsp_tag;
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assign dcache_snp_rsp_if.snp_rsp_ready = snp_rsp_ready;
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VX_dmem_ctrl #(
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.CORE_ID(CORE_ID)
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) dmem_ctrl (
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.clk (clk),
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.reset (reset),
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// Core <-> Dcache
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.core_dcache_req_if (arb_dcache_req_if),
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.core_dcache_rsp_if (arb_dcache_rsp_if),
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// Dram <-> Dcache
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.dcache_dram_req_if (dcache_dram_req_if),
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.dcache_dram_rsp_if (dcache_dram_rsp_if),
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.dcache_snp_req_if (dcache_snp_req_if),
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.dcache_snp_rsp_if (dcache_snp_rsp_if),
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// Core <-> Icache
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.core_icache_req_if (core_icache_req_if),
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.core_icache_rsp_if (core_icache_rsp_if),
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// Dram <-> Icache
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.icache_dram_req_if (icache_dram_req_if),
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.icache_dram_rsp_if (icache_dram_rsp_if)
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);
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// use "case equality" to handle uninitialized address value
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wire io_select = (({core_dcache_req_if.core_req_addr[0], 2'b0} >= `IO_BUS_BASE_ADDR) === 1'b1);
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VX_dcache_io_arb dcache_io_arb (
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.io_select (io_select),
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.core_req_if (core_dcache_req_if),
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.core_dcache_req_if (arb_dcache_req_if),
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.core_io_req_if (arb_io_req_if),
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.core_dcache_rsp_if (arb_dcache_rsp_if),
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.core_io_rsp_if (arb_io_rsp_if),
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.core_rsp_if (core_dcache_rsp_if)
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);
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endmodule // Vortex
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