87 lines
1.7 KiB
Verilog
87 lines
1.7 KiB
Verilog
module VX_scope #(
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parameter DATAW = 64,
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parameter BUSW = 64,
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parameter SIZE = 1024
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) (
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input wire clk,
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input wire reset,
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input wire start,
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input wire [DATAW-1:0] data_in,
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input wire [BUSW-1:0] bus_in,
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output wire [BUSW-1:0] bus_out,
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input wire bus_write,
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input wire bus_read
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);
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reg [DATAW-1:0] mem [SIZE-1:0];
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reg [`CLOG2(SIZE)-1:0] raddr, waddr;
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reg started, running, done;
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reg [BUSW-1:0] delay_cntr;
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reg data_valid, data_end;
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reg [`LOG2UP(DATAW)-1:0] read_offset;
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wire [BUSW-3:0] data_part;
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always @(posedge clk) begin
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if (reset) begin
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raddr <= 0;
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waddr <= 0;
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started <= 0;
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running <= 0;
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done <= 0;
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delay_cntr <= 0;
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read_offset <= 0;
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end else begin
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if (bus_write) begin
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delay_cntr <= bus_in;
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end
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if (start) begin
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started <= 1;
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end
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if (start || started) begin
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if (0 == delay_cntr) begin
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running <= 1;
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end else begin
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delay_cntr <= delay_cntr - 1;
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end
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end
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if (running && !done) begin
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mem[waddr] <= data_in;
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waddr <= waddr + 1;
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if (waddr == $bits(waddr)'(SIZE-1)) begin
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done <= 1;
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end
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end
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if (bus_read) begin
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if (DATAW > (BUSW-2)) begin
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if (read_offset < $bits(read_offset)'(DATAW-(BUSW-2))) begin
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read_offset <= read_offset + $bits(read_offset)'(BUSW-2);
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end else begin
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read_offset <= 0;
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raddr <= raddr + 1;
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end
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end else begin
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raddr <= raddr + 1;
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end
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end
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end
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end
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assign data_valid = (waddr != 0) && (raddr <= waddr);
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assign data_end = (0 == read_offset) || (raddr == waddr);
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assign data_part = (BUSW-2)'(mem[raddr] >> read_offset);
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assign bus_out = {data_valid, data_end, data_part};
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endmodule |