49 lines
1.4 KiB
Verilog
49 lines
1.4 KiB
Verilog
`include "VX_platform.vh"
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module VX_bypass_buffer #(
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parameter DATAW = 1,
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parameter PASSTHRU = 0
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) (
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input wire clk,
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input wire reset,
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input wire valid_in,
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output wire ready_in,
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input wire [DATAW-1:0] data_in,
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output wire [DATAW-1:0] data_out,
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input wire ready_out,
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output wire valid_out
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);
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if (PASSTHRU) begin
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`UNUSED_VAR (clk)
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`UNUSED_VAR (reset)
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assign ready_in = ready_out;
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assign valid_out = valid_in;
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assign data_out = data_in;
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end else begin
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reg [DATAW-1:0] buffer;
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reg buffer_valid;
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always @(posedge clk) begin
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if (reset) begin
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buffer_valid <= 0;
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end else begin
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if (ready_out) begin
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buffer_valid <= 0;
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end
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if (valid_in && ~ready_out) begin
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assert(!buffer_valid);
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buffer_valid <= 1;
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end
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end
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if (valid_in && ~ready_out) begin
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buffer <= data_in;
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end
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end
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assign ready_in = ready_out || !buffer_valid;
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assign data_out = buffer_valid ? buffer : data_in;
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assign valid_out = valid_in || buffer_valid;
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end
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endmodule |