60 lines
1.7 KiB
Verilog
60 lines
1.7 KiB
Verilog
`include "VX_platform.vh"
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`TRACING_OFF
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module VX_fair_arbiter #(
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parameter NUM_REQS = 1,
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parameter LOCK_ENABLE = 0,
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parameter LOG_NUM_REQS = $clog2(NUM_REQS)
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) (
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input wire clk,
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input wire reset,
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input wire enable,
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input wire [NUM_REQS-1:0] requests,
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output wire [LOG_NUM_REQS-1:0] grant_index,
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output wire [NUM_REQS-1:0] grant_onehot,
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output wire grant_valid
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);
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if (NUM_REQS == 1) begin
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`UNUSED_VAR (clk)
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`UNUSED_VAR (reset)
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assign grant_index = 0;
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assign grant_onehot = requests;
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assign grant_valid = requests[0];
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end else begin
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reg [NUM_REQS-1:0] buffer;
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reg use_buffer;
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wire [NUM_REQS-1:0] requests_qual = use_buffer ? buffer : requests;
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wire [NUM_REQS-1:0] buffer_n = requests_qual & ~grant_onehot;
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always @(posedge clk) begin
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if (reset) begin
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use_buffer <= 0;
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end else if (!LOCK_ENABLE || enable) begin
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use_buffer <= (buffer_n != 0);
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end
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if (!LOCK_ENABLE || enable) begin
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buffer <= buffer_n;
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end
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end
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VX_fixed_arbiter #(
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.NUM_REQS (NUM_REQS),
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.LOCK_ENABLE (LOCK_ENABLE)
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) fixed_arbiter (
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.clk (clk),
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.reset (reset),
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.enable (enable),
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.requests (requests_qual),
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.grant_index (grant_index),
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.grant_onehot (grant_onehot),
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.grant_valid (grant_valid)
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);
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end
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endmodule
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`TRACING_ON |