169 lines
5.8 KiB
Systemverilog
169 lines
5.8 KiB
Systemverilog
// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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`include "VX_cache_define.vh"
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module VX_cache_top import VX_gpu_pkg::*; #(
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parameter `STRING INSTANCE_ID = "",
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// Number of Word requests per cycle
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parameter NUM_REQS = 4,
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// Size of cache in bytes
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parameter CACHE_SIZE = 16384,
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// Size of line inside a bank in bytes
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parameter LINE_SIZE = 64,
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// Number of banks
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parameter NUM_BANKS = 4,
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// Number of associative ways
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parameter NUM_WAYS = 4,
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// Size of a word in bytes
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parameter WORD_SIZE = 4,
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// Core Response Queue Size
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parameter CRSQ_SIZE = 2,
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// Miss Reserv Queue Knob
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parameter MSHR_SIZE = 16,
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// Memory Response Queue Size
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parameter MRSQ_SIZE = 0,
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// Memory Request Queue Size
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parameter MREQ_SIZE = 4,
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// Enable cache writeable
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parameter WRITE_ENABLE = 1,
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// Request debug identifier
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parameter UUID_WIDTH = 0,
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// core request tag size
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parameter TAG_WIDTH = 16,
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// Core response output register
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parameter CORE_OUT_REG = 2,
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// Memory request output register
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parameter MEM_OUT_REG = 2,
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parameter MEM_TAG_WIDTH = `CLOG2(MSHR_SIZE) + `CLOG2(NUM_BANKS)
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) (
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input wire clk,
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input wire reset,
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// PERF
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`ifdef PERF_ENABLE
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output cache_perf_t cache_perf,
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`endif
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// Core request
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input wire [NUM_REQS-1:0] core_req_valid,
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input wire [NUM_REQS-1:0] core_req_rw,
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input wire [NUM_REQS-1:0][WORD_SIZE-1:0] core_req_byteen,
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input wire [NUM_REQS-1:0][`CS_WORD_ADDR_WIDTH-1:0] core_req_addr,
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input wire [NUM_REQS-1:0][`CS_WORD_WIDTH-1:0] core_req_data,
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input wire [NUM_REQS-1:0][TAG_WIDTH-1:0] core_req_tag,
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output wire [NUM_REQS-1:0] core_req_ready,
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// Core response
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output wire [NUM_REQS-1:0] core_rsp_valid,
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output wire [NUM_REQS-1:0][`CS_WORD_WIDTH-1:0] core_rsp_data,
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output wire [NUM_REQS-1:0][TAG_WIDTH-1:0] core_rsp_tag,
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input wire [NUM_REQS-1:0] core_rsp_ready,
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// Memory request
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output wire mem_req_valid,
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output wire mem_req_rw,
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output wire [LINE_SIZE-1:0] mem_req_byteen,
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output wire [`CS_MEM_ADDR_WIDTH-1:0] mem_req_addr,
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output wire [`CS_LINE_WIDTH-1:0] mem_req_data,
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output wire [MEM_TAG_WIDTH-1:0] mem_req_tag,
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input wire mem_req_ready,
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// Memory response
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input wire mem_rsp_valid,
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input wire [`CS_LINE_WIDTH-1:0] mem_rsp_data,
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input wire [MEM_TAG_WIDTH-1:0] mem_rsp_tag,
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output wire mem_rsp_ready
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);
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VX_mem_bus_if #(
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.DATA_SIZE (WORD_SIZE),
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.TAG_WIDTH (TAG_WIDTH)
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) core_bus_if[NUM_REQS]();
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VX_mem_bus_if #(
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.DATA_SIZE (LINE_SIZE),
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.TAG_WIDTH (MEM_TAG_WIDTH)
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) mem_bus_if();
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// Core request
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for (genvar i = 0; i < NUM_REQS; ++i) begin
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assign core_bus_if[i].req_valid = core_req_valid[i];
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assign core_bus_if[i].req_data.rw = core_req_rw[i];
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assign core_bus_if[i].req_data.byteen = core_req_byteen[i];
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assign core_bus_if[i].req_data.addr = core_req_addr[i];
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assign core_bus_if[i].req_data.data = core_req_data[i];
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assign core_bus_if[i].req_data.tag = core_req_tag[i];
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assign core_req_ready[i] = core_bus_if[i].req_ready;
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end
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// Core response
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for (genvar i = 0; i < NUM_REQS; ++i) begin
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assign core_rsp_valid[i] = core_bus_if[i].rsp_valid;
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assign core_rsp_data[i] = core_bus_if[i].rsp_data.data;
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assign core_rsp_tag[i] = core_bus_if[i].rsp_data.tag;
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assign core_bus_if[i].rsp_ready = core_rsp_ready[i];
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end
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// Memory request
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assign mem_req_valid = mem_bus_if.req_valid;
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assign mem_req_rw = mem_bus_if.req_data.rw;
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assign mem_req_byteen = mem_bus_if.req_data.byteen;
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assign mem_req_addr = mem_bus_if.req_data.addr;
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assign mem_req_data = mem_bus_if.req_data.data;
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assign mem_req_tag = mem_bus_if.req_data.tag;
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assign mem_bus_if.req_ready = mem_req_ready;
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// Memory response
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assign mem_bus_if.rsp_valid = mem_rsp_valid;
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assign mem_bus_if.rsp_data.data = mem_rsp_data;
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assign mem_bus_if.rsp_data.tag = mem_rsp_tag;
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assign mem_rsp_ready = mem_bus_if.rsp_ready;
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VX_cache #(
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.INSTANCE_ID (INSTANCE_ID),
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.CACHE_SIZE (CACHE_SIZE),
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.LINE_SIZE (LINE_SIZE),
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.NUM_BANKS (NUM_BANKS),
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.NUM_WAYS (NUM_WAYS),
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.WORD_SIZE (WORD_SIZE),
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.NUM_REQS (NUM_REQS),
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.CRSQ_SIZE (CRSQ_SIZE),
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.MSHR_SIZE (MSHR_SIZE),
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.MRSQ_SIZE (MRSQ_SIZE),
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.MREQ_SIZE (MREQ_SIZE),
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.TAG_WIDTH (TAG_WIDTH),
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.UUID_WIDTH (UUID_WIDTH),
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.WRITE_ENABLE (WRITE_ENABLE),
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.CORE_OUT_REG (CORE_OUT_REG),
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.MEM_OUT_REG (MEM_OUT_REG)
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) cache (
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`ifdef PERF_ENABLE
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.cache_perf (cache_perf),
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`endif
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.clk (clk),
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.reset (reset),
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.core_bus_if (core_bus_if),
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.mem_bus_if (mem_bus_if)
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);
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endmodule
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