176 lines
6.5 KiB
Verilog
176 lines
6.5 KiB
Verilog
`include "VX_define.vh"
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module VX_avs_wrapper #(
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parameter AVS_DATA_WIDTH = 1,
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parameter AVS_ADDR_WIDTH = 1,
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parameter AVS_BURST_WIDTH = 1,
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parameter AVS_BANKS = 1,
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parameter REQ_TAG_WIDTH = 1,
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parameter RD_QUEUE_SIZE = 1,
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parameter AVS_BYTEENW = (AVS_DATA_WIDTH / 8),
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parameter RD_QUEUE_ADDR_WIDTH = $clog2(RD_QUEUE_SIZE+1)
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) (
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input wire clk,
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input wire reset,
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// Memory request
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input wire mem_req_valid,
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input wire mem_req_rw,
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input wire [AVS_BYTEENW-1:0] mem_req_byteen,
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input wire [AVS_ADDR_WIDTH-1:0] mem_req_addr,
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input wire [AVS_DATA_WIDTH-1:0] mem_req_data,
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input wire [REQ_TAG_WIDTH-1:0] mem_req_tag,
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output wire mem_req_ready,
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// Memory response
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output wire mem_rsp_valid,
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output wire [AVS_DATA_WIDTH-1:0] mem_rsp_data,
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output wire [REQ_TAG_WIDTH-1:0] mem_rsp_tag,
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input wire mem_rsp_ready,
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// AVS bus
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output wire [AVS_DATA_WIDTH-1:0] avs_writedata [AVS_BANKS],
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input wire [AVS_DATA_WIDTH-1:0] avs_readdata [AVS_BANKS],
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output wire [AVS_ADDR_WIDTH-1:0] avs_address [AVS_BANKS],
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input wire avs_waitrequest [AVS_BANKS],
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output wire avs_write [AVS_BANKS],
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output wire avs_read [AVS_BANKS],
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output wire [AVS_BYTEENW-1:0] avs_byteenable [AVS_BANKS],
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output wire [AVS_BURST_WIDTH-1:0] avs_burstcount [AVS_BANKS],
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input avs_readdatavalid [AVS_BANKS]
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);
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localparam BANK_ADDRW = `LOG2UP(AVS_BANKS);
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// Requests handling
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wire [AVS_BANKS-1:0] avs_reqq_push, avs_reqq_pop, avs_reqq_ready;
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wire [AVS_BANKS-1:0][REQ_TAG_WIDTH-1:0] avs_reqq_tag_out;
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wire [AVS_BANKS-1:0] req_queue_going_full;
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wire [AVS_BANKS-1:0][RD_QUEUE_ADDR_WIDTH-1:0] req_queue_size;
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wire [BANK_ADDRW-1:0] req_bank_sel;
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if (AVS_BANKS >= 2) begin
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assign req_bank_sel = mem_req_addr[BANK_ADDRW-1:0];
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end else begin
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assign req_bank_sel = 0;
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end
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for (genvar i = 0; i < AVS_BANKS; i++) begin
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assign avs_reqq_ready[i] = !req_queue_going_full[i] && !avs_waitrequest[i];
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assign avs_reqq_push[i] = mem_req_valid && !mem_req_rw && avs_reqq_ready[i] && (req_bank_sel == i);
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end
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for (genvar i = 0; i < AVS_BANKS; i++) begin
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VX_pending_size #(
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.SIZE (RD_QUEUE_SIZE)
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) pending_size (
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.clk (clk),
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.reset (reset),
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.incr (avs_reqq_push[i]),
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.decr (avs_reqq_pop[i]),
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.full (req_queue_going_full[i]),
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.size (req_queue_size[i]),
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`UNUSED_PIN (empty)
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);
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`UNUSED_VAR (req_queue_size)
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VX_fifo_queue #(
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.DATAW (REQ_TAG_WIDTH),
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.SIZE (RD_QUEUE_SIZE)
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) rd_req_queue (
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.clk (clk),
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.reset (reset),
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.push (avs_reqq_push[i]),
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.pop (avs_reqq_pop[i]),
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.data_in (mem_req_tag),
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.data_out (avs_reqq_tag_out[i]),
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`UNUSED_PIN (empty),
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`UNUSED_PIN (full),
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`UNUSED_PIN (alm_empty),
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`UNUSED_PIN (alm_full),
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`UNUSED_PIN (size)
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);
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end
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for (genvar i = 0; i < AVS_BANKS; i++) begin
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assign avs_read[i] = mem_req_valid && !mem_req_rw && !req_queue_going_full[i] && (req_bank_sel == i);
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assign avs_write[i] = mem_req_valid && mem_req_rw && !req_queue_going_full[i] && (req_bank_sel == i);
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assign avs_address[i] = mem_req_addr;
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assign avs_byteenable[i] = mem_req_byteen;
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assign avs_writedata[i] = mem_req_data;
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assign avs_burstcount[i] = AVS_BURST_WIDTH'(1);
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end
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if (AVS_BANKS >= 2) begin
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assign mem_req_ready = avs_reqq_ready[req_bank_sel];
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end else begin
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assign mem_req_ready = avs_reqq_ready;
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end
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// Responses handling
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wire [AVS_BANKS-1:0] rsp_arb_valid_in;
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wire [AVS_BANKS-1:0][AVS_DATA_WIDTH+REQ_TAG_WIDTH-1:0] rsp_arb_data_in;
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wire [AVS_BANKS-1:0] rsp_arb_ready_in;
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wire [AVS_BANKS-1:0][AVS_DATA_WIDTH-1:0] avs_rspq_data_out;
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wire [AVS_BANKS-1:0] avs_rspq_empty;
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for (genvar i = 0; i < AVS_BANKS; i++) begin
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VX_fifo_queue #(
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.DATAW (AVS_DATA_WIDTH),
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.SIZE (RD_QUEUE_SIZE)
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) rd_rsp_queue (
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.clk (clk),
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.reset (reset),
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.push (avs_readdatavalid[i]),
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.pop (avs_reqq_pop[i]),
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.data_in (avs_readdata[i]),
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.data_out (avs_rspq_data_out[i]),
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.empty (avs_rspq_empty[i]),
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`UNUSED_PIN (full),
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`UNUSED_PIN (alm_empty),
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`UNUSED_PIN (alm_full),
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`UNUSED_PIN (size)
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);
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end
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for (genvar i = 0; i < AVS_BANKS; i++) begin
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assign rsp_arb_valid_in[i] = !avs_rspq_empty[i];
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assign rsp_arb_data_in[i] = {avs_rspq_data_out[i], avs_reqq_tag_out[i]};
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assign avs_reqq_pop[i] = rsp_arb_valid_in[i] && rsp_arb_ready_in[i];
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end
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VX_stream_arbiter #(
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.NUM_REQS (AVS_BANKS),
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.DATAW (AVS_DATA_WIDTH + REQ_TAG_WIDTH),
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.TYPE ("R")
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) rsp_arb (
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.clk (clk),
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.reset (reset),
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.valid_in (rsp_arb_valid_in),
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.data_in (rsp_arb_data_in),
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.ready_in (rsp_arb_ready_in),
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.valid_out (mem_rsp_valid),
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.data_out ({mem_rsp_data, mem_rsp_tag}),
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.ready_out (mem_rsp_ready)
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);
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`ifdef DBG_PRINT_AVS
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always @(posedge clk) begin
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if (mem_req_valid && mem_req_ready) begin
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if (mem_req_rw) begin
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dpi_trace("%d: AVS Wr Req: addr=%0h, byteen=%0h, tag=%0h, data=%0h\n", $time, `TO_FULL_ADDR(mem_req_addr), mem_req_byteen, mem_req_tag, mem_req_data);
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end else begin
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dpi_trace("%d: AVS Rd Req: addr=%0h, byteen=%0h, tag=%0h, pending=%0d\n", $time, `TO_FULL_ADDR(mem_req_addr), mem_req_byteen, mem_req_tag, req_queue_size);
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end
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end
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if (mem_rsp_valid && mem_rsp_ready) begin
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dpi_trace("%d: AVS Rd Rsp: tag=%0h, data=%0h, pending=%0d\n", $time, mem_rsp_tag, mem_rsp_data, req_queue_size);
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end
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end
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`endif
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endmodule |