35 lines
619 B
Verilog
35 lines
619 B
Verilog
`ifndef VX_WARP_CTL_IF
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`define VX_WARP_CTL_IF
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`include "VX_define.vh"
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interface VX_warp_ctl_if ();
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wire valid;
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wire [`NW_BITS-1:0] wid;
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gpu_tmc_t tmc;
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gpu_wspawn_t wspawn;
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gpu_barrier_t barrier;
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gpu_split_t split;
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modport master (
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output valid,
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output wid,
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output tmc,
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output wspawn,
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output barrier,
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output split
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);
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modport slave (
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input valid,
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input wid,
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input tmc,
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input wspawn,
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input barrier,
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input split
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);
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endinterface
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`endif |