65 lines
1.3 KiB
Bash
Executable File
65 lines
1.3 KiB
Bash
Executable File
#!/bin/bash
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# this script uses sv2v and yosys tools to run.
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# sv2v: https://github.com/zachjs/sv2v
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# yosys: http://www.clifford.at/yosys/
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# exit when any command fails
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set -e
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source=""
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top_level=""
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dir_list=()
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inc_args=""
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macro_args=""
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usage() { echo "$0 usage:" && grep " .)\ #" $0; exit 0; }
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[ $# -eq 0 ] && usage
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while getopts "s:t:I:D:h" arg; do
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case $arg in
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s) # source
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source=${OPTARG}
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;;
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t) # top-level
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top_level=${OPTARG}
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;;
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I) # include directory
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dir_list+=(${OPTARG})
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inc_args="$inc_args -I${OPTARG}"
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;;
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D) # macro definition
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macro_args="$macro_args -D${OPTARG}"
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;;
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h | *)
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usage
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exit 0
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;;
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esac
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done
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{
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# read design sources
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for dir in "${dir_list[@]}"
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do
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for file in $(find $dir -maxdepth 1 -name '*.v' -o -name '*.sv' -type f)
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do
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echo "read_verilog $macro_args $inc_args -sv $file"
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done
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done
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if [ -n "$source" ]; then
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echo "read_verilog $macro_args $inc_args -sv $source"
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fi
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# generic synthesis
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echo "synth -top $top_level"
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# mapping to mycells.lib
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echo "dfflibmap -liberty mycells.lib"
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echo "abc -liberty mycells.lib"
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echo "clean"
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# write synthesized design
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echo "write_verilog synth.v"
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} > synth.ys
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yosys -l yosys.log synth.ys |