143 lines
5.9 KiB
Systemverilog
143 lines
5.9 KiB
Systemverilog
// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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`include "VX_define.vh"
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module VX_scoreboard import VX_gpu_pkg::*; #(
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parameter CORE_ID = 0
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) (
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input wire clk,
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input wire reset,
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VX_writeback_if.slave writeback_if [`ISSUE_WIDTH],
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VX_ibuffer_if.slave ibuffer_if [`ISSUE_WIDTH],
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VX_ibuffer_if.master scoreboard_if [`ISSUE_WIDTH]
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);
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`UNUSED_PARAM (CORE_ID)
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localparam DATAW = `UUID_WIDTH + ISSUE_WIS_W + `NUM_THREADS + `XLEN + `EX_BITS + `INST_OP_BITS + `INST_MOD_BITS + 1 + 1 + `XLEN + (`NR_BITS * 4) + 1;
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for (genvar i = 0; i < `ISSUE_WIDTH; ++i) begin
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reg [`UP(ISSUE_RATIO)-1:0][`NUM_REGS-1:0] inuse_regs, inuse_regs_n;
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reg [3:0] ready_masks, ready_masks_n;
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VX_ibuffer_if staging_if();
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wire writeback_fire = writeback_if[i].valid && writeback_if[i].data.eop;
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always @(*) begin
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inuse_regs_n = inuse_regs;
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ready_masks_n = ready_masks;
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if (writeback_fire) begin
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inuse_regs_n[writeback_if[i].data.wis][writeback_if[i].data.rd] = 0;
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ready_masks_n |= {4{(ISSUE_RATIO == 0) || writeback_if[i].data.wis == staging_if.data.wis}}
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& {(writeback_if[i].data.rd == staging_if.data.rd),
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(writeback_if[i].data.rd == staging_if.data.rs1),
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(writeback_if[i].data.rd == staging_if.data.rs2),
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(writeback_if[i].data.rd == staging_if.data.rs3)};
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end
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if (staging_if.valid && staging_if.ready && staging_if.data.wb) begin
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inuse_regs_n[staging_if.data.wis][staging_if.data.rd] = 1;
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ready_masks_n = '0;
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end
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if (ibuffer_if[i].valid && ibuffer_if[i].ready) begin
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ready_masks_n = ~{inuse_regs_n[ibuffer_if[i].data.wis][ibuffer_if[i].data.rd],
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inuse_regs_n[ibuffer_if[i].data.wis][ibuffer_if[i].data.rs1],
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inuse_regs_n[ibuffer_if[i].data.wis][ibuffer_if[i].data.rs2],
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inuse_regs_n[ibuffer_if[i].data.wis][ibuffer_if[i].data.rs3]};
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end
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end
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always @(posedge clk) begin
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if (reset) begin
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inuse_regs <= '0;
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ready_masks <= '0;
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end else begin
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inuse_regs <= inuse_regs_n;
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ready_masks <= ready_masks_n;
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end
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end
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// staging buffer
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`RESET_RELAY (stg_buf_reset, reset);
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VX_elastic_buffer #(
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.DATAW (DATAW)
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) stg_buf (
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.clk (clk),
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.reset (stg_buf_reset),
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.valid_in (ibuffer_if[i].valid),
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.ready_in (ibuffer_if[i].ready),
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.data_in (ibuffer_if[i].data),
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.data_out (staging_if.data),
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.valid_out (staging_if.valid),
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.ready_out (staging_if.ready)
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);
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// output buffer
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wire valid_stg, ready_stg;
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wire regs_ready = (& ready_masks);
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assign valid_stg = staging_if.valid && regs_ready;
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assign staging_if.ready = ready_stg && regs_ready;
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`RESET_RELAY (out_buf_reset, reset);
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VX_elastic_buffer #(
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.DATAW (DATAW),
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.SIZE (2),
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.OUT_REG (2)
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) out_buf (
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.clk (clk),
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.reset (out_buf_reset),
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.valid_in (valid_stg),
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.ready_in (ready_stg),
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.data_in (staging_if.data),
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.data_out (scoreboard_if[i].data),
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.valid_out (scoreboard_if[i].valid),
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.ready_out (scoreboard_if[i].ready)
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);
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`ifdef SIMULATION
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reg [31:0] timeout_ctr;
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always @(posedge clk) begin
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if (reset) begin
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timeout_ctr <= '0;
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end else begin
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if (staging_if.valid && ~regs_ready) begin
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`ifdef DBG_TRACE_CORE_PIPELINE
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`TRACE(3, ("%d: *** core%0d-scoreboard-stall: wid=%0d, PC=0x%0h, tmask=%b, cycles=%0d, inuse=%b (#%0d)\n",
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$time, CORE_ID, wis_to_wid(staging_if.data.wis, i), staging_if.data.PC, staging_if.data.tmask, timeout_ctr,
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~ready_masks, staging_if.data.uuid));
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`endif
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timeout_ctr <= timeout_ctr + 1;
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end else if (staging_if.valid && staging_if.ready) begin
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timeout_ctr <= '0;
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end
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end
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end
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`RUNTIME_ASSERT((timeout_ctr < `STALL_TIMEOUT),
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("%t: *** core%0d-scoreboard-timeout: wid=%0d, PC=0x%0h, tmask=%b, cycles=%0d, inuse=%b (#%0d)",
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$time, CORE_ID, wis_to_wid(staging_if.data.wis, i), staging_if.data.PC, staging_if.data.tmask, timeout_ctr,
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~ready_masks, staging_if.data.uuid));
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`RUNTIME_ASSERT(~writeback_fire || inuse_regs[writeback_if[i].data.wis][writeback_if[i].data.rd] != 0,
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("%t: *** core%0d: invalid writeback register: wid=%0d, PC=0x%0h, tmask=%b, rd=%0d (#%0d)",
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$time, CORE_ID, wis_to_wid(writeback_if[i].data.wis, i), writeback_if[i].data.PC, writeback_if[i].data.tmask, writeback_if[i].data.rd, writeback_if[i].data.uuid));
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`endif
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end
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endmodule
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