128 lines
3.0 KiB
Verilog
128 lines
3.0 KiB
Verilog
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`include "VX_define.v"
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module cache_simX (
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input wire clk, // Clock
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input wire reset,
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// Icache
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input wire[31:0] in_icache_pc_addr,
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input wire in_icache_valid_pc_addr,
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output wire out_icache_stall,
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// Dcache
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input wire[2:0] in_dcache_mem_read,
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input wire[2:0] in_dcache_mem_write,
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input wire in_dcache_in_valid[`NT_M1:0],
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input wire[31:0] in_dcache_in_address[`NT_M1:0],
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output wire out_dcache_stall
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);
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//////////////////// ICACHE ///////////////////
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VX_icache_request_if VX_icache_req;
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assign VX_icache_req.pc_address = in_icache_pc_addr;
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assign VX_icache_req.out_cache_driver_in_mem_read = (in_icache_valid_pc_addr) ? `LW_MEM_READ : `NO_MEM_READ;
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assign VX_icache_req.out_cache_driver_in_mem_write = `NO_MEM_WRITE;
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assign VX_icache_req.out_cache_driver_in_valid = in_icache_valid_pc_addr;
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assign VX_icache_req.out_cache_driver_in_data = 0;
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VX_icache_response_if VX_icache_rsp;
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assign out_icache_stall = VX_icache_rsp.delay;
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VX_dram_req_rsp_if #(
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.NUMBER_BANKS(`ICACHE_BANKS),
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.NUM_WORDS_PER_BLOCK(`ICACHE_NUM_WORDS_PER_BLOCK)
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) VX_dram_req_rsp_icache();
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reg icache_i_m_ready;
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assign VX_dram_req_rsp_icache.i_m_ready = icache_i_m_ready;
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//////////////////// DCACHE ///////////////////
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VX_dcache_request_if VX_dcache_req;
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assign VX_dcache_req.out_cache_driver_in_mem_read = in_dcache_mem_read;
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assign VX_dcache_req.out_cache_driver_in_mem_write = in_dcache_mem_write;
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assign VX_dcache_req.out_cache_driver_in_data = 0;
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genvar curr_t;
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for (curr_t = 0; curr_t < `NT; curr_t=curr_t+1)
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begin
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assign VX_dcache_req.out_cache_driver_in_address[curr_t] = in_dcache_in_address[curr_t];
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assign VX_dcache_req.out_cache_driver_in_valid[curr_t] = in_dcache_in_valid[curr_t];
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end
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VX_dcache_response_if VX_dcache_rsp;
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assign out_dcache_stall = VX_dcache_rsp.delay;
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VX_dram_req_rsp_if #(
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.NUMBER_BANKS(`DCACHE_BANKS),
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.NUM_WORDS_PER_BLOCK(`DCACHE_NUM_WORDS_PER_BLOCK)
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) VX_dram_req_rsp();
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reg dcache_i_m_ready;
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assign VX_dram_req_rsp.i_m_ready = dcache_i_m_ready;
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VX_dmem_controller dmem_controller (
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.clk (clk),
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.reset (reset),
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.VX_dram_req_rsp (VX_dram_req_rsp),
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.VX_dram_req_rsp_icache(VX_dram_req_rsp_icache),
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.VX_icache_req (VX_icache_req),
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.VX_icache_rsp (VX_icache_rsp),
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.VX_dcache_req (VX_dcache_req),
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.VX_dcache_rsp (VX_dcache_rsp)
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);
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always @(posedge clk, posedge reset) begin
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if (reset)
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begin
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icache_i_m_ready = 0;
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dcache_i_m_ready = 0;
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end else begin
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if (VX_dram_req_rsp_icache.o_m_valid) begin
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icache_i_m_ready = 1;
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// $display("cache_simX.v: setting icache_i_m_ready = %d", icache_i_m_ready);
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end else if (icache_i_m_ready) begin
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icache_i_m_ready = 0;
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end else begin
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icache_i_m_ready = 0;
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end
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if (VX_dram_req_rsp.o_m_valid) begin
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dcache_i_m_ready = 1;
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end else if (dcache_i_m_ready) begin
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dcache_i_m_ready = 0;
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end else begin
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dcache_i_m_ready = 0;
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end
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end
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end
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endmodule
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