45 lines
679 B
Verilog
45 lines
679 B
Verilog
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`include "VX_define.v"
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`ifndef VX_MEM_WB_INST_INTER
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`define VX_MEM_WB_INST_INTER
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interface VX_inst_mem_wb_inter ();
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wire[`NT_M1:0][31:0] alu_result;
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wire[`NT_M1:0][31:0] mem_result;
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wire[4:0] rd;
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wire[1:0] wb;
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wire[31:0] PC_next;
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wire[`NT_M1:0] valid;
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wire[`NW_M1:0] warp_num;
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// source-side view
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modport snk (
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input alu_result,
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input mem_result,
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input rd,
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input wb,
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input PC_next,
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input valid,
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input warp_num
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);
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// source-side view
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modport src (
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output alu_result,
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output mem_result,
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output rd,
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output wb,
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output PC_next,
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output valid,
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output warp_num
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);
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endinterface
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`endif |