Blaise Tine b3a52f4002 minor update

2020-09-20 00:43:01 -04:00

..

configs

project directories reorganization

2020-04-14 06:35:20 -04:00

models/memory

RTL code refactoring

2020-04-19 03:38:00 -04:00

modelsim

yosys synthesis refactoring

2020-07-10 18:56:41 -04:00

old_rtl

refactoring fixes

2020-04-14 19:39:59 -04:00

opae

adding prebuilt CI script

2020-09-19 16:08:28 -04:00

rtl

mutiple fixes: parallel printf, fixed cycle in cache, opencl refactored vecadd and sgemm, regen opencl kernels with hard-float, fixed vortex io bus interface, fixed dpi floats APi to support multicore mode, make vlsim multicore default, make rtlsim multi-core default, removed POCL binaries from repository, updated Makefiles to use external POCL

2020-09-19 14:45:42 -04:00

scripts

FPU DPI fallback

2020-08-31 09:19:55 -04:00

simulate

CI script updates

2020-09-20 00:17:42 -04:00

syn

minor update

2020-09-01 00:56:10 -07:00

unit_tests

updated from GT repo

2020-09-08 18:35:47 -04:00

.gitignore

adding dram writeenable support + scheduler bug fixes

2020-05-27 19:00:23 -04:00

Makefile

minor update

2020-09-20 00:43:01 -04:00