128 lines
6.0 KiB
Verilog
128 lines
6.0 KiB
Verilog
`include "VX_define.vh"
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module VX_commit #(
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parameter CORE_ID = 0
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) (
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input wire clk,
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input wire reset,
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// inputs
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VX_exu_to_cmt_if alu_commit_if,
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VX_exu_to_cmt_if lsu_commit_if,
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VX_exu_to_cmt_if mul_commit_if,
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VX_exu_to_cmt_if csr_commit_if,
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VX_fpu_to_cmt_if fpu_commit_if,
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VX_exu_to_cmt_if gpu_commit_if,
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// outputs
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VX_cmt_to_issue_if cmt_to_issue_if,
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VX_wb_if writeback_if,
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VX_cmt_to_csr_if cmt_to_csr_if
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);
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// update CRSs
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wire [`NUM_EXS-1:0] commited_mask;
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assign commited_mask = {(alu_commit_if.valid && alu_commit_if.ready),
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(lsu_commit_if.valid && lsu_commit_if.ready),
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(csr_commit_if.valid && csr_commit_if.ready),
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(mul_commit_if.valid && mul_commit_if.ready),
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(fpu_commit_if.valid && fpu_commit_if.ready),
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(gpu_commit_if.valid && gpu_commit_if.ready)};
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wire [`NE_BITS:0] num_commits;
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VX_countones #(
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.N(`NUM_EXS)
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) valids_counter (
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.valids(commited_mask),
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.count (num_commits)
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);
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assign cmt_to_csr_if.valid = (| commited_mask);
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assign cmt_to_csr_if.warp_num = cmt_to_issue_if.fpu_data.warp_num;
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assign cmt_to_csr_if.num_commits = num_commits;
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assign cmt_to_csr_if.has_fflags = (fpu_commit_if.valid && fpu_commit_if.ready) && fpu_commit_if.has_fflags;
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integer i;
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reg [`FFG_BITS-1:0] fflags;
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always @(*) begin
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fflags = 0;
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for (i = 0; i < `NUM_THREADS; i++) begin
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if (cmt_to_issue_if.fpu_data.thread_mask[i]) begin
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fflags[0] |= fpu_commit_if.fflags[i][0];
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fflags[1] |= fpu_commit_if.fflags[i][1];
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fflags[2] |= fpu_commit_if.fflags[i][2];
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fflags[3] |= fpu_commit_if.fflags[i][3];
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fflags[4] |= fpu_commit_if.fflags[i][4];
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end
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end
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end
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assign cmt_to_csr_if.fflags = fflags;
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// Notify issue stage
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assign cmt_to_issue_if.alu_valid = alu_commit_if.valid && alu_commit_if.ready;
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assign cmt_to_issue_if.lsu_valid = lsu_commit_if.valid && lsu_commit_if.ready;
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assign cmt_to_issue_if.csr_valid = csr_commit_if.valid && csr_commit_if.ready;
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assign cmt_to_issue_if.mul_valid = mul_commit_if.valid && mul_commit_if.ready;
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assign cmt_to_issue_if.fpu_valid = fpu_commit_if.valid && fpu_commit_if.ready;
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assign cmt_to_issue_if.gpu_valid = gpu_commit_if.valid && gpu_commit_if.ready;
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assign cmt_to_issue_if.alu_tag = alu_commit_if.issue_tag;
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assign cmt_to_issue_if.lsu_tag = lsu_commit_if.issue_tag;
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assign cmt_to_issue_if.csr_tag = csr_commit_if.issue_tag;
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assign cmt_to_issue_if.mul_tag = mul_commit_if.issue_tag;
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assign cmt_to_issue_if.fpu_tag = fpu_commit_if.issue_tag;
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assign cmt_to_issue_if.gpu_tag = gpu_commit_if.issue_tag;
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VX_writeback #(
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.CORE_ID(CORE_ID)
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) writeback (
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.clk (clk),
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.reset (reset),
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.alu_commit_if (alu_commit_if),
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.lsu_commit_if (lsu_commit_if),
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.csr_commit_if (csr_commit_if),
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.mul_commit_if (mul_commit_if),
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.fpu_commit_if (fpu_commit_if),
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.gpu_commit_if (gpu_commit_if),
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.cmt_to_issue_if(cmt_to_issue_if),
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.writeback_if (writeback_if)
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);
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`ifdef DBG_PRINT_PIPELINE
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always @(posedge clk) begin
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if (alu_commit_if.valid && alu_commit_if.ready) begin
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$display("%t: Core%0d-commit: warp=%0d, PC=%0h, ex=ALU, istag=%0d, tmask=%b, wb=%0d, rd=%0d, data=%0h", $time, CORE_ID, cmt_to_issue_if.alu_data.warp_num, cmt_to_issue_if.alu_data.curr_PC, alu_commit_if.issue_tag, cmt_to_issue_if.alu_data.thread_mask, cmt_to_issue_if.alu_data.wb, cmt_to_issue_if.alu_data.rd, alu_commit_if.data);
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end
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if (lsu_commit_if.valid && lsu_commit_if.ready) begin
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$display("%t: Core%0d-commit: warp=%0d, PC=%0h, ex=LSU, istag=%0d, tmask=%b, wb=%0d, rd=%0d, data=%0h", $time, CORE_ID, cmt_to_issue_if.lsu_data.warp_num, cmt_to_issue_if.lsu_data.curr_PC, lsu_commit_if.issue_tag, cmt_to_issue_if.lsu_data.thread_mask, cmt_to_issue_if.lsu_data.wb, cmt_to_issue_if.lsu_data.rd, lsu_commit_if.data);
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end
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if (csr_commit_if.valid && csr_commit_if.ready) begin
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$display("%t: Core%0d-commit: warp=%0d, PC=%0h, ex=CSR, istag=%0d, tmask=%b, wb=%0d, rd=%0d, data=%0h", $time, CORE_ID, cmt_to_issue_if.csr_data.warp_num, cmt_to_issue_if.csr_data.curr_PC, csr_commit_if.issue_tag, cmt_to_issue_if.csr_data.thread_mask, cmt_to_issue_if.csr_data.wb, cmt_to_issue_if.csr_data.rd, csr_commit_if.data);
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end
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if (mul_commit_if.valid && mul_commit_if.ready) begin
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$display("%t: Core%0d-commit: warp=%0d, PC=%0h, ex=MUL, istag=%0d, tmask=%b, wb=%0d, rd=%0d, data=%0h", $time, CORE_ID, cmt_to_issue_if.mul_data.warp_num, cmt_to_issue_if.mul_data.curr_PC, mul_commit_if.issue_tag, cmt_to_issue_if.mul_data.thread_mask, cmt_to_issue_if.mul_data.wb, cmt_to_issue_if.mul_data.rd, mul_commit_if.data);
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end
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if (fpu_commit_if.valid && fpu_commit_if.ready) begin
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$display("%t: Core%0d-commit: warp=%0d, PC=%0h, ex=FPU, istag=%0d, tmask=%b, wb=%0d, rd=%0d, data=%0h", $time, CORE_ID, cmt_to_issue_if.fpu_data.warp_num, cmt_to_issue_if.fpu_data.curr_PC, fpu_commit_if.issue_tag, cmt_to_issue_if.fpu_data.thread_mask, cmt_to_issue_if.fpu_data.wb, cmt_to_issue_if.fpu_data.rd, fpu_commit_if.data);
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end
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if (gpu_commit_if.valid && gpu_commit_if.ready) begin
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$display("%t: Core%0d-commit: warp=%0d, PC=%0h, ex=GPU, istag=%0d, tmask=%b, wb=%0d, rd=%0d, data=%0h", $time, CORE_ID, cmt_to_issue_if.gpu_data.warp_num, cmt_to_issue_if.gpu_data.curr_PC, gpu_commit_if.issue_tag, cmt_to_issue_if.gpu_data.thread_mask, cmt_to_issue_if.gpu_data.wb, cmt_to_issue_if.gpu_data.rd, gpu_commit_if.data);
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end
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end
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`endif
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endmodule
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