96 lines
4.3 KiB
Verilog
96 lines
4.3 KiB
Verilog
`include "VX_platform.vh"
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module VX_priority_encoder #(
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parameter N = 1,
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parameter FAST = 1,
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parameter LN = `LOG2UP(N)
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) (
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input wire [N-1:0] data_in,
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output wire [N-1:0] onehot,
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output wire [LN-1:0] index,
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output wire valid_out
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);
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if (N == 1) begin
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assign onehot = data_in;
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assign index = 0;
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assign valid_out = data_in;
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end else if (N == 2) begin
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assign onehot = {~data_in[0], data_in[0]};
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assign index = ~data_in[0];
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assign valid_out = (| data_in);
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end else begin
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reg [LN-1:0] index_r;
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reg [N-1:0] onehot_r;
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if (N == 4) begin
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always @(*) begin
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casez (data_in)
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4'b???1: begin onehot_r = 4'b0001; index_r = LN'(0); end
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4'b??10: begin onehot_r = 4'b0010; index_r = LN'(1); end
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4'b?100: begin onehot_r = 4'b0100; index_r = LN'(2); end
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4'b1000: begin onehot_r = 4'b1000; index_r = LN'(3); end
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default: begin onehot_r = 'x; index_r = 'x; end
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endcase
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end
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end else if (N == 8) begin
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always @(*) begin
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casez (data_in)
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8'b???????1: begin onehot_r = 8'b00000001; index_r = LN'(0); end
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8'b??????10: begin onehot_r = 8'b00000010; index_r = LN'(1); end
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8'b?????100: begin onehot_r = 8'b00000100; index_r = LN'(2); end
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8'b????1000: begin onehot_r = 8'b00001000; index_r = LN'(3); end
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8'b???10000: begin onehot_r = 8'b00010000; index_r = LN'(4); end
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8'b??100000: begin onehot_r = 8'b00100000; index_r = LN'(5); end
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8'b?1000000: begin onehot_r = 8'b01000000; index_r = LN'(6); end
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8'b10000000: begin onehot_r = 8'b10000000; index_r = LN'(7); end
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default: begin onehot_r = 'x; index_r = 'x; end
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endcase
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end
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end else if (N == 16) begin
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always @(*) begin
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casez (data_in)
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16'b???????????????1: begin onehot_r = 16'b0000000000000001; index_r = LN'(0); end
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16'b??????????????10: begin onehot_r = 16'b0000000000000010; index_r = LN'(1); end
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16'b?????????????100: begin onehot_r = 16'b0000000000000100; index_r = LN'(2); end
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16'b????????????1000: begin onehot_r = 16'b0000000000001000; index_r = LN'(3); end
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16'b???????????10000: begin onehot_r = 16'b0000000000010000; index_r = LN'(4); end
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16'b??????????100000: begin onehot_r = 16'b0000000000100000; index_r = LN'(5); end
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16'b?????????1000000: begin onehot_r = 16'b0000000001000000; index_r = LN'(6); end
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16'b????????10000000: begin onehot_r = 16'b0000000010000000; index_r = LN'(7); end
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16'b???????100000000: begin onehot_r = 16'b0000000100000000; index_r = LN'(8); end
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16'b??????1000000000: begin onehot_r = 16'b0000001000000000; index_r = LN'(9); end
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16'b?????10000000000: begin onehot_r = 16'b0000010000000000; index_r = LN'(10); end
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16'b????100000000000: begin onehot_r = 16'b0000100000000000; index_r = LN'(11); end
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16'b???1000000000000: begin onehot_r = 16'b0001000000000000; index_r = LN'(12); end
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16'b??10000000000000: begin onehot_r = 16'b0010000000000000; index_r = LN'(13); end
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16'b?100000000000000: begin onehot_r = 16'b0100000000000000; index_r = LN'(14); end
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16'b1000000000000000: begin onehot_r = 16'b1000000000000000; index_r = LN'(15); end
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default: begin onehot_r = 'x; index_r = 'x; end
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endcase
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end
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end else begin
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always @(*) begin
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index_r = 'x;
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onehot_r = 'x;
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for (integer i = N-1; i >= 0; --i) begin
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if (data_in[i]) begin
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index_r = LN'(i);
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onehot_r = 0;
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onehot_r[i] = 1'b1;
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end
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end
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end
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end
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assign index = index_r;
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assign onehot = onehot_r;
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assign valid_out = (| data_in);
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end
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endmodule |