73 lines
2.7 KiB
Systemverilog
73 lines
2.7 KiB
Systemverilog
`ifndef VX_CACHE_DEFINE
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`define VX_CACHE_DEFINE
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`include "VX_platform.vh"
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`ifdef DBG_CACHE_REQ_INFO
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`include "VX_define.vh"
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`endif
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`define REQS_BITS `LOG2UP(NUM_REQS)
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// tag valid tid word_sel
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`define MSHR_DATA_WIDTH (CORE_TAG_WIDTH + (1 + `REQS_BITS + `UP(`WORD_SELECT_BITS)) * NUM_PORTS)
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`define WORD_WIDTH (8 * WORD_SIZE)
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`define CACHE_LINE_WIDTH (8 * CACHE_LINE_SIZE)
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`define BANK_SIZE (CACHE_SIZE / NUM_BANKS)
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`define LINES_PER_BANK (`BANK_SIZE / CACHE_LINE_SIZE)
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`define WORDS_PER_LINE (CACHE_LINE_SIZE / WORD_SIZE)
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`define WORD_ADDR_WIDTH (32-`CLOG2(WORD_SIZE))
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`define MEM_ADDR_WIDTH (32-`CLOG2(CACHE_LINE_SIZE))
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`define LINE_ADDR_WIDTH (`MEM_ADDR_WIDTH-`BANK_SELECT_BITS)
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// Word select
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`define WORD_SELECT_BITS `CLOG2(`WORDS_PER_LINE)
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`define WORD_SELECT_ADDR_START 0
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`define WORD_SELECT_ADDR_END (`WORD_SELECT_ADDR_START+`WORD_SELECT_BITS-1)
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// Bank select
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`define BANK_SELECT_BITS `CLOG2(NUM_BANKS)
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`define BANK_SELECT_ADDR_START (1+`WORD_SELECT_ADDR_END+BANK_ADDR_OFFSET)
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`define BANK_SELECT_ADDR_END (`BANK_SELECT_ADDR_START+`BANK_SELECT_BITS-1)
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// Line select
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`define LINE_SELECT_BITS `CLOG2(`LINES_PER_BANK)
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`define LINE_SELECT_ADDR_START (1+`BANK_SELECT_ADDR_END)
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`define LINE_SELECT_ADDR_END (`LINE_SELECT_ADDR_START-BANK_ADDR_OFFSET+`LINE_SELECT_BITS-1)
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// Tag select
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`define TAG_SELECT_BITS (`WORD_ADDR_WIDTH-1-`LINE_SELECT_ADDR_END)
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`define TAG_SELECT_ADDR_START (1+`LINE_SELECT_ADDR_END)
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`define TAG_SELECT_ADDR_END (`WORD_ADDR_WIDTH-1)
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`define BANK_SELECT_ADDR(x) x[`BANK_SELECT_ADDR_END : `BANK_SELECT_ADDR_START]
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`define LINE_SELECT_ADDR0(x) x[`WORD_ADDR_WIDTH-1 : `LINE_SELECT_ADDR_START]
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`define LINE_SELECT_ADDRX(x) {x[`WORD_ADDR_WIDTH-1 : `LINE_SELECT_ADDR_START], x[`BANK_SELECT_ADDR_START-1 : 1+`WORD_SELECT_ADDR_END]}
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`define LINE_TAG_ADDR(x) x[`LINE_ADDR_WIDTH-1 : `LINE_SELECT_BITS]
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`define CACHE_REQ_INFO_RNG CORE_TAG_WIDTH-1:(CORE_TAG_WIDTH-`NW_BITS-32)
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///////////////////////////////////////////////////////////////////////////////
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`define CORE_RSP_TAGS ((CORE_TAG_ID_BITS != 0) ? 1 : NUM_REQS)
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`define BANK_READY_COUNT ((SHARED_BANK_READY != 0) ? 1 : NUM_BANKS)
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`define MEM_ADDR_BANK(x) x[`BANK_SELECT_BITS+BANK_ADDR_OFFSET-1 : BANK_ADDR_OFFSET]
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`define MEM_TO_LINE_ADDR(x) x[`MEM_ADDR_WIDTH-1 : `BANK_SELECT_BITS]
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`define LINE_TO_MEM_ADDR(x, i) {x, `BANK_SELECT_BITS'(i)}
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`define LINE_TO_BYTE_ADDR(x, i) {x, (32-$bits(x))'(i << (32-$bits(x)-`BANK_SELECT_BITS))}
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`define TO_FULL_ADDR(x) {x, (32-$bits(x))'(0)}
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`endif
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