Files
kernels/hw/rtl/interfaces/VX_tex_csr_if.v
2021-07-30 21:03:14 -07:00

14 lines
252 B
Verilog

`ifndef VX_TEX_CSR_IF
`define VX_TEX_CSR_IF
`include "VX_define.vh"
interface VX_tex_csr_if ();
wire write_enable;
wire [`CSR_ADDR_BITS-1:0] write_addr;
wire [31:0] write_data;
endinterface
`endif