137 lines
4.0 KiB
Verilog
137 lines
4.0 KiB
Verilog
`include "VX_platform.vh"
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module VX_skid_buffer #(
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parameter DATAW = 1,
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parameter PASSTHRU = 0,
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parameter NOBACKPRESSURE = 0,
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parameter BUFFERED = 0
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) (
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input wire clk,
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input wire reset,
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input wire valid_in,
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output wire ready_in,
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input wire [DATAW-1:0] data_in,
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output wire [DATAW-1:0] data_out,
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input wire ready_out,
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output wire valid_out
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);
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if (PASSTHRU) begin
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`UNUSED_VAR (clk)
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`UNUSED_VAR (reset)
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assign valid_out = valid_in;
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assign data_out = data_in;
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assign ready_in = ready_out;
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end else if (NOBACKPRESSURE) begin
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always @(posedge clk) begin
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assert(ready_out) else $error("ready_out should always be asserted");
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end
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wire stall = valid_out && ~ready_out;
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VX_pipe_register #(
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.DATAW (1 + DATAW),
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.RESETW (1)
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) pipe_reg (
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.clk (clk),
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.reset (reset),
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.enable (!stall),
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.data_in ({valid_in, data_in}),
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.data_out ({valid_out, data_out})
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);
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assign ready_in = ~stall;
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end else begin
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if (BUFFERED) begin
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reg [DATAW-1:0] data_out_r;
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reg [DATAW-1:0] buffer;
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reg valid_out_r;
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reg use_buffer;
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wire push = valid_in && ready_in;
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wire pop = !valid_out_r || ready_out;
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always @(posedge clk) begin
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if (reset) begin
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valid_out_r <= 0;
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use_buffer <= 0;
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end else begin
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if (ready_out) begin
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use_buffer <= 0;
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end else if (push && valid_out_r) begin
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assert(!use_buffer);
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use_buffer <= 1;
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end
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if (pop) begin
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valid_out_r <= valid_in || use_buffer;
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end
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end
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end
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always @(posedge clk) begin
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if (push) begin
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buffer <= data_in;
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end
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if (pop && !use_buffer) begin
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data_out_r <= data_in;
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end else if (pop) begin
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data_out_r <= buffer;
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end
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end
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assign ready_in = !use_buffer;
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assign valid_out = valid_out_r;
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assign data_out = data_out_r;
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end else begin
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reg [DATAW-1:0] shift_reg [1:0];
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reg valid_out_r, ready_in_r, rd_ptr_r;
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wire push = valid_in && ready_in;
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wire pop = valid_out_r && ready_out;
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always @(posedge clk) begin
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if (reset) begin
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valid_out_r <= 0;
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ready_in_r <= 1;
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rd_ptr_r <= 1;
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end else begin
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if (push) begin
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if (!pop) begin
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ready_in_r <= rd_ptr_r;
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valid_out_r <= 1;
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end
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end else if (pop) begin
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ready_in_r <= 1;
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valid_out_r <= rd_ptr_r;
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end
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`IGNORE_WARNINGS_BEGIN
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rd_ptr_r <= rd_ptr_r ^ (push ^ pop);
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`IGNORE_WARNINGS_END
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end
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end
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always @(posedge clk) begin
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if (push) begin
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shift_reg[1] <= shift_reg[0];
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shift_reg[0] <= data_in;
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end
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end
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assign ready_in = ready_in_r;
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assign valid_out = valid_out_r;
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assign data_out = shift_reg[rd_ptr_r];
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end
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end
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endmodule |