72 lines
2.1 KiB
Verilog
72 lines
2.1 KiB
Verilog
`include "VX_cache_config.vh"
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module VX_fill_invalidator #(
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// Size of line inside a bank in bytes
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parameter BANK_LINE_SIZE = 0,
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// Number of banks {1, 2, 4, 8,...}
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parameter NUM_BANKS = 0,
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// Fill Invalidator Size {Fill invalidator must be active}
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parameter FILL_INVALIDAOR_SIZE = 0
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) (
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input wire clk,
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input wire reset,
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input wire possible_fill,
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input wire success_fill,
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input wire[`LINE_ADDR_WIDTH-1:0] fill_addr,
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output reg invalidate_fill
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);
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if (FILL_INVALIDAOR_SIZE == 0) begin
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assign invalidate_fill = 0;
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end else begin
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reg [FILL_INVALIDAOR_SIZE-1:0] fills_active;
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reg [FILL_INVALIDAOR_SIZE-1:0][`LINE_ADDR_WIDTH-1:0] fills_address;
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reg [FILL_INVALIDAOR_SIZE-1:0] matched_fill;
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wire matched;
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integer i;
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always @(*) begin
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for (i = 0; i < FILL_INVALIDAOR_SIZE; i+=1) begin
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matched_fill[i] = fills_active[i]
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&& ((fills_address[i] == fill_addr) === 1); // use "case equality" to handle uninitialized entry
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end
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end
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assign matched = (|(matched_fill));
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wire [(`LOG2UP(FILL_INVALIDAOR_SIZE))-1:0] enqueue_index;
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wire enqueue_found;
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VX_generic_priority_encoder #(
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.N(FILL_INVALIDAOR_SIZE)
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) sel_bank (
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.valids(~fills_active),
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.index (enqueue_index),
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.found (enqueue_found)
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);
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assign invalidate_fill = possible_fill && matched;
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always @(posedge clk) begin
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if (reset) begin
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fills_active <= 0;
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end else begin
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if (possible_fill && !matched && enqueue_found) begin
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fills_active [enqueue_index] <= 1;
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fills_address[enqueue_index] <= fill_addr;
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end else if (success_fill && matched) begin
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fills_active <= fills_active & (~matched_fill);
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end
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end
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end
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end
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endmodule |