415 lines
14 KiB
Systemverilog
415 lines
14 KiB
Systemverilog
`ifndef VX_DEFINE
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`define VX_DEFINE
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`include "VX_platform.vh"
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`include "VX_config.vh"
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///////////////////////////////////////////////////////////////////////////////
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`define NW_BITS `LOG2UP(`NUM_WARPS)
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`define NT_BITS `LOG2UP(`NUM_THREADS)
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`define NC_BITS `LOG2UP(`NUM_CORES)
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`define NB_BITS `LOG2UP(`NUM_BARRIERS)
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`define REQS_BITS `LOG2UP(NUM_REQS)
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`ifdef EXT_F_ENABLE
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`define NUM_REGS 64
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`else
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`define NUM_REGS 32
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`endif
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`define NR_BITS `LOG2UP(`NUM_REGS)
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`define CSR_ADDR_BITS 12
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`define CSR_WIDTH 12
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`define PERF_CTR_BITS 44
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///////////////////////////////////////////////////////////////////////////////
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`define INST_LUI 7'b0110111
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`define INST_AUIPC 7'b0010111
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`define INST_JAL 7'b1101111
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`define INST_JALR 7'b1100111
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`define INST_B 7'b1100011 // branch instructions
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`define INST_L 7'b0000011 // load instructions
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`define INST_S 7'b0100011 // store instructions
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`define INST_I 7'b0010011 // immediate instructions
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`define INST_R 7'b0110011 // register instructions
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`define INST_F 7'b0001111 // Fence instructions
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`define INST_SYS 7'b1110011 // system instructions
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`define INST_FL 7'b0000111 // float load instruction
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`define INST_FS 7'b0100111 // float store instruction
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`define INST_FMADD 7'b1000011
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`define INST_FMSUB 7'b1000111
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`define INST_FNMSUB 7'b1001011
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`define INST_FNMADD 7'b1001111
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`define INST_FCI 7'b1010011 // float common instructions
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`define INST_GPU 7'b1101011
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///////////////////////////////////////////////////////////////////////////////
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`define FRM_RNE 3'b000 // round to nearest even
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`define FRM_RTZ 3'b001 // round to zero
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`define FRM_RDN 3'b010 // round to -inf
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`define FRM_RUP 3'b011 // round to +inf
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`define FRM_RMM 3'b100 // round to nearest max magnitude
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`define FRM_DYN 3'b111 // dynamic mode
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`define FRM_BITS 3
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///////////////////////////////////////////////////////////////////////////////
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`define EX_NOP 3'h0
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`define EX_ALU 3'h1
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`define EX_LSU 3'h2
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`define EX_CSR 3'h3
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`define EX_FPU 3'h4
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`define EX_GPU 3'h5
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`define EX_BITS 3
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`define NUM_EXS 6
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`define NE_BITS `LOG2UP(`NUM_EXS)
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///////////////////////////////////////////////////////////////////////////////
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`define OP_BITS 4
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`define MOD_BITS 3
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`define ALU_ADD 4'b0000
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`define ALU_LUI 4'b0010
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`define ALU_AUIPC 4'b0011
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`define ALU_SLTU 4'b0100
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`define ALU_SLT 4'b0101
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`define ALU_SRL 4'b1000
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`define ALU_SRA 4'b1001
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`define ALU_SUB 4'b1011
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`define ALU_AND 4'b1100
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`define ALU_OR 4'b1101
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`define ALU_XOR 4'b1110
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`define ALU_SLL 4'b1111
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`define ALU_OTHER 4'b0111
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`define ALU_BITS 4
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`define ALU_OP(x) x[`ALU_BITS-1:0]
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`define ALU_OP_CLASS(x) x[3:2]
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`define ALU_SIGNED(x) x[0]
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`define ALU_IS_BR(x) x[0]
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`define ALU_IS_MUL(x) x[1]
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`define BR_EQ 4'b0000
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`define BR_NE 4'b0010
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`define BR_LTU 4'b0100
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`define BR_GEU 4'b0110
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`define BR_LT 4'b0101
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`define BR_GE 4'b0111
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`define BR_JAL 4'b1000
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`define BR_JALR 4'b1001
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`define BR_ECALL 4'b1010
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`define BR_EBREAK 4'b1011
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`define BR_MRET 4'b1100
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`define BR_SRET 4'b1101
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`define BR_DRET 4'b1110
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`define BR_OTHER 4'b1111
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`define BR_BITS 4
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`define BR_OP(x) x[`BR_BITS-1:0]
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`define BR_NEG(x) x[1]
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`define BR_LESS(x) x[2]
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`define BR_STATIC(x) x[3]
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`define MUL_MUL 3'h0
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`define MUL_MULH 3'h1
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`define MUL_MULHSU 3'h2
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`define MUL_MULHU 3'h3
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`define MUL_DIV 3'h4
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`define MUL_DIVU 3'h5
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`define MUL_REM 3'h6
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`define MUL_REMU 3'h7
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`define MUL_BITS 3
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`define MUL_OP(x) x[`MUL_BITS-1:0]
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`define MUL_IS_DIV(x) x[2]
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`define FMT_B 3'b000
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`define FMT_H 3'b001
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`define FMT_W 3'b010
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`define FMT_BU 3'b100
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`define FMT_HU 3'b101
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`define LSU_LB 4'b0000
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`define LSU_LH 4'b0001
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`define LSU_LW 4'b0010
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`define LSU_LBU 4'b0100
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`define LSU_LHU 4'b0101
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`define LSU_SB 4'b1000
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`define LSU_SH 4'b1001
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`define LSU_SW 4'b1010
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`define LSU_BITS 4
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`define LSU_FMT(x) x[2:0]
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`define LSU_WSIZE(x) x[1:0]
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`define LSU_OP(x) x[`LSU_BITS-1:0]
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`define LSU_IS_FENCE(x) x[0]
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`define CSR_RW 2'h1
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`define CSR_RS 2'h2
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`define CSR_RC 2'h3
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`define CSR_OTHER 2'h0
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`define CSR_BITS 2
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`define CSR_OP(x) x[`CSR_BITS-1:0]
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`define FPU_ADD 4'h0
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`define FPU_SUB 4'h4
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`define FPU_MUL 4'h8
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`define FPU_DIV 4'hC
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`define FPU_CVTWS 4'h1 // FCVT.W.S
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`define FPU_CVTWUS 4'h5 // FCVT.WU.S
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`define FPU_CVTSW 4'h9 // FCVT.S.W
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`define FPU_CVTSWU 4'hD // FCVT.S.WU
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`define FPU_SQRT 4'h2
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`define FPU_CLASS 4'h6
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`define FPU_CMP 4'hA
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`define FPU_MISC 4'hE // SGNJ, SGNJN, SGNJX, FMIN, FMAX, MVXW, MVWX
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`define FPU_MADD 4'h3
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`define FPU_MSUB 4'h7
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`define FPU_NMSUB 4'hB
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`define FPU_NMADD 4'hF
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`define FPU_BITS 4
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`define FPU_OP(x) x[`FPU_BITS-1:0]
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`define GPU_TMC 3'h0
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`define GPU_WSPAWN 3'h1
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`define GPU_SPLIT 3'h2
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`define GPU_JOIN 3'h3
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`define GPU_BAR 3'h4
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`define GPU_PRED 3'h5
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`define GPU_BITS 3
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`define GPU_OP(x) x[`GPU_BITS-1:0]
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///////////////////////////////////////////////////////////////////////////////
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`ifdef EXT_M_ENABLE
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`define ISA_EXT_M (1 << 12)
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`else
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`define ISA_EXT_M 0
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`endif
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`ifdef EXT_F_ENABLE
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`define ISA_EXT_F (1 << 5)
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`else
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`define ISA_EXT_F 0
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`endif
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`define ISA_CODE (0 << 0) // A - Atomic Instructions extension \
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| (0 << 1) // B - Tentatively reserved for Bit operations extension \
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| (0 << 2) // C - Compressed extension \
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| (0 << 3) // D - Double precsision floating-point extension \
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| (0 << 4) // E - RV32E base ISA \
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|`ISA_EXT_F // F - Single precsision floating-point extension \
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| (0 << 6) // G - Additional standard extensions present \
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| (0 << 7) // H - Hypervisor mode implemented \
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| (1 << 8) // I - RV32I/64I/128I base ISA \
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| (0 << 9) // J - Reserved \
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| (0 << 10) // K - Reserved \
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| (0 << 11) // L - Tentatively reserved for Bit operations extension \
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|`ISA_EXT_M // M - Integer Multiply/Divide extension \
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| (0 << 13) // N - User level interrupts supported \
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| (0 << 14) // O - Reserved \
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| (0 << 15) // P - Tentatively reserved for Packed-SIMD extension \
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| (0 << 16) // Q - Quad-precision floating-point extension \
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| (0 << 17) // R - Reserved \
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| (0 << 18) // S - Supervisor mode implemented \
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| (0 << 19) // T - Tentatively reserved for Transactional Memory extension \
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| (1 << 20) // U - User mode implemented \
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| (0 << 21) // V - Tentatively reserved for Vector extension \
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| (0 << 22) // W - Reserved \
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| (1 << 23) // X - Non-standard extensions present \
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| (0 << 24) // Y - Reserved \
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| (0 << 25) // Z - Reserved
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///////////////////////////////////////////////////////////////////////////////
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`ifdef DBG_CACHE_REQ_INFO // wid PC
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`define DBG_CACHE_REQ_MDATAW (`NW_BITS + 32)
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`else
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`define DBG_CACHE_REQ_MDATAW 0
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`endif
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// non-cacheable address bit
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`define NC_ADDR_BITS 1
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////////////////////////// Icache Configurable Knobs //////////////////////////
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// Cache ID
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`define ICACHE_ID (32'(`L3_ENABLE) + 32'(`L2_ENABLE) * `NUM_CLUSTERS + CORE_ID * 3 + 0)
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// Block size in bytes
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`define ICACHE_LINE_SIZE (`L2_ENABLE ? `L1_BLOCK_SIZE : `MEM_BLOCK_SIZE)
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// Word size in bytes
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`define IWORD_SIZE 4
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// Number of banks
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`define INUM_BANKS 1
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// Core request address bits
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`define ICORE_ADDR_WIDTH (32-`CLOG2(`IWORD_SIZE))
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// Core request byte enable bits
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`define ICORE_BYTEEN_WIDTH `DWORD_SIZE
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// TAG sharing enable
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`define ICORE_TAG_ID_BITS `NW_BITS
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// Core request tag bits
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`define ICORE_TAG_WIDTH (`DBG_CACHE_REQ_MDATAW + `ICORE_TAG_ID_BITS)
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// Memory request data bits
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`define IMEM_DATA_WIDTH (`ICACHE_LINE_SIZE * 8)
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// Memory request address bits
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`define IMEM_ADDR_WIDTH (32 - `CLOG2(`ICACHE_LINE_SIZE))
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// Memory byte enable bits
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`define IMEM_BYTEEN_WIDTH `ICACHE_LINE_SIZE
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// Memory request tag bits
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`define IMEM_TAG_WIDTH (`IMEM_ADDR_WIDTH + `CLOG2(`IMSHR_SIZE))
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////////////////////////// Dcache Configurable Knobs //////////////////////////
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// Cache ID
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`define DCACHE_ID (32'(`L3_ENABLE) + 32'(`L2_ENABLE) * `NUM_CLUSTERS + CORE_ID * 3 + 1)
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// Block size in bytes
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`define DCACHE_LINE_SIZE (`L2_ENABLE ? `L1_BLOCK_SIZE : `MEM_BLOCK_SIZE)
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// Word size in bytes
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`define DWORD_SIZE 4
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// Core request address bits
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`define DCORE_ADDR_WIDTH (32-`CLOG2(`DWORD_SIZE))
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// TAG sharing enable
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`define LSUQ_ADDR_BITS `LOG2UP(`LSUQ_SIZE)
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`define DCORE_TAG_ID_BITS (`LSUQ_ADDR_BITS + `NC_ADDR_BITS + `SM_ENABLE)
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// Input request tag bits
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`define DCORE_TAG_WIDTH (`DBG_CACHE_REQ_MDATAW + `DCORE_TAG_ID_BITS)
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// Memory request data bits
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`define DMEM_DATA_WIDTH (`DCACHE_LINE_SIZE * 8)
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// Memory request address bits
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`define DMEM_ADDR_WIDTH (32 - `CLOG2(`DCACHE_LINE_SIZE))
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// Memory byte enable bits
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`define DMEM_BYTEEN_WIDTH `DCACHE_LINE_SIZE
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// Input request size
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`define DNUM_REQS `NUM_THREADS
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// Memory request tag bits
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`define _DMEM_ADDR_RATIO_W $clog2(`DCACHE_LINE_SIZE / `DWORD_SIZE)
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`define _DNC_MEM_TAG_WIDTH ($clog2(`DNUM_REQS) + `_DMEM_ADDR_RATIO_W + `DCORE_TAG_WIDTH)
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`define DMEM_TAG_WIDTH `MAX((`DMEM_ADDR_WIDTH + `CLOG2(`DMSHR_SIZE) + `NC_ADDR_BITS), `_DNC_MEM_TAG_WIDTH)
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////////////////////////// SM Configurable Knobs //////////////////////////////
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// Cache ID
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`define SCACHE_ID (32'(`L3_ENABLE) + 32'(`L2_ENABLE) * `NUM_CLUSTERS + CORE_ID * 3 + 2)
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// Word size in bytes
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`define SWORD_SIZE 4
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// bank address offset
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`define SBANK_ADDR_OFFSET `CLOG2(`STACK_SIZE / `SWORD_SIZE)
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// Input request size
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`define SNUM_REQS `NUM_THREADS
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////////////////////////// L2cache Configurable Knobs /////////////////////////
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// Cache ID
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`define L2CACHE_ID (32'(`L3_ENABLE) + CLUSTER_ID)
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// Block size in bytes
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`define L2CACHE_LINE_SIZE `MEM_BLOCK_SIZE
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// Word size in bytes
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`define L2WORD_SIZE `DCACHE_LINE_SIZE
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// Input request tag bits
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`define L2CORE_TAG_WIDTH (`DCORE_TAG_WIDTH + `CLOG2(`NUM_CORES))
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// Memory request data bits
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`define L2MEM_DATA_WIDTH (`L2CACHE_LINE_SIZE * 8)
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// Memory request address bits
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`define L2MEM_ADDR_WIDTH (32 - `CLOG2(`L2CACHE_LINE_SIZE))
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// Memory byte enable bits
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`define L2MEM_BYTEEN_WIDTH `L2CACHE_LINE_SIZE
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// Input request size
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`define L2NUM_REQS `NUM_CORES
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// Memory request tag bits
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`define _L2MEM_ADDR_RATIO_W $clog2(`L2CACHE_LINE_SIZE / `L2WORD_SIZE)
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`define _L2NC_MEM_TAG_WIDTH ($clog2(`L2NUM_REQS) + `_L2MEM_ADDR_RATIO_W + `XMEM_TAG_WIDTH)
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`define _L2MEM_TAG_WIDTH `MAX((`L2MEM_ADDR_WIDTH + `CLOG2(`L2MSHR_SIZE) + `NC_ADDR_BITS), `_L2NC_MEM_TAG_WIDTH)
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`define L2MEM_TAG_WIDTH (`L2_ENABLE ? `_L2MEM_TAG_WIDTH : (`XMEM_TAG_WIDTH + `CLOG2(`L2NUM_REQS)))
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////////////////////////// L3cache Configurable Knobs /////////////////////////
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// Cache ID
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`define L3CACHE_ID 0
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// Block size in bytes
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`define L3CACHE_LINE_SIZE `MEM_BLOCK_SIZE
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// Word size in bytes
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`define L3WORD_SIZE `L2CACHE_LINE_SIZE
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// Input request tag bits
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`define L3CORE_TAG_WIDTH (`L2CORE_TAG_WIDTH + `CLOG2(`NUM_CLUSTERS))
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// Memory request data bits
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`define L3MEM_DATA_WIDTH (`L3CACHE_LINE_SIZE * 8)
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// Memory request address bits
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`define L3MEM_ADDR_WIDTH (32 - `CLOG2(`L3CACHE_LINE_SIZE))
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// Memory byte enable bits
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`define L3MEM_BYTEEN_WIDTH `L3CACHE_LINE_SIZE
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// Input request size
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`define L3NUM_REQS `NUM_CLUSTERS
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// Memory request tag bits
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`define _L3MEM_ADDR_RATIO_W $clog2(`L3CACHE_LINE_SIZE / `L3WORD_SIZE)
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`define _L3NC_MEM_TAG_WIDTH ($clog2(`L3NUM_REQS) + `_L3MEM_ADDR_RATIO_W + `L2MEM_TAG_WIDTH)
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`define _L3MEM_TAG_WIDTH `MAX((`L3MEM_ADDR_WIDTH + `CLOG2(`L3MSHR_SIZE) + `NC_ADDR_BITS), `_L3NC_MEM_TAG_WIDTH)
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`define L3MEM_TAG_WIDTH (`L3_ENABLE ? `_L3MEM_TAG_WIDTH : (`L2MEM_TAG_WIDTH + `CLOG2(`L3NUM_REQS)))
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///////////////////////////////////////////////////////////////////////////////
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`define VX_MEM_BYTEEN_WIDTH `L3MEM_BYTEEN_WIDTH
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`define VX_MEM_ADDR_WIDTH `L3MEM_ADDR_WIDTH
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`define VX_MEM_DATA_WIDTH `L3MEM_DATA_WIDTH
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`define VX_MEM_TAG_WIDTH `L3MEM_TAG_WIDTH
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`define VX_CORE_TAG_WIDTH `L3CORE_TAG_WIDTH
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`define VX_CSR_ID_WIDTH `LOG2UP(`NUM_CLUSTERS * `NUM_CORES)
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`define TO_FULL_ADDR(x) {x, (32-$bits(x))'(0)}
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// Merged D-cache/I-cache memory tag
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`define XMEM_TAG_WIDTH (`DMEM_TAG_WIDTH + `CLOG2(2))
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`include "VX_types.vh"
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`endif
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