c1e168fdbe
+ Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes minor update minor update minor update minor update minor update minor update cleanup cleanup cache bindings and memory perf refactory minor update minor update hw unit tests fixes minor update minor update minor update minor update minor update minor udpate minor update minor update minor update minor update minor update minor update minor update minor updates minor updates minor update minor update minor update minor update minor update minor update minor updates minor updates minor updates minor updates minor update minor update
109 lines
5.3 KiB
Systemverilog
109 lines
5.3 KiB
Systemverilog
// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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`ifndef VORTEX_AFU_VH
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`define VORTEX_AFU_VH
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`ifndef M_AXI_MEM_NUM_BANKS
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`define M_AXI_MEM_NUM_BANKS 1
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`endif
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`ifndef M_AXI_MEM_ID_WIDTH
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`define M_AXI_MEM_ID_WIDTH 32
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`endif
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`define GEN_AXI_MEM(i) \
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output wire m_axi_mem_``i``_awvalid, \
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input wire m_axi_mem_``i``_awready, \
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output wire [C_M_AXI_MEM_ADDR_WIDTH-1:0] m_axi_mem_``i``_awaddr, \
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output wire [C_M_AXI_MEM_ID_WIDTH-1:0] m_axi_mem_``i``_awid, \
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output wire [7:0] m_axi_mem_``i``_awlen, \
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output wire m_axi_mem_``i``_wvalid, \
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input wire m_axi_mem_``i``_wready, \
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output wire [C_M_AXI_MEM_DATA_WIDTH-1:0] m_axi_mem_``i``_wdata, \
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output wire [C_M_AXI_MEM_DATA_WIDTH/8-1:0] m_axi_mem_``i``_wstrb, \
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output wire m_axi_mem_``i``_wlast, \
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output wire m_axi_mem_``i``_arvalid, \
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input wire m_axi_mem_``i``_arready, \
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output wire [C_M_AXI_MEM_ADDR_WIDTH-1:0] m_axi_mem_``i``_araddr, \
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output wire [C_M_AXI_MEM_ID_WIDTH-1:0] m_axi_mem_``i``_arid, \
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output wire [7:0] m_axi_mem_``i``_arlen, \
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input wire m_axi_mem_``i``_rvalid, \
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output wire m_axi_mem_``i``_rready, \
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input wire [C_M_AXI_MEM_DATA_WIDTH-1:0] m_axi_mem_``i``_rdata, \
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input wire m_axi_mem_``i``_rlast, \
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input wire [C_M_AXI_MEM_ID_WIDTH-1:0] m_axi_mem_``i``_rid, \
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input wire [1:0] m_axi_mem_``i``_rresp, \
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input wire m_axi_mem_``i``_bvalid, \
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output wire m_axi_mem_``i``_bready, \
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input wire [1:0] m_axi_mem_``i``_bresp, \
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input wire [C_M_AXI_MEM_ID_WIDTH-1:0] m_axi_mem_``i``_bid
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`define AXI_MEM_ARGS(i) \
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.m_axi_mem_``i``_awvalid(m_axi_mem_``i``_awvalid), \
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.m_axi_mem_``i``_awready(m_axi_mem_``i``_awready), \
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.m_axi_mem_``i``_awaddr(m_axi_mem_``i``_awaddr), \
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.m_axi_mem_``i``_awid(m_axi_mem_``i``_awid), \
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.m_axi_mem_``i``_awlen(m_axi_mem_``i``_awlen), \
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.m_axi_mem_``i``_wvalid(m_axi_mem_``i``_wvalid), \
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.m_axi_mem_``i``_wready(m_axi_mem_``i``_wready), \
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.m_axi_mem_``i``_wdata(m_axi_mem_``i``_wdata), \
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.m_axi_mem_``i``_wstrb(m_axi_mem_``i``_wstrb), \
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.m_axi_mem_``i``_wlast(m_axi_mem_``i``_wlast), \
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.m_axi_mem_``i``_arvalid(m_axi_mem_``i``_arvalid), \
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.m_axi_mem_``i``_arready(m_axi_mem_``i``_arready), \
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.m_axi_mem_``i``_araddr(m_axi_mem_``i``_araddr), \
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.m_axi_mem_``i``_arid(m_axi_mem_``i``_arid), \
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.m_axi_mem_``i``_arlen(m_axi_mem_``i``_arlen), \
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.m_axi_mem_``i``_rvalid(m_axi_mem_``i``_rvalid), \
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.m_axi_mem_``i``_rready(m_axi_mem_``i``_rready), \
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.m_axi_mem_``i``_rdata(m_axi_mem_``i``_rdata), \
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.m_axi_mem_``i``_rlast(m_axi_mem_``i``_rlast), \
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.m_axi_mem_``i``_rid(m_axi_mem_``i``_rid), \
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.m_axi_mem_``i``_rresp(m_axi_mem_``i``_rresp), \
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.m_axi_mem_``i``_bvalid(m_axi_mem_``i``_bvalid), \
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.m_axi_mem_``i``_bready(m_axi_mem_``i``_bready), \
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.m_axi_mem_``i``_bresp(m_axi_mem_``i``_bresp), \
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.m_axi_mem_``i``_bid(m_axi_mem_``i``_bid)
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`define AXI_MEM_TO_ARRAY(i) \
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assign m_axi_mem_``i``_awvalid = m_axi_mem_awvalid_a[i]; \
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assign m_axi_mem_awready_a[i] = m_axi_mem_``i``_awready; \
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assign m_axi_mem_``i``_awaddr = m_axi_mem_awaddr_a[i]; \
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assign m_axi_mem_``i``_awid = m_axi_mem_awid_a[i]; \
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assign m_axi_mem_``i``_awlen = m_axi_mem_awlen_a[i]; \
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assign m_axi_mem_``i``_wvalid = m_axi_mem_wvalid_a[i]; \
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assign m_axi_mem_wready_a[i] = m_axi_mem_``i``_wready; \
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assign m_axi_mem_``i``_wdata = m_axi_mem_wdata_a[i]; \
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assign m_axi_mem_``i``_wstrb = m_axi_mem_wstrb_a[i]; \
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assign m_axi_mem_``i``_wlast = m_axi_mem_wlast_a[i]; \
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assign m_axi_mem_``i``_arvalid = m_axi_mem_arvalid_a[i]; \
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assign m_axi_mem_arready_a[i] = m_axi_mem_``i``_arready; \
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assign m_axi_mem_``i``_araddr = m_axi_mem_araddr_a[i]; \
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assign m_axi_mem_``i``_arid = m_axi_mem_arid_a[i]; \
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assign m_axi_mem_``i``_arlen = m_axi_mem_arlen_a[i]; \
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assign m_axi_mem_rvalid_a[i] = m_axi_mem_``i``_rvalid; \
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assign m_axi_mem_``i``_rready = m_axi_mem_rready_a[i]; \
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assign m_axi_mem_rdata_a[i] = m_axi_mem_``i``_rdata; \
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assign m_axi_mem_rlast_a[i] = m_axi_mem_``i``_rlast; \
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assign m_axi_mem_rid_a[i] = m_axi_mem_``i``_rid; \
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assign m_axi_mem_rresp_a[i] = m_axi_mem_``i``_rresp; \
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assign m_axi_mem_bvalid_a[i] = m_axi_mem_``i``_bvalid; \
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assign m_axi_mem_``i``_bready = m_axi_mem_bready_a[i]; \
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assign m_axi_mem_bresp_a[i] = m_axi_mem_``i``_bresp; \
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assign m_axi_mem_bid_a[i] = m_axi_mem_``i``_bid
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`include "VX_define.vh"
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`endif // VORTEX_AFU_VH
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