c1e168fdbe
+ Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes minor update minor update minor update minor update minor update minor update cleanup cleanup cache bindings and memory perf refactory minor update minor update hw unit tests fixes minor update minor update minor update minor update minor update minor udpate minor update minor update minor update minor update minor update minor update minor update minor updates minor updates minor update minor update minor update minor update minor update minor update minor updates minor updates minor updates minor updates minor update minor update
349 lines
13 KiB
Systemverilog
349 lines
13 KiB
Systemverilog
// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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`include "VX_platform.vh"
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module VX_cache_bypass #(
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parameter NUM_REQS = 1,
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parameter NC_TAG_BIT = 0,
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parameter NC_ENABLE = 0,
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parameter PASSTHRU = 0,
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parameter CORE_ADDR_WIDTH = 1,
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parameter CORE_DATA_SIZE = 1,
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parameter CORE_TAG_IN_WIDTH = 1,
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parameter MEM_ADDR_WIDTH = 1,
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parameter MEM_DATA_SIZE = 1,
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parameter MEM_TAG_IN_WIDTH = 1,
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parameter MEM_TAG_OUT_WIDTH = 1,
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parameter UUID_WIDTH = 0,
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parameter CORE_DATA_WIDTH = CORE_DATA_SIZE * 8,
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parameter MEM_DATA_WIDTH = MEM_DATA_SIZE * 8,
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parameter CORE_TAG_OUT_WIDTH= CORE_TAG_IN_WIDTH - NC_ENABLE
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) (
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input wire clk,
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input wire reset,
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// Core request in
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input wire [NUM_REQS-1:0] core_req_valid_in,
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input wire [NUM_REQS-1:0] core_req_rw_in,
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input wire [NUM_REQS-1:0][CORE_ADDR_WIDTH-1:0] core_req_addr_in,
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input wire [NUM_REQS-1:0][CORE_DATA_SIZE-1:0] core_req_byteen_in,
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input wire [NUM_REQS-1:0][CORE_DATA_WIDTH-1:0] core_req_data_in,
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input wire [NUM_REQS-1:0][CORE_TAG_IN_WIDTH-1:0] core_req_tag_in,
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output wire [NUM_REQS-1:0] core_req_ready_in,
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// Core request out
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output wire [NUM_REQS-1:0] core_req_valid_out,
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output wire [NUM_REQS-1:0] core_req_rw_out,
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output wire [NUM_REQS-1:0][CORE_ADDR_WIDTH-1:0] core_req_addr_out,
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output wire [NUM_REQS-1:0][CORE_DATA_SIZE-1:0] core_req_byteen_out,
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output wire [NUM_REQS-1:0][CORE_DATA_WIDTH-1:0] core_req_data_out,
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output wire [NUM_REQS-1:0][CORE_TAG_OUT_WIDTH-1:0] core_req_tag_out,
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input wire [NUM_REQS-1:0] core_req_ready_out,
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// Core response in
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input wire [NUM_REQS-1:0] core_rsp_valid_in,
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input wire [NUM_REQS-1:0][CORE_DATA_WIDTH-1:0] core_rsp_data_in,
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input wire [NUM_REQS-1:0][CORE_TAG_OUT_WIDTH-1:0] core_rsp_tag_in,
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output wire [NUM_REQS-1:0] core_rsp_ready_in,
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// Core response out
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output wire [NUM_REQS-1:0] core_rsp_valid_out,
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output wire [NUM_REQS-1:0][CORE_DATA_WIDTH-1:0] core_rsp_data_out,
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output wire [NUM_REQS-1:0][CORE_TAG_IN_WIDTH-1:0] core_rsp_tag_out,
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input wire [NUM_REQS-1:0] core_rsp_ready_out,
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// Memory request in
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input wire mem_req_valid_in,
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input wire mem_req_rw_in,
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input wire [MEM_ADDR_WIDTH-1:0] mem_req_addr_in,
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input wire [MEM_DATA_SIZE-1:0] mem_req_byteen_in,
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input wire [MEM_DATA_WIDTH-1:0] mem_req_data_in,
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input wire [MEM_TAG_IN_WIDTH-1:0] mem_req_tag_in,
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output wire mem_req_ready_in,
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// Memory request out
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output wire mem_req_valid_out,
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output wire mem_req_rw_out,
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output wire [MEM_ADDR_WIDTH-1:0] mem_req_addr_out,
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output wire [MEM_DATA_SIZE-1:0] mem_req_byteen_out,
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output wire [MEM_DATA_WIDTH-1:0] mem_req_data_out,
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output wire [MEM_TAG_OUT_WIDTH-1:0] mem_req_tag_out,
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input wire mem_req_ready_out,
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// Memory response in
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input wire mem_rsp_valid_in,
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input wire [MEM_DATA_WIDTH-1:0] mem_rsp_data_in,
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input wire [MEM_TAG_OUT_WIDTH-1:0] mem_rsp_tag_in,
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output wire mem_rsp_ready_in,
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// Memory response out
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output wire mem_rsp_valid_out,
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output wire [MEM_DATA_WIDTH-1:0] mem_rsp_data_out,
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output wire [MEM_TAG_IN_WIDTH-1:0] mem_rsp_tag_out,
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input wire mem_rsp_ready_out
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);
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`UNUSED_VAR (clk)
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`UNUSED_VAR (reset)
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localparam REQ_SEL_BITS = `CLOG2(NUM_REQS);
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localparam MUX_DATAW = CORE_TAG_IN_WIDTH + CORE_DATA_WIDTH + CORE_DATA_SIZE + CORE_ADDR_WIDTH + 1;
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localparam WORDS_PER_LINE = MEM_DATA_SIZE / CORE_DATA_SIZE;
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localparam WSEL_BITS = `CLOG2(WORDS_PER_LINE);
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localparam CORE_TAG_ID_BITS = CORE_TAG_IN_WIDTH - UUID_WIDTH;
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localparam MEM_TAG_ID_BITS = REQ_SEL_BITS + WSEL_BITS + CORE_TAG_ID_BITS;
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localparam MEM_TAG_OUT_NC_WIDTH = MEM_TAG_OUT_WIDTH - 1 + NC_ENABLE;
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// core request handling
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wire [NUM_REQS-1:0] core_req_valid_in_nc;
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wire [NUM_REQS-1:0] core_req_nc_idxs;
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wire [`UP(REQ_SEL_BITS)-1:0] core_req_nc_idx;
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wire [NUM_REQS-1:0] core_req_nc_sel;
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wire core_req_nc_valid;
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for (genvar i = 0; i < NUM_REQS; ++i) begin
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if (PASSTHRU != 0) begin
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assign core_req_nc_idxs[i] = 1'b1;
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end else begin
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assign core_req_nc_idxs[i] = core_req_tag_in[i][NC_TAG_BIT];
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end
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end
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assign core_req_valid_in_nc = core_req_valid_in & core_req_nc_idxs;
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wire core_req_in_fire = | (core_req_valid_in & core_req_ready_in);
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VX_generic_arbiter #(
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.NUM_REQS (NUM_REQS),
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.TYPE (PASSTHRU ? "R" : "P"),
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.LOCK_ENABLE (1)
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) req_arb (
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.clk (clk),
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.reset (reset),
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.unlock (core_req_in_fire),
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.requests (core_req_valid_in_nc),
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.grant_index (core_req_nc_idx),
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.grant_onehot (core_req_nc_sel),
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.grant_valid (core_req_nc_valid)
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);
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assign core_req_valid_out = core_req_valid_in & ~core_req_nc_idxs;
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assign core_req_rw_out = core_req_rw_in;
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assign core_req_addr_out = core_req_addr_in;
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assign core_req_byteen_out = core_req_byteen_in;
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assign core_req_data_out = core_req_data_in;
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for (genvar i = 0; i < NUM_REQS; ++i) begin
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VX_bits_remove #(
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.N (CORE_TAG_IN_WIDTH),
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.S (NC_ENABLE),
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.POS (NC_TAG_BIT)
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) core_req_tag_nc_remove (
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.data_in (core_req_tag_in[i]),
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.data_out (core_req_tag_out[i])
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);
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end
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for (genvar i = 0; i < NUM_REQS; ++i) begin
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assign core_req_ready_in[i] = core_req_valid_in_nc[i] ? (~mem_req_valid_in && mem_req_ready_out && core_req_nc_sel[i])
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: core_req_ready_out[i];
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end
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// memory request handling
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assign mem_req_valid_out = mem_req_valid_in || core_req_nc_valid;
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assign mem_req_ready_in = mem_req_ready_out;
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wire [CORE_TAG_IN_WIDTH-1:0] core_req_tag_in_sel;
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wire [CORE_DATA_WIDTH-1:0] core_req_data_in_sel;
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wire [CORE_DATA_SIZE-1:0] core_req_byteen_in_sel;
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wire [CORE_ADDR_WIDTH-1:0] core_req_addr_in_sel;
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wire core_req_rw_in_sel;
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wire [NUM_REQS-1:0][MUX_DATAW-1:0] core_req_nc_mux_in;
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for (genvar i = 0; i < NUM_REQS; ++i) begin
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assign core_req_nc_mux_in[i] = {core_req_tag_in[i], core_req_data_in[i], core_req_byteen_in[i], core_req_addr_in[i], core_req_rw_in[i]};
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end
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assign {core_req_tag_in_sel, core_req_data_in_sel, core_req_byteen_in_sel, core_req_addr_in_sel, core_req_rw_in_sel} = core_req_nc_mux_in[core_req_nc_idx];
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wire [CORE_TAG_ID_BITS-1:0] core_req_in_id = core_req_tag_in_sel[CORE_TAG_ID_BITS-1:0];
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assign mem_req_rw_out = mem_req_valid_in ? mem_req_rw_in : core_req_rw_in_sel;
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assign mem_req_addr_out = mem_req_valid_in ? mem_req_addr_in : core_req_addr_in_sel[WSEL_BITS +: MEM_ADDR_WIDTH];
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wire [MEM_TAG_ID_BITS-1:0] mem_req_tag_id_bypass;
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if (WORDS_PER_LINE > 1) begin
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reg [WORDS_PER_LINE-1:0][CORE_DATA_SIZE-1:0] mem_req_byteen_in_r;
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reg [WORDS_PER_LINE-1:0][CORE_DATA_WIDTH-1:0] mem_req_data_in_r;
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wire [WSEL_BITS-1:0] req_wsel = core_req_addr_in_sel[WSEL_BITS-1:0];
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always @(*) begin
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mem_req_byteen_in_r = '0;
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mem_req_byteen_in_r[req_wsel] = core_req_byteen_in_sel;
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mem_req_data_in_r = 'x;
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mem_req_data_in_r[req_wsel] = core_req_data_in_sel;
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end
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assign mem_req_byteen_out = mem_req_valid_in ? mem_req_byteen_in : mem_req_byteen_in_r;
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assign mem_req_data_out = mem_req_valid_in ? mem_req_data_in : mem_req_data_in_r;
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if (NUM_REQS > 1) begin
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assign mem_req_tag_id_bypass = MEM_TAG_ID_BITS'({core_req_nc_idx, req_wsel, core_req_in_id});
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end else begin
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assign mem_req_tag_id_bypass = MEM_TAG_ID_BITS'({req_wsel, core_req_in_id});
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end
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end else begin
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assign mem_req_byteen_out = mem_req_valid_in ? mem_req_byteen_in : core_req_byteen_in_sel;
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assign mem_req_data_out = mem_req_valid_in ? mem_req_data_in : core_req_data_in_sel;
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if (NUM_REQS > 1) begin
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assign mem_req_tag_id_bypass = MEM_TAG_ID_BITS'({core_req_nc_idx, core_req_in_id});
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end else begin
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assign mem_req_tag_id_bypass = MEM_TAG_ID_BITS'({core_req_in_id});
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end
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end
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wire [MEM_TAG_OUT_NC_WIDTH-1:0] mem_req_tag_bypass;
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if (UUID_WIDTH != 0) begin
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assign mem_req_tag_bypass = {core_req_tag_in_sel[CORE_TAG_ID_BITS +: UUID_WIDTH], mem_req_tag_id_bypass};
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end else begin
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assign mem_req_tag_bypass = mem_req_tag_id_bypass;
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end
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wire [MEM_TAG_OUT_WIDTH-1:0] mem_req_tag_bypass_nc;
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wire [(MEM_TAG_IN_WIDTH + 1)-1:0] mem_req_tag_in_nc;
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VX_bits_insert #(
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.N (MEM_TAG_OUT_NC_WIDTH),
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.S (NC_ENABLE ? 0 : 1),
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.POS (NC_TAG_BIT)
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) mem_req_tag_bypass_nc_insert (
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.data_in (mem_req_tag_bypass),
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.sel_in (1'b0),
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.data_out (mem_req_tag_bypass_nc)
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);
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VX_bits_insert #(
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.N (MEM_TAG_IN_WIDTH),
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.POS (NC_TAG_BIT)
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) mem_req_tag_in_nc_insert (
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.data_in (mem_req_tag_in),
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.sel_in (1'b0),
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.data_out (mem_req_tag_in_nc)
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);
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assign mem_req_tag_out = mem_req_valid_in ? MEM_TAG_OUT_WIDTH'(mem_req_tag_in_nc) : mem_req_tag_bypass_nc;
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// core response handling
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wire [NUM_REQS-1:0][CORE_TAG_IN_WIDTH-1:0] core_rsp_tag_in_nc;
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wire is_mem_rsp_nc;
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if (PASSTHRU != 0) begin
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assign is_mem_rsp_nc = mem_rsp_valid_in;
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end else begin
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assign is_mem_rsp_nc = mem_rsp_valid_in && mem_rsp_tag_in[NC_TAG_BIT];
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end
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for (genvar i = 0; i < NUM_REQS; ++i) begin
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VX_bits_insert #(
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.N (CORE_TAG_OUT_WIDTH),
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.S (NC_ENABLE),
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.POS (NC_TAG_BIT)
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) core_rsp_tag_in_nc_insert (
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.data_in (core_rsp_tag_in[i]),
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.sel_in ('0),
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.data_out (core_rsp_tag_in_nc[i])
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);
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end
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wire [MEM_TAG_OUT_NC_WIDTH-1:0] mem_rsp_tag_in_nc;
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VX_bits_remove #(
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.N (MEM_TAG_OUT_WIDTH),
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.S (NC_ENABLE ? 0 : 1),
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.POS (NC_TAG_BIT)
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) mem_rsp_tag_in_nc_remove (
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.data_in (mem_rsp_tag_in),
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.data_out (mem_rsp_tag_in_nc)
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);
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wire [`UP(REQ_SEL_BITS)-1:0] rsp_idx;
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if (NUM_REQS > 1) begin
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assign rsp_idx = mem_rsp_tag_in_nc[(CORE_TAG_ID_BITS + WSEL_BITS) +: REQ_SEL_BITS];
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end else begin
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assign rsp_idx = 1'b0;
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end
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reg [NUM_REQS-1:0] rsp_nc_valid_r;
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always @(*) begin
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rsp_nc_valid_r = '0;
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rsp_nc_valid_r[rsp_idx] = is_mem_rsp_nc;
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end
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assign core_rsp_valid_out = core_rsp_valid_in | rsp_nc_valid_r;
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assign core_rsp_ready_in = core_rsp_ready_out;
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if (WORDS_PER_LINE > 1) begin
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wire [WSEL_BITS-1:0] rsp_wsel = mem_rsp_tag_in_nc[CORE_TAG_ID_BITS +: WSEL_BITS];
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for (genvar i = 0; i < NUM_REQS; ++i) begin
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assign core_rsp_data_out[i] = core_rsp_valid_in[i] ?
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core_rsp_data_in[i] : mem_rsp_data_in[rsp_wsel * CORE_DATA_WIDTH +: CORE_DATA_WIDTH];
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end
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end else begin
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for (genvar i = 0; i < NUM_REQS; ++i) begin
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assign core_rsp_data_out[i] = core_rsp_valid_in[i] ? core_rsp_data_in[i] : mem_rsp_data_in;
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end
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end
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for (genvar i = 0; i < NUM_REQS; ++i) begin
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if (UUID_WIDTH != 0) begin
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assign core_rsp_tag_out[i] = core_rsp_valid_in[i] ? core_rsp_tag_in_nc[i] : {mem_rsp_tag_in_nc[MEM_TAG_OUT_NC_WIDTH-1 -: UUID_WIDTH], mem_rsp_tag_in_nc[CORE_TAG_ID_BITS-1:0]};
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end else begin
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assign core_rsp_tag_out[i] = core_rsp_valid_in[i] ? core_rsp_tag_in_nc[i] : mem_rsp_tag_in_nc[CORE_TAG_ID_BITS-1:0];
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end
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end
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// memory response handling
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if (PASSTHRU != 0) begin
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assign mem_rsp_valid_out = 1'b0;
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end else begin
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assign mem_rsp_valid_out = mem_rsp_valid_in && ~mem_rsp_tag_in[NC_TAG_BIT];
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end
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assign mem_rsp_data_out = mem_rsp_data_in;
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VX_bits_remove #(
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.N (MEM_TAG_IN_WIDTH + 1),
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.POS (NC_TAG_BIT)
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) mem_rsp_tag_out_remove (
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.data_in (mem_rsp_tag_in[(MEM_TAG_IN_WIDTH + 1)-1:0]),
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.data_out (mem_rsp_tag_out)
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);
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assign mem_rsp_ready_in = is_mem_rsp_nc ? (~core_rsp_valid_in[rsp_idx] && core_rsp_ready_out[rsp_idx]) : mem_rsp_ready_out;
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endmodule
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