c1e168fdbe
+ Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes minor update minor update minor update minor update minor update minor update cleanup cleanup cache bindings and memory perf refactory minor update minor update hw unit tests fixes minor update minor update minor update minor update minor update minor udpate minor update minor update minor update minor update minor update minor update minor update minor updates minor updates minor update minor update minor update minor update minor update minor update minor updates minor updates minor updates minor updates minor update minor update
128 lines
3.1 KiB
C++
128 lines
3.1 KiB
C++
// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include "vl_simulator.h"
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#include "VVX_fifo_queue.h"
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#include <iostream>
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#define MAX_TICKS 20
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#ifndef TRACE_START_TIME
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#define TRACE_START_TIME 0ull
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#endif
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#ifndef TRACE_STOP_TIME
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#define TRACE_STOP_TIME -1ull
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#endif
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#define CHECK(x) \
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do { \
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if (x) \
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break; \
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std::cout << "FAILED: " << #x << std::endl; \
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std::abort(); \
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} while (false)
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static uint64_t timestamp = 0;
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static bool trace_enabled = false;
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static uint64_t trace_start_time = TRACE_START_TIME;
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static uint64_t trace_stop_time = TRACE_STOP_TIME;
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double sc_time_stamp() {
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return timestamp;
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}
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bool sim_trace_enabled() {
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if (timestamp >= trace_start_time
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&& timestamp < trace_stop_time)
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return true;
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return trace_enabled;
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}
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void sim_trace_enable(bool enable) {
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trace_enabled = enable;
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}
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using Device = VVX_fifo_queue;
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int main(int argc, char **argv) {
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// Initialize Verilators variables
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Verilated::commandArgs(argc, argv);
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vl_simulator<Device> sim;
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// run test
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timestamp = sim.reset(0);
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while (timestamp < MAX_TICKS) {
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switch (timestamp) {
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case 0:
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// initial values
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sim->pop = 0;
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sim->push = 0;
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timestamp = sim.step(timestamp, 2);
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break;
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case 2:
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// Verify outputs
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CHECK(sim->full == 0x0);
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CHECK(sim->empty == 0x1);
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// push 0xa
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sim->pop = 0;
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sim->push = 1;
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sim->data_in = 0xa;
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break;
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case 4:
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// verify outputs
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CHECK(sim->data_out == 0xa);
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CHECK(sim->full == 0x0);
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CHECK(sim->empty == 0x0);
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// push 0xb
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sim->pop = 0;
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sim->push = 1;
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sim->data_in = 0xb;
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break;
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case 6:
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// verify outputs
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CHECK(sim->data_out == 0xa);
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CHECK(sim->full == 0x1);
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CHECK(sim->empty == 0x0);
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// pop
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sim->pop = 1;
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sim->push = 0;
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break;
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case 8:
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// verify outputs
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CHECK(sim->data_out == 0xb);
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CHECK(sim->full == 0x0);
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CHECK(sim->empty == 0x0);
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// pop
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sim->pop = 1;
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sim->push = 0;
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break;
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case 10:
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// verify outputs
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CHECK(sim->full == 0x0);
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CHECK(sim->empty == 0x1);
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sim->pop = 0;
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sim->push = 0;
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break;
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}
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// advance clock
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timestamp = sim.step(timestamp, 2);
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}
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std::cout << "PASSED!" << std::endl;
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std::cout << "Simulation time: " << std::dec << timestamp/2 << " cycles" << std::endl;
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return 0;
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} |