460 lines
22 KiB
Verilog
460 lines
22 KiB
Verilog
`include "VX_define.vh"
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`include "VX_cache_config.vh"
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module Vortex_Cluster #(
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parameter CLUSTER_ID = 0
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) (
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// Clock
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input wire clk,
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input wire reset,
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// DRAM request
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output wire dram_req_read,
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output wire dram_req_write,
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output wire[`L2DRAM_ADDR_WIDTH-1:0] dram_req_addr,
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output wire[`L2DRAM_LINE_WIDTH-1:0] dram_req_data,
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output wire[`L2DRAM_TAG_WIDTH-1:0] dram_req_tag,
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input wire dram_req_ready,
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// DRAM response
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input wire dram_rsp_valid,
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input wire[`L2DRAM_LINE_WIDTH-1:0] dram_rsp_data,
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input wire[`L2DRAM_TAG_WIDTH-1:0] dram_rsp_tag,
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output wire dram_rsp_ready,
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// Snoop request
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input wire snp_req_valid,
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input wire[`L2DRAM_ADDR_WIDTH-1:0] snp_req_addr,
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input wire[`L2SNP_TAG_WIDTH-1:0] snp_req_tag,
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output wire snp_req_ready,
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// Snoop response
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output wire snp_rsp_valid,
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output wire[`L2SNP_TAG_WIDTH-1:0] snp_rsp_tag,
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input wire snp_rsp_ready,
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// I/O request
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output wire io_req_read,
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output wire io_req_write,
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output wire[31:0] io_req_addr,
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output wire[31:0] io_req_data,
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output wire[`BYTE_EN_BITS-1:0] io_req_byteen,
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output wire[`CORE_REQ_TAG_WIDTH-1:0] io_req_tag,
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input wire io_req_ready,
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// I/O response
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input wire io_rsp_valid,
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input wire[31:0] io_rsp_data,
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input wire[`CORE_REQ_TAG_WIDTH-1:0] io_rsp_tag,
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output wire io_rsp_ready,
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// Status
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output wire busy,
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output wire ebreak
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);
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wire[`NUM_CORES-1:0] per_core_D_dram_req_read;
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wire[`NUM_CORES-1:0] per_core_D_dram_req_write;
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wire[`NUM_CORES-1:0][`DDRAM_ADDR_WIDTH-1:0] per_core_D_dram_req_addr;
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wire[`NUM_CORES-1:0][`DDRAM_LINE_WIDTH-1:0] per_core_D_dram_req_data;
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wire[`NUM_CORES-1:0][`DDRAM_TAG_WIDTH-1:0] per_core_D_dram_req_tag;
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wire[`NUM_CORES-1:0] per_core_D_dram_req_ready;
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wire[`NUM_CORES-1:0] per_core_D_dram_rsp_valid;
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wire[`NUM_CORES-1:0][`DDRAM_LINE_WIDTH-1:0] per_core_D_dram_rsp_data;
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wire[`NUM_CORES-1:0][`DDRAM_TAG_WIDTH-1:0] per_core_D_dram_rsp_tag;
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wire[`NUM_CORES-1:0] per_core_D_dram_rsp_ready;
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wire[`NUM_CORES-1:0] per_core_I_dram_req_read;
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wire[`NUM_CORES-1:0][`IDRAM_ADDR_WIDTH-1:0] per_core_I_dram_req_addr;
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wire[`NUM_CORES-1:0][`IDRAM_LINE_WIDTH-1:0] per_core_I_dram_req_data;
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wire[`NUM_CORES-1:0][`IDRAM_TAG_WIDTH-1:0] per_core_I_dram_req_tag;
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wire[`NUM_CORES-1:0] per_core_I_dram_req_ready;
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wire[`NUM_CORES-1:0] per_core_I_dram_rsp_valid;
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wire[`NUM_CORES-1:0][`IDRAM_LINE_WIDTH-1:0] per_core_I_dram_rsp_data;
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wire[`NUM_CORES-1:0][`IDRAM_TAG_WIDTH-1:0] per_core_I_dram_rsp_tag;
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wire[`NUM_CORES-1:0] per_core_I_dram_rsp_ready;
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wire[`NUM_CORES-1:0] per_core_snp_req_valid;
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wire[`NUM_CORES-1:0][`DDRAM_ADDR_WIDTH-1:0] per_core_snp_req_addr;
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wire[`NUM_CORES-1:0][`DSNP_TAG_WIDTH-1:0] per_core_snp_req_tag;
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wire[`NUM_CORES-1:0] per_core_snp_req_ready;
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wire[`NUM_CORES-1:0] per_core_snp_rsp_valid;
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wire[`NUM_CORES-1:0][`DSNP_TAG_WIDTH-1:0] per_core_snp_rsp_tag;
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wire[`NUM_CORES-1:0] per_core_snp_rsp_ready;
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`IGNORE_WARNINGS_BEGIN
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wire[`NUM_CORES-1:0] per_core_io_req_read;
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wire[`NUM_CORES-1:0] per_core_io_req_write;
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wire[`NUM_CORES-1:0][31:0] per_core_io_req_addr;
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wire[`NUM_CORES-1:0][31:0] per_core_io_req_data;
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wire[`NUM_CORES-1:0][`BYTE_EN_BITS-1:0] per_core_io_req_byteen;
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wire[`NUM_CORES-1:0][`CORE_REQ_TAG_WIDTH-1:0] per_core_io_req_tag;
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wire[`NUM_CORES-1:0] per_core_io_rsp_ready;
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`IGNORE_WARNINGS_END
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wire[`NUM_CORES-1:0] per_core_busy;
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wire[`NUM_CORES-1:0] per_core_ebreak;
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genvar i;
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for (i = 0; i < `NUM_CORES; i++) begin
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Vortex #(
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.CORE_ID(i + (CLUSTER_ID * `NUM_CORES))
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) vortex_core (
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.clk (clk),
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.reset (reset),
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.D_dram_req_read (per_core_D_dram_req_read [i]),
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.D_dram_req_write (per_core_D_dram_req_write [i]),
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.D_dram_req_addr (per_core_D_dram_req_addr [i]),
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.D_dram_req_data (per_core_D_dram_req_data [i]),
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.D_dram_req_tag (per_core_D_dram_req_tag [i]),
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.D_dram_req_ready (per_core_D_dram_req_ready [i]),
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.D_dram_rsp_valid (per_core_D_dram_rsp_valid [i]),
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.D_dram_rsp_data (per_core_D_dram_rsp_data [i]),
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.D_dram_rsp_tag (per_core_D_dram_rsp_tag [i]),
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.D_dram_rsp_ready (per_core_D_dram_rsp_ready [i]),
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.I_dram_req_read (per_core_I_dram_req_read [i]),
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`IGNORE_WARNINGS_BEGIN
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.I_dram_req_write (),
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`IGNORE_WARNINGS_END
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.I_dram_req_addr (per_core_I_dram_req_addr [i]),
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.I_dram_req_data (per_core_I_dram_req_data [i]),
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.I_dram_req_tag (per_core_I_dram_req_tag [i]),
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.I_dram_req_ready (per_core_I_dram_req_ready [i]),
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.I_dram_rsp_valid (per_core_I_dram_rsp_valid [i]),
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.I_dram_rsp_tag (per_core_I_dram_rsp_tag [i]),
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.I_dram_rsp_data (per_core_I_dram_rsp_data [i]),
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.I_dram_rsp_ready (per_core_I_dram_rsp_ready [i]),
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.snp_req_valid (per_core_snp_req_valid [i]),
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.snp_req_addr (per_core_snp_req_addr [i]),
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.snp_req_tag (per_core_snp_req_tag [i]),
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.snp_req_ready (per_core_snp_req_ready [i]),
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.snp_rsp_valid (per_core_snp_rsp_valid [i]),
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.snp_rsp_tag (per_core_snp_rsp_tag [i]),
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.snp_rsp_ready (per_core_snp_rsp_ready [i]),
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.io_req_read (per_core_io_req_read [i]),
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.io_req_write (per_core_io_req_write [i]),
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.io_req_addr (per_core_io_req_addr [i]),
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.io_req_data (per_core_io_req_data [i]),
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.io_req_byteen (per_core_io_req_byteen [i]),
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.io_req_tag (per_core_io_req_tag [i]),
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.io_req_ready (io_req_ready),
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.io_rsp_valid (io_rsp_valid),
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.io_rsp_data (io_rsp_data),
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.io_rsp_tag (io_rsp_tag),
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.io_rsp_ready (per_core_io_rsp_ready [i]),
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.busy (per_core_busy [i]),
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.ebreak (per_core_ebreak [i])
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);
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end
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assign io_req_read = per_core_io_req_read[0];
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assign io_req_write = per_core_io_req_write[0];
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assign io_req_addr = per_core_io_req_addr[0];
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assign io_req_data = per_core_io_req_data[0];
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assign io_req_byteen = per_core_io_req_byteen[0];
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assign io_req_tag = per_core_io_req_tag[0];
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assign io_rsp_ready = per_core_io_rsp_ready[0];
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assign busy = (| per_core_busy);
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assign ebreak = (& per_core_ebreak);
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if (`L2_ENABLE) begin
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// L2 Cache ///////////////////////////////////////////////////////////
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wire[`L2NUM_REQUESTS-1:0] l2_core_req_valid;
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wire[`L2NUM_REQUESTS-1:0][`BYTE_EN_BITS-1:0] l2_core_req_write;
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wire[`L2NUM_REQUESTS-1:0][`BYTE_EN_BITS-1:0] l2_core_req_read;
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wire[`L2NUM_REQUESTS-1:0][31:0] l2_core_req_addr;
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wire[`L2NUM_REQUESTS-1:0][`DDRAM_TAG_WIDTH-1:0] l2_core_req_tag;
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wire[`L2NUM_REQUESTS-1:0][`DDRAM_LINE_WIDTH-1:0] l2_core_req_data;
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wire l2_core_req_ready;
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wire[`L2NUM_REQUESTS-1:0] l2_core_rsp_valid;
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wire[`L2NUM_REQUESTS-1:0][`DDRAM_LINE_WIDTH-1:0] l2_core_rsp_data;
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wire[`L2NUM_REQUESTS-1:0][`DDRAM_TAG_WIDTH-1:0] l2_core_rsp_tag;
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wire l2_core_rsp_ready;
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wire[`NUM_CORES-1:0] l2_snp_fwdout_valid;
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wire[`NUM_CORES-1:0][`DDRAM_ADDR_WIDTH-1:0] l2_snp_fwdout_addr;
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wire[`NUM_CORES-1:0][`DSNP_TAG_WIDTH-1:0] l2_snp_fwdout_tag;
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wire[`NUM_CORES-1:0] l2_snp_fwdout_ready;
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wire[`NUM_CORES-1:0] l2_snp_fwdin_valid;
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wire[`NUM_CORES-1:0][`DSNP_TAG_WIDTH-1:0] l2_snp_fwdin_tag;
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wire[`NUM_CORES-1:0] l2_snp_fwdin_ready;
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for (i = 0; i < `L2NUM_REQUESTS; i = i + 2) begin
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assign l2_core_req_valid [i] = (per_core_D_dram_req_read[(i/2)] | per_core_D_dram_req_write[(i/2)]);
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assign l2_core_req_valid [i+1] = per_core_I_dram_req_read[(i/2)];
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assign l2_core_req_read [i] = per_core_D_dram_req_read[(i/2)] ? `BYTE_EN_LW : `BYTE_EN_NO;
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assign l2_core_req_read [i+1] = per_core_I_dram_req_read[(i/2)] ? `BYTE_EN_LW : `BYTE_EN_NO;
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assign l2_core_req_write [i] = per_core_D_dram_req_write[(i/2)] ? `BYTE_EN_LW : `BYTE_EN_NO;
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assign l2_core_req_write [i+1] = `BYTE_EN_NO;
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assign l2_core_req_addr [i] = {per_core_D_dram_req_addr[(i/2)], {`LOG2UP(`DBANK_LINE_SIZE){1'b0}}};
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assign l2_core_req_addr [i+1] = {per_core_I_dram_req_addr[(i/2)], {`LOG2UP(`IBANK_LINE_SIZE){1'b0}}};
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assign l2_core_req_data [i] = per_core_D_dram_req_data[(i/2)];
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assign l2_core_req_data [i+1] = per_core_I_dram_req_data[(i/2)];
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assign l2_core_req_tag [i] = per_core_D_dram_req_tag[(i/2)];
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assign l2_core_req_tag [i+1] = per_core_I_dram_req_tag[(i/2)];
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assign per_core_D_dram_req_ready [(i/2)] = l2_core_req_ready;
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assign per_core_I_dram_req_ready [(i/2)] = l2_core_req_ready;
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assign per_core_D_dram_rsp_valid [(i/2)] = l2_core_rsp_valid[i] && l2_core_rsp_ready;
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assign per_core_I_dram_rsp_valid [(i/2)] = l2_core_rsp_valid[i+1] && l2_core_rsp_ready;
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assign per_core_D_dram_rsp_data [(i/2)] = l2_core_rsp_data[i];
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assign per_core_I_dram_rsp_data [(i/2)] = l2_core_rsp_data[i+1];
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assign per_core_D_dram_rsp_tag [(i/2)] = l2_core_rsp_tag[i];
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assign per_core_I_dram_rsp_tag [(i/2)] = l2_core_rsp_tag[i+1];
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assign per_core_snp_req_valid [(i/2)] = l2_snp_fwdout_valid [(i/2)];
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assign per_core_snp_req_addr [(i/2)] = l2_snp_fwdout_addr [(i/2)];
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assign per_core_snp_req_tag [(i/2)] = l2_snp_fwdout_tag [(i/2)];
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assign l2_snp_fwdout_ready [(i/2)] = per_core_snp_req_ready[(i/2)];
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assign l2_snp_fwdin_valid [(i/2)] = per_core_snp_rsp_valid [(i/2)];
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assign l2_snp_fwdin_tag [(i/2)] = per_core_snp_rsp_tag [(i/2)];
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assign per_core_snp_rsp_ready [(i/2)] = l2_snp_fwdin_ready [(i/2)];
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end
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assign l2_core_rsp_ready = (& per_core_D_dram_rsp_ready) && (& per_core_I_dram_rsp_ready);
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VX_cache #(
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.CACHE_SIZE (`L2CACHE_SIZE),
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.BANK_LINE_SIZE (`L2BANK_LINE_SIZE),
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.NUM_BANKS (`L2NUM_BANKS),
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.WORD_SIZE (`L2WORD_SIZE),
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.NUM_REQUESTS (`L2NUM_REQUESTS),
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.STAGE_1_CYCLES (`L2STAGE_1_CYCLES),
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.REQQ_SIZE (`L2REQQ_SIZE),
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.MRVQ_SIZE (`L2MRVQ_SIZE),
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.DFPQ_SIZE (`L2DFPQ_SIZE),
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.SNRQ_SIZE (`L2SNRQ_SIZE),
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.CWBQ_SIZE (`L2CWBQ_SIZE),
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.DWBQ_SIZE (`L2DWBQ_SIZE),
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.DFQQ_SIZE (`L2DFQQ_SIZE),
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.LLVQ_SIZE (`L2LLVQ_SIZE),
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.SRPQ_SIZE (`L2SRPQ_SIZE),
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.PRFQ_SIZE (`L2PRFQ_SIZE),
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.PRFQ_STRIDE (`L2PRFQ_STRIDE),
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.FILL_INVALIDAOR_SIZE (`L2FILL_INVALIDAOR_SIZE),
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.DRAM_ENABLE (1),
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.WRITE_ENABLE (1),
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.SNOOP_FORWARDING (1),
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.CORE_TAG_WIDTH (`DDRAM_TAG_WIDTH),
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.CORE_TAG_ID_BITS (0),
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.DRAM_TAG_WIDTH (`L2DRAM_TAG_WIDTH),
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.NUM_SNP_REQUESTS (`NUM_CORES),
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.SNP_REQ_TAG_WIDTH (`L2SNP_TAG_WIDTH),
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.SNP_FWD_TAG_WIDTH (`DSNP_TAG_WIDTH)
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) gpu_l2cache (
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.clk (clk),
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.reset (reset),
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// Core request
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.core_req_valid (l2_core_req_valid),
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.core_req_read (l2_core_req_read),
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.core_req_write (l2_core_req_write),
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.core_req_addr (l2_core_req_addr),
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.core_req_data (l2_core_req_data),
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.core_req_tag (l2_core_req_tag),
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.core_req_ready (l2_core_req_ready),
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// Core response
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.core_rsp_valid (l2_core_rsp_valid),
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.core_rsp_data (l2_core_rsp_data),
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.core_rsp_tag (l2_core_rsp_tag),
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.core_rsp_ready (l2_core_rsp_ready),
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// DRAM request
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.dram_req_read (dram_req_read),
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.dram_req_write (dram_req_write),
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.dram_req_addr (dram_req_addr),
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.dram_req_data (dram_req_data),
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.dram_req_tag (dram_req_tag),
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.dram_req_ready (dram_req_ready),
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// DRAM response
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.dram_rsp_valid (dram_rsp_valid),
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.dram_rsp_tag (dram_rsp_tag),
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.dram_rsp_data (dram_rsp_data),
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.dram_rsp_ready (dram_rsp_ready),
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// Snoop request
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.snp_req_valid (snp_req_valid),
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.snp_req_addr (snp_req_addr),
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.snp_req_tag (snp_req_tag),
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.snp_req_ready (snp_req_ready),
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// Snoop response
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.snp_rsp_valid (snp_rsp_valid),
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.snp_rsp_tag (snp_rsp_tag),
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.snp_rsp_ready (snp_rsp_ready),
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// Snoop forwarding out
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.snp_fwdout_valid (l2_snp_fwdout_valid),
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.snp_fwdout_addr (l2_snp_fwdout_addr),
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.snp_fwdout_tag (l2_snp_fwdout_tag),
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.snp_fwdout_ready (l2_snp_fwdout_ready),
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// Snoop forwarding in
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.snp_fwdin_valid (l2_snp_fwdin_valid),
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.snp_fwdin_tag (l2_snp_fwdin_tag),
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.snp_fwdin_ready (l2_snp_fwdin_ready)
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);
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end else begin
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wire[`L2NUM_REQUESTS-1:0] arb_core_req_read;
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wire[`L2NUM_REQUESTS-1:0] arb_core_req_write;
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wire[`L2NUM_REQUESTS-1:0][`DDRAM_ADDR_WIDTH-1:0] arb_core_req_addr;
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wire[`L2NUM_REQUESTS-1:0][`DDRAM_TAG_WIDTH-1:0] arb_core_req_tag;
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wire[`L2NUM_REQUESTS-1:0][`DDRAM_LINE_WIDTH-1:0] arb_core_req_data;
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wire[`L2NUM_REQUESTS-1:0] arb_core_req_ready;
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wire[`L2NUM_REQUESTS-1:0] arb_core_rsp_valid;
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wire[`L2NUM_REQUESTS-1:0][`DDRAM_LINE_WIDTH-1:0] arb_core_rsp_data;
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wire[`L2NUM_REQUESTS-1:0][`DDRAM_TAG_WIDTH-1:0] arb_core_rsp_tag;
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wire[`L2NUM_REQUESTS-1:0] arb_core_rsp_ready;
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wire[`NUM_CORES-1:0] arb_snp_fwdout_valid;
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wire[`NUM_CORES-1:0][`DDRAM_ADDR_WIDTH-1:0] arb_snp_fwdout_addr;
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wire[`NUM_CORES-1:0][`DSNP_TAG_WIDTH-1:0] arb_snp_fwdout_tag;
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wire[`NUM_CORES-1:0] arb_snp_fwdout_ready;
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wire[`NUM_CORES-1:0] arb_snp_fwdin_valid;
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wire[`NUM_CORES-1:0][`DSNP_TAG_WIDTH-1:0] arb_snp_fwdin_tag;
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wire[`NUM_CORES-1:0] arb_snp_fwdin_ready;
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for (i = 0; i < `L2NUM_REQUESTS; i = i + 2) begin
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assign arb_core_req_read [i] = per_core_D_dram_req_read[(i/2)];
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assign arb_core_req_read [i+1] = per_core_I_dram_req_read[(i/2)];
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assign arb_core_req_write [i] = per_core_D_dram_req_write[(i/2)];
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assign arb_core_req_write [i+1] = 0;
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assign arb_core_req_addr [i] = per_core_D_dram_req_addr[(i/2)];
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assign arb_core_req_addr [i+1] = per_core_I_dram_req_addr[(i/2)];
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|
|
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assign arb_core_req_data [i] = per_core_D_dram_req_data[(i/2)];
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assign arb_core_req_data [i+1] = per_core_I_dram_req_data[(i/2)];
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|
|
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assign arb_core_req_tag [i] = per_core_D_dram_req_tag[(i/2)];
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assign arb_core_req_tag [i+1] = per_core_I_dram_req_tag[(i/2)];
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|
|
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assign per_core_D_dram_req_ready [(i/2)] = arb_core_req_ready[i];
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assign per_core_I_dram_req_ready [(i/2)] = arb_core_req_ready[i+1];
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|
|
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assign per_core_D_dram_rsp_valid [(i/2)] = arb_core_rsp_valid[i];
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assign per_core_I_dram_rsp_valid [(i/2)] = arb_core_rsp_valid[i+1];
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|
|
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assign per_core_D_dram_rsp_data [(i/2)] = arb_core_rsp_data[i];
|
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assign per_core_I_dram_rsp_data [(i/2)] = arb_core_rsp_data[i+1];
|
|
|
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assign per_core_D_dram_rsp_tag [(i/2)] = arb_core_rsp_tag[i];
|
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assign per_core_I_dram_rsp_tag [(i/2)] = arb_core_rsp_tag[i+1];
|
|
|
|
assign arb_core_rsp_ready [i] = per_core_D_dram_rsp_ready[(i/2)];
|
|
assign arb_core_rsp_ready [i+1] = per_core_I_dram_rsp_ready[(i/2)];
|
|
|
|
assign per_core_snp_req_valid [(i/2)] = arb_snp_fwdout_valid [(i/2)];
|
|
assign per_core_snp_req_addr [(i/2)] = arb_snp_fwdout_addr [(i/2)];
|
|
assign per_core_snp_req_tag [(i/2)] = arb_snp_fwdout_tag [(i/2)];
|
|
assign arb_snp_fwdout_ready [(i/2)] = per_core_snp_req_ready[(i/2)];
|
|
|
|
assign arb_snp_fwdin_valid [(i/2)] = per_core_snp_rsp_valid [(i/2)];
|
|
assign arb_snp_fwdin_tag [(i/2)] = per_core_snp_rsp_tag [(i/2)];
|
|
assign per_core_snp_rsp_ready [(i/2)] = arb_snp_fwdin_ready [(i/2)];
|
|
end
|
|
|
|
VX_snp_forwarder #(
|
|
.BANK_LINE_SIZE(`L2BANK_LINE_SIZE),
|
|
.NUM_REQUESTS(`NUM_CORES),
|
|
.SNRQ_SIZE(`L2SNRQ_SIZE),
|
|
.SNP_REQ_TAG_WIDTH(`L2SNP_TAG_WIDTH),
|
|
.SNP_FWD_TAG_WIDTH(`DSNP_TAG_WIDTH)
|
|
) snp_forwarder (
|
|
.clk (clk),
|
|
.reset (reset),
|
|
|
|
.snp_req_valid (snp_req_valid),
|
|
.snp_req_addr (snp_req_addr),
|
|
.snp_req_tag (snp_req_tag),
|
|
.snp_req_ready (snp_req_ready),
|
|
|
|
.snp_rsp_valid (snp_rsp_valid),
|
|
.snp_rsp_tag (snp_rsp_tag),
|
|
`IGNORE_WARNINGS_BEGIN
|
|
.snp_rsp_addr (),
|
|
`IGNORE_WARNINGS_END
|
|
.snp_rsp_ready (snp_rsp_ready),
|
|
|
|
.snp_fwdout_valid (arb_snp_fwdout_valid),
|
|
.snp_fwdout_addr (arb_snp_fwdout_addr),
|
|
.snp_fwdout_tag (arb_snp_fwdout_tag),
|
|
.snp_fwdout_ready (arb_snp_fwdout_ready),
|
|
|
|
.snp_fwdin_valid (arb_snp_fwdin_valid),
|
|
.snp_fwdin_tag (arb_snp_fwdin_tag),
|
|
.snp_fwdin_ready (arb_snp_fwdin_ready)
|
|
);
|
|
|
|
VX_dram_arb #(
|
|
.BANK_LINE_SIZE (`L2BANK_LINE_SIZE),
|
|
.NUM_REQUESTS (`L2NUM_REQUESTS),
|
|
.CORE_TAG_WIDTH (`DDRAM_TAG_WIDTH),
|
|
.DRAM_TAG_WIDTH (`L2DRAM_TAG_WIDTH)
|
|
) dram_arb (
|
|
.clk (clk),
|
|
.reset (reset),
|
|
|
|
// Core request
|
|
.core_req_read (arb_core_req_read),
|
|
.core_req_write (arb_core_req_write),
|
|
.core_req_addr (arb_core_req_addr),
|
|
.core_req_data (arb_core_req_data),
|
|
.core_req_tag (arb_core_req_tag),
|
|
.core_req_ready (arb_core_req_ready),
|
|
|
|
// Core response
|
|
.core_rsp_valid (arb_core_rsp_valid),
|
|
.core_rsp_data (arb_core_rsp_data),
|
|
.core_rsp_tag (arb_core_rsp_tag),
|
|
.core_rsp_ready (arb_core_rsp_ready),
|
|
|
|
// DRAM request
|
|
.dram_req_read (dram_req_read),
|
|
.dram_req_write (dram_req_write),
|
|
.dram_req_addr (dram_req_addr),
|
|
.dram_req_data (dram_req_data),
|
|
.dram_req_tag (dram_req_tag),
|
|
.dram_req_ready (dram_req_ready),
|
|
|
|
// DRAM response
|
|
.dram_rsp_valid (dram_rsp_valid),
|
|
.dram_rsp_tag (dram_rsp_tag),
|
|
.dram_rsp_data (dram_rsp_data),
|
|
.dram_rsp_ready (dram_rsp_ready)
|
|
);
|
|
|
|
end
|
|
|
|
endmodule |