83 lines
3.4 KiB
Verilog
83 lines
3.4 KiB
Verilog
`include "VX_define.vh"
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module VX_scheduler (
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input wire clk,
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input wire reset,
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input wire memory_delay,
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input wire exec_delay,
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input wire gpr_stage_delay,
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VX_backend_req_if bckE_req_if,
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VX_wb_if writeback_if,
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output wire schedule_delay,
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output wire is_empty
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);
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localparam CTVW = `CLOG2(`NUM_WARPS * 32 + 1);
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reg [31:0][`NUM_THREADS-1:0] rename_table[`NUM_WARPS-1:0];
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reg [CTVW-1:0] count_valid;
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wire is_store = (bckE_req_if.mem_write != `BYTE_EN_NO);
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wire is_load = (bckE_req_if.mem_read != `BYTE_EN_NO);
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wire is_mem = (is_store || is_load);
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wire is_gpu = (bckE_req_if.is_wspawn || bckE_req_if.is_tmc || bckE_req_if.is_barrier || bckE_req_if.is_split);
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wire is_csr = bckE_req_if.is_csr;
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wire is_exec = !is_mem && !is_gpu && !is_csr;
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wire using_rs2 = is_store
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|| (bckE_req_if.rs2_src == `RS2_REG)
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|| bckE_req_if.is_barrier
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|| bckE_req_if.is_wspawn;
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wire rs1_rename = (rename_table[bckE_req_if.warp_num][bckE_req_if.rs1] != 0);
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wire rs2_rename = (rename_table[bckE_req_if.warp_num][bckE_req_if.rs2] != 0);
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wire rd_rename = (rename_table[bckE_req_if.warp_num][bckE_req_if.rd ] != 0);
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wire rs1_rename_qual = (rs1_rename) && (bckE_req_if.rs1 != 0);
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wire rs2_rename_qual = (rs2_rename) && (bckE_req_if.rs2 != 0 && using_rs2);
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wire rd_rename_qual = (rd_rename) && (bckE_req_if.rd != 0);
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wire rename_valid = rs1_rename_qual || rs2_rename_qual || rd_rename_qual;
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assign schedule_delay = (| bckE_req_if.valid)
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&& ((rename_valid)
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|| (memory_delay && is_mem)
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|| (gpr_stage_delay && (is_mem || is_exec))
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|| (exec_delay && is_exec));
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assign is_empty = (count_valid == 0);
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integer i, w;
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wire acquire_rd = (| bckE_req_if.valid) && (bckE_req_if.wb != 0) && (bckE_req_if.rd != 0) && !schedule_delay;
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wire release_rd = (| writeback_if.valid) && (writeback_if.wb != 0) && (writeback_if.rd != 0);
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wire [`NUM_THREADS-1:0] valid_wb_new_mask = rename_table[writeback_if.warp_num][writeback_if.rd] & ~writeback_if.valid;
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reg [CTVW-1:0] count_valid_next = (acquire_rd && !(release_rd && (0 == valid_wb_new_mask))) ? (count_valid + 1) :
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(~acquire_rd && (release_rd && (0 == valid_wb_new_mask))) ? (count_valid - 1) :
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count_valid;
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always @(posedge clk) begin
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if (reset) begin
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for (w = 0; w < `NUM_WARPS; w++) begin
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for (i = 0; i < 32; i++) begin
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rename_table[w][i] <= 0;
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end
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end
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count_valid <= 0;
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end else begin
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if (acquire_rd) begin
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rename_table[bckE_req_if.warp_num][bckE_req_if.rd] <= bckE_req_if.valid;
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end
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if (release_rd) begin
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assert(rename_table[writeback_if.warp_num][writeback_if.rd] != 0);
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rename_table[writeback_if.warp_num][writeback_if.rd] <= valid_wb_new_mask;
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end
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count_valid <= count_valid_next;
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end
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end
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endmodule |