139 lines
5.2 KiB
Verilog
139 lines
5.2 KiB
Verilog
`include "VX_define.vh"
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module VX_csr_data #(
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parameter CORE_ID = 0
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) (
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input wire clk,
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input wire reset,
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VX_cmt_to_csr_if cmt_to_csr_if,
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VX_csr_to_fpu_if csr_to_fpu_if,
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input wire[`NW_BITS-1:0] warp_num,
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input wire read_enable,
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input wire[`CSR_ADDR_BITS-1:0] read_addr,
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output reg[31:0] read_data,
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input wire write_enable,
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input wire[`CSR_ADDR_BITS-1:0] write_addr,
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input wire[`CSR_WIDTH-1:0] write_data
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);
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reg [`CSR_WIDTH-1:0] csr_satp;
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reg [`CSR_WIDTH-1:0] csr_mstatus;
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reg [`CSR_WIDTH-1:0] csr_medeleg;
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reg [`CSR_WIDTH-1:0] csr_mideleg;
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reg [`CSR_WIDTH-1:0] csr_mie;
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reg [`CSR_WIDTH-1:0] csr_mtvec;
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reg [`CSR_WIDTH-1:0] csr_mepc;
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reg [`CSR_WIDTH-1:0] csr_pmpcfg [0:0];
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reg [`CSR_WIDTH-1:0] csr_pmpaddr [0:0];
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reg [63:0] csr_cycle;
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reg [63:0] csr_instret;
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reg [`FFG_BITS-1:0] csr_fflags [`NUM_WARPS-1:0];
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reg [`FRM_BITS-1:0] csr_frm [`NUM_WARPS-1:0];
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reg [`FRM_BITS+`FFG_BITS-1:0] csr_fcsr [`NUM_WARPS-1:0]; // fflags + frm
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always @(posedge clk) begin
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if (cmt_to_csr_if.upd_fflags) begin
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csr_fflags[cmt_to_csr_if.warp_num] <= cmt_to_csr_if.fflags;
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csr_fcsr[cmt_to_csr_if.warp_num][`FFG_BITS-1:0] <= cmt_to_csr_if.fflags;
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end
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if (write_enable) begin
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case (write_addr)
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`CSR_FFLAGS: begin
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csr_fcsr[warp_num][`FFG_BITS-1:0] <= write_data[`FFG_BITS-1:0];
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csr_fflags[warp_num] <= write_data[`FFG_BITS-1:0];
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end
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`CSR_FRM: begin
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csr_fcsr[warp_num][`FFG_BITS+`FRM_BITS-1:`FFG_BITS] <= write_data[`FRM_BITS-1:0];
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csr_frm[warp_num] <= write_data[`FRM_BITS-1:0];
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end
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`CSR_FCSR: begin
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csr_fcsr[warp_num] <= write_data[`FFG_BITS+`FRM_BITS-1:0];
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csr_frm[warp_num] <= write_data[`FFG_BITS+`FRM_BITS-1:`FFG_BITS];
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csr_fflags[warp_num] <= write_data[`FFG_BITS-1:0];
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end
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`CSR_SATP: csr_satp <= write_data;
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`CSR_MSTATUS: csr_mstatus <= write_data;
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`CSR_MEDELEG: csr_medeleg <= write_data;
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`CSR_MIDELEG: csr_mideleg <= write_data;
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`CSR_MIE: csr_mie <= write_data;
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`CSR_MTVEC: csr_mtvec <= write_data;
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`CSR_MEPC: csr_mepc <= write_data;
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`CSR_PMPCFG0: csr_pmpcfg[0] <= write_data;
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`CSR_PMPADDR0: csr_pmpaddr[0] <= write_data;
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default: begin
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assert(~write_enable) else $error("%t: invalid CSR write address: %0h", $time, write_addr);
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end
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endcase
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end
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end
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always @(posedge clk) begin
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if (reset) begin
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csr_cycle <= 0;
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csr_instret <= 0;
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end else begin
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csr_cycle <= csr_cycle + 1;
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if (cmt_to_csr_if.valid) begin
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csr_instret <= csr_instret + 64'(cmt_to_csr_if.num_commits);
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end
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end
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end
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always @(*) begin
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case (read_addr)
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`CSR_FFLAGS : read_data = 32'(csr_fflags[warp_num]);
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`CSR_FRM : read_data = 32'(csr_frm[warp_num]);
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`CSR_FCSR : read_data = 32'(csr_fcsr[warp_num]);
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`CSR_LWID : read_data = 32'(warp_num);
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`CSR_LTID ,
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`CSR_GTID ,
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`CSR_MHARTID ,
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`CSR_GWID : read_data = CORE_ID * `NUM_WARPS + 32'(warp_num);
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`CSR_GCID : read_data = CORE_ID;
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`CSR_NT : read_data = `NUM_THREADS;
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`CSR_NW : read_data = `NUM_WARPS;
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`CSR_NC : read_data = `NUM_CORES * `NUM_CLUSTERS;
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`CSR_SATP : read_data = 32'(csr_satp);
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`CSR_MSTATUS : read_data = 32'(csr_mstatus);
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`CSR_MISA : read_data = `ISA_CODE;
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`CSR_MEDELEG : read_data = 32'(csr_medeleg);
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`CSR_MIDELEG : read_data = 32'(csr_mideleg);
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`CSR_MIE : read_data = 32'(csr_mie);
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`CSR_MTVEC : read_data = 32'(csr_mtvec);
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`CSR_MEPC : read_data = 32'(csr_mepc);
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`CSR_PMPCFG0 : read_data = 32'(csr_pmpcfg[0]);
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`CSR_PMPADDR0: read_data = 32'(csr_pmpaddr[0]);
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`CSR_CYCLE : read_data = csr_cycle[31:0];
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`CSR_CYCLE_H : read_data = csr_cycle[63:32];
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`CSR_INSTRET : read_data = csr_instret[31:0];
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`CSR_INSTRET_H:read_data = csr_instret[63:32];
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`CSR_MVENDORID:read_data = `VENDOR_ID;
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`CSR_MARCHID : read_data = `ARCHITECTURE_ID;
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`CSR_MIMPID : read_data = `IMPLEMENTATION_ID;
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default: begin
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assert(~read_enable) else $error("%t: invalid CSR read address: %0h", $time, read_addr);
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end
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endcase
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end
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assign csr_to_fpu_if.frm = csr_frm[csr_to_fpu_if.warp_num];
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endmodule |